1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 */ 6 7 #include <linux/pci.h> 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/spinlock.h> 11 #include <linux/bitops.h> 12 13 #include "core.h" 14 #include "debug.h" 15 #include "coredump.h" 16 17 #include "targaddrs.h" 18 #include "bmi.h" 19 20 #include "hif.h" 21 #include "htc.h" 22 23 #include "ce.h" 24 #include "pci.h" 25 26 enum ath10k_pci_reset_mode { 27 ATH10K_PCI_RESET_AUTO = 0, 28 ATH10K_PCI_RESET_WARM_ONLY = 1, 29 }; 30 31 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; 32 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; 33 34 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); 35 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); 36 37 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); 38 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); 39 40 /* how long wait to wait for target to initialise, in ms */ 41 #define ATH10K_PCI_TARGET_WAIT 3000 42 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 43 44 /* Maximum number of bytes that can be handled atomically by 45 * diag read and write. 46 */ 47 #define ATH10K_DIAG_TRANSFER_LIMIT 0x5000 48 49 #define QCA99X0_PCIE_BAR0_START_REG 0x81030 50 #define QCA99X0_CPU_MEM_ADDR_REG 0x4d00c 51 #define QCA99X0_CPU_MEM_DATA_REG 0x4d010 52 53 static const struct pci_device_id ath10k_pci_id_table[] = { 54 /* PCI-E QCA988X V2 (Ubiquiti branded) */ 55 { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) }, 56 57 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ 58 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */ 59 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ 60 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */ 61 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */ 62 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */ 63 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */ 64 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */ 65 {0} 66 }; 67 68 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { 69 /* QCA988X pre 2.0 chips are not supported because they need some nasty 70 * hacks. ath10k doesn't have them and these devices crash horribly 71 * because of that. 72 */ 73 { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV }, 74 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, 75 76 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 77 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 78 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 79 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 80 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 81 82 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 83 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 84 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 85 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 86 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 87 88 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, 89 90 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV }, 91 92 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV }, 93 94 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV }, 95 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV }, 96 97 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV }, 98 }; 99 100 static void ath10k_pci_buffer_cleanup(struct ath10k *ar); 101 static int ath10k_pci_cold_reset(struct ath10k *ar); 102 static int ath10k_pci_safe_chip_reset(struct ath10k *ar); 103 static int ath10k_pci_init_irq(struct ath10k *ar); 104 static int ath10k_pci_deinit_irq(struct ath10k *ar); 105 static int ath10k_pci_request_irq(struct ath10k *ar); 106 static void ath10k_pci_free_irq(struct ath10k *ar); 107 static int ath10k_pci_bmi_wait(struct ath10k *ar, 108 struct ath10k_ce_pipe *tx_pipe, 109 struct ath10k_ce_pipe *rx_pipe, 110 struct bmi_xfer *xfer); 111 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar); 112 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state); 113 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 114 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 115 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 116 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 117 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); 118 119 static struct ce_attr host_ce_config_wlan[] = { 120 /* CE0: host->target HTC control and raw streams */ 121 { 122 .flags = CE_ATTR_FLAGS, 123 .src_nentries = 16, 124 .src_sz_max = 256, 125 .dest_nentries = 0, 126 .send_cb = ath10k_pci_htc_tx_cb, 127 }, 128 129 /* CE1: target->host HTT + HTC control */ 130 { 131 .flags = CE_ATTR_FLAGS, 132 .src_nentries = 0, 133 .src_sz_max = 2048, 134 .dest_nentries = 512, 135 .recv_cb = ath10k_pci_htt_htc_rx_cb, 136 }, 137 138 /* CE2: target->host WMI */ 139 { 140 .flags = CE_ATTR_FLAGS, 141 .src_nentries = 0, 142 .src_sz_max = 2048, 143 .dest_nentries = 128, 144 .recv_cb = ath10k_pci_htc_rx_cb, 145 }, 146 147 /* CE3: host->target WMI */ 148 { 149 .flags = CE_ATTR_FLAGS, 150 .src_nentries = 32, 151 .src_sz_max = 2048, 152 .dest_nentries = 0, 153 .send_cb = ath10k_pci_htc_tx_cb, 154 }, 155 156 /* CE4: host->target HTT */ 157 { 158 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 159 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, 160 .src_sz_max = 256, 161 .dest_nentries = 0, 162 .send_cb = ath10k_pci_htt_tx_cb, 163 }, 164 165 /* CE5: target->host HTT (HIF->HTT) */ 166 { 167 .flags = CE_ATTR_FLAGS, 168 .src_nentries = 0, 169 .src_sz_max = 512, 170 .dest_nentries = 512, 171 .recv_cb = ath10k_pci_htt_rx_cb, 172 }, 173 174 /* CE6: target autonomous hif_memcpy */ 175 { 176 .flags = CE_ATTR_FLAGS, 177 .src_nentries = 0, 178 .src_sz_max = 0, 179 .dest_nentries = 0, 180 }, 181 182 /* CE7: ce_diag, the Diagnostic Window */ 183 { 184 .flags = CE_ATTR_FLAGS | CE_ATTR_POLL, 185 .src_nentries = 2, 186 .src_sz_max = DIAG_TRANSFER_LIMIT, 187 .dest_nentries = 2, 188 }, 189 190 /* CE8: target->host pktlog */ 191 { 192 .flags = CE_ATTR_FLAGS, 193 .src_nentries = 0, 194 .src_sz_max = 2048, 195 .dest_nentries = 128, 196 .recv_cb = ath10k_pci_pktlog_rx_cb, 197 }, 198 199 /* CE9 target autonomous qcache memcpy */ 200 { 201 .flags = CE_ATTR_FLAGS, 202 .src_nentries = 0, 203 .src_sz_max = 0, 204 .dest_nentries = 0, 205 }, 206 207 /* CE10: target autonomous hif memcpy */ 208 { 209 .flags = CE_ATTR_FLAGS, 210 .src_nentries = 0, 211 .src_sz_max = 0, 212 .dest_nentries = 0, 213 }, 214 215 /* CE11: target autonomous hif memcpy */ 216 { 217 .flags = CE_ATTR_FLAGS, 218 .src_nentries = 0, 219 .src_sz_max = 0, 220 .dest_nentries = 0, 221 }, 222 }; 223 224 /* Target firmware's Copy Engine configuration. */ 225 static struct ce_pipe_config target_ce_config_wlan[] = { 226 /* CE0: host->target HTC control and raw streams */ 227 { 228 .pipenum = __cpu_to_le32(0), 229 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 230 .nentries = __cpu_to_le32(32), 231 .nbytes_max = __cpu_to_le32(256), 232 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 233 .reserved = __cpu_to_le32(0), 234 }, 235 236 /* CE1: target->host HTT + HTC control */ 237 { 238 .pipenum = __cpu_to_le32(1), 239 .pipedir = __cpu_to_le32(PIPEDIR_IN), 240 .nentries = __cpu_to_le32(32), 241 .nbytes_max = __cpu_to_le32(2048), 242 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 243 .reserved = __cpu_to_le32(0), 244 }, 245 246 /* CE2: target->host WMI */ 247 { 248 .pipenum = __cpu_to_le32(2), 249 .pipedir = __cpu_to_le32(PIPEDIR_IN), 250 .nentries = __cpu_to_le32(64), 251 .nbytes_max = __cpu_to_le32(2048), 252 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 253 .reserved = __cpu_to_le32(0), 254 }, 255 256 /* CE3: host->target WMI */ 257 { 258 .pipenum = __cpu_to_le32(3), 259 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 260 .nentries = __cpu_to_le32(32), 261 .nbytes_max = __cpu_to_le32(2048), 262 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 263 .reserved = __cpu_to_le32(0), 264 }, 265 266 /* CE4: host->target HTT */ 267 { 268 .pipenum = __cpu_to_le32(4), 269 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 270 .nentries = __cpu_to_le32(256), 271 .nbytes_max = __cpu_to_le32(256), 272 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 273 .reserved = __cpu_to_le32(0), 274 }, 275 276 /* NB: 50% of src nentries, since tx has 2 frags */ 277 278 /* CE5: target->host HTT (HIF->HTT) */ 279 { 280 .pipenum = __cpu_to_le32(5), 281 .pipedir = __cpu_to_le32(PIPEDIR_IN), 282 .nentries = __cpu_to_le32(32), 283 .nbytes_max = __cpu_to_le32(512), 284 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 285 .reserved = __cpu_to_le32(0), 286 }, 287 288 /* CE6: Reserved for target autonomous hif_memcpy */ 289 { 290 .pipenum = __cpu_to_le32(6), 291 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 292 .nentries = __cpu_to_le32(32), 293 .nbytes_max = __cpu_to_le32(4096), 294 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 295 .reserved = __cpu_to_le32(0), 296 }, 297 298 /* CE7 used only by Host */ 299 { 300 .pipenum = __cpu_to_le32(7), 301 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 302 .nentries = __cpu_to_le32(0), 303 .nbytes_max = __cpu_to_le32(0), 304 .flags = __cpu_to_le32(0), 305 .reserved = __cpu_to_le32(0), 306 }, 307 308 /* CE8 target->host packtlog */ 309 { 310 .pipenum = __cpu_to_le32(8), 311 .pipedir = __cpu_to_le32(PIPEDIR_IN), 312 .nentries = __cpu_to_le32(64), 313 .nbytes_max = __cpu_to_le32(2048), 314 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 315 .reserved = __cpu_to_le32(0), 316 }, 317 318 /* CE9 target autonomous qcache memcpy */ 319 { 320 .pipenum = __cpu_to_le32(9), 321 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 322 .nentries = __cpu_to_le32(32), 323 .nbytes_max = __cpu_to_le32(2048), 324 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 325 .reserved = __cpu_to_le32(0), 326 }, 327 328 /* It not necessary to send target wlan configuration for CE10 & CE11 329 * as these CEs are not actively used in target. 330 */ 331 }; 332 333 /* 334 * Map from service/endpoint to Copy Engine. 335 * This table is derived from the CE_PCI TABLE, above. 336 * It is passed to the Target at startup for use by firmware. 337 */ 338 static struct service_to_pipe target_service_to_ce_map_wlan[] = { 339 { 340 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 341 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 342 __cpu_to_le32(3), 343 }, 344 { 345 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 346 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 347 __cpu_to_le32(2), 348 }, 349 { 350 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 351 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 352 __cpu_to_le32(3), 353 }, 354 { 355 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 356 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 357 __cpu_to_le32(2), 358 }, 359 { 360 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 361 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 362 __cpu_to_le32(3), 363 }, 364 { 365 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 366 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 367 __cpu_to_le32(2), 368 }, 369 { 370 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 371 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 372 __cpu_to_le32(3), 373 }, 374 { 375 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 376 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 377 __cpu_to_le32(2), 378 }, 379 { 380 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 381 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 382 __cpu_to_le32(3), 383 }, 384 { 385 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 386 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 387 __cpu_to_le32(2), 388 }, 389 { 390 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 391 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 392 __cpu_to_le32(0), 393 }, 394 { 395 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 396 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 397 __cpu_to_le32(1), 398 }, 399 { /* not used */ 400 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 401 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 402 __cpu_to_le32(0), 403 }, 404 { /* not used */ 405 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 406 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 407 __cpu_to_le32(1), 408 }, 409 { 410 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 411 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 412 __cpu_to_le32(4), 413 }, 414 { 415 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 416 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 417 __cpu_to_le32(5), 418 }, 419 420 /* (Additions here) */ 421 422 { /* must be last */ 423 __cpu_to_le32(0), 424 __cpu_to_le32(0), 425 __cpu_to_le32(0), 426 }, 427 }; 428 429 static bool ath10k_pci_is_awake(struct ath10k *ar) 430 { 431 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 432 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 433 RTC_STATE_ADDRESS); 434 435 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; 436 } 437 438 static void __ath10k_pci_wake(struct ath10k *ar) 439 { 440 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 441 442 lockdep_assert_held(&ar_pci->ps_lock); 443 444 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n", 445 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 446 447 iowrite32(PCIE_SOC_WAKE_V_MASK, 448 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 449 PCIE_SOC_WAKE_ADDRESS); 450 } 451 452 static void __ath10k_pci_sleep(struct ath10k *ar) 453 { 454 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 455 456 lockdep_assert_held(&ar_pci->ps_lock); 457 458 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n", 459 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 460 461 iowrite32(PCIE_SOC_WAKE_RESET, 462 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 463 PCIE_SOC_WAKE_ADDRESS); 464 ar_pci->ps_awake = false; 465 } 466 467 static int ath10k_pci_wake_wait(struct ath10k *ar) 468 { 469 int tot_delay = 0; 470 int curr_delay = 5; 471 472 while (tot_delay < PCIE_WAKE_TIMEOUT) { 473 if (ath10k_pci_is_awake(ar)) { 474 if (tot_delay > PCIE_WAKE_LATE_US) 475 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n", 476 tot_delay / 1000); 477 return 0; 478 } 479 480 udelay(curr_delay); 481 tot_delay += curr_delay; 482 483 if (curr_delay < 50) 484 curr_delay += 5; 485 } 486 487 return -ETIMEDOUT; 488 } 489 490 static int ath10k_pci_force_wake(struct ath10k *ar) 491 { 492 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 493 unsigned long flags; 494 int ret = 0; 495 496 if (ar_pci->pci_ps) 497 return ret; 498 499 spin_lock_irqsave(&ar_pci->ps_lock, flags); 500 501 if (!ar_pci->ps_awake) { 502 iowrite32(PCIE_SOC_WAKE_V_MASK, 503 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 504 PCIE_SOC_WAKE_ADDRESS); 505 506 ret = ath10k_pci_wake_wait(ar); 507 if (ret == 0) 508 ar_pci->ps_awake = true; 509 } 510 511 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 512 513 return ret; 514 } 515 516 static void ath10k_pci_force_sleep(struct ath10k *ar) 517 { 518 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 519 unsigned long flags; 520 521 spin_lock_irqsave(&ar_pci->ps_lock, flags); 522 523 iowrite32(PCIE_SOC_WAKE_RESET, 524 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 525 PCIE_SOC_WAKE_ADDRESS); 526 ar_pci->ps_awake = false; 527 528 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 529 } 530 531 static int ath10k_pci_wake(struct ath10k *ar) 532 { 533 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 534 unsigned long flags; 535 int ret = 0; 536 537 if (ar_pci->pci_ps == 0) 538 return ret; 539 540 spin_lock_irqsave(&ar_pci->ps_lock, flags); 541 542 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n", 543 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 544 545 /* This function can be called very frequently. To avoid excessive 546 * CPU stalls for MMIO reads use a cache var to hold the device state. 547 */ 548 if (!ar_pci->ps_awake) { 549 __ath10k_pci_wake(ar); 550 551 ret = ath10k_pci_wake_wait(ar); 552 if (ret == 0) 553 ar_pci->ps_awake = true; 554 } 555 556 if (ret == 0) { 557 ar_pci->ps_wake_refcount++; 558 WARN_ON(ar_pci->ps_wake_refcount == 0); 559 } 560 561 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 562 563 return ret; 564 } 565 566 static void ath10k_pci_sleep(struct ath10k *ar) 567 { 568 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 569 unsigned long flags; 570 571 if (ar_pci->pci_ps == 0) 572 return; 573 574 spin_lock_irqsave(&ar_pci->ps_lock, flags); 575 576 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n", 577 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 578 579 if (WARN_ON(ar_pci->ps_wake_refcount == 0)) 580 goto skip; 581 582 ar_pci->ps_wake_refcount--; 583 584 mod_timer(&ar_pci->ps_timer, jiffies + 585 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC)); 586 587 skip: 588 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 589 } 590 591 static void ath10k_pci_ps_timer(struct timer_list *t) 592 { 593 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, ps_timer); 594 struct ath10k *ar = ar_pci->ar; 595 unsigned long flags; 596 597 spin_lock_irqsave(&ar_pci->ps_lock, flags); 598 599 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n", 600 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 601 602 if (ar_pci->ps_wake_refcount > 0) 603 goto skip; 604 605 __ath10k_pci_sleep(ar); 606 607 skip: 608 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 609 } 610 611 static void ath10k_pci_sleep_sync(struct ath10k *ar) 612 { 613 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 614 unsigned long flags; 615 616 if (ar_pci->pci_ps == 0) { 617 ath10k_pci_force_sleep(ar); 618 return; 619 } 620 621 del_timer_sync(&ar_pci->ps_timer); 622 623 spin_lock_irqsave(&ar_pci->ps_lock, flags); 624 WARN_ON(ar_pci->ps_wake_refcount > 0); 625 __ath10k_pci_sleep(ar); 626 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 627 } 628 629 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value) 630 { 631 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 632 int ret; 633 634 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { 635 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 636 offset, offset + sizeof(value), ar_pci->mem_len); 637 return; 638 } 639 640 ret = ath10k_pci_wake(ar); 641 if (ret) { 642 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n", 643 value, offset, ret); 644 return; 645 } 646 647 iowrite32(value, ar_pci->mem + offset); 648 ath10k_pci_sleep(ar); 649 } 650 651 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) 652 { 653 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 654 u32 val; 655 int ret; 656 657 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { 658 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 659 offset, offset + sizeof(val), ar_pci->mem_len); 660 return 0; 661 } 662 663 ret = ath10k_pci_wake(ar); 664 if (ret) { 665 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n", 666 offset, ret); 667 return 0xffffffff; 668 } 669 670 val = ioread32(ar_pci->mem + offset); 671 ath10k_pci_sleep(ar); 672 673 return val; 674 } 675 676 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) 677 { 678 struct ath10k_ce *ce = ath10k_ce_priv(ar); 679 680 ce->bus_ops->write32(ar, offset, value); 681 } 682 683 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) 684 { 685 struct ath10k_ce *ce = ath10k_ce_priv(ar); 686 687 return ce->bus_ops->read32(ar, offset); 688 } 689 690 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) 691 { 692 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 693 } 694 695 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) 696 { 697 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); 698 } 699 700 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) 701 { 702 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr); 703 } 704 705 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) 706 { 707 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); 708 } 709 710 bool ath10k_pci_irq_pending(struct ath10k *ar) 711 { 712 u32 cause; 713 714 /* Check if the shared legacy irq is for us */ 715 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 716 PCIE_INTR_CAUSE_ADDRESS); 717 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) 718 return true; 719 720 return false; 721 } 722 723 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) 724 { 725 /* IMPORTANT: INTR_CLR register has to be set after 726 * INTR_ENABLE is set to 0, otherwise interrupt can not be 727 * really cleared. 728 */ 729 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 730 0); 731 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, 732 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 733 734 /* IMPORTANT: this extra read transaction is required to 735 * flush the posted write buffer. 736 */ 737 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 738 PCIE_INTR_ENABLE_ADDRESS); 739 } 740 741 void ath10k_pci_enable_legacy_irq(struct ath10k *ar) 742 { 743 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 744 PCIE_INTR_ENABLE_ADDRESS, 745 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 746 747 /* IMPORTANT: this extra read transaction is required to 748 * flush the posted write buffer. 749 */ 750 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 751 PCIE_INTR_ENABLE_ADDRESS); 752 } 753 754 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) 755 { 756 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 757 758 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI) 759 return "msi"; 760 761 return "legacy"; 762 } 763 764 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) 765 { 766 struct ath10k *ar = pipe->hif_ce_state; 767 struct ath10k_ce *ce = ath10k_ce_priv(ar); 768 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 769 struct sk_buff *skb; 770 dma_addr_t paddr; 771 int ret; 772 773 skb = dev_alloc_skb(pipe->buf_sz); 774 if (!skb) 775 return -ENOMEM; 776 777 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 778 779 paddr = dma_map_single(ar->dev, skb->data, 780 skb->len + skb_tailroom(skb), 781 DMA_FROM_DEVICE); 782 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 783 ath10k_warn(ar, "failed to dma map pci rx buf\n"); 784 dev_kfree_skb_any(skb); 785 return -EIO; 786 } 787 788 ATH10K_SKB_RXCB(skb)->paddr = paddr; 789 790 spin_lock_bh(&ce->ce_lock); 791 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr); 792 spin_unlock_bh(&ce->ce_lock); 793 if (ret) { 794 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 795 DMA_FROM_DEVICE); 796 dev_kfree_skb_any(skb); 797 return ret; 798 } 799 800 return 0; 801 } 802 803 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) 804 { 805 struct ath10k *ar = pipe->hif_ce_state; 806 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 807 struct ath10k_ce *ce = ath10k_ce_priv(ar); 808 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 809 int ret, num; 810 811 if (pipe->buf_sz == 0) 812 return; 813 814 if (!ce_pipe->dest_ring) 815 return; 816 817 spin_lock_bh(&ce->ce_lock); 818 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 819 spin_unlock_bh(&ce->ce_lock); 820 821 while (num >= 0) { 822 ret = __ath10k_pci_rx_post_buf(pipe); 823 if (ret) { 824 if (ret == -ENOSPC) 825 break; 826 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); 827 mod_timer(&ar_pci->rx_post_retry, jiffies + 828 ATH10K_PCI_RX_POST_RETRY_MS); 829 break; 830 } 831 num--; 832 } 833 } 834 835 void ath10k_pci_rx_post(struct ath10k *ar) 836 { 837 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 838 int i; 839 840 for (i = 0; i < CE_COUNT; i++) 841 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); 842 } 843 844 void ath10k_pci_rx_replenish_retry(struct timer_list *t) 845 { 846 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, rx_post_retry); 847 struct ath10k *ar = ar_pci->ar; 848 849 ath10k_pci_rx_post(ar); 850 } 851 852 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 853 { 854 u32 val = 0, region = addr & 0xfffff; 855 856 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 857 & 0x7ff) << 21; 858 val |= 0x100000 | region; 859 return val; 860 } 861 862 /* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr. 863 * Support to access target space below 1M for qca6174 and qca9377. 864 * If target space is below 1M, the bit[20] of converted CE addr is 0. 865 * Otherwise bit[20] of converted CE addr is 1. 866 */ 867 static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 868 { 869 u32 val = 0, region = addr & 0xfffff; 870 871 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 872 & 0x7ff) << 21; 873 val |= ((addr >= 0x100000) ? 0x100000 : 0) | region; 874 return val; 875 } 876 877 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 878 { 879 u32 val = 0, region = addr & 0xfffff; 880 881 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); 882 val |= 0x100000 | region; 883 return val; 884 } 885 886 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 887 { 888 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 889 890 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr)) 891 return -ENOTSUPP; 892 893 return ar_pci->targ_cpu_to_ce_addr(ar, addr); 894 } 895 896 /* 897 * Diagnostic read/write access is provided for startup/config/debug usage. 898 * Caller must guarantee proper alignment, when applicable, and single user 899 * at any moment. 900 */ 901 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, 902 int nbytes) 903 { 904 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 905 int ret = 0; 906 u32 *buf; 907 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 908 struct ath10k_ce_pipe *ce_diag; 909 /* Host buffer address in CE space */ 910 u32 ce_data; 911 dma_addr_t ce_data_base = 0; 912 void *data_buf = NULL; 913 int i; 914 915 mutex_lock(&ar_pci->ce_diag_mutex); 916 ce_diag = ar_pci->ce_diag; 917 918 /* 919 * Allocate a temporary bounce buffer to hold caller's data 920 * to be DMA'ed from Target. This guarantees 921 * 1) 4-byte alignment 922 * 2) Buffer in DMA-able space 923 */ 924 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 925 926 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, alloc_nbytes, 927 &ce_data_base, 928 GFP_ATOMIC); 929 930 if (!data_buf) { 931 ret = -ENOMEM; 932 goto done; 933 } 934 935 /* The address supplied by the caller is in the 936 * Target CPU virtual address space. 937 * 938 * In order to use this address with the diagnostic CE, 939 * convert it from Target CPU virtual address space 940 * to CE address space 941 */ 942 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 943 944 remaining_bytes = nbytes; 945 ce_data = ce_data_base; 946 while (remaining_bytes) { 947 nbytes = min_t(unsigned int, remaining_bytes, 948 DIAG_TRANSFER_LIMIT); 949 950 ret = ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data); 951 if (ret != 0) 952 goto done; 953 954 /* Request CE to send from Target(!) address to Host buffer */ 955 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0, 0); 956 if (ret) 957 goto done; 958 959 i = 0; 960 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) { 961 udelay(DIAG_ACCESS_CE_WAIT_US); 962 i += DIAG_ACCESS_CE_WAIT_US; 963 964 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 965 ret = -EBUSY; 966 goto done; 967 } 968 } 969 970 i = 0; 971 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf, 972 &completed_nbytes) != 0) { 973 udelay(DIAG_ACCESS_CE_WAIT_US); 974 i += DIAG_ACCESS_CE_WAIT_US; 975 976 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 977 ret = -EBUSY; 978 goto done; 979 } 980 } 981 982 if (nbytes != completed_nbytes) { 983 ret = -EIO; 984 goto done; 985 } 986 987 if (*buf != ce_data) { 988 ret = -EIO; 989 goto done; 990 } 991 992 remaining_bytes -= nbytes; 993 memcpy(data, data_buf, nbytes); 994 995 address += nbytes; 996 data += nbytes; 997 } 998 999 done: 1000 1001 if (data_buf) 1002 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 1003 ce_data_base); 1004 1005 mutex_unlock(&ar_pci->ce_diag_mutex); 1006 1007 return ret; 1008 } 1009 1010 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) 1011 { 1012 __le32 val = 0; 1013 int ret; 1014 1015 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); 1016 *value = __le32_to_cpu(val); 1017 1018 return ret; 1019 } 1020 1021 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, 1022 u32 src, u32 len) 1023 { 1024 u32 host_addr, addr; 1025 int ret; 1026 1027 host_addr = host_interest_item_address(src); 1028 1029 ret = ath10k_pci_diag_read32(ar, host_addr, &addr); 1030 if (ret != 0) { 1031 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", 1032 src, ret); 1033 return ret; 1034 } 1035 1036 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); 1037 if (ret != 0) { 1038 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", 1039 addr, len, ret); 1040 return ret; 1041 } 1042 1043 return 0; 1044 } 1045 1046 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ 1047 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) 1048 1049 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, 1050 const void *data, int nbytes) 1051 { 1052 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1053 int ret = 0; 1054 u32 *buf; 1055 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 1056 struct ath10k_ce_pipe *ce_diag; 1057 void *data_buf = NULL; 1058 dma_addr_t ce_data_base = 0; 1059 int i; 1060 1061 mutex_lock(&ar_pci->ce_diag_mutex); 1062 ce_diag = ar_pci->ce_diag; 1063 1064 /* 1065 * Allocate a temporary bounce buffer to hold caller's data 1066 * to be DMA'ed to Target. This guarantees 1067 * 1) 4-byte alignment 1068 * 2) Buffer in DMA-able space 1069 */ 1070 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 1071 1072 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, 1073 alloc_nbytes, 1074 &ce_data_base, 1075 GFP_ATOMIC); 1076 if (!data_buf) { 1077 ret = -ENOMEM; 1078 goto done; 1079 } 1080 1081 /* 1082 * The address supplied by the caller is in the 1083 * Target CPU virtual address space. 1084 * 1085 * In order to use this address with the diagnostic CE, 1086 * convert it from 1087 * Target CPU virtual address space 1088 * to 1089 * CE address space 1090 */ 1091 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 1092 1093 remaining_bytes = nbytes; 1094 while (remaining_bytes) { 1095 /* FIXME: check cast */ 1096 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); 1097 1098 /* Copy caller's data to allocated DMA buf */ 1099 memcpy(data_buf, data, nbytes); 1100 1101 /* Set up to receive directly into Target(!) address */ 1102 ret = ath10k_ce_rx_post_buf(ce_diag, &address, address); 1103 if (ret != 0) 1104 goto done; 1105 1106 /* 1107 * Request CE to send caller-supplied data that 1108 * was copied to bounce buffer to Target(!) address. 1109 */ 1110 ret = ath10k_ce_send(ce_diag, NULL, ce_data_base, nbytes, 0, 0); 1111 if (ret != 0) 1112 goto done; 1113 1114 i = 0; 1115 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) { 1116 udelay(DIAG_ACCESS_CE_WAIT_US); 1117 i += DIAG_ACCESS_CE_WAIT_US; 1118 1119 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1120 ret = -EBUSY; 1121 goto done; 1122 } 1123 } 1124 1125 i = 0; 1126 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf, 1127 &completed_nbytes) != 0) { 1128 udelay(DIAG_ACCESS_CE_WAIT_US); 1129 i += DIAG_ACCESS_CE_WAIT_US; 1130 1131 if (i > DIAG_ACCESS_CE_TIMEOUT_US) { 1132 ret = -EBUSY; 1133 goto done; 1134 } 1135 } 1136 1137 if (nbytes != completed_nbytes) { 1138 ret = -EIO; 1139 goto done; 1140 } 1141 1142 if (*buf != address) { 1143 ret = -EIO; 1144 goto done; 1145 } 1146 1147 remaining_bytes -= nbytes; 1148 address += nbytes; 1149 data += nbytes; 1150 } 1151 1152 done: 1153 if (data_buf) { 1154 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 1155 ce_data_base); 1156 } 1157 1158 if (ret != 0) 1159 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", 1160 address, ret); 1161 1162 mutex_unlock(&ar_pci->ce_diag_mutex); 1163 1164 return ret; 1165 } 1166 1167 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) 1168 { 1169 __le32 val = __cpu_to_le32(value); 1170 1171 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); 1172 } 1173 1174 /* Called by lower (CE) layer when a send to Target completes. */ 1175 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state) 1176 { 1177 struct ath10k *ar = ce_state->ar; 1178 struct sk_buff_head list; 1179 struct sk_buff *skb; 1180 1181 __skb_queue_head_init(&list); 1182 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1183 /* no need to call tx completion for NULL pointers */ 1184 if (skb == NULL) 1185 continue; 1186 1187 __skb_queue_tail(&list, skb); 1188 } 1189 1190 while ((skb = __skb_dequeue(&list))) 1191 ath10k_htc_tx_completion_handler(ar, skb); 1192 } 1193 1194 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state, 1195 void (*callback)(struct ath10k *ar, 1196 struct sk_buff *skb)) 1197 { 1198 struct ath10k *ar = ce_state->ar; 1199 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1200 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1201 struct sk_buff *skb; 1202 struct sk_buff_head list; 1203 void *transfer_context; 1204 unsigned int nbytes, max_nbytes; 1205 1206 __skb_queue_head_init(&list); 1207 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 1208 &nbytes) == 0) { 1209 skb = transfer_context; 1210 max_nbytes = skb->len + skb_tailroom(skb); 1211 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1212 max_nbytes, DMA_FROM_DEVICE); 1213 1214 if (unlikely(max_nbytes < nbytes)) { 1215 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1216 nbytes, max_nbytes); 1217 dev_kfree_skb_any(skb); 1218 continue; 1219 } 1220 1221 skb_put(skb, nbytes); 1222 __skb_queue_tail(&list, skb); 1223 } 1224 1225 while ((skb = __skb_dequeue(&list))) { 1226 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1227 ce_state->id, skb->len); 1228 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1229 skb->data, skb->len); 1230 1231 callback(ar, skb); 1232 } 1233 1234 ath10k_pci_rx_post_pipe(pipe_info); 1235 } 1236 1237 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state, 1238 void (*callback)(struct ath10k *ar, 1239 struct sk_buff *skb)) 1240 { 1241 struct ath10k *ar = ce_state->ar; 1242 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1243 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1244 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl; 1245 struct sk_buff *skb; 1246 struct sk_buff_head list; 1247 void *transfer_context; 1248 unsigned int nbytes, max_nbytes, nentries; 1249 int orig_len; 1250 1251 /* No need to aquire ce_lock for CE5, since this is the only place CE5 1252 * is processed other than init and deinit. Before releasing CE5 1253 * buffers, interrupts are disabled. Thus CE5 access is serialized. 1254 */ 1255 __skb_queue_head_init(&list); 1256 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context, 1257 &nbytes) == 0) { 1258 skb = transfer_context; 1259 max_nbytes = skb->len + skb_tailroom(skb); 1260 1261 if (unlikely(max_nbytes < nbytes)) { 1262 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1263 nbytes, max_nbytes); 1264 continue; 1265 } 1266 1267 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1268 max_nbytes, DMA_FROM_DEVICE); 1269 skb_put(skb, nbytes); 1270 __skb_queue_tail(&list, skb); 1271 } 1272 1273 nentries = skb_queue_len(&list); 1274 while ((skb = __skb_dequeue(&list))) { 1275 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1276 ce_state->id, skb->len); 1277 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1278 skb->data, skb->len); 1279 1280 orig_len = skb->len; 1281 callback(ar, skb); 1282 skb_push(skb, orig_len - skb->len); 1283 skb_reset_tail_pointer(skb); 1284 skb_trim(skb, 0); 1285 1286 /*let device gain the buffer again*/ 1287 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1288 skb->len + skb_tailroom(skb), 1289 DMA_FROM_DEVICE); 1290 } 1291 ath10k_ce_rx_update_write_idx(ce_pipe, nentries); 1292 } 1293 1294 /* Called by lower (CE) layer when data is received from the Target. */ 1295 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1296 { 1297 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1298 } 1299 1300 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1301 { 1302 /* CE4 polling needs to be done whenever CE pipe which transports 1303 * HTT Rx (target->host) is processed. 1304 */ 1305 ath10k_ce_per_engine_service(ce_state->ar, 4); 1306 1307 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1308 } 1309 1310 /* Called by lower (CE) layer when data is received from the Target. 1311 * Only 10.4 firmware uses separate CE to transfer pktlog data. 1312 */ 1313 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) 1314 { 1315 ath10k_pci_process_rx_cb(ce_state, 1316 ath10k_htt_rx_pktlog_completion_handler); 1317 } 1318 1319 /* Called by lower (CE) layer when a send to HTT Target completes. */ 1320 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 1321 { 1322 struct ath10k *ar = ce_state->ar; 1323 struct sk_buff *skb; 1324 1325 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1326 /* no need to call tx completion for NULL pointers */ 1327 if (!skb) 1328 continue; 1329 1330 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 1331 skb->len, DMA_TO_DEVICE); 1332 ath10k_htt_hif_tx_complete(ar, skb); 1333 } 1334 } 1335 1336 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) 1337 { 1338 skb_pull(skb, sizeof(struct ath10k_htc_hdr)); 1339 ath10k_htt_t2h_msg_handler(ar, skb); 1340 } 1341 1342 /* Called by lower (CE) layer when HTT data is received from the Target. */ 1343 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state) 1344 { 1345 /* CE4 polling needs to be done whenever CE pipe which transports 1346 * HTT Rx (target->host) is processed. 1347 */ 1348 ath10k_ce_per_engine_service(ce_state->ar, 4); 1349 1350 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver); 1351 } 1352 1353 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 1354 struct ath10k_hif_sg_item *items, int n_items) 1355 { 1356 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1357 struct ath10k_ce *ce = ath10k_ce_priv(ar); 1358 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; 1359 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; 1360 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; 1361 unsigned int nentries_mask; 1362 unsigned int sw_index; 1363 unsigned int write_index; 1364 int err, i = 0; 1365 1366 spin_lock_bh(&ce->ce_lock); 1367 1368 nentries_mask = src_ring->nentries_mask; 1369 sw_index = src_ring->sw_index; 1370 write_index = src_ring->write_index; 1371 1372 if (unlikely(CE_RING_DELTA(nentries_mask, 1373 write_index, sw_index - 1) < n_items)) { 1374 err = -ENOBUFS; 1375 goto err; 1376 } 1377 1378 for (i = 0; i < n_items - 1; i++) { 1379 ath10k_dbg(ar, ATH10K_DBG_PCI, 1380 "pci tx item %d paddr %pad len %d n_items %d\n", 1381 i, &items[i].paddr, items[i].len, n_items); 1382 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1383 items[i].vaddr, items[i].len); 1384 1385 err = ath10k_ce_send_nolock(ce_pipe, 1386 items[i].transfer_context, 1387 items[i].paddr, 1388 items[i].len, 1389 items[i].transfer_id, 1390 CE_SEND_FLAG_GATHER); 1391 if (err) 1392 goto err; 1393 } 1394 1395 /* `i` is equal to `n_items -1` after for() */ 1396 1397 ath10k_dbg(ar, ATH10K_DBG_PCI, 1398 "pci tx item %d paddr %pad len %d n_items %d\n", 1399 i, &items[i].paddr, items[i].len, n_items); 1400 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1401 items[i].vaddr, items[i].len); 1402 1403 err = ath10k_ce_send_nolock(ce_pipe, 1404 items[i].transfer_context, 1405 items[i].paddr, 1406 items[i].len, 1407 items[i].transfer_id, 1408 0); 1409 if (err) 1410 goto err; 1411 1412 spin_unlock_bh(&ce->ce_lock); 1413 return 0; 1414 1415 err: 1416 for (; i > 0; i--) 1417 __ath10k_ce_send_revert(ce_pipe); 1418 1419 spin_unlock_bh(&ce->ce_lock); 1420 return err; 1421 } 1422 1423 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, 1424 size_t buf_len) 1425 { 1426 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); 1427 } 1428 1429 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 1430 { 1431 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1432 1433 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); 1434 1435 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); 1436 } 1437 1438 static void ath10k_pci_dump_registers(struct ath10k *ar, 1439 struct ath10k_fw_crash_data *crash_data) 1440 { 1441 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; 1442 int i, ret; 1443 1444 lockdep_assert_held(&ar->data_lock); 1445 1446 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], 1447 hi_failure_state, 1448 REG_DUMP_COUNT_QCA988X * sizeof(__le32)); 1449 if (ret) { 1450 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); 1451 return; 1452 } 1453 1454 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); 1455 1456 ath10k_err(ar, "firmware register dump:\n"); 1457 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) 1458 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", 1459 i, 1460 __le32_to_cpu(reg_dump_values[i]), 1461 __le32_to_cpu(reg_dump_values[i + 1]), 1462 __le32_to_cpu(reg_dump_values[i + 2]), 1463 __le32_to_cpu(reg_dump_values[i + 3])); 1464 1465 if (!crash_data) 1466 return; 1467 1468 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) 1469 crash_data->registers[i] = reg_dump_values[i]; 1470 } 1471 1472 static int ath10k_pci_dump_memory_section(struct ath10k *ar, 1473 const struct ath10k_mem_region *mem_region, 1474 u8 *buf, size_t buf_len) 1475 { 1476 const struct ath10k_mem_section *cur_section, *next_section; 1477 unsigned int count, section_size, skip_size; 1478 int ret, i, j; 1479 1480 if (!mem_region || !buf) 1481 return 0; 1482 1483 cur_section = &mem_region->section_table.sections[0]; 1484 1485 if (mem_region->start > cur_section->start) { 1486 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n", 1487 mem_region->start, cur_section->start); 1488 return 0; 1489 } 1490 1491 skip_size = cur_section->start - mem_region->start; 1492 1493 /* fill the gap between the first register section and register 1494 * start address 1495 */ 1496 for (i = 0; i < skip_size; i++) { 1497 *buf = ATH10K_MAGIC_NOT_COPIED; 1498 buf++; 1499 } 1500 1501 count = 0; 1502 1503 for (i = 0; cur_section != NULL; i++) { 1504 section_size = cur_section->end - cur_section->start; 1505 1506 if (section_size <= 0) { 1507 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n", 1508 cur_section->start, 1509 cur_section->end); 1510 break; 1511 } 1512 1513 if ((i + 1) == mem_region->section_table.size) { 1514 /* last section */ 1515 next_section = NULL; 1516 skip_size = 0; 1517 } else { 1518 next_section = cur_section + 1; 1519 1520 if (cur_section->end > next_section->start) { 1521 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n", 1522 next_section->start, 1523 cur_section->end); 1524 break; 1525 } 1526 1527 skip_size = next_section->start - cur_section->end; 1528 } 1529 1530 if (buf_len < (skip_size + section_size)) { 1531 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len); 1532 break; 1533 } 1534 1535 buf_len -= skip_size + section_size; 1536 1537 /* read section to dest memory */ 1538 ret = ath10k_pci_diag_read_mem(ar, cur_section->start, 1539 buf, section_size); 1540 if (ret) { 1541 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n", 1542 cur_section->start, ret); 1543 break; 1544 } 1545 1546 buf += section_size; 1547 count += section_size; 1548 1549 /* fill in the gap between this section and the next */ 1550 for (j = 0; j < skip_size; j++) { 1551 *buf = ATH10K_MAGIC_NOT_COPIED; 1552 buf++; 1553 } 1554 1555 count += skip_size; 1556 1557 if (!next_section) 1558 /* this was the last section */ 1559 break; 1560 1561 cur_section = next_section; 1562 } 1563 1564 return count; 1565 } 1566 1567 static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config) 1568 { 1569 u32 val; 1570 1571 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1572 FW_RAM_CONFIG_ADDRESS, config); 1573 1574 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1575 FW_RAM_CONFIG_ADDRESS); 1576 if (val != config) { 1577 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n", 1578 val, config); 1579 return -EIO; 1580 } 1581 1582 return 0; 1583 } 1584 1585 /* if an error happened returns < 0, otherwise the length */ 1586 static int ath10k_pci_dump_memory_sram(struct ath10k *ar, 1587 const struct ath10k_mem_region *region, 1588 u8 *buf) 1589 { 1590 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1591 u32 base_addr, i; 1592 1593 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG); 1594 base_addr += region->start; 1595 1596 for (i = 0; i < region->len; i += 4) { 1597 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG); 1598 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG); 1599 } 1600 1601 return region->len; 1602 } 1603 1604 /* if an error happened returns < 0, otherwise the length */ 1605 static int ath10k_pci_dump_memory_reg(struct ath10k *ar, 1606 const struct ath10k_mem_region *region, 1607 u8 *buf) 1608 { 1609 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1610 u32 i; 1611 1612 for (i = 0; i < region->len; i += 4) 1613 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i); 1614 1615 return region->len; 1616 } 1617 1618 /* if an error happened returns < 0, otherwise the length */ 1619 static int ath10k_pci_dump_memory_generic(struct ath10k *ar, 1620 const struct ath10k_mem_region *current_region, 1621 u8 *buf) 1622 { 1623 int ret; 1624 1625 if (current_region->section_table.size > 0) 1626 /* Copy each section individually. */ 1627 return ath10k_pci_dump_memory_section(ar, 1628 current_region, 1629 buf, 1630 current_region->len); 1631 1632 /* No individiual memory sections defined so we can 1633 * copy the entire memory region. 1634 */ 1635 ret = ath10k_pci_diag_read_mem(ar, 1636 current_region->start, 1637 buf, 1638 current_region->len); 1639 if (ret) { 1640 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n", 1641 current_region->name, ret); 1642 return ret; 1643 } 1644 1645 return current_region->len; 1646 } 1647 1648 static void ath10k_pci_dump_memory(struct ath10k *ar, 1649 struct ath10k_fw_crash_data *crash_data) 1650 { 1651 const struct ath10k_hw_mem_layout *mem_layout; 1652 const struct ath10k_mem_region *current_region; 1653 struct ath10k_dump_ram_data_hdr *hdr; 1654 u32 count, shift; 1655 size_t buf_len; 1656 int ret, i; 1657 u8 *buf; 1658 1659 lockdep_assert_held(&ar->data_lock); 1660 1661 if (!crash_data) 1662 return; 1663 1664 mem_layout = ath10k_coredump_get_mem_layout(ar); 1665 if (!mem_layout) 1666 return; 1667 1668 current_region = &mem_layout->region_table.regions[0]; 1669 1670 buf = crash_data->ramdump_buf; 1671 buf_len = crash_data->ramdump_buf_len; 1672 1673 memset(buf, 0, buf_len); 1674 1675 for (i = 0; i < mem_layout->region_table.size; i++) { 1676 count = 0; 1677 1678 if (current_region->len > buf_len) { 1679 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n", 1680 current_region->name, 1681 current_region->len, 1682 buf_len); 1683 break; 1684 } 1685 1686 /* To get IRAM dump, the host driver needs to switch target 1687 * ram config from DRAM to IRAM. 1688 */ 1689 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 || 1690 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) { 1691 shift = current_region->start >> 20; 1692 1693 ret = ath10k_pci_set_ram_config(ar, shift); 1694 if (ret) { 1695 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n", 1696 current_region->name, ret); 1697 break; 1698 } 1699 } 1700 1701 /* Reserve space for the header. */ 1702 hdr = (void *)buf; 1703 buf += sizeof(*hdr); 1704 buf_len -= sizeof(*hdr); 1705 1706 switch (current_region->type) { 1707 case ATH10K_MEM_REGION_TYPE_IOSRAM: 1708 count = ath10k_pci_dump_memory_sram(ar, current_region, buf); 1709 break; 1710 case ATH10K_MEM_REGION_TYPE_IOREG: 1711 count = ath10k_pci_dump_memory_reg(ar, current_region, buf); 1712 break; 1713 default: 1714 ret = ath10k_pci_dump_memory_generic(ar, current_region, buf); 1715 if (ret < 0) 1716 break; 1717 1718 count = ret; 1719 break; 1720 } 1721 1722 hdr->region_type = cpu_to_le32(current_region->type); 1723 hdr->start = cpu_to_le32(current_region->start); 1724 hdr->length = cpu_to_le32(count); 1725 1726 if (count == 0) 1727 /* Note: the header remains, just with zero length. */ 1728 break; 1729 1730 buf += count; 1731 buf_len -= count; 1732 1733 current_region++; 1734 } 1735 } 1736 1737 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) 1738 { 1739 struct ath10k_fw_crash_data *crash_data; 1740 char guid[UUID_STRING_LEN + 1]; 1741 1742 spin_lock_bh(&ar->data_lock); 1743 1744 ar->stats.fw_crash_counter++; 1745 1746 crash_data = ath10k_coredump_new(ar); 1747 1748 if (crash_data) 1749 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); 1750 else 1751 scnprintf(guid, sizeof(guid), "n/a"); 1752 1753 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid); 1754 ath10k_print_driver_info(ar); 1755 ath10k_pci_dump_registers(ar, crash_data); 1756 ath10k_ce_dump_registers(ar, crash_data); 1757 ath10k_pci_dump_memory(ar, crash_data); 1758 1759 spin_unlock_bh(&ar->data_lock); 1760 1761 queue_work(ar->workqueue, &ar->restart_work); 1762 } 1763 1764 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, 1765 int force) 1766 { 1767 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); 1768 1769 if (!force) { 1770 int resources; 1771 /* 1772 * Decide whether to actually poll for completions, or just 1773 * wait for a later chance. 1774 * If there seem to be plenty of resources left, then just wait 1775 * since checking involves reading a CE register, which is a 1776 * relatively expensive operation. 1777 */ 1778 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); 1779 1780 /* 1781 * If at least 50% of the total resources are still available, 1782 * don't bother checking again yet. 1783 */ 1784 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1)) 1785 return; 1786 } 1787 ath10k_ce_per_engine_service(ar, pipe); 1788 } 1789 1790 static void ath10k_pci_rx_retry_sync(struct ath10k *ar) 1791 { 1792 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1793 1794 del_timer_sync(&ar_pci->rx_post_retry); 1795 } 1796 1797 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, 1798 u8 *ul_pipe, u8 *dl_pipe) 1799 { 1800 const struct service_to_pipe *entry; 1801 bool ul_set = false, dl_set = false; 1802 int i; 1803 1804 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); 1805 1806 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { 1807 entry = &target_service_to_ce_map_wlan[i]; 1808 1809 if (__le32_to_cpu(entry->service_id) != service_id) 1810 continue; 1811 1812 switch (__le32_to_cpu(entry->pipedir)) { 1813 case PIPEDIR_NONE: 1814 break; 1815 case PIPEDIR_IN: 1816 WARN_ON(dl_set); 1817 *dl_pipe = __le32_to_cpu(entry->pipenum); 1818 dl_set = true; 1819 break; 1820 case PIPEDIR_OUT: 1821 WARN_ON(ul_set); 1822 *ul_pipe = __le32_to_cpu(entry->pipenum); 1823 ul_set = true; 1824 break; 1825 case PIPEDIR_INOUT: 1826 WARN_ON(dl_set); 1827 WARN_ON(ul_set); 1828 *dl_pipe = __le32_to_cpu(entry->pipenum); 1829 *ul_pipe = __le32_to_cpu(entry->pipenum); 1830 dl_set = true; 1831 ul_set = true; 1832 break; 1833 } 1834 } 1835 1836 if (!ul_set || !dl_set) 1837 return -ENOENT; 1838 1839 return 0; 1840 } 1841 1842 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, 1843 u8 *ul_pipe, u8 *dl_pipe) 1844 { 1845 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); 1846 1847 (void)ath10k_pci_hif_map_service_to_pipe(ar, 1848 ATH10K_HTC_SVC_ID_RSVD_CTRL, 1849 ul_pipe, dl_pipe); 1850 } 1851 1852 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) 1853 { 1854 u32 val; 1855 1856 switch (ar->hw_rev) { 1857 case ATH10K_HW_QCA988X: 1858 case ATH10K_HW_QCA9887: 1859 case ATH10K_HW_QCA6174: 1860 case ATH10K_HW_QCA9377: 1861 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1862 CORE_CTRL_ADDRESS); 1863 val &= ~CORE_CTRL_PCIE_REG_31_MASK; 1864 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1865 CORE_CTRL_ADDRESS, val); 1866 break; 1867 case ATH10K_HW_QCA99X0: 1868 case ATH10K_HW_QCA9984: 1869 case ATH10K_HW_QCA9888: 1870 case ATH10K_HW_QCA4019: 1871 /* TODO: Find appropriate register configuration for QCA99X0 1872 * to mask irq/MSI. 1873 */ 1874 break; 1875 case ATH10K_HW_WCN3990: 1876 break; 1877 } 1878 } 1879 1880 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) 1881 { 1882 u32 val; 1883 1884 switch (ar->hw_rev) { 1885 case ATH10K_HW_QCA988X: 1886 case ATH10K_HW_QCA9887: 1887 case ATH10K_HW_QCA6174: 1888 case ATH10K_HW_QCA9377: 1889 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1890 CORE_CTRL_ADDRESS); 1891 val |= CORE_CTRL_PCIE_REG_31_MASK; 1892 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1893 CORE_CTRL_ADDRESS, val); 1894 break; 1895 case ATH10K_HW_QCA99X0: 1896 case ATH10K_HW_QCA9984: 1897 case ATH10K_HW_QCA9888: 1898 case ATH10K_HW_QCA4019: 1899 /* TODO: Find appropriate register configuration for QCA99X0 1900 * to unmask irq/MSI. 1901 */ 1902 break; 1903 case ATH10K_HW_WCN3990: 1904 break; 1905 } 1906 } 1907 1908 static void ath10k_pci_irq_disable(struct ath10k *ar) 1909 { 1910 ath10k_ce_disable_interrupts(ar); 1911 ath10k_pci_disable_and_clear_legacy_irq(ar); 1912 ath10k_pci_irq_msi_fw_mask(ar); 1913 } 1914 1915 static void ath10k_pci_irq_sync(struct ath10k *ar) 1916 { 1917 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1918 1919 synchronize_irq(ar_pci->pdev->irq); 1920 } 1921 1922 static void ath10k_pci_irq_enable(struct ath10k *ar) 1923 { 1924 ath10k_ce_enable_interrupts(ar); 1925 ath10k_pci_enable_legacy_irq(ar); 1926 ath10k_pci_irq_msi_fw_unmask(ar); 1927 } 1928 1929 static int ath10k_pci_hif_start(struct ath10k *ar) 1930 { 1931 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1932 1933 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 1934 1935 napi_enable(&ar->napi); 1936 1937 ath10k_pci_irq_enable(ar); 1938 ath10k_pci_rx_post(ar); 1939 1940 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 1941 ar_pci->link_ctl); 1942 1943 return 0; 1944 } 1945 1946 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1947 { 1948 struct ath10k *ar; 1949 struct ath10k_ce_pipe *ce_pipe; 1950 struct ath10k_ce_ring *ce_ring; 1951 struct sk_buff *skb; 1952 int i; 1953 1954 ar = pci_pipe->hif_ce_state; 1955 ce_pipe = pci_pipe->ce_hdl; 1956 ce_ring = ce_pipe->dest_ring; 1957 1958 if (!ce_ring) 1959 return; 1960 1961 if (!pci_pipe->buf_sz) 1962 return; 1963 1964 for (i = 0; i < ce_ring->nentries; i++) { 1965 skb = ce_ring->per_transfer_context[i]; 1966 if (!skb) 1967 continue; 1968 1969 ce_ring->per_transfer_context[i] = NULL; 1970 1971 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1972 skb->len + skb_tailroom(skb), 1973 DMA_FROM_DEVICE); 1974 dev_kfree_skb_any(skb); 1975 } 1976 } 1977 1978 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1979 { 1980 struct ath10k *ar; 1981 struct ath10k_ce_pipe *ce_pipe; 1982 struct ath10k_ce_ring *ce_ring; 1983 struct sk_buff *skb; 1984 int i; 1985 1986 ar = pci_pipe->hif_ce_state; 1987 ce_pipe = pci_pipe->ce_hdl; 1988 ce_ring = ce_pipe->src_ring; 1989 1990 if (!ce_ring) 1991 return; 1992 1993 if (!pci_pipe->buf_sz) 1994 return; 1995 1996 for (i = 0; i < ce_ring->nentries; i++) { 1997 skb = ce_ring->per_transfer_context[i]; 1998 if (!skb) 1999 continue; 2000 2001 ce_ring->per_transfer_context[i] = NULL; 2002 2003 ath10k_htc_tx_completion_handler(ar, skb); 2004 } 2005 } 2006 2007 /* 2008 * Cleanup residual buffers for device shutdown: 2009 * buffers that were enqueued for receive 2010 * buffers that were to be sent 2011 * Note: Buffers that had completed but which were 2012 * not yet processed are on a completion queue. They 2013 * are handled when the completion thread shuts down. 2014 */ 2015 static void ath10k_pci_buffer_cleanup(struct ath10k *ar) 2016 { 2017 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2018 int pipe_num; 2019 2020 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 2021 struct ath10k_pci_pipe *pipe_info; 2022 2023 pipe_info = &ar_pci->pipe_info[pipe_num]; 2024 ath10k_pci_rx_pipe_cleanup(pipe_info); 2025 ath10k_pci_tx_pipe_cleanup(pipe_info); 2026 } 2027 } 2028 2029 void ath10k_pci_ce_deinit(struct ath10k *ar) 2030 { 2031 int i; 2032 2033 for (i = 0; i < CE_COUNT; i++) 2034 ath10k_ce_deinit_pipe(ar, i); 2035 } 2036 2037 void ath10k_pci_flush(struct ath10k *ar) 2038 { 2039 ath10k_pci_rx_retry_sync(ar); 2040 ath10k_pci_buffer_cleanup(ar); 2041 } 2042 2043 static void ath10k_pci_hif_stop(struct ath10k *ar) 2044 { 2045 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2046 unsigned long flags; 2047 2048 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 2049 2050 /* Most likely the device has HTT Rx ring configured. The only way to 2051 * prevent the device from accessing (and possible corrupting) host 2052 * memory is to reset the chip now. 2053 * 2054 * There's also no known way of masking MSI interrupts on the device. 2055 * For ranged MSI the CE-related interrupts can be masked. However 2056 * regardless how many MSI interrupts are assigned the first one 2057 * is always used for firmware indications (crashes) and cannot be 2058 * masked. To prevent the device from asserting the interrupt reset it 2059 * before proceeding with cleanup. 2060 */ 2061 ath10k_pci_safe_chip_reset(ar); 2062 2063 ath10k_pci_irq_disable(ar); 2064 ath10k_pci_irq_sync(ar); 2065 napi_synchronize(&ar->napi); 2066 napi_disable(&ar->napi); 2067 ath10k_pci_flush(ar); 2068 2069 spin_lock_irqsave(&ar_pci->ps_lock, flags); 2070 WARN_ON(ar_pci->ps_wake_refcount > 0); 2071 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 2072 } 2073 2074 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, 2075 void *req, u32 req_len, 2076 void *resp, u32 *resp_len) 2077 { 2078 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2079 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; 2080 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; 2081 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; 2082 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; 2083 dma_addr_t req_paddr = 0; 2084 dma_addr_t resp_paddr = 0; 2085 struct bmi_xfer xfer = {}; 2086 void *treq, *tresp = NULL; 2087 int ret = 0; 2088 2089 might_sleep(); 2090 2091 if (resp && !resp_len) 2092 return -EINVAL; 2093 2094 if (resp && resp_len && *resp_len == 0) 2095 return -EINVAL; 2096 2097 treq = kmemdup(req, req_len, GFP_KERNEL); 2098 if (!treq) 2099 return -ENOMEM; 2100 2101 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); 2102 ret = dma_mapping_error(ar->dev, req_paddr); 2103 if (ret) { 2104 ret = -EIO; 2105 goto err_dma; 2106 } 2107 2108 if (resp && resp_len) { 2109 tresp = kzalloc(*resp_len, GFP_KERNEL); 2110 if (!tresp) { 2111 ret = -ENOMEM; 2112 goto err_req; 2113 } 2114 2115 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, 2116 DMA_FROM_DEVICE); 2117 ret = dma_mapping_error(ar->dev, resp_paddr); 2118 if (ret) { 2119 ret = -EIO; 2120 goto err_req; 2121 } 2122 2123 xfer.wait_for_resp = true; 2124 xfer.resp_len = 0; 2125 2126 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); 2127 } 2128 2129 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); 2130 if (ret) 2131 goto err_resp; 2132 2133 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer); 2134 if (ret) { 2135 dma_addr_t unused_buffer; 2136 unsigned int unused_nbytes; 2137 unsigned int unused_id; 2138 2139 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, 2140 &unused_nbytes, &unused_id); 2141 } else { 2142 /* non-zero means we did not time out */ 2143 ret = 0; 2144 } 2145 2146 err_resp: 2147 if (resp) { 2148 dma_addr_t unused_buffer; 2149 2150 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); 2151 dma_unmap_single(ar->dev, resp_paddr, 2152 *resp_len, DMA_FROM_DEVICE); 2153 } 2154 err_req: 2155 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); 2156 2157 if (ret == 0 && resp_len) { 2158 *resp_len = min(*resp_len, xfer.resp_len); 2159 memcpy(resp, tresp, xfer.resp_len); 2160 } 2161 err_dma: 2162 kfree(treq); 2163 kfree(tresp); 2164 2165 return ret; 2166 } 2167 2168 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) 2169 { 2170 struct bmi_xfer *xfer; 2171 2172 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer)) 2173 return; 2174 2175 xfer->tx_done = true; 2176 } 2177 2178 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) 2179 { 2180 struct ath10k *ar = ce_state->ar; 2181 struct bmi_xfer *xfer; 2182 unsigned int nbytes; 2183 2184 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, 2185 &nbytes)) 2186 return; 2187 2188 if (WARN_ON_ONCE(!xfer)) 2189 return; 2190 2191 if (!xfer->wait_for_resp) { 2192 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); 2193 return; 2194 } 2195 2196 xfer->resp_len = nbytes; 2197 xfer->rx_done = true; 2198 } 2199 2200 static int ath10k_pci_bmi_wait(struct ath10k *ar, 2201 struct ath10k_ce_pipe *tx_pipe, 2202 struct ath10k_ce_pipe *rx_pipe, 2203 struct bmi_xfer *xfer) 2204 { 2205 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; 2206 unsigned long started = jiffies; 2207 unsigned long dur; 2208 int ret; 2209 2210 while (time_before_eq(jiffies, timeout)) { 2211 ath10k_pci_bmi_send_done(tx_pipe); 2212 ath10k_pci_bmi_recv_data(rx_pipe); 2213 2214 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) { 2215 ret = 0; 2216 goto out; 2217 } 2218 2219 schedule(); 2220 } 2221 2222 ret = -ETIMEDOUT; 2223 2224 out: 2225 dur = jiffies - started; 2226 if (dur > HZ) 2227 ath10k_dbg(ar, ATH10K_DBG_BMI, 2228 "bmi cmd took %lu jiffies hz %d ret %d\n", 2229 dur, HZ, ret); 2230 return ret; 2231 } 2232 2233 /* 2234 * Send an interrupt to the device to wake up the Target CPU 2235 * so it has an opportunity to notice any changed state. 2236 */ 2237 static int ath10k_pci_wake_target_cpu(struct ath10k *ar) 2238 { 2239 u32 addr, val; 2240 2241 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS; 2242 val = ath10k_pci_read32(ar, addr); 2243 val |= CORE_CTRL_CPU_INTR_MASK; 2244 ath10k_pci_write32(ar, addr, val); 2245 2246 return 0; 2247 } 2248 2249 static int ath10k_pci_get_num_banks(struct ath10k *ar) 2250 { 2251 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2252 2253 switch (ar_pci->pdev->device) { 2254 case QCA988X_2_0_DEVICE_ID_UBNT: 2255 case QCA988X_2_0_DEVICE_ID: 2256 case QCA99X0_2_0_DEVICE_ID: 2257 case QCA9888_2_0_DEVICE_ID: 2258 case QCA9984_1_0_DEVICE_ID: 2259 case QCA9887_1_0_DEVICE_ID: 2260 return 1; 2261 case QCA6164_2_1_DEVICE_ID: 2262 case QCA6174_2_1_DEVICE_ID: 2263 switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) { 2264 case QCA6174_HW_1_0_CHIP_ID_REV: 2265 case QCA6174_HW_1_1_CHIP_ID_REV: 2266 case QCA6174_HW_2_1_CHIP_ID_REV: 2267 case QCA6174_HW_2_2_CHIP_ID_REV: 2268 return 3; 2269 case QCA6174_HW_1_3_CHIP_ID_REV: 2270 return 2; 2271 case QCA6174_HW_3_0_CHIP_ID_REV: 2272 case QCA6174_HW_3_1_CHIP_ID_REV: 2273 case QCA6174_HW_3_2_CHIP_ID_REV: 2274 return 9; 2275 } 2276 break; 2277 case QCA9377_1_0_DEVICE_ID: 2278 return 9; 2279 } 2280 2281 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 2282 return 1; 2283 } 2284 2285 static int ath10k_bus_get_num_banks(struct ath10k *ar) 2286 { 2287 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2288 2289 return ce->bus_ops->get_num_banks(ar); 2290 } 2291 2292 int ath10k_pci_init_config(struct ath10k *ar) 2293 { 2294 u32 interconnect_targ_addr; 2295 u32 pcie_state_targ_addr = 0; 2296 u32 pipe_cfg_targ_addr = 0; 2297 u32 svc_to_pipe_map = 0; 2298 u32 pcie_config_flags = 0; 2299 u32 ealloc_value; 2300 u32 ealloc_targ_addr; 2301 u32 flag2_value; 2302 u32 flag2_targ_addr; 2303 int ret = 0; 2304 2305 /* Download to Target the CE Config and the service-to-CE map */ 2306 interconnect_targ_addr = 2307 host_interest_item_address(HI_ITEM(hi_interconnect_state)); 2308 2309 /* Supply Target-side CE configuration */ 2310 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, 2311 &pcie_state_targ_addr); 2312 if (ret != 0) { 2313 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); 2314 return ret; 2315 } 2316 2317 if (pcie_state_targ_addr == 0) { 2318 ret = -EIO; 2319 ath10k_err(ar, "Invalid pcie state addr\n"); 2320 return ret; 2321 } 2322 2323 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2324 offsetof(struct pcie_state, 2325 pipe_cfg_addr)), 2326 &pipe_cfg_targ_addr); 2327 if (ret != 0) { 2328 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); 2329 return ret; 2330 } 2331 2332 if (pipe_cfg_targ_addr == 0) { 2333 ret = -EIO; 2334 ath10k_err(ar, "Invalid pipe cfg addr\n"); 2335 return ret; 2336 } 2337 2338 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, 2339 target_ce_config_wlan, 2340 sizeof(struct ce_pipe_config) * 2341 NUM_TARGET_CE_CONFIG_WLAN); 2342 2343 if (ret != 0) { 2344 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); 2345 return ret; 2346 } 2347 2348 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2349 offsetof(struct pcie_state, 2350 svc_to_pipe_map)), 2351 &svc_to_pipe_map); 2352 if (ret != 0) { 2353 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); 2354 return ret; 2355 } 2356 2357 if (svc_to_pipe_map == 0) { 2358 ret = -EIO; 2359 ath10k_err(ar, "Invalid svc_to_pipe map\n"); 2360 return ret; 2361 } 2362 2363 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, 2364 target_service_to_ce_map_wlan, 2365 sizeof(target_service_to_ce_map_wlan)); 2366 if (ret != 0) { 2367 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); 2368 return ret; 2369 } 2370 2371 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2372 offsetof(struct pcie_state, 2373 config_flags)), 2374 &pcie_config_flags); 2375 if (ret != 0) { 2376 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); 2377 return ret; 2378 } 2379 2380 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; 2381 2382 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + 2383 offsetof(struct pcie_state, 2384 config_flags)), 2385 pcie_config_flags); 2386 if (ret != 0) { 2387 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); 2388 return ret; 2389 } 2390 2391 /* configure early allocation */ 2392 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); 2393 2394 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); 2395 if (ret != 0) { 2396 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret); 2397 return ret; 2398 } 2399 2400 /* first bank is switched to IRAM */ 2401 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & 2402 HI_EARLY_ALLOC_MAGIC_MASK); 2403 ealloc_value |= ((ath10k_bus_get_num_banks(ar) << 2404 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & 2405 HI_EARLY_ALLOC_IRAM_BANKS_MASK); 2406 2407 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); 2408 if (ret != 0) { 2409 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); 2410 return ret; 2411 } 2412 2413 /* Tell Target to proceed with initialization */ 2414 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); 2415 2416 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); 2417 if (ret != 0) { 2418 ath10k_err(ar, "Failed to get option val: %d\n", ret); 2419 return ret; 2420 } 2421 2422 flag2_value |= HI_OPTION_EARLY_CFG_DONE; 2423 2424 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); 2425 if (ret != 0) { 2426 ath10k_err(ar, "Failed to set option val: %d\n", ret); 2427 return ret; 2428 } 2429 2430 return 0; 2431 } 2432 2433 static void ath10k_pci_override_ce_config(struct ath10k *ar) 2434 { 2435 struct ce_attr *attr; 2436 struct ce_pipe_config *config; 2437 2438 /* For QCA6174 we're overriding the Copy Engine 5 configuration, 2439 * since it is currently used for other feature. 2440 */ 2441 2442 /* Override Host's Copy Engine 5 configuration */ 2443 attr = &host_ce_config_wlan[5]; 2444 attr->src_sz_max = 0; 2445 attr->dest_nentries = 0; 2446 2447 /* Override Target firmware's Copy Engine configuration */ 2448 config = &target_ce_config_wlan[5]; 2449 config->pipedir = __cpu_to_le32(PIPEDIR_OUT); 2450 config->nbytes_max = __cpu_to_le32(2048); 2451 2452 /* Map from service/endpoint to Copy Engine */ 2453 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1); 2454 } 2455 2456 int ath10k_pci_alloc_pipes(struct ath10k *ar) 2457 { 2458 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2459 struct ath10k_pci_pipe *pipe; 2460 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2461 int i, ret; 2462 2463 for (i = 0; i < CE_COUNT; i++) { 2464 pipe = &ar_pci->pipe_info[i]; 2465 pipe->ce_hdl = &ce->ce_states[i]; 2466 pipe->pipe_num = i; 2467 pipe->hif_ce_state = ar; 2468 2469 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]); 2470 if (ret) { 2471 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 2472 i, ret); 2473 return ret; 2474 } 2475 2476 /* Last CE is Diagnostic Window */ 2477 if (i == CE_DIAG_PIPE) { 2478 ar_pci->ce_diag = pipe->ce_hdl; 2479 continue; 2480 } 2481 2482 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max); 2483 } 2484 2485 return 0; 2486 } 2487 2488 void ath10k_pci_free_pipes(struct ath10k *ar) 2489 { 2490 int i; 2491 2492 for (i = 0; i < CE_COUNT; i++) 2493 ath10k_ce_free_pipe(ar, i); 2494 } 2495 2496 int ath10k_pci_init_pipes(struct ath10k *ar) 2497 { 2498 int i, ret; 2499 2500 for (i = 0; i < CE_COUNT; i++) { 2501 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]); 2502 if (ret) { 2503 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 2504 i, ret); 2505 return ret; 2506 } 2507 } 2508 2509 return 0; 2510 } 2511 2512 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) 2513 { 2514 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & 2515 FW_IND_EVENT_PENDING; 2516 } 2517 2518 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) 2519 { 2520 u32 val; 2521 2522 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2523 val &= ~FW_IND_EVENT_PENDING; 2524 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); 2525 } 2526 2527 static bool ath10k_pci_has_device_gone(struct ath10k *ar) 2528 { 2529 u32 val; 2530 2531 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2532 return (val == 0xffffffff); 2533 } 2534 2535 /* this function effectively clears target memory controller assert line */ 2536 static void ath10k_pci_warm_reset_si0(struct ath10k *ar) 2537 { 2538 u32 val; 2539 2540 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2541 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2542 val | SOC_RESET_CONTROL_SI0_RST_MASK); 2543 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2544 2545 msleep(10); 2546 2547 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2548 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2549 val & ~SOC_RESET_CONTROL_SI0_RST_MASK); 2550 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2551 2552 msleep(10); 2553 } 2554 2555 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) 2556 { 2557 u32 val; 2558 2559 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); 2560 2561 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2562 SOC_RESET_CONTROL_ADDRESS); 2563 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2564 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); 2565 } 2566 2567 static void ath10k_pci_warm_reset_ce(struct ath10k *ar) 2568 { 2569 u32 val; 2570 2571 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2572 SOC_RESET_CONTROL_ADDRESS); 2573 2574 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2575 val | SOC_RESET_CONTROL_CE_RST_MASK); 2576 msleep(10); 2577 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2578 val & ~SOC_RESET_CONTROL_CE_RST_MASK); 2579 } 2580 2581 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) 2582 { 2583 u32 val; 2584 2585 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2586 SOC_LF_TIMER_CONTROL0_ADDRESS); 2587 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + 2588 SOC_LF_TIMER_CONTROL0_ADDRESS, 2589 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); 2590 } 2591 2592 static int ath10k_pci_warm_reset(struct ath10k *ar) 2593 { 2594 int ret; 2595 2596 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); 2597 2598 spin_lock_bh(&ar->data_lock); 2599 ar->stats.fw_warm_reset_counter++; 2600 spin_unlock_bh(&ar->data_lock); 2601 2602 ath10k_pci_irq_disable(ar); 2603 2604 /* Make sure the target CPU is not doing anything dangerous, e.g. if it 2605 * were to access copy engine while host performs copy engine reset 2606 * then it is possible for the device to confuse pci-e controller to 2607 * the point of bringing host system to a complete stop (i.e. hang). 2608 */ 2609 ath10k_pci_warm_reset_si0(ar); 2610 ath10k_pci_warm_reset_cpu(ar); 2611 ath10k_pci_init_pipes(ar); 2612 ath10k_pci_wait_for_target_init(ar); 2613 2614 ath10k_pci_warm_reset_clear_lf(ar); 2615 ath10k_pci_warm_reset_ce(ar); 2616 ath10k_pci_warm_reset_cpu(ar); 2617 ath10k_pci_init_pipes(ar); 2618 2619 ret = ath10k_pci_wait_for_target_init(ar); 2620 if (ret) { 2621 ath10k_warn(ar, "failed to wait for target init: %d\n", ret); 2622 return ret; 2623 } 2624 2625 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); 2626 2627 return 0; 2628 } 2629 2630 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) 2631 { 2632 ath10k_pci_irq_disable(ar); 2633 return ath10k_pci_qca99x0_chip_reset(ar); 2634 } 2635 2636 static int ath10k_pci_safe_chip_reset(struct ath10k *ar) 2637 { 2638 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2639 2640 if (!ar_pci->pci_soft_reset) 2641 return -ENOTSUPP; 2642 2643 return ar_pci->pci_soft_reset(ar); 2644 } 2645 2646 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) 2647 { 2648 int i, ret; 2649 u32 val; 2650 2651 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); 2652 2653 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. 2654 * It is thus preferred to use warm reset which is safer but may not be 2655 * able to recover the device from all possible fail scenarios. 2656 * 2657 * Warm reset doesn't always work on first try so attempt it a few 2658 * times before giving up. 2659 */ 2660 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { 2661 ret = ath10k_pci_warm_reset(ar); 2662 if (ret) { 2663 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", 2664 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, 2665 ret); 2666 continue; 2667 } 2668 2669 /* FIXME: Sometimes copy engine doesn't recover after warm 2670 * reset. In most cases this needs cold reset. In some of these 2671 * cases the device is in such a state that a cold reset may 2672 * lock up the host. 2673 * 2674 * Reading any host interest register via copy engine is 2675 * sufficient to verify if device is capable of booting 2676 * firmware blob. 2677 */ 2678 ret = ath10k_pci_init_pipes(ar); 2679 if (ret) { 2680 ath10k_warn(ar, "failed to init copy engine: %d\n", 2681 ret); 2682 continue; 2683 } 2684 2685 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, 2686 &val); 2687 if (ret) { 2688 ath10k_warn(ar, "failed to poke copy engine: %d\n", 2689 ret); 2690 continue; 2691 } 2692 2693 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); 2694 return 0; 2695 } 2696 2697 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { 2698 ath10k_warn(ar, "refusing cold reset as requested\n"); 2699 return -EPERM; 2700 } 2701 2702 ret = ath10k_pci_cold_reset(ar); 2703 if (ret) { 2704 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2705 return ret; 2706 } 2707 2708 ret = ath10k_pci_wait_for_target_init(ar); 2709 if (ret) { 2710 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2711 ret); 2712 return ret; 2713 } 2714 2715 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); 2716 2717 return 0; 2718 } 2719 2720 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) 2721 { 2722 int ret; 2723 2724 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); 2725 2726 /* FIXME: QCA6174 requires cold + warm reset to work. */ 2727 2728 ret = ath10k_pci_cold_reset(ar); 2729 if (ret) { 2730 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2731 return ret; 2732 } 2733 2734 ret = ath10k_pci_wait_for_target_init(ar); 2735 if (ret) { 2736 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2737 ret); 2738 return ret; 2739 } 2740 2741 ret = ath10k_pci_warm_reset(ar); 2742 if (ret) { 2743 ath10k_warn(ar, "failed to warm reset: %d\n", ret); 2744 return ret; 2745 } 2746 2747 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); 2748 2749 return 0; 2750 } 2751 2752 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) 2753 { 2754 int ret; 2755 2756 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n"); 2757 2758 ret = ath10k_pci_cold_reset(ar); 2759 if (ret) { 2760 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2761 return ret; 2762 } 2763 2764 ret = ath10k_pci_wait_for_target_init(ar); 2765 if (ret) { 2766 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2767 ret); 2768 return ret; 2769 } 2770 2771 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n"); 2772 2773 return 0; 2774 } 2775 2776 static int ath10k_pci_chip_reset(struct ath10k *ar) 2777 { 2778 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2779 2780 if (WARN_ON(!ar_pci->pci_hard_reset)) 2781 return -ENOTSUPP; 2782 2783 return ar_pci->pci_hard_reset(ar); 2784 } 2785 2786 static int ath10k_pci_hif_power_up(struct ath10k *ar, 2787 enum ath10k_firmware_mode fw_mode) 2788 { 2789 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2790 int ret; 2791 2792 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); 2793 2794 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2795 &ar_pci->link_ctl); 2796 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2797 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 2798 2799 /* 2800 * Bring the target up cleanly. 2801 * 2802 * The target may be in an undefined state with an AUX-powered Target 2803 * and a Host in WoW mode. If the Host crashes, loses power, or is 2804 * restarted (without unloading the driver) then the Target is left 2805 * (aux) powered and running. On a subsequent driver load, the Target 2806 * is in an unexpected state. We try to catch that here in order to 2807 * reset the Target and retry the probe. 2808 */ 2809 ret = ath10k_pci_chip_reset(ar); 2810 if (ret) { 2811 if (ath10k_pci_has_fw_crashed(ar)) { 2812 ath10k_warn(ar, "firmware crashed during chip reset\n"); 2813 ath10k_pci_fw_crashed_clear(ar); 2814 ath10k_pci_fw_crashed_dump(ar); 2815 } 2816 2817 ath10k_err(ar, "failed to reset chip: %d\n", ret); 2818 goto err_sleep; 2819 } 2820 2821 ret = ath10k_pci_init_pipes(ar); 2822 if (ret) { 2823 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 2824 goto err_sleep; 2825 } 2826 2827 ret = ath10k_pci_init_config(ar); 2828 if (ret) { 2829 ath10k_err(ar, "failed to setup init config: %d\n", ret); 2830 goto err_ce; 2831 } 2832 2833 ret = ath10k_pci_wake_target_cpu(ar); 2834 if (ret) { 2835 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 2836 goto err_ce; 2837 } 2838 2839 return 0; 2840 2841 err_ce: 2842 ath10k_pci_ce_deinit(ar); 2843 2844 err_sleep: 2845 return ret; 2846 } 2847 2848 void ath10k_pci_hif_power_down(struct ath10k *ar) 2849 { 2850 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 2851 2852 /* Currently hif_power_up performs effectively a reset and hif_stop 2853 * resets the chip as well so there's no point in resetting here. 2854 */ 2855 } 2856 2857 static int ath10k_pci_hif_suspend(struct ath10k *ar) 2858 { 2859 /* Nothing to do; the important stuff is in the driver suspend. */ 2860 return 0; 2861 } 2862 2863 static int ath10k_pci_suspend(struct ath10k *ar) 2864 { 2865 /* The grace timer can still be counting down and ar->ps_awake be true. 2866 * It is known that the device may be asleep after resuming regardless 2867 * of the SoC powersave state before suspending. Hence make sure the 2868 * device is asleep before proceeding. 2869 */ 2870 ath10k_pci_sleep_sync(ar); 2871 2872 return 0; 2873 } 2874 2875 static int ath10k_pci_hif_resume(struct ath10k *ar) 2876 { 2877 /* Nothing to do; the important stuff is in the driver resume. */ 2878 return 0; 2879 } 2880 2881 static int ath10k_pci_resume(struct ath10k *ar) 2882 { 2883 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2884 struct pci_dev *pdev = ar_pci->pdev; 2885 u32 val; 2886 int ret = 0; 2887 2888 ret = ath10k_pci_force_wake(ar); 2889 if (ret) { 2890 ath10k_err(ar, "failed to wake up target: %d\n", ret); 2891 return ret; 2892 } 2893 2894 /* Suspend/Resume resets the PCI configuration space, so we have to 2895 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries 2896 * from interfering with C3 CPU state. pci_restore_state won't help 2897 * here since it only restores the first 64 bytes pci config header. 2898 */ 2899 pci_read_config_dword(pdev, 0x40, &val); 2900 if ((val & 0x0000ff00) != 0) 2901 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 2902 2903 return ret; 2904 } 2905 2906 static bool ath10k_pci_validate_cal(void *data, size_t size) 2907 { 2908 __le16 *cal_words = data; 2909 u16 checksum = 0; 2910 size_t i; 2911 2912 if (size % 2 != 0) 2913 return false; 2914 2915 for (i = 0; i < size / 2; i++) 2916 checksum ^= le16_to_cpu(cal_words[i]); 2917 2918 return checksum == 0xffff; 2919 } 2920 2921 static void ath10k_pci_enable_eeprom(struct ath10k *ar) 2922 { 2923 /* Enable SI clock */ 2924 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0); 2925 2926 /* Configure GPIOs for I2C operation */ 2927 ath10k_pci_write32(ar, 2928 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2929 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN, 2930 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG, 2931 GPIO_PIN0_CONFIG) | 2932 SM(1, GPIO_PIN0_PAD_PULL)); 2933 2934 ath10k_pci_write32(ar, 2935 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2936 4 * QCA9887_1_0_SI_CLK_GPIO_PIN, 2937 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) | 2938 SM(1, GPIO_PIN0_PAD_PULL)); 2939 2940 ath10k_pci_write32(ar, 2941 GPIO_BASE_ADDRESS + 2942 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS, 2943 1u << QCA9887_1_0_SI_CLK_GPIO_PIN); 2944 2945 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */ 2946 ath10k_pci_write32(ar, 2947 SI_BASE_ADDRESS + SI_CONFIG_OFFSET, 2948 SM(1, SI_CONFIG_ERR_INT) | 2949 SM(1, SI_CONFIG_BIDIR_OD_DATA) | 2950 SM(1, SI_CONFIG_I2C) | 2951 SM(1, SI_CONFIG_POS_SAMPLE) | 2952 SM(1, SI_CONFIG_INACTIVE_DATA) | 2953 SM(1, SI_CONFIG_INACTIVE_CLK) | 2954 SM(8, SI_CONFIG_DIVIDER)); 2955 } 2956 2957 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out) 2958 { 2959 u32 reg; 2960 int wait_limit; 2961 2962 /* set device select byte and for the read operation */ 2963 reg = QCA9887_EEPROM_SELECT_READ | 2964 SM(addr, QCA9887_EEPROM_ADDR_LO) | 2965 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI); 2966 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg); 2967 2968 /* write transmit data, transfer length, and START bit */ 2969 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, 2970 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) | 2971 SM(4, SI_CS_TX_CNT)); 2972 2973 /* wait max 1 sec */ 2974 wait_limit = 100000; 2975 2976 /* wait for SI_CS_DONE_INT */ 2977 do { 2978 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET); 2979 if (MS(reg, SI_CS_DONE_INT)) 2980 break; 2981 2982 wait_limit--; 2983 udelay(10); 2984 } while (wait_limit > 0); 2985 2986 if (!MS(reg, SI_CS_DONE_INT)) { 2987 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n", 2988 addr); 2989 return -ETIMEDOUT; 2990 } 2991 2992 /* clear SI_CS_DONE_INT */ 2993 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg); 2994 2995 if (MS(reg, SI_CS_DONE_ERR)) { 2996 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr); 2997 return -EIO; 2998 } 2999 3000 /* extract receive data */ 3001 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET); 3002 *out = reg; 3003 3004 return 0; 3005 } 3006 3007 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data, 3008 size_t *data_len) 3009 { 3010 u8 *caldata = NULL; 3011 size_t calsize, i; 3012 int ret; 3013 3014 if (!QCA_REV_9887(ar)) 3015 return -EOPNOTSUPP; 3016 3017 calsize = ar->hw_params.cal_data_len; 3018 caldata = kmalloc(calsize, GFP_KERNEL); 3019 if (!caldata) 3020 return -ENOMEM; 3021 3022 ath10k_pci_enable_eeprom(ar); 3023 3024 for (i = 0; i < calsize; i++) { 3025 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]); 3026 if (ret) 3027 goto err_free; 3028 } 3029 3030 if (!ath10k_pci_validate_cal(caldata, calsize)) 3031 goto err_free; 3032 3033 *data = caldata; 3034 *data_len = calsize; 3035 3036 return 0; 3037 3038 err_free: 3039 kfree(caldata); 3040 3041 return -EINVAL; 3042 } 3043 3044 static const struct ath10k_hif_ops ath10k_pci_hif_ops = { 3045 .tx_sg = ath10k_pci_hif_tx_sg, 3046 .diag_read = ath10k_pci_hif_diag_read, 3047 .diag_write = ath10k_pci_diag_write_mem, 3048 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 3049 .start = ath10k_pci_hif_start, 3050 .stop = ath10k_pci_hif_stop, 3051 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 3052 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 3053 .send_complete_check = ath10k_pci_hif_send_complete_check, 3054 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 3055 .power_up = ath10k_pci_hif_power_up, 3056 .power_down = ath10k_pci_hif_power_down, 3057 .read32 = ath10k_pci_read32, 3058 .write32 = ath10k_pci_write32, 3059 .suspend = ath10k_pci_hif_suspend, 3060 .resume = ath10k_pci_hif_resume, 3061 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom, 3062 }; 3063 3064 /* 3065 * Top-level interrupt handler for all PCI interrupts from a Target. 3066 * When a block of MSI interrupts is allocated, this top-level handler 3067 * is not used; instead, we directly call the correct sub-handler. 3068 */ 3069 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) 3070 { 3071 struct ath10k *ar = arg; 3072 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3073 int ret; 3074 3075 if (ath10k_pci_has_device_gone(ar)) 3076 return IRQ_NONE; 3077 3078 ret = ath10k_pci_force_wake(ar); 3079 if (ret) { 3080 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret); 3081 return IRQ_NONE; 3082 } 3083 3084 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) && 3085 !ath10k_pci_irq_pending(ar)) 3086 return IRQ_NONE; 3087 3088 ath10k_pci_disable_and_clear_legacy_irq(ar); 3089 ath10k_pci_irq_msi_fw_mask(ar); 3090 napi_schedule(&ar->napi); 3091 3092 return IRQ_HANDLED; 3093 } 3094 3095 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget) 3096 { 3097 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 3098 int done = 0; 3099 3100 if (ath10k_pci_has_fw_crashed(ar)) { 3101 ath10k_pci_fw_crashed_clear(ar); 3102 ath10k_pci_fw_crashed_dump(ar); 3103 napi_complete(ctx); 3104 return done; 3105 } 3106 3107 ath10k_ce_per_engine_service_any(ar); 3108 3109 done = ath10k_htt_txrx_compl_task(ar, budget); 3110 3111 if (done < budget) { 3112 napi_complete_done(ctx, done); 3113 /* In case of MSI, it is possible that interrupts are received 3114 * while NAPI poll is inprogress. So pending interrupts that are 3115 * received after processing all copy engine pipes by NAPI poll 3116 * will not be handled again. This is causing failure to 3117 * complete boot sequence in x86 platform. So before enabling 3118 * interrupts safer to check for pending interrupts for 3119 * immediate servicing. 3120 */ 3121 if (ath10k_ce_interrupt_summary(ar)) { 3122 napi_reschedule(ctx); 3123 goto out; 3124 } 3125 ath10k_pci_enable_legacy_irq(ar); 3126 ath10k_pci_irq_msi_fw_unmask(ar); 3127 } 3128 3129 out: 3130 return done; 3131 } 3132 3133 static int ath10k_pci_request_irq_msi(struct ath10k *ar) 3134 { 3135 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3136 int ret; 3137 3138 ret = request_irq(ar_pci->pdev->irq, 3139 ath10k_pci_interrupt_handler, 3140 IRQF_SHARED, "ath10k_pci", ar); 3141 if (ret) { 3142 ath10k_warn(ar, "failed to request MSI irq %d: %d\n", 3143 ar_pci->pdev->irq, ret); 3144 return ret; 3145 } 3146 3147 return 0; 3148 } 3149 3150 static int ath10k_pci_request_irq_legacy(struct ath10k *ar) 3151 { 3152 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3153 int ret; 3154 3155 ret = request_irq(ar_pci->pdev->irq, 3156 ath10k_pci_interrupt_handler, 3157 IRQF_SHARED, "ath10k_pci", ar); 3158 if (ret) { 3159 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 3160 ar_pci->pdev->irq, ret); 3161 return ret; 3162 } 3163 3164 return 0; 3165 } 3166 3167 static int ath10k_pci_request_irq(struct ath10k *ar) 3168 { 3169 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3170 3171 switch (ar_pci->oper_irq_mode) { 3172 case ATH10K_PCI_IRQ_LEGACY: 3173 return ath10k_pci_request_irq_legacy(ar); 3174 case ATH10K_PCI_IRQ_MSI: 3175 return ath10k_pci_request_irq_msi(ar); 3176 default: 3177 return -EINVAL; 3178 } 3179 } 3180 3181 static void ath10k_pci_free_irq(struct ath10k *ar) 3182 { 3183 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3184 3185 free_irq(ar_pci->pdev->irq, ar); 3186 } 3187 3188 void ath10k_pci_init_napi(struct ath10k *ar) 3189 { 3190 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll, 3191 ATH10K_NAPI_BUDGET); 3192 } 3193 3194 static int ath10k_pci_init_irq(struct ath10k *ar) 3195 { 3196 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3197 int ret; 3198 3199 ath10k_pci_init_napi(ar); 3200 3201 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) 3202 ath10k_info(ar, "limiting irq mode to: %d\n", 3203 ath10k_pci_irq_mode); 3204 3205 /* Try MSI */ 3206 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) { 3207 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI; 3208 ret = pci_enable_msi(ar_pci->pdev); 3209 if (ret == 0) 3210 return 0; 3211 3212 /* fall-through */ 3213 } 3214 3215 /* Try legacy irq 3216 * 3217 * A potential race occurs here: The CORE_BASE write 3218 * depends on target correctly decoding AXI address but 3219 * host won't know when target writes BAR to CORE_CTRL. 3220 * This write might get lost if target has NOT written BAR. 3221 * For now, fix the race by repeating the write in below 3222 * synchronization checking. 3223 */ 3224 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; 3225 3226 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 3227 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 3228 3229 return 0; 3230 } 3231 3232 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) 3233 { 3234 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 3235 0); 3236 } 3237 3238 static int ath10k_pci_deinit_irq(struct ath10k *ar) 3239 { 3240 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3241 3242 switch (ar_pci->oper_irq_mode) { 3243 case ATH10K_PCI_IRQ_LEGACY: 3244 ath10k_pci_deinit_irq_legacy(ar); 3245 break; 3246 default: 3247 pci_disable_msi(ar_pci->pdev); 3248 break; 3249 } 3250 3251 return 0; 3252 } 3253 3254 int ath10k_pci_wait_for_target_init(struct ath10k *ar) 3255 { 3256 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3257 unsigned long timeout; 3258 u32 val; 3259 3260 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); 3261 3262 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); 3263 3264 do { 3265 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 3266 3267 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", 3268 val); 3269 3270 /* target should never return this */ 3271 if (val == 0xffffffff) 3272 continue; 3273 3274 /* the device has crashed so don't bother trying anymore */ 3275 if (val & FW_IND_EVENT_PENDING) 3276 break; 3277 3278 if (val & FW_IND_INITIALIZED) 3279 break; 3280 3281 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) 3282 /* Fix potential race by repeating CORE_BASE writes */ 3283 ath10k_pci_enable_legacy_irq(ar); 3284 3285 mdelay(10); 3286 } while (time_before(jiffies, timeout)); 3287 3288 ath10k_pci_disable_and_clear_legacy_irq(ar); 3289 ath10k_pci_irq_msi_fw_mask(ar); 3290 3291 if (val == 0xffffffff) { 3292 ath10k_err(ar, "failed to read device register, device is gone\n"); 3293 return -EIO; 3294 } 3295 3296 if (val & FW_IND_EVENT_PENDING) { 3297 ath10k_warn(ar, "device has crashed during init\n"); 3298 return -ECOMM; 3299 } 3300 3301 if (!(val & FW_IND_INITIALIZED)) { 3302 ath10k_err(ar, "failed to receive initialized event from target: %08x\n", 3303 val); 3304 return -ETIMEDOUT; 3305 } 3306 3307 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); 3308 return 0; 3309 } 3310 3311 static int ath10k_pci_cold_reset(struct ath10k *ar) 3312 { 3313 u32 val; 3314 3315 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); 3316 3317 spin_lock_bh(&ar->data_lock); 3318 3319 ar->stats.fw_cold_reset_counter++; 3320 3321 spin_unlock_bh(&ar->data_lock); 3322 3323 /* Put Target, including PCIe, into RESET. */ 3324 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); 3325 val |= 1; 3326 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3327 3328 /* After writing into SOC_GLOBAL_RESET to put device into 3329 * reset and pulling out of reset pcie may not be stable 3330 * for any immediate pcie register access and cause bus error, 3331 * add delay before any pcie access request to fix this issue. 3332 */ 3333 msleep(20); 3334 3335 /* Pull Target, including PCIe, out of RESET. */ 3336 val &= ~1; 3337 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3338 3339 msleep(20); 3340 3341 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); 3342 3343 return 0; 3344 } 3345 3346 static int ath10k_pci_claim(struct ath10k *ar) 3347 { 3348 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3349 struct pci_dev *pdev = ar_pci->pdev; 3350 int ret; 3351 3352 pci_set_drvdata(pdev, ar); 3353 3354 ret = pci_enable_device(pdev); 3355 if (ret) { 3356 ath10k_err(ar, "failed to enable pci device: %d\n", ret); 3357 return ret; 3358 } 3359 3360 ret = pci_request_region(pdev, BAR_NUM, "ath"); 3361 if (ret) { 3362 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, 3363 ret); 3364 goto err_device; 3365 } 3366 3367 /* Target expects 32 bit DMA. Enforce it. */ 3368 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3369 if (ret) { 3370 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); 3371 goto err_region; 3372 } 3373 3374 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3375 if (ret) { 3376 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n", 3377 ret); 3378 goto err_region; 3379 } 3380 3381 pci_set_master(pdev); 3382 3383 /* Arrange for access to Target SoC registers. */ 3384 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); 3385 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); 3386 if (!ar_pci->mem) { 3387 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); 3388 ret = -EIO; 3389 goto err_master; 3390 } 3391 3392 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem); 3393 return 0; 3394 3395 err_master: 3396 pci_clear_master(pdev); 3397 3398 err_region: 3399 pci_release_region(pdev, BAR_NUM); 3400 3401 err_device: 3402 pci_disable_device(pdev); 3403 3404 return ret; 3405 } 3406 3407 static void ath10k_pci_release(struct ath10k *ar) 3408 { 3409 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3410 struct pci_dev *pdev = ar_pci->pdev; 3411 3412 pci_iounmap(pdev, ar_pci->mem); 3413 pci_release_region(pdev, BAR_NUM); 3414 pci_clear_master(pdev); 3415 pci_disable_device(pdev); 3416 } 3417 3418 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) 3419 { 3420 const struct ath10k_pci_supp_chip *supp_chip; 3421 int i; 3422 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); 3423 3424 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { 3425 supp_chip = &ath10k_pci_supp_chips[i]; 3426 3427 if (supp_chip->dev_id == dev_id && 3428 supp_chip->rev_id == rev_id) 3429 return true; 3430 } 3431 3432 return false; 3433 } 3434 3435 int ath10k_pci_setup_resource(struct ath10k *ar) 3436 { 3437 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3438 struct ath10k_ce *ce = ath10k_ce_priv(ar); 3439 int ret; 3440 3441 spin_lock_init(&ce->ce_lock); 3442 spin_lock_init(&ar_pci->ps_lock); 3443 mutex_init(&ar_pci->ce_diag_mutex); 3444 3445 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0); 3446 3447 if (QCA_REV_6174(ar) || QCA_REV_9377(ar)) 3448 ath10k_pci_override_ce_config(ar); 3449 3450 ret = ath10k_pci_alloc_pipes(ar); 3451 if (ret) { 3452 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", 3453 ret); 3454 return ret; 3455 } 3456 3457 return 0; 3458 } 3459 3460 void ath10k_pci_release_resource(struct ath10k *ar) 3461 { 3462 ath10k_pci_rx_retry_sync(ar); 3463 netif_napi_del(&ar->napi); 3464 ath10k_pci_ce_deinit(ar); 3465 ath10k_pci_free_pipes(ar); 3466 } 3467 3468 static const struct ath10k_bus_ops ath10k_pci_bus_ops = { 3469 .read32 = ath10k_bus_pci_read32, 3470 .write32 = ath10k_bus_pci_write32, 3471 .get_num_banks = ath10k_pci_get_num_banks, 3472 }; 3473 3474 static int ath10k_pci_probe(struct pci_dev *pdev, 3475 const struct pci_device_id *pci_dev) 3476 { 3477 int ret = 0; 3478 struct ath10k *ar; 3479 struct ath10k_pci *ar_pci; 3480 enum ath10k_hw_rev hw_rev; 3481 struct ath10k_bus_params bus_params; 3482 bool pci_ps; 3483 int (*pci_soft_reset)(struct ath10k *ar); 3484 int (*pci_hard_reset)(struct ath10k *ar); 3485 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); 3486 3487 switch (pci_dev->device) { 3488 case QCA988X_2_0_DEVICE_ID_UBNT: 3489 case QCA988X_2_0_DEVICE_ID: 3490 hw_rev = ATH10K_HW_QCA988X; 3491 pci_ps = false; 3492 pci_soft_reset = ath10k_pci_warm_reset; 3493 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3494 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3495 break; 3496 case QCA9887_1_0_DEVICE_ID: 3497 hw_rev = ATH10K_HW_QCA9887; 3498 pci_ps = false; 3499 pci_soft_reset = ath10k_pci_warm_reset; 3500 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3501 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3502 break; 3503 case QCA6164_2_1_DEVICE_ID: 3504 case QCA6174_2_1_DEVICE_ID: 3505 hw_rev = ATH10K_HW_QCA6174; 3506 pci_ps = true; 3507 pci_soft_reset = ath10k_pci_warm_reset; 3508 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3509 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; 3510 break; 3511 case QCA99X0_2_0_DEVICE_ID: 3512 hw_rev = ATH10K_HW_QCA99X0; 3513 pci_ps = false; 3514 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3515 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3516 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3517 break; 3518 case QCA9984_1_0_DEVICE_ID: 3519 hw_rev = ATH10K_HW_QCA9984; 3520 pci_ps = false; 3521 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3522 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3523 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3524 break; 3525 case QCA9888_2_0_DEVICE_ID: 3526 hw_rev = ATH10K_HW_QCA9888; 3527 pci_ps = false; 3528 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3529 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3530 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3531 break; 3532 case QCA9377_1_0_DEVICE_ID: 3533 hw_rev = ATH10K_HW_QCA9377; 3534 pci_ps = true; 3535 pci_soft_reset = ath10k_pci_warm_reset; 3536 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3537 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr; 3538 break; 3539 default: 3540 WARN_ON(1); 3541 return -ENOTSUPP; 3542 } 3543 3544 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, 3545 hw_rev, &ath10k_pci_hif_ops); 3546 if (!ar) { 3547 dev_err(&pdev->dev, "failed to allocate core\n"); 3548 return -ENOMEM; 3549 } 3550 3551 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 3552 pdev->vendor, pdev->device, 3553 pdev->subsystem_vendor, pdev->subsystem_device); 3554 3555 ar_pci = ath10k_pci_priv(ar); 3556 ar_pci->pdev = pdev; 3557 ar_pci->dev = &pdev->dev; 3558 ar_pci->ar = ar; 3559 ar->dev_id = pci_dev->device; 3560 ar_pci->pci_ps = pci_ps; 3561 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops; 3562 ar_pci->pci_soft_reset = pci_soft_reset; 3563 ar_pci->pci_hard_reset = pci_hard_reset; 3564 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; 3565 ar->ce_priv = &ar_pci->ce; 3566 3567 ar->id.vendor = pdev->vendor; 3568 ar->id.device = pdev->device; 3569 ar->id.subsystem_vendor = pdev->subsystem_vendor; 3570 ar->id.subsystem_device = pdev->subsystem_device; 3571 3572 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0); 3573 3574 ret = ath10k_pci_setup_resource(ar); 3575 if (ret) { 3576 ath10k_err(ar, "failed to setup resource: %d\n", ret); 3577 goto err_core_destroy; 3578 } 3579 3580 ret = ath10k_pci_claim(ar); 3581 if (ret) { 3582 ath10k_err(ar, "failed to claim device: %d\n", ret); 3583 goto err_free_pipes; 3584 } 3585 3586 ret = ath10k_pci_force_wake(ar); 3587 if (ret) { 3588 ath10k_warn(ar, "failed to wake up device : %d\n", ret); 3589 goto err_sleep; 3590 } 3591 3592 ath10k_pci_ce_deinit(ar); 3593 ath10k_pci_irq_disable(ar); 3594 3595 ret = ath10k_pci_init_irq(ar); 3596 if (ret) { 3597 ath10k_err(ar, "failed to init irqs: %d\n", ret); 3598 goto err_sleep; 3599 } 3600 3601 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n", 3602 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode, 3603 ath10k_pci_irq_mode, ath10k_pci_reset_mode); 3604 3605 ret = ath10k_pci_request_irq(ar); 3606 if (ret) { 3607 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 3608 goto err_deinit_irq; 3609 } 3610 3611 ret = ath10k_pci_chip_reset(ar); 3612 if (ret) { 3613 ath10k_err(ar, "failed to reset chip: %d\n", ret); 3614 goto err_free_irq; 3615 } 3616 3617 bus_params.dev_type = ATH10K_DEV_TYPE_LL; 3618 bus_params.link_can_suspend = true; 3619 bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 3620 if (bus_params.chip_id == 0xffffffff) { 3621 ath10k_err(ar, "failed to get chip id\n"); 3622 goto err_free_irq; 3623 } 3624 3625 if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) { 3626 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", 3627 pdev->device, bus_params.chip_id); 3628 goto err_free_irq; 3629 } 3630 3631 ret = ath10k_core_register(ar, &bus_params); 3632 if (ret) { 3633 ath10k_err(ar, "failed to register driver core: %d\n", ret); 3634 goto err_free_irq; 3635 } 3636 3637 return 0; 3638 3639 err_free_irq: 3640 ath10k_pci_free_irq(ar); 3641 ath10k_pci_rx_retry_sync(ar); 3642 3643 err_deinit_irq: 3644 ath10k_pci_deinit_irq(ar); 3645 3646 err_sleep: 3647 ath10k_pci_sleep_sync(ar); 3648 ath10k_pci_release(ar); 3649 3650 err_free_pipes: 3651 ath10k_pci_free_pipes(ar); 3652 3653 err_core_destroy: 3654 ath10k_core_destroy(ar); 3655 3656 return ret; 3657 } 3658 3659 static void ath10k_pci_remove(struct pci_dev *pdev) 3660 { 3661 struct ath10k *ar = pci_get_drvdata(pdev); 3662 struct ath10k_pci *ar_pci; 3663 3664 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); 3665 3666 if (!ar) 3667 return; 3668 3669 ar_pci = ath10k_pci_priv(ar); 3670 3671 if (!ar_pci) 3672 return; 3673 3674 ath10k_core_unregister(ar); 3675 ath10k_pci_free_irq(ar); 3676 ath10k_pci_deinit_irq(ar); 3677 ath10k_pci_release_resource(ar); 3678 ath10k_pci_sleep_sync(ar); 3679 ath10k_pci_release(ar); 3680 ath10k_core_destroy(ar); 3681 } 3682 3683 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); 3684 3685 static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev) 3686 { 3687 struct ath10k *ar = dev_get_drvdata(dev); 3688 int ret; 3689 3690 ret = ath10k_pci_suspend(ar); 3691 if (ret) 3692 ath10k_warn(ar, "failed to suspend hif: %d\n", ret); 3693 3694 return ret; 3695 } 3696 3697 static __maybe_unused int ath10k_pci_pm_resume(struct device *dev) 3698 { 3699 struct ath10k *ar = dev_get_drvdata(dev); 3700 int ret; 3701 3702 ret = ath10k_pci_resume(ar); 3703 if (ret) 3704 ath10k_warn(ar, "failed to resume hif: %d\n", ret); 3705 3706 return ret; 3707 } 3708 3709 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops, 3710 ath10k_pci_pm_suspend, 3711 ath10k_pci_pm_resume); 3712 3713 static struct pci_driver ath10k_pci_driver = { 3714 .name = "ath10k_pci", 3715 .id_table = ath10k_pci_id_table, 3716 .probe = ath10k_pci_probe, 3717 .remove = ath10k_pci_remove, 3718 #ifdef CONFIG_PM 3719 .driver.pm = &ath10k_pci_pm_ops, 3720 #endif 3721 }; 3722 3723 static int __init ath10k_pci_init(void) 3724 { 3725 int ret; 3726 3727 ret = pci_register_driver(&ath10k_pci_driver); 3728 if (ret) 3729 printk(KERN_ERR "failed to register ath10k pci driver: %d\n", 3730 ret); 3731 3732 ret = ath10k_ahb_init(); 3733 if (ret) 3734 printk(KERN_ERR "ahb init failed: %d\n", ret); 3735 3736 return ret; 3737 } 3738 module_init(ath10k_pci_init); 3739 3740 static void __exit ath10k_pci_exit(void) 3741 { 3742 pci_unregister_driver(&ath10k_pci_driver); 3743 ath10k_ahb_exit(); 3744 } 3745 3746 module_exit(ath10k_pci_exit); 3747 3748 MODULE_AUTHOR("Qualcomm Atheros"); 3749 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices"); 3750 MODULE_LICENSE("Dual BSD/GPL"); 3751 3752 /* QCA988x 2.0 firmware files */ 3753 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); 3754 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); 3755 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3756 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3757 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); 3758 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3759 3760 /* QCA9887 1.0 firmware files */ 3761 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3762 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE); 3763 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3764 3765 /* QCA6174 2.1 firmware files */ 3766 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE); 3767 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE); 3768 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE); 3769 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3770 3771 /* QCA6174 3.1 firmware files */ 3772 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3773 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3774 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3775 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE); 3776 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3777 3778 /* QCA9377 1.0 firmware files */ 3779 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3780 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3781 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE); 3782