1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/pci.h> 19 #include <linux/module.h> 20 #include <linux/interrupt.h> 21 #include <linux/spinlock.h> 22 #include <linux/bitops.h> 23 24 #include "core.h" 25 #include "debug.h" 26 27 #include "targaddrs.h" 28 #include "bmi.h" 29 30 #include "hif.h" 31 #include "htc.h" 32 33 #include "ce.h" 34 #include "pci.h" 35 36 enum ath10k_pci_reset_mode { 37 ATH10K_PCI_RESET_AUTO = 0, 38 ATH10K_PCI_RESET_WARM_ONLY = 1, 39 }; 40 41 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; 42 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; 43 44 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); 45 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); 46 47 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); 48 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); 49 50 /* how long wait to wait for target to initialise, in ms */ 51 #define ATH10K_PCI_TARGET_WAIT 3000 52 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 53 54 static const struct pci_device_id ath10k_pci_id_table[] = { 55 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ 56 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */ 57 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ 58 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */ 59 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */ 60 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */ 61 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */ 62 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */ 63 {0} 64 }; 65 66 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { 67 /* QCA988X pre 2.0 chips are not supported because they need some nasty 68 * hacks. ath10k doesn't have them and these devices crash horribly 69 * because of that. 70 */ 71 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, 72 73 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 74 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 75 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 76 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 77 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 78 79 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 80 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 81 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 82 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 83 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 84 85 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, 86 87 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV }, 88 89 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV }, 90 91 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV }, 92 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV }, 93 94 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV }, 95 }; 96 97 static void ath10k_pci_buffer_cleanup(struct ath10k *ar); 98 static int ath10k_pci_cold_reset(struct ath10k *ar); 99 static int ath10k_pci_safe_chip_reset(struct ath10k *ar); 100 static int ath10k_pci_init_irq(struct ath10k *ar); 101 static int ath10k_pci_deinit_irq(struct ath10k *ar); 102 static int ath10k_pci_request_irq(struct ath10k *ar); 103 static void ath10k_pci_free_irq(struct ath10k *ar); 104 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe, 105 struct ath10k_ce_pipe *rx_pipe, 106 struct bmi_xfer *xfer); 107 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar); 108 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state); 109 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 110 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 111 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 112 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 113 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); 114 115 static struct ce_attr host_ce_config_wlan[] = { 116 /* CE0: host->target HTC control and raw streams */ 117 { 118 .flags = CE_ATTR_FLAGS, 119 .src_nentries = 16, 120 .src_sz_max = 256, 121 .dest_nentries = 0, 122 .send_cb = ath10k_pci_htc_tx_cb, 123 }, 124 125 /* CE1: target->host HTT + HTC control */ 126 { 127 .flags = CE_ATTR_FLAGS, 128 .src_nentries = 0, 129 .src_sz_max = 2048, 130 .dest_nentries = 512, 131 .recv_cb = ath10k_pci_htt_htc_rx_cb, 132 }, 133 134 /* CE2: target->host WMI */ 135 { 136 .flags = CE_ATTR_FLAGS, 137 .src_nentries = 0, 138 .src_sz_max = 2048, 139 .dest_nentries = 128, 140 .recv_cb = ath10k_pci_htc_rx_cb, 141 }, 142 143 /* CE3: host->target WMI */ 144 { 145 .flags = CE_ATTR_FLAGS, 146 .src_nentries = 32, 147 .src_sz_max = 2048, 148 .dest_nentries = 0, 149 .send_cb = ath10k_pci_htc_tx_cb, 150 }, 151 152 /* CE4: host->target HTT */ 153 { 154 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 155 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, 156 .src_sz_max = 256, 157 .dest_nentries = 0, 158 .send_cb = ath10k_pci_htt_tx_cb, 159 }, 160 161 /* CE5: target->host HTT (HIF->HTT) */ 162 { 163 .flags = CE_ATTR_FLAGS, 164 .src_nentries = 0, 165 .src_sz_max = 512, 166 .dest_nentries = 512, 167 .recv_cb = ath10k_pci_htt_rx_cb, 168 }, 169 170 /* CE6: target autonomous hif_memcpy */ 171 { 172 .flags = CE_ATTR_FLAGS, 173 .src_nentries = 0, 174 .src_sz_max = 0, 175 .dest_nentries = 0, 176 }, 177 178 /* CE7: ce_diag, the Diagnostic Window */ 179 { 180 .flags = CE_ATTR_FLAGS, 181 .src_nentries = 2, 182 .src_sz_max = DIAG_TRANSFER_LIMIT, 183 .dest_nentries = 2, 184 }, 185 186 /* CE8: target->host pktlog */ 187 { 188 .flags = CE_ATTR_FLAGS, 189 .src_nentries = 0, 190 .src_sz_max = 2048, 191 .dest_nentries = 128, 192 .recv_cb = ath10k_pci_pktlog_rx_cb, 193 }, 194 195 /* CE9 target autonomous qcache memcpy */ 196 { 197 .flags = CE_ATTR_FLAGS, 198 .src_nentries = 0, 199 .src_sz_max = 0, 200 .dest_nentries = 0, 201 }, 202 203 /* CE10: target autonomous hif memcpy */ 204 { 205 .flags = CE_ATTR_FLAGS, 206 .src_nentries = 0, 207 .src_sz_max = 0, 208 .dest_nentries = 0, 209 }, 210 211 /* CE11: target autonomous hif memcpy */ 212 { 213 .flags = CE_ATTR_FLAGS, 214 .src_nentries = 0, 215 .src_sz_max = 0, 216 .dest_nentries = 0, 217 }, 218 }; 219 220 /* Target firmware's Copy Engine configuration. */ 221 static struct ce_pipe_config target_ce_config_wlan[] = { 222 /* CE0: host->target HTC control and raw streams */ 223 { 224 .pipenum = __cpu_to_le32(0), 225 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 226 .nentries = __cpu_to_le32(32), 227 .nbytes_max = __cpu_to_le32(256), 228 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 229 .reserved = __cpu_to_le32(0), 230 }, 231 232 /* CE1: target->host HTT + HTC control */ 233 { 234 .pipenum = __cpu_to_le32(1), 235 .pipedir = __cpu_to_le32(PIPEDIR_IN), 236 .nentries = __cpu_to_le32(32), 237 .nbytes_max = __cpu_to_le32(2048), 238 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 239 .reserved = __cpu_to_le32(0), 240 }, 241 242 /* CE2: target->host WMI */ 243 { 244 .pipenum = __cpu_to_le32(2), 245 .pipedir = __cpu_to_le32(PIPEDIR_IN), 246 .nentries = __cpu_to_le32(64), 247 .nbytes_max = __cpu_to_le32(2048), 248 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 249 .reserved = __cpu_to_le32(0), 250 }, 251 252 /* CE3: host->target WMI */ 253 { 254 .pipenum = __cpu_to_le32(3), 255 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 256 .nentries = __cpu_to_le32(32), 257 .nbytes_max = __cpu_to_le32(2048), 258 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 259 .reserved = __cpu_to_le32(0), 260 }, 261 262 /* CE4: host->target HTT */ 263 { 264 .pipenum = __cpu_to_le32(4), 265 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 266 .nentries = __cpu_to_le32(256), 267 .nbytes_max = __cpu_to_le32(256), 268 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 269 .reserved = __cpu_to_le32(0), 270 }, 271 272 /* NB: 50% of src nentries, since tx has 2 frags */ 273 274 /* CE5: target->host HTT (HIF->HTT) */ 275 { 276 .pipenum = __cpu_to_le32(5), 277 .pipedir = __cpu_to_le32(PIPEDIR_IN), 278 .nentries = __cpu_to_le32(32), 279 .nbytes_max = __cpu_to_le32(512), 280 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 281 .reserved = __cpu_to_le32(0), 282 }, 283 284 /* CE6: Reserved for target autonomous hif_memcpy */ 285 { 286 .pipenum = __cpu_to_le32(6), 287 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 288 .nentries = __cpu_to_le32(32), 289 .nbytes_max = __cpu_to_le32(4096), 290 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 291 .reserved = __cpu_to_le32(0), 292 }, 293 294 /* CE7 used only by Host */ 295 { 296 .pipenum = __cpu_to_le32(7), 297 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 298 .nentries = __cpu_to_le32(0), 299 .nbytes_max = __cpu_to_le32(0), 300 .flags = __cpu_to_le32(0), 301 .reserved = __cpu_to_le32(0), 302 }, 303 304 /* CE8 target->host packtlog */ 305 { 306 .pipenum = __cpu_to_le32(8), 307 .pipedir = __cpu_to_le32(PIPEDIR_IN), 308 .nentries = __cpu_to_le32(64), 309 .nbytes_max = __cpu_to_le32(2048), 310 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 311 .reserved = __cpu_to_le32(0), 312 }, 313 314 /* CE9 target autonomous qcache memcpy */ 315 { 316 .pipenum = __cpu_to_le32(9), 317 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 318 .nentries = __cpu_to_le32(32), 319 .nbytes_max = __cpu_to_le32(2048), 320 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 321 .reserved = __cpu_to_le32(0), 322 }, 323 324 /* It not necessary to send target wlan configuration for CE10 & CE11 325 * as these CEs are not actively used in target. 326 */ 327 }; 328 329 /* 330 * Map from service/endpoint to Copy Engine. 331 * This table is derived from the CE_PCI TABLE, above. 332 * It is passed to the Target at startup for use by firmware. 333 */ 334 static struct service_to_pipe target_service_to_ce_map_wlan[] = { 335 { 336 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 337 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 338 __cpu_to_le32(3), 339 }, 340 { 341 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 342 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 343 __cpu_to_le32(2), 344 }, 345 { 346 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 347 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 348 __cpu_to_le32(3), 349 }, 350 { 351 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 352 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 353 __cpu_to_le32(2), 354 }, 355 { 356 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 357 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 358 __cpu_to_le32(3), 359 }, 360 { 361 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 362 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 363 __cpu_to_le32(2), 364 }, 365 { 366 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 367 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 368 __cpu_to_le32(3), 369 }, 370 { 371 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 372 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 373 __cpu_to_le32(2), 374 }, 375 { 376 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 377 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 378 __cpu_to_le32(3), 379 }, 380 { 381 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 382 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 383 __cpu_to_le32(2), 384 }, 385 { 386 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 387 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 388 __cpu_to_le32(0), 389 }, 390 { 391 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 392 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 393 __cpu_to_le32(1), 394 }, 395 { /* not used */ 396 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 397 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 398 __cpu_to_le32(0), 399 }, 400 { /* not used */ 401 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 402 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 403 __cpu_to_le32(1), 404 }, 405 { 406 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 407 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 408 __cpu_to_le32(4), 409 }, 410 { 411 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 412 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 413 __cpu_to_le32(5), 414 }, 415 416 /* (Additions here) */ 417 418 { /* must be last */ 419 __cpu_to_le32(0), 420 __cpu_to_le32(0), 421 __cpu_to_le32(0), 422 }, 423 }; 424 425 static bool ath10k_pci_is_awake(struct ath10k *ar) 426 { 427 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 428 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 429 RTC_STATE_ADDRESS); 430 431 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; 432 } 433 434 static void __ath10k_pci_wake(struct ath10k *ar) 435 { 436 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 437 438 lockdep_assert_held(&ar_pci->ps_lock); 439 440 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n", 441 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 442 443 iowrite32(PCIE_SOC_WAKE_V_MASK, 444 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 445 PCIE_SOC_WAKE_ADDRESS); 446 } 447 448 static void __ath10k_pci_sleep(struct ath10k *ar) 449 { 450 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 451 452 lockdep_assert_held(&ar_pci->ps_lock); 453 454 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n", 455 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 456 457 iowrite32(PCIE_SOC_WAKE_RESET, 458 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 459 PCIE_SOC_WAKE_ADDRESS); 460 ar_pci->ps_awake = false; 461 } 462 463 static int ath10k_pci_wake_wait(struct ath10k *ar) 464 { 465 int tot_delay = 0; 466 int curr_delay = 5; 467 468 while (tot_delay < PCIE_WAKE_TIMEOUT) { 469 if (ath10k_pci_is_awake(ar)) { 470 if (tot_delay > PCIE_WAKE_LATE_US) 471 ath10k_warn(ar, "device wakeup took %d ms which is unusally long, otherwise it works normally.\n", 472 tot_delay / 1000); 473 return 0; 474 } 475 476 udelay(curr_delay); 477 tot_delay += curr_delay; 478 479 if (curr_delay < 50) 480 curr_delay += 5; 481 } 482 483 return -ETIMEDOUT; 484 } 485 486 static int ath10k_pci_force_wake(struct ath10k *ar) 487 { 488 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 489 unsigned long flags; 490 int ret = 0; 491 492 if (ar_pci->pci_ps) 493 return ret; 494 495 spin_lock_irqsave(&ar_pci->ps_lock, flags); 496 497 if (!ar_pci->ps_awake) { 498 iowrite32(PCIE_SOC_WAKE_V_MASK, 499 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 500 PCIE_SOC_WAKE_ADDRESS); 501 502 ret = ath10k_pci_wake_wait(ar); 503 if (ret == 0) 504 ar_pci->ps_awake = true; 505 } 506 507 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 508 509 return ret; 510 } 511 512 static void ath10k_pci_force_sleep(struct ath10k *ar) 513 { 514 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 515 unsigned long flags; 516 517 spin_lock_irqsave(&ar_pci->ps_lock, flags); 518 519 iowrite32(PCIE_SOC_WAKE_RESET, 520 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 521 PCIE_SOC_WAKE_ADDRESS); 522 ar_pci->ps_awake = false; 523 524 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 525 } 526 527 static int ath10k_pci_wake(struct ath10k *ar) 528 { 529 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 530 unsigned long flags; 531 int ret = 0; 532 533 if (ar_pci->pci_ps == 0) 534 return ret; 535 536 spin_lock_irqsave(&ar_pci->ps_lock, flags); 537 538 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n", 539 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 540 541 /* This function can be called very frequently. To avoid excessive 542 * CPU stalls for MMIO reads use a cache var to hold the device state. 543 */ 544 if (!ar_pci->ps_awake) { 545 __ath10k_pci_wake(ar); 546 547 ret = ath10k_pci_wake_wait(ar); 548 if (ret == 0) 549 ar_pci->ps_awake = true; 550 } 551 552 if (ret == 0) { 553 ar_pci->ps_wake_refcount++; 554 WARN_ON(ar_pci->ps_wake_refcount == 0); 555 } 556 557 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 558 559 return ret; 560 } 561 562 static void ath10k_pci_sleep(struct ath10k *ar) 563 { 564 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 565 unsigned long flags; 566 567 if (ar_pci->pci_ps == 0) 568 return; 569 570 spin_lock_irqsave(&ar_pci->ps_lock, flags); 571 572 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n", 573 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 574 575 if (WARN_ON(ar_pci->ps_wake_refcount == 0)) 576 goto skip; 577 578 ar_pci->ps_wake_refcount--; 579 580 mod_timer(&ar_pci->ps_timer, jiffies + 581 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC)); 582 583 skip: 584 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 585 } 586 587 static void ath10k_pci_ps_timer(unsigned long ptr) 588 { 589 struct ath10k *ar = (void *)ptr; 590 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 591 unsigned long flags; 592 593 spin_lock_irqsave(&ar_pci->ps_lock, flags); 594 595 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n", 596 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 597 598 if (ar_pci->ps_wake_refcount > 0) 599 goto skip; 600 601 __ath10k_pci_sleep(ar); 602 603 skip: 604 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 605 } 606 607 static void ath10k_pci_sleep_sync(struct ath10k *ar) 608 { 609 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 610 unsigned long flags; 611 612 if (ar_pci->pci_ps == 0) { 613 ath10k_pci_force_sleep(ar); 614 return; 615 } 616 617 del_timer_sync(&ar_pci->ps_timer); 618 619 spin_lock_irqsave(&ar_pci->ps_lock, flags); 620 WARN_ON(ar_pci->ps_wake_refcount > 0); 621 __ath10k_pci_sleep(ar); 622 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 623 } 624 625 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value) 626 { 627 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 628 int ret; 629 630 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { 631 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 632 offset, offset + sizeof(value), ar_pci->mem_len); 633 return; 634 } 635 636 ret = ath10k_pci_wake(ar); 637 if (ret) { 638 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n", 639 value, offset, ret); 640 return; 641 } 642 643 iowrite32(value, ar_pci->mem + offset); 644 ath10k_pci_sleep(ar); 645 } 646 647 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) 648 { 649 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 650 u32 val; 651 int ret; 652 653 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { 654 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 655 offset, offset + sizeof(val), ar_pci->mem_len); 656 return 0; 657 } 658 659 ret = ath10k_pci_wake(ar); 660 if (ret) { 661 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n", 662 offset, ret); 663 return 0xffffffff; 664 } 665 666 val = ioread32(ar_pci->mem + offset); 667 ath10k_pci_sleep(ar); 668 669 return val; 670 } 671 672 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) 673 { 674 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 675 676 ar_pci->bus_ops->write32(ar, offset, value); 677 } 678 679 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) 680 { 681 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 682 683 return ar_pci->bus_ops->read32(ar, offset); 684 } 685 686 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) 687 { 688 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 689 } 690 691 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) 692 { 693 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); 694 } 695 696 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) 697 { 698 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr); 699 } 700 701 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) 702 { 703 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); 704 } 705 706 bool ath10k_pci_irq_pending(struct ath10k *ar) 707 { 708 u32 cause; 709 710 /* Check if the shared legacy irq is for us */ 711 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 712 PCIE_INTR_CAUSE_ADDRESS); 713 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) 714 return true; 715 716 return false; 717 } 718 719 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) 720 { 721 /* IMPORTANT: INTR_CLR register has to be set after 722 * INTR_ENABLE is set to 0, otherwise interrupt can not be 723 * really cleared. 724 */ 725 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 726 0); 727 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, 728 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 729 730 /* IMPORTANT: this extra read transaction is required to 731 * flush the posted write buffer. 732 */ 733 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 734 PCIE_INTR_ENABLE_ADDRESS); 735 } 736 737 void ath10k_pci_enable_legacy_irq(struct ath10k *ar) 738 { 739 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 740 PCIE_INTR_ENABLE_ADDRESS, 741 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 742 743 /* IMPORTANT: this extra read transaction is required to 744 * flush the posted write buffer. 745 */ 746 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 747 PCIE_INTR_ENABLE_ADDRESS); 748 } 749 750 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) 751 { 752 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 753 754 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI) 755 return "msi"; 756 757 return "legacy"; 758 } 759 760 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) 761 { 762 struct ath10k *ar = pipe->hif_ce_state; 763 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 764 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 765 struct sk_buff *skb; 766 dma_addr_t paddr; 767 int ret; 768 769 skb = dev_alloc_skb(pipe->buf_sz); 770 if (!skb) 771 return -ENOMEM; 772 773 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 774 775 paddr = dma_map_single(ar->dev, skb->data, 776 skb->len + skb_tailroom(skb), 777 DMA_FROM_DEVICE); 778 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 779 ath10k_warn(ar, "failed to dma map pci rx buf\n"); 780 dev_kfree_skb_any(skb); 781 return -EIO; 782 } 783 784 ATH10K_SKB_RXCB(skb)->paddr = paddr; 785 786 spin_lock_bh(&ar_pci->ce_lock); 787 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr); 788 spin_unlock_bh(&ar_pci->ce_lock); 789 if (ret) { 790 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 791 DMA_FROM_DEVICE); 792 dev_kfree_skb_any(skb); 793 return ret; 794 } 795 796 return 0; 797 } 798 799 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) 800 { 801 struct ath10k *ar = pipe->hif_ce_state; 802 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 803 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 804 int ret, num; 805 806 if (pipe->buf_sz == 0) 807 return; 808 809 if (!ce_pipe->dest_ring) 810 return; 811 812 spin_lock_bh(&ar_pci->ce_lock); 813 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 814 spin_unlock_bh(&ar_pci->ce_lock); 815 816 while (num >= 0) { 817 ret = __ath10k_pci_rx_post_buf(pipe); 818 if (ret) { 819 if (ret == -ENOSPC) 820 break; 821 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); 822 mod_timer(&ar_pci->rx_post_retry, jiffies + 823 ATH10K_PCI_RX_POST_RETRY_MS); 824 break; 825 } 826 num--; 827 } 828 } 829 830 void ath10k_pci_rx_post(struct ath10k *ar) 831 { 832 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 833 int i; 834 835 for (i = 0; i < CE_COUNT; i++) 836 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); 837 } 838 839 void ath10k_pci_rx_replenish_retry(unsigned long ptr) 840 { 841 struct ath10k *ar = (void *)ptr; 842 843 ath10k_pci_rx_post(ar); 844 } 845 846 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 847 { 848 u32 val = 0, region = addr & 0xfffff; 849 850 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 851 & 0x7ff) << 21; 852 val |= 0x100000 | region; 853 return val; 854 } 855 856 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 857 { 858 u32 val = 0, region = addr & 0xfffff; 859 860 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); 861 val |= 0x100000 | region; 862 return val; 863 } 864 865 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 866 { 867 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 868 869 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr)) 870 return -ENOTSUPP; 871 872 return ar_pci->targ_cpu_to_ce_addr(ar, addr); 873 } 874 875 /* 876 * Diagnostic read/write access is provided for startup/config/debug usage. 877 * Caller must guarantee proper alignment, when applicable, and single user 878 * at any moment. 879 */ 880 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, 881 int nbytes) 882 { 883 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 884 int ret = 0; 885 u32 *buf; 886 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 887 struct ath10k_ce_pipe *ce_diag; 888 /* Host buffer address in CE space */ 889 u32 ce_data; 890 dma_addr_t ce_data_base = 0; 891 void *data_buf = NULL; 892 int i; 893 894 spin_lock_bh(&ar_pci->ce_lock); 895 896 ce_diag = ar_pci->ce_diag; 897 898 /* 899 * Allocate a temporary bounce buffer to hold caller's data 900 * to be DMA'ed from Target. This guarantees 901 * 1) 4-byte alignment 902 * 2) Buffer in DMA-able space 903 */ 904 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 905 906 data_buf = (unsigned char *)dma_zalloc_coherent(ar->dev, 907 alloc_nbytes, 908 &ce_data_base, 909 GFP_ATOMIC); 910 911 if (!data_buf) { 912 ret = -ENOMEM; 913 goto done; 914 } 915 916 remaining_bytes = nbytes; 917 ce_data = ce_data_base; 918 while (remaining_bytes) { 919 nbytes = min_t(unsigned int, remaining_bytes, 920 DIAG_TRANSFER_LIMIT); 921 922 ret = __ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data); 923 if (ret != 0) 924 goto done; 925 926 /* Request CE to send from Target(!) address to Host buffer */ 927 /* 928 * The address supplied by the caller is in the 929 * Target CPU virtual address space. 930 * 931 * In order to use this address with the diagnostic CE, 932 * convert it from Target CPU virtual address space 933 * to CE address space 934 */ 935 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 936 937 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0, 938 0); 939 if (ret) 940 goto done; 941 942 i = 0; 943 while (ath10k_ce_completed_send_next_nolock(ce_diag, 944 NULL) != 0) { 945 mdelay(1); 946 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 947 ret = -EBUSY; 948 goto done; 949 } 950 } 951 952 i = 0; 953 while (ath10k_ce_completed_recv_next_nolock(ce_diag, 954 (void **)&buf, 955 &completed_nbytes) 956 != 0) { 957 mdelay(1); 958 959 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 960 ret = -EBUSY; 961 goto done; 962 } 963 } 964 965 if (nbytes != completed_nbytes) { 966 ret = -EIO; 967 goto done; 968 } 969 970 if (*buf != ce_data) { 971 ret = -EIO; 972 goto done; 973 } 974 975 remaining_bytes -= nbytes; 976 memcpy(data, data_buf, nbytes); 977 978 address += nbytes; 979 data += nbytes; 980 } 981 982 done: 983 984 if (data_buf) 985 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 986 ce_data_base); 987 988 spin_unlock_bh(&ar_pci->ce_lock); 989 990 return ret; 991 } 992 993 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) 994 { 995 __le32 val = 0; 996 int ret; 997 998 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); 999 *value = __le32_to_cpu(val); 1000 1001 return ret; 1002 } 1003 1004 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, 1005 u32 src, u32 len) 1006 { 1007 u32 host_addr, addr; 1008 int ret; 1009 1010 host_addr = host_interest_item_address(src); 1011 1012 ret = ath10k_pci_diag_read32(ar, host_addr, &addr); 1013 if (ret != 0) { 1014 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", 1015 src, ret); 1016 return ret; 1017 } 1018 1019 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); 1020 if (ret != 0) { 1021 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", 1022 addr, len, ret); 1023 return ret; 1024 } 1025 1026 return 0; 1027 } 1028 1029 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ 1030 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) 1031 1032 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, 1033 const void *data, int nbytes) 1034 { 1035 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1036 int ret = 0; 1037 u32 *buf; 1038 unsigned int completed_nbytes, orig_nbytes, remaining_bytes; 1039 struct ath10k_ce_pipe *ce_diag; 1040 void *data_buf = NULL; 1041 u32 ce_data; /* Host buffer address in CE space */ 1042 dma_addr_t ce_data_base = 0; 1043 int i; 1044 1045 spin_lock_bh(&ar_pci->ce_lock); 1046 1047 ce_diag = ar_pci->ce_diag; 1048 1049 /* 1050 * Allocate a temporary bounce buffer to hold caller's data 1051 * to be DMA'ed to Target. This guarantees 1052 * 1) 4-byte alignment 1053 * 2) Buffer in DMA-able space 1054 */ 1055 orig_nbytes = nbytes; 1056 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, 1057 orig_nbytes, 1058 &ce_data_base, 1059 GFP_ATOMIC); 1060 if (!data_buf) { 1061 ret = -ENOMEM; 1062 goto done; 1063 } 1064 1065 /* Copy caller's data to allocated DMA buf */ 1066 memcpy(data_buf, data, orig_nbytes); 1067 1068 /* 1069 * The address supplied by the caller is in the 1070 * Target CPU virtual address space. 1071 * 1072 * In order to use this address with the diagnostic CE, 1073 * convert it from 1074 * Target CPU virtual address space 1075 * to 1076 * CE address space 1077 */ 1078 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 1079 1080 remaining_bytes = orig_nbytes; 1081 ce_data = ce_data_base; 1082 while (remaining_bytes) { 1083 /* FIXME: check cast */ 1084 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); 1085 1086 /* Set up to receive directly into Target(!) address */ 1087 ret = __ath10k_ce_rx_post_buf(ce_diag, &address, address); 1088 if (ret != 0) 1089 goto done; 1090 1091 /* 1092 * Request CE to send caller-supplied data that 1093 * was copied to bounce buffer to Target(!) address. 1094 */ 1095 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data, 1096 nbytes, 0, 0); 1097 if (ret != 0) 1098 goto done; 1099 1100 i = 0; 1101 while (ath10k_ce_completed_send_next_nolock(ce_diag, 1102 NULL) != 0) { 1103 mdelay(1); 1104 1105 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 1106 ret = -EBUSY; 1107 goto done; 1108 } 1109 } 1110 1111 i = 0; 1112 while (ath10k_ce_completed_recv_next_nolock(ce_diag, 1113 (void **)&buf, 1114 &completed_nbytes) 1115 != 0) { 1116 mdelay(1); 1117 1118 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 1119 ret = -EBUSY; 1120 goto done; 1121 } 1122 } 1123 1124 if (nbytes != completed_nbytes) { 1125 ret = -EIO; 1126 goto done; 1127 } 1128 1129 if (*buf != address) { 1130 ret = -EIO; 1131 goto done; 1132 } 1133 1134 remaining_bytes -= nbytes; 1135 address += nbytes; 1136 ce_data += nbytes; 1137 } 1138 1139 done: 1140 if (data_buf) { 1141 dma_free_coherent(ar->dev, orig_nbytes, data_buf, 1142 ce_data_base); 1143 } 1144 1145 if (ret != 0) 1146 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", 1147 address, ret); 1148 1149 spin_unlock_bh(&ar_pci->ce_lock); 1150 1151 return ret; 1152 } 1153 1154 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) 1155 { 1156 __le32 val = __cpu_to_le32(value); 1157 1158 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); 1159 } 1160 1161 /* Called by lower (CE) layer when a send to Target completes. */ 1162 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state) 1163 { 1164 struct ath10k *ar = ce_state->ar; 1165 struct sk_buff_head list; 1166 struct sk_buff *skb; 1167 1168 __skb_queue_head_init(&list); 1169 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1170 /* no need to call tx completion for NULL pointers */ 1171 if (skb == NULL) 1172 continue; 1173 1174 __skb_queue_tail(&list, skb); 1175 } 1176 1177 while ((skb = __skb_dequeue(&list))) 1178 ath10k_htc_tx_completion_handler(ar, skb); 1179 } 1180 1181 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state, 1182 void (*callback)(struct ath10k *ar, 1183 struct sk_buff *skb)) 1184 { 1185 struct ath10k *ar = ce_state->ar; 1186 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1187 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1188 struct sk_buff *skb; 1189 struct sk_buff_head list; 1190 void *transfer_context; 1191 unsigned int nbytes, max_nbytes; 1192 1193 __skb_queue_head_init(&list); 1194 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 1195 &nbytes) == 0) { 1196 skb = transfer_context; 1197 max_nbytes = skb->len + skb_tailroom(skb); 1198 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1199 max_nbytes, DMA_FROM_DEVICE); 1200 1201 if (unlikely(max_nbytes < nbytes)) { 1202 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1203 nbytes, max_nbytes); 1204 dev_kfree_skb_any(skb); 1205 continue; 1206 } 1207 1208 skb_put(skb, nbytes); 1209 __skb_queue_tail(&list, skb); 1210 } 1211 1212 while ((skb = __skb_dequeue(&list))) { 1213 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1214 ce_state->id, skb->len); 1215 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1216 skb->data, skb->len); 1217 1218 callback(ar, skb); 1219 } 1220 1221 ath10k_pci_rx_post_pipe(pipe_info); 1222 } 1223 1224 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state, 1225 void (*callback)(struct ath10k *ar, 1226 struct sk_buff *skb)) 1227 { 1228 struct ath10k *ar = ce_state->ar; 1229 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1230 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1231 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl; 1232 struct sk_buff *skb; 1233 struct sk_buff_head list; 1234 void *transfer_context; 1235 unsigned int nbytes, max_nbytes, nentries; 1236 int orig_len; 1237 1238 /* No need to aquire ce_lock for CE5, since this is the only place CE5 1239 * is processed other than init and deinit. Before releasing CE5 1240 * buffers, interrupts are disabled. Thus CE5 access is serialized. 1241 */ 1242 __skb_queue_head_init(&list); 1243 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context, 1244 &nbytes) == 0) { 1245 skb = transfer_context; 1246 max_nbytes = skb->len + skb_tailroom(skb); 1247 1248 if (unlikely(max_nbytes < nbytes)) { 1249 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1250 nbytes, max_nbytes); 1251 continue; 1252 } 1253 1254 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1255 max_nbytes, DMA_FROM_DEVICE); 1256 skb_put(skb, nbytes); 1257 __skb_queue_tail(&list, skb); 1258 } 1259 1260 nentries = skb_queue_len(&list); 1261 while ((skb = __skb_dequeue(&list))) { 1262 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1263 ce_state->id, skb->len); 1264 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1265 skb->data, skb->len); 1266 1267 orig_len = skb->len; 1268 callback(ar, skb); 1269 skb_push(skb, orig_len - skb->len); 1270 skb_reset_tail_pointer(skb); 1271 skb_trim(skb, 0); 1272 1273 /*let device gain the buffer again*/ 1274 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1275 skb->len + skb_tailroom(skb), 1276 DMA_FROM_DEVICE); 1277 } 1278 ath10k_ce_rx_update_write_idx(ce_pipe, nentries); 1279 } 1280 1281 /* Called by lower (CE) layer when data is received from the Target. */ 1282 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1283 { 1284 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1285 } 1286 1287 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1288 { 1289 /* CE4 polling needs to be done whenever CE pipe which transports 1290 * HTT Rx (target->host) is processed. 1291 */ 1292 ath10k_ce_per_engine_service(ce_state->ar, 4); 1293 1294 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1295 } 1296 1297 /* Called by lower (CE) layer when data is received from the Target. 1298 * Only 10.4 firmware uses separate CE to transfer pktlog data. 1299 */ 1300 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) 1301 { 1302 ath10k_pci_process_rx_cb(ce_state, 1303 ath10k_htt_rx_pktlog_completion_handler); 1304 } 1305 1306 /* Called by lower (CE) layer when a send to HTT Target completes. */ 1307 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 1308 { 1309 struct ath10k *ar = ce_state->ar; 1310 struct sk_buff *skb; 1311 1312 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1313 /* no need to call tx completion for NULL pointers */ 1314 if (!skb) 1315 continue; 1316 1317 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 1318 skb->len, DMA_TO_DEVICE); 1319 ath10k_htt_hif_tx_complete(ar, skb); 1320 } 1321 } 1322 1323 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) 1324 { 1325 skb_pull(skb, sizeof(struct ath10k_htc_hdr)); 1326 ath10k_htt_t2h_msg_handler(ar, skb); 1327 } 1328 1329 /* Called by lower (CE) layer when HTT data is received from the Target. */ 1330 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state) 1331 { 1332 /* CE4 polling needs to be done whenever CE pipe which transports 1333 * HTT Rx (target->host) is processed. 1334 */ 1335 ath10k_ce_per_engine_service(ce_state->ar, 4); 1336 1337 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver); 1338 } 1339 1340 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 1341 struct ath10k_hif_sg_item *items, int n_items) 1342 { 1343 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1344 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; 1345 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; 1346 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; 1347 unsigned int nentries_mask; 1348 unsigned int sw_index; 1349 unsigned int write_index; 1350 int err, i = 0; 1351 1352 spin_lock_bh(&ar_pci->ce_lock); 1353 1354 nentries_mask = src_ring->nentries_mask; 1355 sw_index = src_ring->sw_index; 1356 write_index = src_ring->write_index; 1357 1358 if (unlikely(CE_RING_DELTA(nentries_mask, 1359 write_index, sw_index - 1) < n_items)) { 1360 err = -ENOBUFS; 1361 goto err; 1362 } 1363 1364 for (i = 0; i < n_items - 1; i++) { 1365 ath10k_dbg(ar, ATH10K_DBG_PCI, 1366 "pci tx item %d paddr 0x%08x len %d n_items %d\n", 1367 i, items[i].paddr, items[i].len, n_items); 1368 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1369 items[i].vaddr, items[i].len); 1370 1371 err = ath10k_ce_send_nolock(ce_pipe, 1372 items[i].transfer_context, 1373 items[i].paddr, 1374 items[i].len, 1375 items[i].transfer_id, 1376 CE_SEND_FLAG_GATHER); 1377 if (err) 1378 goto err; 1379 } 1380 1381 /* `i` is equal to `n_items -1` after for() */ 1382 1383 ath10k_dbg(ar, ATH10K_DBG_PCI, 1384 "pci tx item %d paddr 0x%08x len %d n_items %d\n", 1385 i, items[i].paddr, items[i].len, n_items); 1386 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1387 items[i].vaddr, items[i].len); 1388 1389 err = ath10k_ce_send_nolock(ce_pipe, 1390 items[i].transfer_context, 1391 items[i].paddr, 1392 items[i].len, 1393 items[i].transfer_id, 1394 0); 1395 if (err) 1396 goto err; 1397 1398 spin_unlock_bh(&ar_pci->ce_lock); 1399 return 0; 1400 1401 err: 1402 for (; i > 0; i--) 1403 __ath10k_ce_send_revert(ce_pipe); 1404 1405 spin_unlock_bh(&ar_pci->ce_lock); 1406 return err; 1407 } 1408 1409 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, 1410 size_t buf_len) 1411 { 1412 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); 1413 } 1414 1415 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 1416 { 1417 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1418 1419 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); 1420 1421 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); 1422 } 1423 1424 static void ath10k_pci_dump_registers(struct ath10k *ar, 1425 struct ath10k_fw_crash_data *crash_data) 1426 { 1427 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; 1428 int i, ret; 1429 1430 lockdep_assert_held(&ar->data_lock); 1431 1432 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], 1433 hi_failure_state, 1434 REG_DUMP_COUNT_QCA988X * sizeof(__le32)); 1435 if (ret) { 1436 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); 1437 return; 1438 } 1439 1440 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); 1441 1442 ath10k_err(ar, "firmware register dump:\n"); 1443 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) 1444 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", 1445 i, 1446 __le32_to_cpu(reg_dump_values[i]), 1447 __le32_to_cpu(reg_dump_values[i + 1]), 1448 __le32_to_cpu(reg_dump_values[i + 2]), 1449 __le32_to_cpu(reg_dump_values[i + 3])); 1450 1451 if (!crash_data) 1452 return; 1453 1454 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) 1455 crash_data->registers[i] = reg_dump_values[i]; 1456 } 1457 1458 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) 1459 { 1460 struct ath10k_fw_crash_data *crash_data; 1461 char uuid[50]; 1462 1463 spin_lock_bh(&ar->data_lock); 1464 1465 ar->stats.fw_crash_counter++; 1466 1467 crash_data = ath10k_debug_get_new_fw_crash_data(ar); 1468 1469 if (crash_data) 1470 scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid); 1471 else 1472 scnprintf(uuid, sizeof(uuid), "n/a"); 1473 1474 ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid); 1475 ath10k_print_driver_info(ar); 1476 ath10k_pci_dump_registers(ar, crash_data); 1477 ath10k_ce_dump_registers(ar, crash_data); 1478 1479 spin_unlock_bh(&ar->data_lock); 1480 1481 queue_work(ar->workqueue, &ar->restart_work); 1482 } 1483 1484 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, 1485 int force) 1486 { 1487 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); 1488 1489 if (!force) { 1490 int resources; 1491 /* 1492 * Decide whether to actually poll for completions, or just 1493 * wait for a later chance. 1494 * If there seem to be plenty of resources left, then just wait 1495 * since checking involves reading a CE register, which is a 1496 * relatively expensive operation. 1497 */ 1498 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); 1499 1500 /* 1501 * If at least 50% of the total resources are still available, 1502 * don't bother checking again yet. 1503 */ 1504 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1)) 1505 return; 1506 } 1507 ath10k_ce_per_engine_service(ar, pipe); 1508 } 1509 1510 static void ath10k_pci_rx_retry_sync(struct ath10k *ar) 1511 { 1512 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1513 1514 del_timer_sync(&ar_pci->rx_post_retry); 1515 } 1516 1517 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, 1518 u8 *ul_pipe, u8 *dl_pipe) 1519 { 1520 const struct service_to_pipe *entry; 1521 bool ul_set = false, dl_set = false; 1522 int i; 1523 1524 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); 1525 1526 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { 1527 entry = &target_service_to_ce_map_wlan[i]; 1528 1529 if (__le32_to_cpu(entry->service_id) != service_id) 1530 continue; 1531 1532 switch (__le32_to_cpu(entry->pipedir)) { 1533 case PIPEDIR_NONE: 1534 break; 1535 case PIPEDIR_IN: 1536 WARN_ON(dl_set); 1537 *dl_pipe = __le32_to_cpu(entry->pipenum); 1538 dl_set = true; 1539 break; 1540 case PIPEDIR_OUT: 1541 WARN_ON(ul_set); 1542 *ul_pipe = __le32_to_cpu(entry->pipenum); 1543 ul_set = true; 1544 break; 1545 case PIPEDIR_INOUT: 1546 WARN_ON(dl_set); 1547 WARN_ON(ul_set); 1548 *dl_pipe = __le32_to_cpu(entry->pipenum); 1549 *ul_pipe = __le32_to_cpu(entry->pipenum); 1550 dl_set = true; 1551 ul_set = true; 1552 break; 1553 } 1554 } 1555 1556 if (WARN_ON(!ul_set || !dl_set)) 1557 return -ENOENT; 1558 1559 return 0; 1560 } 1561 1562 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, 1563 u8 *ul_pipe, u8 *dl_pipe) 1564 { 1565 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); 1566 1567 (void)ath10k_pci_hif_map_service_to_pipe(ar, 1568 ATH10K_HTC_SVC_ID_RSVD_CTRL, 1569 ul_pipe, dl_pipe); 1570 } 1571 1572 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) 1573 { 1574 u32 val; 1575 1576 switch (ar->hw_rev) { 1577 case ATH10K_HW_QCA988X: 1578 case ATH10K_HW_QCA9887: 1579 case ATH10K_HW_QCA6174: 1580 case ATH10K_HW_QCA9377: 1581 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1582 CORE_CTRL_ADDRESS); 1583 val &= ~CORE_CTRL_PCIE_REG_31_MASK; 1584 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1585 CORE_CTRL_ADDRESS, val); 1586 break; 1587 case ATH10K_HW_QCA99X0: 1588 case ATH10K_HW_QCA9984: 1589 case ATH10K_HW_QCA9888: 1590 case ATH10K_HW_QCA4019: 1591 /* TODO: Find appropriate register configuration for QCA99X0 1592 * to mask irq/MSI. 1593 */ 1594 break; 1595 } 1596 } 1597 1598 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) 1599 { 1600 u32 val; 1601 1602 switch (ar->hw_rev) { 1603 case ATH10K_HW_QCA988X: 1604 case ATH10K_HW_QCA9887: 1605 case ATH10K_HW_QCA6174: 1606 case ATH10K_HW_QCA9377: 1607 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1608 CORE_CTRL_ADDRESS); 1609 val |= CORE_CTRL_PCIE_REG_31_MASK; 1610 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1611 CORE_CTRL_ADDRESS, val); 1612 break; 1613 case ATH10K_HW_QCA99X0: 1614 case ATH10K_HW_QCA9984: 1615 case ATH10K_HW_QCA9888: 1616 case ATH10K_HW_QCA4019: 1617 /* TODO: Find appropriate register configuration for QCA99X0 1618 * to unmask irq/MSI. 1619 */ 1620 break; 1621 } 1622 } 1623 1624 static void ath10k_pci_irq_disable(struct ath10k *ar) 1625 { 1626 ath10k_ce_disable_interrupts(ar); 1627 ath10k_pci_disable_and_clear_legacy_irq(ar); 1628 ath10k_pci_irq_msi_fw_mask(ar); 1629 } 1630 1631 static void ath10k_pci_irq_sync(struct ath10k *ar) 1632 { 1633 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1634 1635 synchronize_irq(ar_pci->pdev->irq); 1636 } 1637 1638 static void ath10k_pci_irq_enable(struct ath10k *ar) 1639 { 1640 ath10k_ce_enable_interrupts(ar); 1641 ath10k_pci_enable_legacy_irq(ar); 1642 ath10k_pci_irq_msi_fw_unmask(ar); 1643 } 1644 1645 static int ath10k_pci_hif_start(struct ath10k *ar) 1646 { 1647 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1648 1649 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 1650 1651 napi_enable(&ar->napi); 1652 1653 ath10k_pci_irq_enable(ar); 1654 ath10k_pci_rx_post(ar); 1655 1656 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 1657 ar_pci->link_ctl); 1658 1659 return 0; 1660 } 1661 1662 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1663 { 1664 struct ath10k *ar; 1665 struct ath10k_ce_pipe *ce_pipe; 1666 struct ath10k_ce_ring *ce_ring; 1667 struct sk_buff *skb; 1668 int i; 1669 1670 ar = pci_pipe->hif_ce_state; 1671 ce_pipe = pci_pipe->ce_hdl; 1672 ce_ring = ce_pipe->dest_ring; 1673 1674 if (!ce_ring) 1675 return; 1676 1677 if (!pci_pipe->buf_sz) 1678 return; 1679 1680 for (i = 0; i < ce_ring->nentries; i++) { 1681 skb = ce_ring->per_transfer_context[i]; 1682 if (!skb) 1683 continue; 1684 1685 ce_ring->per_transfer_context[i] = NULL; 1686 1687 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1688 skb->len + skb_tailroom(skb), 1689 DMA_FROM_DEVICE); 1690 dev_kfree_skb_any(skb); 1691 } 1692 } 1693 1694 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1695 { 1696 struct ath10k *ar; 1697 struct ath10k_ce_pipe *ce_pipe; 1698 struct ath10k_ce_ring *ce_ring; 1699 struct sk_buff *skb; 1700 int i; 1701 1702 ar = pci_pipe->hif_ce_state; 1703 ce_pipe = pci_pipe->ce_hdl; 1704 ce_ring = ce_pipe->src_ring; 1705 1706 if (!ce_ring) 1707 return; 1708 1709 if (!pci_pipe->buf_sz) 1710 return; 1711 1712 for (i = 0; i < ce_ring->nentries; i++) { 1713 skb = ce_ring->per_transfer_context[i]; 1714 if (!skb) 1715 continue; 1716 1717 ce_ring->per_transfer_context[i] = NULL; 1718 1719 ath10k_htc_tx_completion_handler(ar, skb); 1720 } 1721 } 1722 1723 /* 1724 * Cleanup residual buffers for device shutdown: 1725 * buffers that were enqueued for receive 1726 * buffers that were to be sent 1727 * Note: Buffers that had completed but which were 1728 * not yet processed are on a completion queue. They 1729 * are handled when the completion thread shuts down. 1730 */ 1731 static void ath10k_pci_buffer_cleanup(struct ath10k *ar) 1732 { 1733 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1734 int pipe_num; 1735 1736 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 1737 struct ath10k_pci_pipe *pipe_info; 1738 1739 pipe_info = &ar_pci->pipe_info[pipe_num]; 1740 ath10k_pci_rx_pipe_cleanup(pipe_info); 1741 ath10k_pci_tx_pipe_cleanup(pipe_info); 1742 } 1743 } 1744 1745 void ath10k_pci_ce_deinit(struct ath10k *ar) 1746 { 1747 int i; 1748 1749 for (i = 0; i < CE_COUNT; i++) 1750 ath10k_ce_deinit_pipe(ar, i); 1751 } 1752 1753 void ath10k_pci_flush(struct ath10k *ar) 1754 { 1755 ath10k_pci_rx_retry_sync(ar); 1756 ath10k_pci_buffer_cleanup(ar); 1757 } 1758 1759 static void ath10k_pci_hif_stop(struct ath10k *ar) 1760 { 1761 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1762 unsigned long flags; 1763 1764 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 1765 1766 /* Most likely the device has HTT Rx ring configured. The only way to 1767 * prevent the device from accessing (and possible corrupting) host 1768 * memory is to reset the chip now. 1769 * 1770 * There's also no known way of masking MSI interrupts on the device. 1771 * For ranged MSI the CE-related interrupts can be masked. However 1772 * regardless how many MSI interrupts are assigned the first one 1773 * is always used for firmware indications (crashes) and cannot be 1774 * masked. To prevent the device from asserting the interrupt reset it 1775 * before proceeding with cleanup. 1776 */ 1777 ath10k_pci_safe_chip_reset(ar); 1778 1779 ath10k_pci_irq_disable(ar); 1780 ath10k_pci_irq_sync(ar); 1781 ath10k_pci_flush(ar); 1782 napi_synchronize(&ar->napi); 1783 napi_disable(&ar->napi); 1784 1785 spin_lock_irqsave(&ar_pci->ps_lock, flags); 1786 WARN_ON(ar_pci->ps_wake_refcount > 0); 1787 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 1788 } 1789 1790 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, 1791 void *req, u32 req_len, 1792 void *resp, u32 *resp_len) 1793 { 1794 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1795 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; 1796 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; 1797 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; 1798 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; 1799 dma_addr_t req_paddr = 0; 1800 dma_addr_t resp_paddr = 0; 1801 struct bmi_xfer xfer = {}; 1802 void *treq, *tresp = NULL; 1803 int ret = 0; 1804 1805 might_sleep(); 1806 1807 if (resp && !resp_len) 1808 return -EINVAL; 1809 1810 if (resp && resp_len && *resp_len == 0) 1811 return -EINVAL; 1812 1813 treq = kmemdup(req, req_len, GFP_KERNEL); 1814 if (!treq) 1815 return -ENOMEM; 1816 1817 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); 1818 ret = dma_mapping_error(ar->dev, req_paddr); 1819 if (ret) { 1820 ret = -EIO; 1821 goto err_dma; 1822 } 1823 1824 if (resp && resp_len) { 1825 tresp = kzalloc(*resp_len, GFP_KERNEL); 1826 if (!tresp) { 1827 ret = -ENOMEM; 1828 goto err_req; 1829 } 1830 1831 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, 1832 DMA_FROM_DEVICE); 1833 ret = dma_mapping_error(ar->dev, resp_paddr); 1834 if (ret) { 1835 ret = -EIO; 1836 goto err_req; 1837 } 1838 1839 xfer.wait_for_resp = true; 1840 xfer.resp_len = 0; 1841 1842 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); 1843 } 1844 1845 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); 1846 if (ret) 1847 goto err_resp; 1848 1849 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer); 1850 if (ret) { 1851 u32 unused_buffer; 1852 unsigned int unused_nbytes; 1853 unsigned int unused_id; 1854 1855 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, 1856 &unused_nbytes, &unused_id); 1857 } else { 1858 /* non-zero means we did not time out */ 1859 ret = 0; 1860 } 1861 1862 err_resp: 1863 if (resp) { 1864 u32 unused_buffer; 1865 1866 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); 1867 dma_unmap_single(ar->dev, resp_paddr, 1868 *resp_len, DMA_FROM_DEVICE); 1869 } 1870 err_req: 1871 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); 1872 1873 if (ret == 0 && resp_len) { 1874 *resp_len = min(*resp_len, xfer.resp_len); 1875 memcpy(resp, tresp, xfer.resp_len); 1876 } 1877 err_dma: 1878 kfree(treq); 1879 kfree(tresp); 1880 1881 return ret; 1882 } 1883 1884 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) 1885 { 1886 struct bmi_xfer *xfer; 1887 1888 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer)) 1889 return; 1890 1891 xfer->tx_done = true; 1892 } 1893 1894 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) 1895 { 1896 struct ath10k *ar = ce_state->ar; 1897 struct bmi_xfer *xfer; 1898 unsigned int nbytes; 1899 1900 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, 1901 &nbytes)) 1902 return; 1903 1904 if (WARN_ON_ONCE(!xfer)) 1905 return; 1906 1907 if (!xfer->wait_for_resp) { 1908 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); 1909 return; 1910 } 1911 1912 xfer->resp_len = nbytes; 1913 xfer->rx_done = true; 1914 } 1915 1916 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe, 1917 struct ath10k_ce_pipe *rx_pipe, 1918 struct bmi_xfer *xfer) 1919 { 1920 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; 1921 1922 while (time_before_eq(jiffies, timeout)) { 1923 ath10k_pci_bmi_send_done(tx_pipe); 1924 ath10k_pci_bmi_recv_data(rx_pipe); 1925 1926 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) 1927 return 0; 1928 1929 schedule(); 1930 } 1931 1932 return -ETIMEDOUT; 1933 } 1934 1935 /* 1936 * Send an interrupt to the device to wake up the Target CPU 1937 * so it has an opportunity to notice any changed state. 1938 */ 1939 static int ath10k_pci_wake_target_cpu(struct ath10k *ar) 1940 { 1941 u32 addr, val; 1942 1943 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS; 1944 val = ath10k_pci_read32(ar, addr); 1945 val |= CORE_CTRL_CPU_INTR_MASK; 1946 ath10k_pci_write32(ar, addr, val); 1947 1948 return 0; 1949 } 1950 1951 static int ath10k_pci_get_num_banks(struct ath10k *ar) 1952 { 1953 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1954 1955 switch (ar_pci->pdev->device) { 1956 case QCA988X_2_0_DEVICE_ID: 1957 case QCA99X0_2_0_DEVICE_ID: 1958 case QCA9888_2_0_DEVICE_ID: 1959 case QCA9984_1_0_DEVICE_ID: 1960 case QCA9887_1_0_DEVICE_ID: 1961 return 1; 1962 case QCA6164_2_1_DEVICE_ID: 1963 case QCA6174_2_1_DEVICE_ID: 1964 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) { 1965 case QCA6174_HW_1_0_CHIP_ID_REV: 1966 case QCA6174_HW_1_1_CHIP_ID_REV: 1967 case QCA6174_HW_2_1_CHIP_ID_REV: 1968 case QCA6174_HW_2_2_CHIP_ID_REV: 1969 return 3; 1970 case QCA6174_HW_1_3_CHIP_ID_REV: 1971 return 2; 1972 case QCA6174_HW_3_0_CHIP_ID_REV: 1973 case QCA6174_HW_3_1_CHIP_ID_REV: 1974 case QCA6174_HW_3_2_CHIP_ID_REV: 1975 return 9; 1976 } 1977 break; 1978 case QCA9377_1_0_DEVICE_ID: 1979 return 4; 1980 } 1981 1982 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 1983 return 1; 1984 } 1985 1986 static int ath10k_bus_get_num_banks(struct ath10k *ar) 1987 { 1988 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1989 1990 return ar_pci->bus_ops->get_num_banks(ar); 1991 } 1992 1993 int ath10k_pci_init_config(struct ath10k *ar) 1994 { 1995 u32 interconnect_targ_addr; 1996 u32 pcie_state_targ_addr = 0; 1997 u32 pipe_cfg_targ_addr = 0; 1998 u32 svc_to_pipe_map = 0; 1999 u32 pcie_config_flags = 0; 2000 u32 ealloc_value; 2001 u32 ealloc_targ_addr; 2002 u32 flag2_value; 2003 u32 flag2_targ_addr; 2004 int ret = 0; 2005 2006 /* Download to Target the CE Config and the service-to-CE map */ 2007 interconnect_targ_addr = 2008 host_interest_item_address(HI_ITEM(hi_interconnect_state)); 2009 2010 /* Supply Target-side CE configuration */ 2011 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, 2012 &pcie_state_targ_addr); 2013 if (ret != 0) { 2014 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); 2015 return ret; 2016 } 2017 2018 if (pcie_state_targ_addr == 0) { 2019 ret = -EIO; 2020 ath10k_err(ar, "Invalid pcie state addr\n"); 2021 return ret; 2022 } 2023 2024 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2025 offsetof(struct pcie_state, 2026 pipe_cfg_addr)), 2027 &pipe_cfg_targ_addr); 2028 if (ret != 0) { 2029 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); 2030 return ret; 2031 } 2032 2033 if (pipe_cfg_targ_addr == 0) { 2034 ret = -EIO; 2035 ath10k_err(ar, "Invalid pipe cfg addr\n"); 2036 return ret; 2037 } 2038 2039 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, 2040 target_ce_config_wlan, 2041 sizeof(struct ce_pipe_config) * 2042 NUM_TARGET_CE_CONFIG_WLAN); 2043 2044 if (ret != 0) { 2045 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); 2046 return ret; 2047 } 2048 2049 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2050 offsetof(struct pcie_state, 2051 svc_to_pipe_map)), 2052 &svc_to_pipe_map); 2053 if (ret != 0) { 2054 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); 2055 return ret; 2056 } 2057 2058 if (svc_to_pipe_map == 0) { 2059 ret = -EIO; 2060 ath10k_err(ar, "Invalid svc_to_pipe map\n"); 2061 return ret; 2062 } 2063 2064 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, 2065 target_service_to_ce_map_wlan, 2066 sizeof(target_service_to_ce_map_wlan)); 2067 if (ret != 0) { 2068 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); 2069 return ret; 2070 } 2071 2072 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2073 offsetof(struct pcie_state, 2074 config_flags)), 2075 &pcie_config_flags); 2076 if (ret != 0) { 2077 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); 2078 return ret; 2079 } 2080 2081 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; 2082 2083 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + 2084 offsetof(struct pcie_state, 2085 config_flags)), 2086 pcie_config_flags); 2087 if (ret != 0) { 2088 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); 2089 return ret; 2090 } 2091 2092 /* configure early allocation */ 2093 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); 2094 2095 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); 2096 if (ret != 0) { 2097 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret); 2098 return ret; 2099 } 2100 2101 /* first bank is switched to IRAM */ 2102 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & 2103 HI_EARLY_ALLOC_MAGIC_MASK); 2104 ealloc_value |= ((ath10k_bus_get_num_banks(ar) << 2105 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & 2106 HI_EARLY_ALLOC_IRAM_BANKS_MASK); 2107 2108 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); 2109 if (ret != 0) { 2110 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); 2111 return ret; 2112 } 2113 2114 /* Tell Target to proceed with initialization */ 2115 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); 2116 2117 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); 2118 if (ret != 0) { 2119 ath10k_err(ar, "Failed to get option val: %d\n", ret); 2120 return ret; 2121 } 2122 2123 flag2_value |= HI_OPTION_EARLY_CFG_DONE; 2124 2125 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); 2126 if (ret != 0) { 2127 ath10k_err(ar, "Failed to set option val: %d\n", ret); 2128 return ret; 2129 } 2130 2131 return 0; 2132 } 2133 2134 static void ath10k_pci_override_ce_config(struct ath10k *ar) 2135 { 2136 struct ce_attr *attr; 2137 struct ce_pipe_config *config; 2138 2139 /* For QCA6174 we're overriding the Copy Engine 5 configuration, 2140 * since it is currently used for other feature. 2141 */ 2142 2143 /* Override Host's Copy Engine 5 configuration */ 2144 attr = &host_ce_config_wlan[5]; 2145 attr->src_sz_max = 0; 2146 attr->dest_nentries = 0; 2147 2148 /* Override Target firmware's Copy Engine configuration */ 2149 config = &target_ce_config_wlan[5]; 2150 config->pipedir = __cpu_to_le32(PIPEDIR_OUT); 2151 config->nbytes_max = __cpu_to_le32(2048); 2152 2153 /* Map from service/endpoint to Copy Engine */ 2154 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1); 2155 } 2156 2157 int ath10k_pci_alloc_pipes(struct ath10k *ar) 2158 { 2159 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2160 struct ath10k_pci_pipe *pipe; 2161 int i, ret; 2162 2163 for (i = 0; i < CE_COUNT; i++) { 2164 pipe = &ar_pci->pipe_info[i]; 2165 pipe->ce_hdl = &ar_pci->ce_states[i]; 2166 pipe->pipe_num = i; 2167 pipe->hif_ce_state = ar; 2168 2169 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]); 2170 if (ret) { 2171 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 2172 i, ret); 2173 return ret; 2174 } 2175 2176 /* Last CE is Diagnostic Window */ 2177 if (i == CE_DIAG_PIPE) { 2178 ar_pci->ce_diag = pipe->ce_hdl; 2179 continue; 2180 } 2181 2182 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max); 2183 } 2184 2185 return 0; 2186 } 2187 2188 void ath10k_pci_free_pipes(struct ath10k *ar) 2189 { 2190 int i; 2191 2192 for (i = 0; i < CE_COUNT; i++) 2193 ath10k_ce_free_pipe(ar, i); 2194 } 2195 2196 int ath10k_pci_init_pipes(struct ath10k *ar) 2197 { 2198 int i, ret; 2199 2200 for (i = 0; i < CE_COUNT; i++) { 2201 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]); 2202 if (ret) { 2203 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 2204 i, ret); 2205 return ret; 2206 } 2207 } 2208 2209 return 0; 2210 } 2211 2212 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) 2213 { 2214 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & 2215 FW_IND_EVENT_PENDING; 2216 } 2217 2218 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) 2219 { 2220 u32 val; 2221 2222 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2223 val &= ~FW_IND_EVENT_PENDING; 2224 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); 2225 } 2226 2227 static bool ath10k_pci_has_device_gone(struct ath10k *ar) 2228 { 2229 u32 val; 2230 2231 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2232 return (val == 0xffffffff); 2233 } 2234 2235 /* this function effectively clears target memory controller assert line */ 2236 static void ath10k_pci_warm_reset_si0(struct ath10k *ar) 2237 { 2238 u32 val; 2239 2240 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2241 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2242 val | SOC_RESET_CONTROL_SI0_RST_MASK); 2243 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2244 2245 msleep(10); 2246 2247 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2248 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2249 val & ~SOC_RESET_CONTROL_SI0_RST_MASK); 2250 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2251 2252 msleep(10); 2253 } 2254 2255 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) 2256 { 2257 u32 val; 2258 2259 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); 2260 2261 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2262 SOC_RESET_CONTROL_ADDRESS); 2263 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2264 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); 2265 } 2266 2267 static void ath10k_pci_warm_reset_ce(struct ath10k *ar) 2268 { 2269 u32 val; 2270 2271 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2272 SOC_RESET_CONTROL_ADDRESS); 2273 2274 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2275 val | SOC_RESET_CONTROL_CE_RST_MASK); 2276 msleep(10); 2277 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2278 val & ~SOC_RESET_CONTROL_CE_RST_MASK); 2279 } 2280 2281 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) 2282 { 2283 u32 val; 2284 2285 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2286 SOC_LF_TIMER_CONTROL0_ADDRESS); 2287 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + 2288 SOC_LF_TIMER_CONTROL0_ADDRESS, 2289 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); 2290 } 2291 2292 static int ath10k_pci_warm_reset(struct ath10k *ar) 2293 { 2294 int ret; 2295 2296 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); 2297 2298 spin_lock_bh(&ar->data_lock); 2299 ar->stats.fw_warm_reset_counter++; 2300 spin_unlock_bh(&ar->data_lock); 2301 2302 ath10k_pci_irq_disable(ar); 2303 2304 /* Make sure the target CPU is not doing anything dangerous, e.g. if it 2305 * were to access copy engine while host performs copy engine reset 2306 * then it is possible for the device to confuse pci-e controller to 2307 * the point of bringing host system to a complete stop (i.e. hang). 2308 */ 2309 ath10k_pci_warm_reset_si0(ar); 2310 ath10k_pci_warm_reset_cpu(ar); 2311 ath10k_pci_init_pipes(ar); 2312 ath10k_pci_wait_for_target_init(ar); 2313 2314 ath10k_pci_warm_reset_clear_lf(ar); 2315 ath10k_pci_warm_reset_ce(ar); 2316 ath10k_pci_warm_reset_cpu(ar); 2317 ath10k_pci_init_pipes(ar); 2318 2319 ret = ath10k_pci_wait_for_target_init(ar); 2320 if (ret) { 2321 ath10k_warn(ar, "failed to wait for target init: %d\n", ret); 2322 return ret; 2323 } 2324 2325 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); 2326 2327 return 0; 2328 } 2329 2330 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) 2331 { 2332 ath10k_pci_irq_disable(ar); 2333 return ath10k_pci_qca99x0_chip_reset(ar); 2334 } 2335 2336 static int ath10k_pci_safe_chip_reset(struct ath10k *ar) 2337 { 2338 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2339 2340 if (!ar_pci->pci_soft_reset) 2341 return -ENOTSUPP; 2342 2343 return ar_pci->pci_soft_reset(ar); 2344 } 2345 2346 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) 2347 { 2348 int i, ret; 2349 u32 val; 2350 2351 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); 2352 2353 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. 2354 * It is thus preferred to use warm reset which is safer but may not be 2355 * able to recover the device from all possible fail scenarios. 2356 * 2357 * Warm reset doesn't always work on first try so attempt it a few 2358 * times before giving up. 2359 */ 2360 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { 2361 ret = ath10k_pci_warm_reset(ar); 2362 if (ret) { 2363 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", 2364 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, 2365 ret); 2366 continue; 2367 } 2368 2369 /* FIXME: Sometimes copy engine doesn't recover after warm 2370 * reset. In most cases this needs cold reset. In some of these 2371 * cases the device is in such a state that a cold reset may 2372 * lock up the host. 2373 * 2374 * Reading any host interest register via copy engine is 2375 * sufficient to verify if device is capable of booting 2376 * firmware blob. 2377 */ 2378 ret = ath10k_pci_init_pipes(ar); 2379 if (ret) { 2380 ath10k_warn(ar, "failed to init copy engine: %d\n", 2381 ret); 2382 continue; 2383 } 2384 2385 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, 2386 &val); 2387 if (ret) { 2388 ath10k_warn(ar, "failed to poke copy engine: %d\n", 2389 ret); 2390 continue; 2391 } 2392 2393 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); 2394 return 0; 2395 } 2396 2397 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { 2398 ath10k_warn(ar, "refusing cold reset as requested\n"); 2399 return -EPERM; 2400 } 2401 2402 ret = ath10k_pci_cold_reset(ar); 2403 if (ret) { 2404 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2405 return ret; 2406 } 2407 2408 ret = ath10k_pci_wait_for_target_init(ar); 2409 if (ret) { 2410 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2411 ret); 2412 return ret; 2413 } 2414 2415 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); 2416 2417 return 0; 2418 } 2419 2420 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) 2421 { 2422 int ret; 2423 2424 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); 2425 2426 /* FIXME: QCA6174 requires cold + warm reset to work. */ 2427 2428 ret = ath10k_pci_cold_reset(ar); 2429 if (ret) { 2430 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2431 return ret; 2432 } 2433 2434 ret = ath10k_pci_wait_for_target_init(ar); 2435 if (ret) { 2436 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2437 ret); 2438 return ret; 2439 } 2440 2441 ret = ath10k_pci_warm_reset(ar); 2442 if (ret) { 2443 ath10k_warn(ar, "failed to warm reset: %d\n", ret); 2444 return ret; 2445 } 2446 2447 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); 2448 2449 return 0; 2450 } 2451 2452 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) 2453 { 2454 int ret; 2455 2456 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n"); 2457 2458 ret = ath10k_pci_cold_reset(ar); 2459 if (ret) { 2460 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2461 return ret; 2462 } 2463 2464 ret = ath10k_pci_wait_for_target_init(ar); 2465 if (ret) { 2466 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2467 ret); 2468 return ret; 2469 } 2470 2471 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n"); 2472 2473 return 0; 2474 } 2475 2476 static int ath10k_pci_chip_reset(struct ath10k *ar) 2477 { 2478 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2479 2480 if (WARN_ON(!ar_pci->pci_hard_reset)) 2481 return -ENOTSUPP; 2482 2483 return ar_pci->pci_hard_reset(ar); 2484 } 2485 2486 static int ath10k_pci_hif_power_up(struct ath10k *ar) 2487 { 2488 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2489 int ret; 2490 2491 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); 2492 2493 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2494 &ar_pci->link_ctl); 2495 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2496 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 2497 2498 /* 2499 * Bring the target up cleanly. 2500 * 2501 * The target may be in an undefined state with an AUX-powered Target 2502 * and a Host in WoW mode. If the Host crashes, loses power, or is 2503 * restarted (without unloading the driver) then the Target is left 2504 * (aux) powered and running. On a subsequent driver load, the Target 2505 * is in an unexpected state. We try to catch that here in order to 2506 * reset the Target and retry the probe. 2507 */ 2508 ret = ath10k_pci_chip_reset(ar); 2509 if (ret) { 2510 if (ath10k_pci_has_fw_crashed(ar)) { 2511 ath10k_warn(ar, "firmware crashed during chip reset\n"); 2512 ath10k_pci_fw_crashed_clear(ar); 2513 ath10k_pci_fw_crashed_dump(ar); 2514 } 2515 2516 ath10k_err(ar, "failed to reset chip: %d\n", ret); 2517 goto err_sleep; 2518 } 2519 2520 ret = ath10k_pci_init_pipes(ar); 2521 if (ret) { 2522 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 2523 goto err_sleep; 2524 } 2525 2526 ret = ath10k_pci_init_config(ar); 2527 if (ret) { 2528 ath10k_err(ar, "failed to setup init config: %d\n", ret); 2529 goto err_ce; 2530 } 2531 2532 ret = ath10k_pci_wake_target_cpu(ar); 2533 if (ret) { 2534 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 2535 goto err_ce; 2536 } 2537 2538 return 0; 2539 2540 err_ce: 2541 ath10k_pci_ce_deinit(ar); 2542 2543 err_sleep: 2544 return ret; 2545 } 2546 2547 void ath10k_pci_hif_power_down(struct ath10k *ar) 2548 { 2549 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 2550 2551 /* Currently hif_power_up performs effectively a reset and hif_stop 2552 * resets the chip as well so there's no point in resetting here. 2553 */ 2554 } 2555 2556 #ifdef CONFIG_PM 2557 2558 static int ath10k_pci_hif_suspend(struct ath10k *ar) 2559 { 2560 /* The grace timer can still be counting down and ar->ps_awake be true. 2561 * It is known that the device may be asleep after resuming regardless 2562 * of the SoC powersave state before suspending. Hence make sure the 2563 * device is asleep before proceeding. 2564 */ 2565 ath10k_pci_sleep_sync(ar); 2566 2567 return 0; 2568 } 2569 2570 static int ath10k_pci_hif_resume(struct ath10k *ar) 2571 { 2572 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2573 struct pci_dev *pdev = ar_pci->pdev; 2574 u32 val; 2575 int ret = 0; 2576 2577 ret = ath10k_pci_force_wake(ar); 2578 if (ret) { 2579 ath10k_err(ar, "failed to wake up target: %d\n", ret); 2580 return ret; 2581 } 2582 2583 /* Suspend/Resume resets the PCI configuration space, so we have to 2584 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries 2585 * from interfering with C3 CPU state. pci_restore_state won't help 2586 * here since it only restores the first 64 bytes pci config header. 2587 */ 2588 pci_read_config_dword(pdev, 0x40, &val); 2589 if ((val & 0x0000ff00) != 0) 2590 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 2591 2592 return ret; 2593 } 2594 #endif 2595 2596 static bool ath10k_pci_validate_cal(void *data, size_t size) 2597 { 2598 __le16 *cal_words = data; 2599 u16 checksum = 0; 2600 size_t i; 2601 2602 if (size % 2 != 0) 2603 return false; 2604 2605 for (i = 0; i < size / 2; i++) 2606 checksum ^= le16_to_cpu(cal_words[i]); 2607 2608 return checksum == 0xffff; 2609 } 2610 2611 static void ath10k_pci_enable_eeprom(struct ath10k *ar) 2612 { 2613 /* Enable SI clock */ 2614 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0); 2615 2616 /* Configure GPIOs for I2C operation */ 2617 ath10k_pci_write32(ar, 2618 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2619 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN, 2620 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG, 2621 GPIO_PIN0_CONFIG) | 2622 SM(1, GPIO_PIN0_PAD_PULL)); 2623 2624 ath10k_pci_write32(ar, 2625 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2626 4 * QCA9887_1_0_SI_CLK_GPIO_PIN, 2627 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) | 2628 SM(1, GPIO_PIN0_PAD_PULL)); 2629 2630 ath10k_pci_write32(ar, 2631 GPIO_BASE_ADDRESS + 2632 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS, 2633 1u << QCA9887_1_0_SI_CLK_GPIO_PIN); 2634 2635 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */ 2636 ath10k_pci_write32(ar, 2637 SI_BASE_ADDRESS + SI_CONFIG_OFFSET, 2638 SM(1, SI_CONFIG_ERR_INT) | 2639 SM(1, SI_CONFIG_BIDIR_OD_DATA) | 2640 SM(1, SI_CONFIG_I2C) | 2641 SM(1, SI_CONFIG_POS_SAMPLE) | 2642 SM(1, SI_CONFIG_INACTIVE_DATA) | 2643 SM(1, SI_CONFIG_INACTIVE_CLK) | 2644 SM(8, SI_CONFIG_DIVIDER)); 2645 } 2646 2647 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out) 2648 { 2649 u32 reg; 2650 int wait_limit; 2651 2652 /* set device select byte and for the read operation */ 2653 reg = QCA9887_EEPROM_SELECT_READ | 2654 SM(addr, QCA9887_EEPROM_ADDR_LO) | 2655 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI); 2656 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg); 2657 2658 /* write transmit data, transfer length, and START bit */ 2659 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, 2660 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) | 2661 SM(4, SI_CS_TX_CNT)); 2662 2663 /* wait max 1 sec */ 2664 wait_limit = 100000; 2665 2666 /* wait for SI_CS_DONE_INT */ 2667 do { 2668 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET); 2669 if (MS(reg, SI_CS_DONE_INT)) 2670 break; 2671 2672 wait_limit--; 2673 udelay(10); 2674 } while (wait_limit > 0); 2675 2676 if (!MS(reg, SI_CS_DONE_INT)) { 2677 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n", 2678 addr); 2679 return -ETIMEDOUT; 2680 } 2681 2682 /* clear SI_CS_DONE_INT */ 2683 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg); 2684 2685 if (MS(reg, SI_CS_DONE_ERR)) { 2686 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr); 2687 return -EIO; 2688 } 2689 2690 /* extract receive data */ 2691 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET); 2692 *out = reg; 2693 2694 return 0; 2695 } 2696 2697 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data, 2698 size_t *data_len) 2699 { 2700 u8 *caldata = NULL; 2701 size_t calsize, i; 2702 int ret; 2703 2704 if (!QCA_REV_9887(ar)) 2705 return -EOPNOTSUPP; 2706 2707 calsize = ar->hw_params.cal_data_len; 2708 caldata = kmalloc(calsize, GFP_KERNEL); 2709 if (!caldata) 2710 return -ENOMEM; 2711 2712 ath10k_pci_enable_eeprom(ar); 2713 2714 for (i = 0; i < calsize; i++) { 2715 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]); 2716 if (ret) 2717 goto err_free; 2718 } 2719 2720 if (!ath10k_pci_validate_cal(caldata, calsize)) 2721 goto err_free; 2722 2723 *data = caldata; 2724 *data_len = calsize; 2725 2726 return 0; 2727 2728 err_free: 2729 kfree(caldata); 2730 2731 return -EINVAL; 2732 } 2733 2734 static const struct ath10k_hif_ops ath10k_pci_hif_ops = { 2735 .tx_sg = ath10k_pci_hif_tx_sg, 2736 .diag_read = ath10k_pci_hif_diag_read, 2737 .diag_write = ath10k_pci_diag_write_mem, 2738 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 2739 .start = ath10k_pci_hif_start, 2740 .stop = ath10k_pci_hif_stop, 2741 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 2742 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 2743 .send_complete_check = ath10k_pci_hif_send_complete_check, 2744 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 2745 .power_up = ath10k_pci_hif_power_up, 2746 .power_down = ath10k_pci_hif_power_down, 2747 .read32 = ath10k_pci_read32, 2748 .write32 = ath10k_pci_write32, 2749 #ifdef CONFIG_PM 2750 .suspend = ath10k_pci_hif_suspend, 2751 .resume = ath10k_pci_hif_resume, 2752 #endif 2753 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom, 2754 }; 2755 2756 /* 2757 * Top-level interrupt handler for all PCI interrupts from a Target. 2758 * When a block of MSI interrupts is allocated, this top-level handler 2759 * is not used; instead, we directly call the correct sub-handler. 2760 */ 2761 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) 2762 { 2763 struct ath10k *ar = arg; 2764 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2765 int ret; 2766 2767 if (ath10k_pci_has_device_gone(ar)) 2768 return IRQ_NONE; 2769 2770 ret = ath10k_pci_force_wake(ar); 2771 if (ret) { 2772 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret); 2773 return IRQ_NONE; 2774 } 2775 2776 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) && 2777 !ath10k_pci_irq_pending(ar)) 2778 return IRQ_NONE; 2779 2780 ath10k_pci_disable_and_clear_legacy_irq(ar); 2781 ath10k_pci_irq_msi_fw_mask(ar); 2782 napi_schedule(&ar->napi); 2783 2784 return IRQ_HANDLED; 2785 } 2786 2787 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget) 2788 { 2789 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 2790 int done = 0; 2791 2792 if (ath10k_pci_has_fw_crashed(ar)) { 2793 ath10k_pci_fw_crashed_clear(ar); 2794 ath10k_pci_fw_crashed_dump(ar); 2795 napi_complete(ctx); 2796 return done; 2797 } 2798 2799 ath10k_ce_per_engine_service_any(ar); 2800 2801 done = ath10k_htt_txrx_compl_task(ar, budget); 2802 2803 if (done < budget) { 2804 napi_complete_done(ctx, done); 2805 /* In case of MSI, it is possible that interrupts are received 2806 * while NAPI poll is inprogress. So pending interrupts that are 2807 * received after processing all copy engine pipes by NAPI poll 2808 * will not be handled again. This is causing failure to 2809 * complete boot sequence in x86 platform. So before enabling 2810 * interrupts safer to check for pending interrupts for 2811 * immediate servicing. 2812 */ 2813 if (CE_INTERRUPT_SUMMARY(ar)) { 2814 napi_reschedule(ctx); 2815 goto out; 2816 } 2817 ath10k_pci_enable_legacy_irq(ar); 2818 ath10k_pci_irq_msi_fw_unmask(ar); 2819 } 2820 2821 out: 2822 return done; 2823 } 2824 2825 static int ath10k_pci_request_irq_msi(struct ath10k *ar) 2826 { 2827 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2828 int ret; 2829 2830 ret = request_irq(ar_pci->pdev->irq, 2831 ath10k_pci_interrupt_handler, 2832 IRQF_SHARED, "ath10k_pci", ar); 2833 if (ret) { 2834 ath10k_warn(ar, "failed to request MSI irq %d: %d\n", 2835 ar_pci->pdev->irq, ret); 2836 return ret; 2837 } 2838 2839 return 0; 2840 } 2841 2842 static int ath10k_pci_request_irq_legacy(struct ath10k *ar) 2843 { 2844 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2845 int ret; 2846 2847 ret = request_irq(ar_pci->pdev->irq, 2848 ath10k_pci_interrupt_handler, 2849 IRQF_SHARED, "ath10k_pci", ar); 2850 if (ret) { 2851 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 2852 ar_pci->pdev->irq, ret); 2853 return ret; 2854 } 2855 2856 return 0; 2857 } 2858 2859 static int ath10k_pci_request_irq(struct ath10k *ar) 2860 { 2861 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2862 2863 switch (ar_pci->oper_irq_mode) { 2864 case ATH10K_PCI_IRQ_LEGACY: 2865 return ath10k_pci_request_irq_legacy(ar); 2866 case ATH10K_PCI_IRQ_MSI: 2867 return ath10k_pci_request_irq_msi(ar); 2868 default: 2869 return -EINVAL; 2870 } 2871 } 2872 2873 static void ath10k_pci_free_irq(struct ath10k *ar) 2874 { 2875 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2876 2877 free_irq(ar_pci->pdev->irq, ar); 2878 } 2879 2880 void ath10k_pci_init_napi(struct ath10k *ar) 2881 { 2882 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll, 2883 ATH10K_NAPI_BUDGET); 2884 } 2885 2886 static int ath10k_pci_init_irq(struct ath10k *ar) 2887 { 2888 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2889 int ret; 2890 2891 ath10k_pci_init_napi(ar); 2892 2893 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) 2894 ath10k_info(ar, "limiting irq mode to: %d\n", 2895 ath10k_pci_irq_mode); 2896 2897 /* Try MSI */ 2898 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) { 2899 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI; 2900 ret = pci_enable_msi(ar_pci->pdev); 2901 if (ret == 0) 2902 return 0; 2903 2904 /* fall-through */ 2905 } 2906 2907 /* Try legacy irq 2908 * 2909 * A potential race occurs here: The CORE_BASE write 2910 * depends on target correctly decoding AXI address but 2911 * host won't know when target writes BAR to CORE_CTRL. 2912 * This write might get lost if target has NOT written BAR. 2913 * For now, fix the race by repeating the write in below 2914 * synchronization checking. 2915 */ 2916 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; 2917 2918 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 2919 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 2920 2921 return 0; 2922 } 2923 2924 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) 2925 { 2926 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 2927 0); 2928 } 2929 2930 static int ath10k_pci_deinit_irq(struct ath10k *ar) 2931 { 2932 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2933 2934 switch (ar_pci->oper_irq_mode) { 2935 case ATH10K_PCI_IRQ_LEGACY: 2936 ath10k_pci_deinit_irq_legacy(ar); 2937 break; 2938 default: 2939 pci_disable_msi(ar_pci->pdev); 2940 break; 2941 } 2942 2943 return 0; 2944 } 2945 2946 int ath10k_pci_wait_for_target_init(struct ath10k *ar) 2947 { 2948 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2949 unsigned long timeout; 2950 u32 val; 2951 2952 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); 2953 2954 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); 2955 2956 do { 2957 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2958 2959 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", 2960 val); 2961 2962 /* target should never return this */ 2963 if (val == 0xffffffff) 2964 continue; 2965 2966 /* the device has crashed so don't bother trying anymore */ 2967 if (val & FW_IND_EVENT_PENDING) 2968 break; 2969 2970 if (val & FW_IND_INITIALIZED) 2971 break; 2972 2973 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) 2974 /* Fix potential race by repeating CORE_BASE writes */ 2975 ath10k_pci_enable_legacy_irq(ar); 2976 2977 mdelay(10); 2978 } while (time_before(jiffies, timeout)); 2979 2980 ath10k_pci_disable_and_clear_legacy_irq(ar); 2981 ath10k_pci_irq_msi_fw_mask(ar); 2982 2983 if (val == 0xffffffff) { 2984 ath10k_err(ar, "failed to read device register, device is gone\n"); 2985 return -EIO; 2986 } 2987 2988 if (val & FW_IND_EVENT_PENDING) { 2989 ath10k_warn(ar, "device has crashed during init\n"); 2990 return -ECOMM; 2991 } 2992 2993 if (!(val & FW_IND_INITIALIZED)) { 2994 ath10k_err(ar, "failed to receive initialized event from target: %08x\n", 2995 val); 2996 return -ETIMEDOUT; 2997 } 2998 2999 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); 3000 return 0; 3001 } 3002 3003 static int ath10k_pci_cold_reset(struct ath10k *ar) 3004 { 3005 u32 val; 3006 3007 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); 3008 3009 spin_lock_bh(&ar->data_lock); 3010 3011 ar->stats.fw_cold_reset_counter++; 3012 3013 spin_unlock_bh(&ar->data_lock); 3014 3015 /* Put Target, including PCIe, into RESET. */ 3016 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); 3017 val |= 1; 3018 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3019 3020 /* After writing into SOC_GLOBAL_RESET to put device into 3021 * reset and pulling out of reset pcie may not be stable 3022 * for any immediate pcie register access and cause bus error, 3023 * add delay before any pcie access request to fix this issue. 3024 */ 3025 msleep(20); 3026 3027 /* Pull Target, including PCIe, out of RESET. */ 3028 val &= ~1; 3029 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3030 3031 msleep(20); 3032 3033 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); 3034 3035 return 0; 3036 } 3037 3038 static int ath10k_pci_claim(struct ath10k *ar) 3039 { 3040 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3041 struct pci_dev *pdev = ar_pci->pdev; 3042 int ret; 3043 3044 pci_set_drvdata(pdev, ar); 3045 3046 ret = pci_enable_device(pdev); 3047 if (ret) { 3048 ath10k_err(ar, "failed to enable pci device: %d\n", ret); 3049 return ret; 3050 } 3051 3052 ret = pci_request_region(pdev, BAR_NUM, "ath"); 3053 if (ret) { 3054 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, 3055 ret); 3056 goto err_device; 3057 } 3058 3059 /* Target expects 32 bit DMA. Enforce it. */ 3060 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3061 if (ret) { 3062 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); 3063 goto err_region; 3064 } 3065 3066 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3067 if (ret) { 3068 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n", 3069 ret); 3070 goto err_region; 3071 } 3072 3073 pci_set_master(pdev); 3074 3075 /* Arrange for access to Target SoC registers. */ 3076 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); 3077 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); 3078 if (!ar_pci->mem) { 3079 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); 3080 ret = -EIO; 3081 goto err_master; 3082 } 3083 3084 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem); 3085 return 0; 3086 3087 err_master: 3088 pci_clear_master(pdev); 3089 3090 err_region: 3091 pci_release_region(pdev, BAR_NUM); 3092 3093 err_device: 3094 pci_disable_device(pdev); 3095 3096 return ret; 3097 } 3098 3099 static void ath10k_pci_release(struct ath10k *ar) 3100 { 3101 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3102 struct pci_dev *pdev = ar_pci->pdev; 3103 3104 pci_iounmap(pdev, ar_pci->mem); 3105 pci_release_region(pdev, BAR_NUM); 3106 pci_clear_master(pdev); 3107 pci_disable_device(pdev); 3108 } 3109 3110 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) 3111 { 3112 const struct ath10k_pci_supp_chip *supp_chip; 3113 int i; 3114 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); 3115 3116 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { 3117 supp_chip = &ath10k_pci_supp_chips[i]; 3118 3119 if (supp_chip->dev_id == dev_id && 3120 supp_chip->rev_id == rev_id) 3121 return true; 3122 } 3123 3124 return false; 3125 } 3126 3127 int ath10k_pci_setup_resource(struct ath10k *ar) 3128 { 3129 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3130 int ret; 3131 3132 spin_lock_init(&ar_pci->ce_lock); 3133 spin_lock_init(&ar_pci->ps_lock); 3134 3135 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 3136 (unsigned long)ar); 3137 3138 if (QCA_REV_6174(ar) || QCA_REV_9377(ar)) 3139 ath10k_pci_override_ce_config(ar); 3140 3141 ret = ath10k_pci_alloc_pipes(ar); 3142 if (ret) { 3143 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", 3144 ret); 3145 return ret; 3146 } 3147 3148 return 0; 3149 } 3150 3151 void ath10k_pci_release_resource(struct ath10k *ar) 3152 { 3153 ath10k_pci_rx_retry_sync(ar); 3154 netif_napi_del(&ar->napi); 3155 ath10k_pci_ce_deinit(ar); 3156 ath10k_pci_free_pipes(ar); 3157 } 3158 3159 static const struct ath10k_bus_ops ath10k_pci_bus_ops = { 3160 .read32 = ath10k_bus_pci_read32, 3161 .write32 = ath10k_bus_pci_write32, 3162 .get_num_banks = ath10k_pci_get_num_banks, 3163 }; 3164 3165 static int ath10k_pci_probe(struct pci_dev *pdev, 3166 const struct pci_device_id *pci_dev) 3167 { 3168 int ret = 0; 3169 struct ath10k *ar; 3170 struct ath10k_pci *ar_pci; 3171 enum ath10k_hw_rev hw_rev; 3172 u32 chip_id; 3173 bool pci_ps; 3174 int (*pci_soft_reset)(struct ath10k *ar); 3175 int (*pci_hard_reset)(struct ath10k *ar); 3176 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); 3177 3178 switch (pci_dev->device) { 3179 case QCA988X_2_0_DEVICE_ID: 3180 hw_rev = ATH10K_HW_QCA988X; 3181 pci_ps = false; 3182 pci_soft_reset = ath10k_pci_warm_reset; 3183 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3184 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3185 break; 3186 case QCA9887_1_0_DEVICE_ID: 3187 hw_rev = ATH10K_HW_QCA9887; 3188 pci_ps = false; 3189 pci_soft_reset = ath10k_pci_warm_reset; 3190 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3191 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3192 break; 3193 case QCA6164_2_1_DEVICE_ID: 3194 case QCA6174_2_1_DEVICE_ID: 3195 hw_rev = ATH10K_HW_QCA6174; 3196 pci_ps = true; 3197 pci_soft_reset = ath10k_pci_warm_reset; 3198 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3199 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3200 break; 3201 case QCA99X0_2_0_DEVICE_ID: 3202 hw_rev = ATH10K_HW_QCA99X0; 3203 pci_ps = false; 3204 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3205 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3206 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3207 break; 3208 case QCA9984_1_0_DEVICE_ID: 3209 hw_rev = ATH10K_HW_QCA9984; 3210 pci_ps = false; 3211 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3212 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3213 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3214 break; 3215 case QCA9888_2_0_DEVICE_ID: 3216 hw_rev = ATH10K_HW_QCA9888; 3217 pci_ps = false; 3218 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3219 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3220 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3221 break; 3222 case QCA9377_1_0_DEVICE_ID: 3223 hw_rev = ATH10K_HW_QCA9377; 3224 pci_ps = true; 3225 pci_soft_reset = NULL; 3226 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3227 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3228 break; 3229 default: 3230 WARN_ON(1); 3231 return -ENOTSUPP; 3232 } 3233 3234 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, 3235 hw_rev, &ath10k_pci_hif_ops); 3236 if (!ar) { 3237 dev_err(&pdev->dev, "failed to allocate core\n"); 3238 return -ENOMEM; 3239 } 3240 3241 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 3242 pdev->vendor, pdev->device, 3243 pdev->subsystem_vendor, pdev->subsystem_device); 3244 3245 ar_pci = ath10k_pci_priv(ar); 3246 ar_pci->pdev = pdev; 3247 ar_pci->dev = &pdev->dev; 3248 ar_pci->ar = ar; 3249 ar->dev_id = pci_dev->device; 3250 ar_pci->pci_ps = pci_ps; 3251 ar_pci->bus_ops = &ath10k_pci_bus_ops; 3252 ar_pci->pci_soft_reset = pci_soft_reset; 3253 ar_pci->pci_hard_reset = pci_hard_reset; 3254 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; 3255 3256 ar->id.vendor = pdev->vendor; 3257 ar->id.device = pdev->device; 3258 ar->id.subsystem_vendor = pdev->subsystem_vendor; 3259 ar->id.subsystem_device = pdev->subsystem_device; 3260 3261 setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer, 3262 (unsigned long)ar); 3263 3264 ret = ath10k_pci_setup_resource(ar); 3265 if (ret) { 3266 ath10k_err(ar, "failed to setup resource: %d\n", ret); 3267 goto err_core_destroy; 3268 } 3269 3270 ret = ath10k_pci_claim(ar); 3271 if (ret) { 3272 ath10k_err(ar, "failed to claim device: %d\n", ret); 3273 goto err_free_pipes; 3274 } 3275 3276 ret = ath10k_pci_force_wake(ar); 3277 if (ret) { 3278 ath10k_warn(ar, "failed to wake up device : %d\n", ret); 3279 goto err_sleep; 3280 } 3281 3282 ath10k_pci_ce_deinit(ar); 3283 ath10k_pci_irq_disable(ar); 3284 3285 ret = ath10k_pci_init_irq(ar); 3286 if (ret) { 3287 ath10k_err(ar, "failed to init irqs: %d\n", ret); 3288 goto err_sleep; 3289 } 3290 3291 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n", 3292 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode, 3293 ath10k_pci_irq_mode, ath10k_pci_reset_mode); 3294 3295 ret = ath10k_pci_request_irq(ar); 3296 if (ret) { 3297 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 3298 goto err_deinit_irq; 3299 } 3300 3301 ret = ath10k_pci_chip_reset(ar); 3302 if (ret) { 3303 ath10k_err(ar, "failed to reset chip: %d\n", ret); 3304 goto err_free_irq; 3305 } 3306 3307 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 3308 if (chip_id == 0xffffffff) { 3309 ath10k_err(ar, "failed to get chip id\n"); 3310 goto err_free_irq; 3311 } 3312 3313 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) { 3314 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", 3315 pdev->device, chip_id); 3316 goto err_free_irq; 3317 } 3318 3319 ret = ath10k_core_register(ar, chip_id); 3320 if (ret) { 3321 ath10k_err(ar, "failed to register driver core: %d\n", ret); 3322 goto err_free_irq; 3323 } 3324 3325 return 0; 3326 3327 err_free_irq: 3328 ath10k_pci_free_irq(ar); 3329 ath10k_pci_rx_retry_sync(ar); 3330 3331 err_deinit_irq: 3332 ath10k_pci_deinit_irq(ar); 3333 3334 err_sleep: 3335 ath10k_pci_sleep_sync(ar); 3336 ath10k_pci_release(ar); 3337 3338 err_free_pipes: 3339 ath10k_pci_free_pipes(ar); 3340 3341 err_core_destroy: 3342 ath10k_core_destroy(ar); 3343 3344 return ret; 3345 } 3346 3347 static void ath10k_pci_remove(struct pci_dev *pdev) 3348 { 3349 struct ath10k *ar = pci_get_drvdata(pdev); 3350 struct ath10k_pci *ar_pci; 3351 3352 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); 3353 3354 if (!ar) 3355 return; 3356 3357 ar_pci = ath10k_pci_priv(ar); 3358 3359 if (!ar_pci) 3360 return; 3361 3362 ath10k_core_unregister(ar); 3363 ath10k_pci_free_irq(ar); 3364 ath10k_pci_deinit_irq(ar); 3365 ath10k_pci_release_resource(ar); 3366 ath10k_pci_sleep_sync(ar); 3367 ath10k_pci_release(ar); 3368 ath10k_core_destroy(ar); 3369 } 3370 3371 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); 3372 3373 static struct pci_driver ath10k_pci_driver = { 3374 .name = "ath10k_pci", 3375 .id_table = ath10k_pci_id_table, 3376 .probe = ath10k_pci_probe, 3377 .remove = ath10k_pci_remove, 3378 }; 3379 3380 static int __init ath10k_pci_init(void) 3381 { 3382 int ret; 3383 3384 ret = pci_register_driver(&ath10k_pci_driver); 3385 if (ret) 3386 printk(KERN_ERR "failed to register ath10k pci driver: %d\n", 3387 ret); 3388 3389 ret = ath10k_ahb_init(); 3390 if (ret) 3391 printk(KERN_ERR "ahb init failed: %d\n", ret); 3392 3393 return ret; 3394 } 3395 module_init(ath10k_pci_init); 3396 3397 static void __exit ath10k_pci_exit(void) 3398 { 3399 pci_unregister_driver(&ath10k_pci_driver); 3400 ath10k_ahb_exit(); 3401 } 3402 3403 module_exit(ath10k_pci_exit); 3404 3405 MODULE_AUTHOR("Qualcomm Atheros"); 3406 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices"); 3407 MODULE_LICENSE("Dual BSD/GPL"); 3408 3409 /* QCA988x 2.0 firmware files */ 3410 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); 3411 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); 3412 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3413 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3414 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); 3415 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3416 3417 /* QCA9887 1.0 firmware files */ 3418 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3419 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE); 3420 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3421 3422 /* QCA6174 2.1 firmware files */ 3423 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE); 3424 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE); 3425 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE); 3426 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3427 3428 /* QCA6174 3.1 firmware files */ 3429 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3430 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3431 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3432 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE); 3433 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3434 3435 /* QCA9377 1.0 firmware files */ 3436 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3437 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE); 3438