1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HW_H_ 19 #define _HW_H_ 20 21 #include "targaddrs.h" 22 23 #define ATH10K_FW_DIR "ath10k" 24 25 /* QCA988X 1.0 definitions (unsupported) */ 26 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 27 28 /* QCA988X 2.0 definitions */ 29 #define QCA988X_HW_2_0_VERSION 0x4100016c 30 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 31 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 32 #define QCA988X_HW_2_0_FW_FILE "firmware.bin" 33 #define QCA988X_HW_2_0_OTP_FILE "otp.bin" 34 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 35 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 36 37 #define ATH10K_FW_API2_FILE "firmware-2.bin" 38 #define ATH10K_FW_API3_FILE "firmware-3.bin" 39 40 #define ATH10K_FW_UTF_FILE "utf.bin" 41 42 /* includes also the null byte */ 43 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 44 45 #define REG_DUMP_COUNT_QCA988X 60 46 47 #define QCA988X_CAL_DATA_LEN 2116 48 49 struct ath10k_fw_ie { 50 __le32 id; 51 __le32 len; 52 u8 data[0]; 53 }; 54 55 enum ath10k_fw_ie_type { 56 ATH10K_FW_IE_FW_VERSION = 0, 57 ATH10K_FW_IE_TIMESTAMP = 1, 58 ATH10K_FW_IE_FEATURES = 2, 59 ATH10K_FW_IE_FW_IMAGE = 3, 60 ATH10K_FW_IE_OTP_IMAGE = 4, 61 }; 62 63 /* Known pecularities: 64 * - current FW doesn't support raw rx mode (last tested v599) 65 * - current FW dumps upon raw tx mode (last tested v599) 66 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 67 * - raw have FCS, nwifi doesn't 68 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 69 * param, llc/snap) are aligned to 4byte boundaries each */ 70 enum ath10k_hw_txrx_mode { 71 ATH10K_HW_TXRX_RAW = 0, 72 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 73 ATH10K_HW_TXRX_ETHERNET = 2, 74 75 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 76 ATH10K_HW_TXRX_MGMT = 3, 77 }; 78 79 enum ath10k_mcast2ucast_mode { 80 ATH10K_MCAST2UCAST_DISABLED = 0, 81 ATH10K_MCAST2UCAST_ENABLED = 1, 82 }; 83 84 struct ath10k_pktlog_hdr { 85 __le16 flags; 86 __le16 missed_cnt; 87 __le16 log_type; 88 __le16 size; 89 __le32 timestamp; 90 u8 payload[0]; 91 } __packed; 92 93 /* Target specific defines for MAIN firmware */ 94 #define TARGET_NUM_VDEVS 8 95 #define TARGET_NUM_PEER_AST 2 96 #define TARGET_NUM_WDS_ENTRIES 32 97 #define TARGET_DMA_BURST_SIZE 0 98 #define TARGET_MAC_AGGR_DELIM 0 99 #define TARGET_AST_SKID_LIMIT 16 100 #define TARGET_NUM_STATIONS 16 101 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 102 (TARGET_NUM_VDEVS)) 103 #define TARGET_NUM_OFFLOAD_PEERS 0 104 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 105 #define TARGET_NUM_PEER_KEYS 2 106 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 107 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 108 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 109 #define TARGET_RX_TIMEOUT_LO_PRI 100 110 #define TARGET_RX_TIMEOUT_HI_PRI 40 111 112 /* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and 113 * avoid a very expensive re-alignment in mac80211. */ 114 #define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 115 116 #define TARGET_SCAN_MAX_PENDING_REQS 4 117 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 118 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 119 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 120 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 121 #define TARGET_NUM_MCAST_GROUPS 0 122 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 123 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 124 #define TARGET_TX_DBG_LOG_SIZE 1024 125 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 126 #define TARGET_VOW_CONFIG 0 127 #define TARGET_NUM_MSDU_DESC (1024 + 400) 128 #define TARGET_MAX_FRAG_ENTRIES 0 129 130 /* Target specific defines for 10.X firmware */ 131 #define TARGET_10X_NUM_VDEVS 16 132 #define TARGET_10X_NUM_PEER_AST 2 133 #define TARGET_10X_NUM_WDS_ENTRIES 32 134 #define TARGET_10X_DMA_BURST_SIZE 0 135 #define TARGET_10X_MAC_AGGR_DELIM 0 136 #define TARGET_10X_AST_SKID_LIMIT 16 137 #define TARGET_10X_NUM_STATIONS 128 138 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 139 (TARGET_10X_NUM_VDEVS)) 140 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 141 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 142 #define TARGET_10X_NUM_PEER_KEYS 2 143 #define TARGET_10X_NUM_TIDS_MAX 256 144 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 145 (TARGET_10X_NUM_PEERS) * 2) 146 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 147 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 148 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 149 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 150 #define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 151 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 152 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 153 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 154 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 155 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 156 #define TARGET_10X_NUM_MCAST_GROUPS 0 157 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 158 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 159 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 160 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 161 #define TARGET_10X_VOW_CONFIG 0 162 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 163 #define TARGET_10X_MAX_FRAG_ENTRIES 0 164 165 /* Number of Copy Engines supported */ 166 #define CE_COUNT 8 167 168 /* 169 * Total number of PCIe MSI interrupts requested for all interrupt sources. 170 * PCIe standard forces this to be a power of 2. 171 * Some Host OS's limit MSI requests that can be granted to 8 172 * so for now we abide by this limit and avoid requesting more 173 * than that. 174 */ 175 #define MSI_NUM_REQUEST_LOG2 3 176 #define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2) 177 178 /* 179 * Granted MSIs are assigned as follows: 180 * Firmware uses the first 181 * Remaining MSIs, if any, are used by Copy Engines 182 * This mapping is known to both Target firmware and Host software. 183 * It may be changed as long as Host and Target are kept in sync. 184 */ 185 /* MSI for firmware (errors, etc.) */ 186 #define MSI_ASSIGN_FW 0 187 188 /* MSIs for Copy Engines */ 189 #define MSI_ASSIGN_CE_INITIAL 1 190 #define MSI_ASSIGN_CE_MAX 7 191 192 /* as of IP3.7.1 */ 193 #define RTC_STATE_V_ON 3 194 195 #define RTC_STATE_COLD_RESET_MASK 0x00000400 196 #define RTC_STATE_V_LSB 0 197 #define RTC_STATE_V_MASK 0x00000007 198 #define RTC_STATE_ADDRESS 0x0000 199 #define PCIE_SOC_WAKE_V_MASK 0x00000001 200 #define PCIE_SOC_WAKE_ADDRESS 0x0004 201 #define PCIE_SOC_WAKE_RESET 0x00000000 202 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 203 204 #define RTC_SOC_BASE_ADDRESS 0x00004000 205 #define RTC_WMAC_BASE_ADDRESS 0x00005000 206 #define MAC_COEX_BASE_ADDRESS 0x00006000 207 #define BT_COEX_BASE_ADDRESS 0x00007000 208 #define SOC_PCIE_BASE_ADDRESS 0x00008000 209 #define SOC_CORE_BASE_ADDRESS 0x00009000 210 #define WLAN_UART_BASE_ADDRESS 0x0000c000 211 #define WLAN_SI_BASE_ADDRESS 0x00010000 212 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 213 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 214 #define WLAN_MAC_BASE_ADDRESS 0x00020000 215 #define EFUSE_BASE_ADDRESS 0x00030000 216 #define FPGA_REG_BASE_ADDRESS 0x00039000 217 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 218 #define CE_WRAPPER_BASE_ADDRESS 0x00057000 219 #define CE0_BASE_ADDRESS 0x00057400 220 #define CE1_BASE_ADDRESS 0x00057800 221 #define CE2_BASE_ADDRESS 0x00057c00 222 #define CE3_BASE_ADDRESS 0x00058000 223 #define CE4_BASE_ADDRESS 0x00058400 224 #define CE5_BASE_ADDRESS 0x00058800 225 #define CE6_BASE_ADDRESS 0x00058c00 226 #define CE7_BASE_ADDRESS 0x00059000 227 #define DBI_BASE_ADDRESS 0x00060000 228 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 229 #define PCIE_LOCAL_BASE_ADDRESS 0x00080000 230 231 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 232 #define SOC_RESET_CONTROL_OFFSET 0x00000000 233 #define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001 234 #define SOC_RESET_CONTROL_CE_RST_MASK 0x00040000 235 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 236 #define SOC_CPU_CLOCK_OFFSET 0x00000020 237 #define SOC_CPU_CLOCK_STANDARD_LSB 0 238 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 239 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 240 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 241 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 242 #define SOC_LPO_CAL_OFFSET 0x000000e0 243 #define SOC_LPO_CAL_ENABLE_LSB 20 244 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 245 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 246 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 247 248 #define SOC_CHIP_ID_ADDRESS 0x000000ec 249 #define SOC_CHIP_ID_REV_LSB 8 250 #define SOC_CHIP_ID_REV_MASK 0x00000f00 251 252 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 253 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 254 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 255 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 256 257 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 258 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 259 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 260 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 261 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 262 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 263 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 264 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 265 266 #define CLOCK_GPIO_OFFSET 0xffffffff 267 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 268 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 269 270 #define SI_CONFIG_OFFSET 0x00000000 271 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 272 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 273 #define SI_CONFIG_I2C_LSB 16 274 #define SI_CONFIG_I2C_MASK 0x00010000 275 #define SI_CONFIG_POS_SAMPLE_LSB 7 276 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 277 #define SI_CONFIG_INACTIVE_DATA_LSB 5 278 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 279 #define SI_CONFIG_INACTIVE_CLK_LSB 4 280 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 281 #define SI_CONFIG_DIVIDER_LSB 0 282 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 283 #define SI_CS_OFFSET 0x00000004 284 #define SI_CS_DONE_ERR_MASK 0x00000400 285 #define SI_CS_DONE_INT_MASK 0x00000200 286 #define SI_CS_START_LSB 8 287 #define SI_CS_START_MASK 0x00000100 288 #define SI_CS_RX_CNT_LSB 4 289 #define SI_CS_RX_CNT_MASK 0x000000f0 290 #define SI_CS_TX_CNT_LSB 0 291 #define SI_CS_TX_CNT_MASK 0x0000000f 292 293 #define SI_TX_DATA0_OFFSET 0x00000008 294 #define SI_TX_DATA1_OFFSET 0x0000000c 295 #define SI_RX_DATA0_OFFSET 0x00000010 296 #define SI_RX_DATA1_OFFSET 0x00000014 297 298 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 299 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 300 #define CORE_CTRL_ADDRESS 0x0000 301 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 302 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 303 #define PCIE_INTR_CLR_ADDRESS 0x0014 304 #define SCRATCH_3_ADDRESS 0x0030 305 #define CPU_INTR_ADDRESS 0x0010 306 307 /* Firmware indications to the Host via SCRATCH_3 register. */ 308 #define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS) 309 #define FW_IND_EVENT_PENDING 1 310 #define FW_IND_INITIALIZED 2 311 312 /* HOST_REG interrupt from firmware */ 313 #define PCIE_INTR_FIRMWARE_MASK 0x00000400 314 #define PCIE_INTR_CE_MASK_ALL 0x0007f800 315 316 #define DRAM_BASE_ADDRESS 0x00400000 317 318 #define MISSING 0 319 320 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 321 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 322 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 323 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 324 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 325 #define RESET_CONTROL_MBOX_RST_MASK MISSING 326 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 327 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 328 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 329 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 330 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 331 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 332 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 333 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 334 #define LOCAL_SCRATCH_OFFSET 0x18 335 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 336 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 337 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 338 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 339 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 340 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 341 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 342 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 343 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 344 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 345 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 346 #define MBOX_BASE_ADDRESS MISSING 347 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 348 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 349 #define INT_STATUS_ENABLE_CPU_LSB MISSING 350 #define INT_STATUS_ENABLE_CPU_MASK MISSING 351 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 352 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 353 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 354 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 355 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 356 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 357 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 358 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 359 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 360 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 361 #define INT_STATUS_ENABLE_ADDRESS MISSING 362 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 363 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 364 #define HOST_INT_STATUS_ADDRESS MISSING 365 #define CPU_INT_STATUS_ADDRESS MISSING 366 #define ERROR_INT_STATUS_ADDRESS MISSING 367 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 368 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 369 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 370 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 371 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 372 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 373 #define COUNT_DEC_ADDRESS MISSING 374 #define HOST_INT_STATUS_CPU_MASK MISSING 375 #define HOST_INT_STATUS_CPU_LSB MISSING 376 #define HOST_INT_STATUS_ERROR_MASK MISSING 377 #define HOST_INT_STATUS_ERROR_LSB MISSING 378 #define HOST_INT_STATUS_COUNTER_MASK MISSING 379 #define HOST_INT_STATUS_COUNTER_LSB MISSING 380 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 381 #define WINDOW_DATA_ADDRESS MISSING 382 #define WINDOW_READ_ADDR_ADDRESS MISSING 383 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 384 385 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 386 387 #endif /* _HW_H_ */ 388