1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HW_H_ 19 #define _HW_H_ 20 21 #include "targaddrs.h" 22 23 #define ATH10K_FW_DIR "ath10k" 24 25 #define QCA988X_2_0_DEVICE_ID (0x003c) 26 #define QCA6164_2_1_DEVICE_ID (0x0041) 27 #define QCA6174_2_1_DEVICE_ID (0x003e) 28 #define QCA99X0_2_0_DEVICE_ID (0x0040) 29 #define QCA9888_2_0_DEVICE_ID (0x0056) 30 #define QCA9984_1_0_DEVICE_ID (0x0046) 31 #define QCA9377_1_0_DEVICE_ID (0x0042) 32 #define QCA9887_1_0_DEVICE_ID (0x0050) 33 34 /* QCA988X 1.0 definitions (unsupported) */ 35 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 36 37 /* QCA988X 2.0 definitions */ 38 #define QCA988X_HW_2_0_VERSION 0x4100016c 39 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 40 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 41 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 43 44 /* QCA9887 1.0 definitions */ 45 #define QCA9887_HW_1_0_VERSION 0x4100016d 46 #define QCA9887_HW_1_0_CHIP_ID_REV 0 47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 48 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" 49 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 50 51 /* QCA6174 target BMI version signatures */ 52 #define QCA6174_HW_1_0_VERSION 0x05000000 53 #define QCA6174_HW_1_1_VERSION 0x05000001 54 #define QCA6174_HW_1_3_VERSION 0x05000003 55 #define QCA6174_HW_2_1_VERSION 0x05010000 56 #define QCA6174_HW_3_0_VERSION 0x05020000 57 #define QCA6174_HW_3_2_VERSION 0x05030000 58 59 /* QCA9377 target BMI version signatures */ 60 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 61 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 62 63 enum qca6174_pci_rev { 64 QCA6174_PCI_REV_1_1 = 0x11, 65 QCA6174_PCI_REV_1_3 = 0x13, 66 QCA6174_PCI_REV_2_0 = 0x20, 67 QCA6174_PCI_REV_3_0 = 0x30, 68 }; 69 70 enum qca6174_chip_id_rev { 71 QCA6174_HW_1_0_CHIP_ID_REV = 0, 72 QCA6174_HW_1_1_CHIP_ID_REV = 1, 73 QCA6174_HW_1_3_CHIP_ID_REV = 2, 74 QCA6174_HW_2_1_CHIP_ID_REV = 4, 75 QCA6174_HW_2_2_CHIP_ID_REV = 5, 76 QCA6174_HW_3_0_CHIP_ID_REV = 8, 77 QCA6174_HW_3_1_CHIP_ID_REV = 9, 78 QCA6174_HW_3_2_CHIP_ID_REV = 10, 79 }; 80 81 enum qca9377_chip_id_rev { 82 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 83 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 84 }; 85 86 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" 87 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 88 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 89 90 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" 91 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 92 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 93 94 /* QCA99X0 1.0 definitions (unsupported) */ 95 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 96 97 /* QCA99X0 2.0 definitions */ 98 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 99 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 100 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 101 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 102 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 103 104 /* QCA9984 1.0 defines */ 105 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 106 #define QCA9984_HW_DEV_TYPE 0xa 107 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 108 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 109 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" 110 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 111 112 /* QCA9888 2.0 defines */ 113 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 114 #define QCA9888_HW_DEV_TYPE 0xc 115 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 116 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 117 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" 118 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 119 120 /* QCA9377 1.0 definitions */ 121 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 122 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 123 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 124 125 /* QCA4019 1.0 definitions */ 126 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 127 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 128 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" 129 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 130 131 #define ATH10K_FW_FILE_BASE "firmware" 132 #define ATH10K_FW_API_MAX 5 133 #define ATH10K_FW_API_MIN 2 134 135 #define ATH10K_FW_API2_FILE "firmware-2.bin" 136 #define ATH10K_FW_API3_FILE "firmware-3.bin" 137 138 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 139 #define ATH10K_FW_API4_FILE "firmware-4.bin" 140 141 /* HTT id conflict fix for management frames over HTT */ 142 #define ATH10K_FW_API5_FILE "firmware-5.bin" 143 144 #define ATH10K_FW_UTF_FILE "utf.bin" 145 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 146 147 /* includes also the null byte */ 148 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 149 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 150 151 #define ATH10K_BOARD_API2_FILE "board-2.bin" 152 153 #define REG_DUMP_COUNT_QCA988X 60 154 155 struct ath10k_fw_ie { 156 __le32 id; 157 __le32 len; 158 u8 data[0]; 159 }; 160 161 enum ath10k_fw_ie_type { 162 ATH10K_FW_IE_FW_VERSION = 0, 163 ATH10K_FW_IE_TIMESTAMP = 1, 164 ATH10K_FW_IE_FEATURES = 2, 165 ATH10K_FW_IE_FW_IMAGE = 3, 166 ATH10K_FW_IE_OTP_IMAGE = 4, 167 168 /* WMI "operations" interface version, 32 bit value. Supported from 169 * FW API 4 and above. 170 */ 171 ATH10K_FW_IE_WMI_OP_VERSION = 5, 172 173 /* HTT "operations" interface version, 32 bit value. Supported from 174 * FW API 5 and above. 175 */ 176 ATH10K_FW_IE_HTT_OP_VERSION = 6, 177 178 /* Code swap image for firmware binary */ 179 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 180 }; 181 182 enum ath10k_fw_wmi_op_version { 183 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 184 185 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 186 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 187 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 188 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 189 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 190 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 191 192 /* keep last */ 193 ATH10K_FW_WMI_OP_VERSION_MAX, 194 }; 195 196 enum ath10k_fw_htt_op_version { 197 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 198 199 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 200 201 /* also used in 10.2 and 10.2.4 branches */ 202 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 203 204 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 205 206 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 207 208 /* keep last */ 209 ATH10K_FW_HTT_OP_VERSION_MAX, 210 }; 211 212 enum ath10k_bd_ie_type { 213 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 214 ATH10K_BD_IE_BOARD = 0, 215 }; 216 217 enum ath10k_bd_ie_board_type { 218 ATH10K_BD_IE_BOARD_NAME = 0, 219 ATH10K_BD_IE_BOARD_DATA = 1, 220 }; 221 222 enum ath10k_hw_rev { 223 ATH10K_HW_QCA988X, 224 ATH10K_HW_QCA6174, 225 ATH10K_HW_QCA99X0, 226 ATH10K_HW_QCA9888, 227 ATH10K_HW_QCA9984, 228 ATH10K_HW_QCA9377, 229 ATH10K_HW_QCA4019, 230 ATH10K_HW_QCA9887, 231 }; 232 233 struct ath10k_hw_regs { 234 u32 rtc_soc_base_address; 235 u32 rtc_wmac_base_address; 236 u32 soc_core_base_address; 237 u32 wlan_mac_base_address; 238 u32 ce_wrapper_base_address; 239 u32 ce0_base_address; 240 u32 ce1_base_address; 241 u32 ce2_base_address; 242 u32 ce3_base_address; 243 u32 ce4_base_address; 244 u32 ce5_base_address; 245 u32 ce6_base_address; 246 u32 ce7_base_address; 247 u32 soc_reset_control_si0_rst_mask; 248 u32 soc_reset_control_ce_rst_mask; 249 u32 soc_chip_id_address; 250 u32 scratch_3_address; 251 u32 fw_indicator_address; 252 u32 pcie_local_base_address; 253 u32 ce_wrap_intr_sum_host_msi_lsb; 254 u32 ce_wrap_intr_sum_host_msi_mask; 255 u32 pcie_intr_fw_mask; 256 u32 pcie_intr_ce_mask_all; 257 u32 pcie_intr_clr_address; 258 }; 259 260 extern const struct ath10k_hw_regs qca988x_regs; 261 extern const struct ath10k_hw_regs qca6174_regs; 262 extern const struct ath10k_hw_regs qca99x0_regs; 263 extern const struct ath10k_hw_regs qca4019_regs; 264 265 struct ath10k_hw_values { 266 u32 rtc_state_val_on; 267 u8 ce_count; 268 u8 msi_assign_ce_max; 269 u8 num_target_ce_config_wlan; 270 u16 ce_desc_meta_data_mask; 271 u8 ce_desc_meta_data_lsb; 272 }; 273 274 extern const struct ath10k_hw_values qca988x_values; 275 extern const struct ath10k_hw_values qca6174_values; 276 extern const struct ath10k_hw_values qca99x0_values; 277 extern const struct ath10k_hw_values qca9888_values; 278 extern const struct ath10k_hw_values qca4019_values; 279 280 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 281 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 282 283 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 284 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 285 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 286 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 287 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 288 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 289 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 290 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 291 292 /* Known peculiarities: 293 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 294 * - raw have FCS, nwifi doesn't 295 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 296 * param, llc/snap) are aligned to 4byte boundaries each */ 297 enum ath10k_hw_txrx_mode { 298 ATH10K_HW_TXRX_RAW = 0, 299 300 /* Native Wifi decap mode is used to align IP frames to 4-byte 301 * boundaries and avoid a very expensive re-alignment in mac80211. 302 */ 303 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 304 ATH10K_HW_TXRX_ETHERNET = 2, 305 306 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 307 ATH10K_HW_TXRX_MGMT = 3, 308 }; 309 310 enum ath10k_mcast2ucast_mode { 311 ATH10K_MCAST2UCAST_DISABLED = 0, 312 ATH10K_MCAST2UCAST_ENABLED = 1, 313 }; 314 315 enum ath10k_hw_rate_ofdm { 316 ATH10K_HW_RATE_OFDM_48M = 0, 317 ATH10K_HW_RATE_OFDM_24M, 318 ATH10K_HW_RATE_OFDM_12M, 319 ATH10K_HW_RATE_OFDM_6M, 320 ATH10K_HW_RATE_OFDM_54M, 321 ATH10K_HW_RATE_OFDM_36M, 322 ATH10K_HW_RATE_OFDM_18M, 323 ATH10K_HW_RATE_OFDM_9M, 324 }; 325 326 enum ath10k_hw_rate_cck { 327 ATH10K_HW_RATE_CCK_LP_11M = 0, 328 ATH10K_HW_RATE_CCK_LP_5_5M, 329 ATH10K_HW_RATE_CCK_LP_2M, 330 ATH10K_HW_RATE_CCK_LP_1M, 331 ATH10K_HW_RATE_CCK_SP_11M, 332 ATH10K_HW_RATE_CCK_SP_5_5M, 333 ATH10K_HW_RATE_CCK_SP_2M, 334 }; 335 336 enum ath10k_hw_rate_rev2_cck { 337 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 338 ATH10K_HW_RATE_REV2_CCK_LP_2M, 339 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 340 ATH10K_HW_RATE_REV2_CCK_LP_11M, 341 ATH10K_HW_RATE_REV2_CCK_SP_2M, 342 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 343 ATH10K_HW_RATE_REV2_CCK_SP_11M, 344 }; 345 346 enum ath10k_hw_cc_wraparound_type { 347 ATH10K_HW_CC_WRAP_DISABLED = 0, 348 349 /* This type is when the HW chip has a quirky Cycle Counter 350 * wraparound which resets to 0x7fffffff instead of 0. All 351 * other CC related counters (e.g. Rx Clear Count) are divided 352 * by 2 so they never wraparound themselves. 353 */ 354 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 355 356 /* Each hw counter wrapsaround independently. When the 357 * counter overflows the repestive counter is right shifted 358 * by 1, i.e reset to 0x7fffffff, and other counters will be 359 * running unaffected. In this type of wraparound, it should 360 * be possible to report accurate Rx busy time unlike the 361 * first type. 362 */ 363 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 364 }; 365 366 struct ath10k_hw_params { 367 u32 id; 368 u16 dev_id; 369 const char *name; 370 u32 patch_load_addr; 371 int uart_pin; 372 u32 otp_exe_param; 373 374 /* Type of hw cycle counter wraparound logic, for more info 375 * refer enum ath10k_hw_cc_wraparound_type. 376 */ 377 enum ath10k_hw_cc_wraparound_type cc_wraparound_type; 378 379 /* Some of chip expects fragment descriptor to be continuous 380 * memory for any TX operation. Set continuous_frag_desc flag 381 * for the hardware which have such requirement. 382 */ 383 bool continuous_frag_desc; 384 385 /* CCK hardware rate table mapping for the newer chipsets 386 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values 387 * are in a proper order with respect to the rate/preamble 388 */ 389 bool cck_rate_map_rev2; 390 391 u32 channel_counters_freq_hz; 392 393 /* Mgmt tx descriptors threshold for limiting probe response 394 * frames. 395 */ 396 u32 max_probe_resp_desc_thres; 397 398 u32 tx_chain_mask; 399 u32 rx_chain_mask; 400 u32 max_spatial_stream; 401 u32 cal_data_len; 402 403 struct ath10k_hw_params_fw { 404 const char *dir; 405 const char *board; 406 size_t board_size; 407 size_t board_ext_size; 408 } fw; 409 410 /* qca99x0 family chips deliver broadcast/multicast management 411 * frames encrypted and expect software do decryption. 412 */ 413 bool sw_decrypt_mcast_mgmt; 414 415 const struct ath10k_hw_ops *hw_ops; 416 417 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ 418 int decap_align_bytes; 419 }; 420 421 struct htt_rx_desc; 422 423 /* Defines needed for Rx descriptor abstraction */ 424 struct ath10k_hw_ops { 425 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 426 void (*set_coverage_class)(struct ath10k *ar, s16 value); 427 }; 428 429 extern const struct ath10k_hw_ops qca988x_ops; 430 extern const struct ath10k_hw_ops qca99x0_ops; 431 432 static inline int 433 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, 434 struct htt_rx_desc *rxd) 435 { 436 if (hw->hw_ops->rx_desc_get_l3_pad_bytes) 437 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd); 438 return 0; 439 } 440 441 /* Target specific defines for MAIN firmware */ 442 #define TARGET_NUM_VDEVS 8 443 #define TARGET_NUM_PEER_AST 2 444 #define TARGET_NUM_WDS_ENTRIES 32 445 #define TARGET_DMA_BURST_SIZE 0 446 #define TARGET_MAC_AGGR_DELIM 0 447 #define TARGET_AST_SKID_LIMIT 16 448 #define TARGET_NUM_STATIONS 16 449 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 450 (TARGET_NUM_VDEVS)) 451 #define TARGET_NUM_OFFLOAD_PEERS 0 452 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 453 #define TARGET_NUM_PEER_KEYS 2 454 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 455 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 456 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 457 #define TARGET_RX_TIMEOUT_LO_PRI 100 458 #define TARGET_RX_TIMEOUT_HI_PRI 40 459 460 #define TARGET_SCAN_MAX_PENDING_REQS 4 461 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 462 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 463 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 464 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 465 #define TARGET_NUM_MCAST_GROUPS 0 466 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 467 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 468 #define TARGET_TX_DBG_LOG_SIZE 1024 469 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 470 #define TARGET_VOW_CONFIG 0 471 #define TARGET_NUM_MSDU_DESC (1024 + 400) 472 #define TARGET_MAX_FRAG_ENTRIES 0 473 474 /* Target specific defines for 10.X firmware */ 475 #define TARGET_10X_NUM_VDEVS 16 476 #define TARGET_10X_NUM_PEER_AST 2 477 #define TARGET_10X_NUM_WDS_ENTRIES 32 478 #define TARGET_10X_DMA_BURST_SIZE 0 479 #define TARGET_10X_MAC_AGGR_DELIM 0 480 #define TARGET_10X_AST_SKID_LIMIT 128 481 #define TARGET_10X_NUM_STATIONS 128 482 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 483 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 484 (TARGET_10X_NUM_VDEVS)) 485 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 486 (TARGET_10X_NUM_VDEVS)) 487 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 488 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 489 #define TARGET_10X_NUM_PEER_KEYS 2 490 #define TARGET_10X_NUM_TIDS_MAX 256 491 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 492 (TARGET_10X_NUM_PEERS) * 2) 493 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 494 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 495 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 496 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 497 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 498 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 499 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 500 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 501 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 502 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 503 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 504 #define TARGET_10X_NUM_MCAST_GROUPS 0 505 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 506 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 507 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 508 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 509 #define TARGET_10X_VOW_CONFIG 0 510 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 511 #define TARGET_10X_MAX_FRAG_ENTRIES 0 512 513 /* 10.2 parameters */ 514 #define TARGET_10_2_DMA_BURST_SIZE 0 515 516 /* Target specific defines for WMI-TLV firmware */ 517 #define TARGET_TLV_NUM_VDEVS 4 518 #define TARGET_TLV_NUM_STATIONS 32 519 #define TARGET_TLV_NUM_PEERS 33 520 #define TARGET_TLV_NUM_TDLS_VDEVS 1 521 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 522 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 523 #define TARGET_TLV_NUM_WOW_PATTERNS 22 524 525 /* Diagnostic Window */ 526 #define CE_DIAG_PIPE 7 527 528 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 529 530 /* Target specific defines for 10.4 firmware */ 531 #define TARGET_10_4_NUM_VDEVS 16 532 #define TARGET_10_4_NUM_STATIONS 32 533 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 534 (TARGET_10_4_NUM_VDEVS)) 535 #define TARGET_10_4_ACTIVE_PEERS 0 536 537 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 538 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 539 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 540 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 541 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 542 #define TARGET_10_4_NUM_PEER_KEYS 2 543 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 544 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 545 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 546 #define TARGET_10_4_AST_SKID_LIMIT 32 547 548 /* 100 ms for video, best-effort, and background */ 549 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 550 551 /* 40 ms for voice */ 552 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 553 554 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 555 #define TARGET_10_4_SCAN_MAX_REQS 4 556 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 557 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 558 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 559 560 /* Note: mcast to ucast is disabled by default */ 561 #define TARGET_10_4_NUM_MCAST_GROUPS 0 562 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 563 #define TARGET_10_4_MCAST2UCAST_MODE 0 564 565 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 566 #define TARGET_10_4_NUM_WDS_ENTRIES 32 567 #define TARGET_10_4_DMA_BURST_SIZE 0 568 #define TARGET_10_4_MAC_AGGR_DELIM 0 569 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 570 #define TARGET_10_4_VOW_CONFIG 0 571 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 572 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 573 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 574 #define TARGET_10_4_SMART_ANT_CAP 0 575 #define TARGET_10_4_BK_MIN_FREE 0 576 #define TARGET_10_4_BE_MIN_FREE 0 577 #define TARGET_10_4_VI_MIN_FREE 0 578 #define TARGET_10_4_VO_MIN_FREE 0 579 #define TARGET_10_4_RX_BATCH_MODE 1 580 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 581 #define TARGET_10_4_ATF_CONFIG 0 582 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 583 #define TARGET_10_4_QWRAP_CONFIG 0 584 585 /* Maximum number of Copy Engine's supported */ 586 #define CE_COUNT_MAX 12 587 588 /* Number of Copy Engines supported */ 589 #define CE_COUNT ar->hw_values->ce_count 590 591 /* 592 * Granted MSIs are assigned as follows: 593 * Firmware uses the first 594 * Remaining MSIs, if any, are used by Copy Engines 595 * This mapping is known to both Target firmware and Host software. 596 * It may be changed as long as Host and Target are kept in sync. 597 */ 598 /* MSI for firmware (errors, etc.) */ 599 #define MSI_ASSIGN_FW 0 600 601 /* MSIs for Copy Engines */ 602 #define MSI_ASSIGN_CE_INITIAL 1 603 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 604 605 /* as of IP3.7.1 */ 606 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 607 608 #define RTC_STATE_V_LSB 0 609 #define RTC_STATE_V_MASK 0x00000007 610 #define RTC_STATE_ADDRESS 0x0000 611 #define PCIE_SOC_WAKE_V_MASK 0x00000001 612 #define PCIE_SOC_WAKE_ADDRESS 0x0004 613 #define PCIE_SOC_WAKE_RESET 0x00000000 614 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 615 616 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 617 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 618 #define MAC_COEX_BASE_ADDRESS 0x00006000 619 #define BT_COEX_BASE_ADDRESS 0x00007000 620 #define SOC_PCIE_BASE_ADDRESS 0x00008000 621 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 622 #define WLAN_UART_BASE_ADDRESS 0x0000c000 623 #define WLAN_SI_BASE_ADDRESS 0x00010000 624 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 625 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 626 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address 627 #define EFUSE_BASE_ADDRESS 0x00030000 628 #define FPGA_REG_BASE_ADDRESS 0x00039000 629 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 630 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 631 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 632 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 633 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 634 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 635 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 636 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 637 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 638 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 639 #define DBI_BASE_ADDRESS 0x00060000 640 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 641 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 642 643 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 644 #define SOC_RESET_CONTROL_OFFSET 0x00000000 645 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 646 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 647 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 648 #define SOC_CPU_CLOCK_OFFSET 0x00000020 649 #define SOC_CPU_CLOCK_STANDARD_LSB 0 650 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 651 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 652 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 653 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 654 #define SOC_LPO_CAL_OFFSET 0x000000e0 655 #define SOC_LPO_CAL_ENABLE_LSB 20 656 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 657 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 658 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 659 660 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 661 #define SOC_CHIP_ID_REV_LSB 8 662 #define SOC_CHIP_ID_REV_MASK 0x00000f00 663 664 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 665 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 666 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 667 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 668 669 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 670 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 671 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 672 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 673 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 674 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 675 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 676 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 677 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 678 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 679 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 680 681 #define CLOCK_GPIO_OFFSET 0xffffffff 682 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 683 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 684 685 #define SI_CONFIG_OFFSET 0x00000000 686 #define SI_CONFIG_ERR_INT_LSB 19 687 #define SI_CONFIG_ERR_INT_MASK 0x00080000 688 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 689 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 690 #define SI_CONFIG_I2C_LSB 16 691 #define SI_CONFIG_I2C_MASK 0x00010000 692 #define SI_CONFIG_POS_SAMPLE_LSB 7 693 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 694 #define SI_CONFIG_INACTIVE_DATA_LSB 5 695 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 696 #define SI_CONFIG_INACTIVE_CLK_LSB 4 697 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 698 #define SI_CONFIG_DIVIDER_LSB 0 699 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 700 #define SI_CS_OFFSET 0x00000004 701 #define SI_CS_DONE_ERR_LSB 10 702 #define SI_CS_DONE_ERR_MASK 0x00000400 703 #define SI_CS_DONE_INT_LSB 9 704 #define SI_CS_DONE_INT_MASK 0x00000200 705 #define SI_CS_START_LSB 8 706 #define SI_CS_START_MASK 0x00000100 707 #define SI_CS_RX_CNT_LSB 4 708 #define SI_CS_RX_CNT_MASK 0x000000f0 709 #define SI_CS_TX_CNT_LSB 0 710 #define SI_CS_TX_CNT_MASK 0x0000000f 711 712 #define SI_TX_DATA0_OFFSET 0x00000008 713 #define SI_TX_DATA1_OFFSET 0x0000000c 714 #define SI_RX_DATA0_OFFSET 0x00000010 715 #define SI_RX_DATA1_OFFSET 0x00000014 716 717 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 718 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 719 #define CORE_CTRL_ADDRESS 0x0000 720 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 721 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 722 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 723 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 724 #define CPU_INTR_ADDRESS 0x0010 725 726 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 727 728 /* Firmware indications to the Host via SCRATCH_3 register. */ 729 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 730 #define FW_IND_EVENT_PENDING 1 731 #define FW_IND_INITIALIZED 2 732 #define FW_IND_HOST_READY 0x80000000 733 734 /* HOST_REG interrupt from firmware */ 735 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 736 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 737 738 #define DRAM_BASE_ADDRESS 0x00400000 739 740 #define PCIE_BAR_REG_ADDRESS 0x40030 741 742 #define MISSING 0 743 744 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 745 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 746 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 747 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 748 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 749 #define RESET_CONTROL_MBOX_RST_MASK MISSING 750 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 751 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 752 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 753 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 754 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 755 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 756 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 757 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 758 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 759 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 760 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 761 #define LOCAL_SCRATCH_OFFSET 0x18 762 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 763 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 764 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 765 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 766 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 767 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 768 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 769 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 770 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 771 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 772 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 773 #define MBOX_BASE_ADDRESS MISSING 774 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 775 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 776 #define INT_STATUS_ENABLE_CPU_LSB MISSING 777 #define INT_STATUS_ENABLE_CPU_MASK MISSING 778 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 779 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 780 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 781 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 782 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 783 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 784 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 785 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 786 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 787 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 788 #define INT_STATUS_ENABLE_ADDRESS MISSING 789 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 790 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 791 #define HOST_INT_STATUS_ADDRESS MISSING 792 #define CPU_INT_STATUS_ADDRESS MISSING 793 #define ERROR_INT_STATUS_ADDRESS MISSING 794 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 795 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 796 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 797 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 798 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 799 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 800 #define COUNT_DEC_ADDRESS MISSING 801 #define HOST_INT_STATUS_CPU_MASK MISSING 802 #define HOST_INT_STATUS_CPU_LSB MISSING 803 #define HOST_INT_STATUS_ERROR_MASK MISSING 804 #define HOST_INT_STATUS_ERROR_LSB MISSING 805 #define HOST_INT_STATUS_COUNTER_MASK MISSING 806 #define HOST_INT_STATUS_COUNTER_LSB MISSING 807 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 808 #define WINDOW_DATA_ADDRESS MISSING 809 #define WINDOW_READ_ADDR_ADDRESS MISSING 810 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 811 812 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 813 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 814 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 815 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 816 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 817 818 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 819 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 820 #define QCA9887_EEPROM_ADDR_HI_LSB 8 821 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 822 #define QCA9887_EEPROM_ADDR_LO_LSB 16 823 824 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 825 826 /* Register definitions for first generation ath10k cards. These cards include 827 * a mac thich has a register allocation similar to ath9k and at least some 828 * registers including the ones relevant for modifying the coverage class are 829 * identical to the ath9k definitions. 830 * These registers are usually managed by the ath10k firmware. However by 831 * overriding them it is possible to support coverage class modifications. 832 */ 833 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014 834 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF 835 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF 836 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0 837 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000 838 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16 839 840 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070 841 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF 842 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF 843 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0 844 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000 845 846 #define WAVE1_PHYCLK 0x801C 847 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F 848 #define WAVE1_PHYCLK_USEC_LSB 0 849 850 #endif /* _HW_H_ */ 851