1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HW_H_ 19 #define _HW_H_ 20 21 #include "targaddrs.h" 22 23 #define ATH10K_FW_DIR "ath10k" 24 25 #define QCA988X_2_0_DEVICE_ID (0x003c) 26 #define QCA6164_2_1_DEVICE_ID (0x0041) 27 #define QCA6174_2_1_DEVICE_ID (0x003e) 28 #define QCA99X0_2_0_DEVICE_ID (0x0040) 29 #define QCA9888_2_0_DEVICE_ID (0x0056) 30 #define QCA9984_1_0_DEVICE_ID (0x0046) 31 #define QCA9377_1_0_DEVICE_ID (0x0042) 32 #define QCA9887_1_0_DEVICE_ID (0x0050) 33 34 /* QCA988X 1.0 definitions (unsupported) */ 35 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 36 37 /* QCA988X 2.0 definitions */ 38 #define QCA988X_HW_2_0_VERSION 0x4100016c 39 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 40 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 41 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 43 44 /* QCA9887 1.0 definitions */ 45 #define QCA9887_HW_1_0_VERSION 0x4100016d 46 #define QCA9887_HW_1_0_CHIP_ID_REV 0 47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 48 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" 49 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 50 51 /* QCA6174 target BMI version signatures */ 52 #define QCA6174_HW_1_0_VERSION 0x05000000 53 #define QCA6174_HW_1_1_VERSION 0x05000001 54 #define QCA6174_HW_1_3_VERSION 0x05000003 55 #define QCA6174_HW_2_1_VERSION 0x05010000 56 #define QCA6174_HW_3_0_VERSION 0x05020000 57 #define QCA6174_HW_3_2_VERSION 0x05030000 58 59 /* QCA9377 target BMI version signatures */ 60 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 61 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 62 63 enum qca6174_pci_rev { 64 QCA6174_PCI_REV_1_1 = 0x11, 65 QCA6174_PCI_REV_1_3 = 0x13, 66 QCA6174_PCI_REV_2_0 = 0x20, 67 QCA6174_PCI_REV_3_0 = 0x30, 68 }; 69 70 enum qca6174_chip_id_rev { 71 QCA6174_HW_1_0_CHIP_ID_REV = 0, 72 QCA6174_HW_1_1_CHIP_ID_REV = 1, 73 QCA6174_HW_1_3_CHIP_ID_REV = 2, 74 QCA6174_HW_2_1_CHIP_ID_REV = 4, 75 QCA6174_HW_2_2_CHIP_ID_REV = 5, 76 QCA6174_HW_3_0_CHIP_ID_REV = 8, 77 QCA6174_HW_3_1_CHIP_ID_REV = 9, 78 QCA6174_HW_3_2_CHIP_ID_REV = 10, 79 }; 80 81 enum qca9377_chip_id_rev { 82 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 83 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 84 }; 85 86 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" 87 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 88 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 89 90 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" 91 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 92 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 93 94 /* QCA99X0 1.0 definitions (unsupported) */ 95 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 96 97 /* QCA99X0 2.0 definitions */ 98 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 99 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 100 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 101 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 102 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 103 104 /* QCA9984 1.0 defines */ 105 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 106 #define QCA9984_HW_DEV_TYPE 0xa 107 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 108 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 109 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" 110 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 111 112 /* QCA9888 2.0 defines */ 113 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 114 #define QCA9888_HW_DEV_TYPE 0xc 115 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 116 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 117 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" 118 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 119 120 /* QCA9377 1.0 definitions */ 121 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 122 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 123 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 124 125 /* QCA4019 1.0 definitions */ 126 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 127 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 128 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" 129 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 130 131 #define ATH10K_FW_API2_FILE "firmware-2.bin" 132 #define ATH10K_FW_API3_FILE "firmware-3.bin" 133 134 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 135 #define ATH10K_FW_API4_FILE "firmware-4.bin" 136 137 /* HTT id conflict fix for management frames over HTT */ 138 #define ATH10K_FW_API5_FILE "firmware-5.bin" 139 140 #define ATH10K_FW_UTF_FILE "utf.bin" 141 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 142 143 /* includes also the null byte */ 144 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 145 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 146 147 #define ATH10K_BOARD_API2_FILE "board-2.bin" 148 149 #define REG_DUMP_COUNT_QCA988X 60 150 151 struct ath10k_fw_ie { 152 __le32 id; 153 __le32 len; 154 u8 data[0]; 155 }; 156 157 enum ath10k_fw_ie_type { 158 ATH10K_FW_IE_FW_VERSION = 0, 159 ATH10K_FW_IE_TIMESTAMP = 1, 160 ATH10K_FW_IE_FEATURES = 2, 161 ATH10K_FW_IE_FW_IMAGE = 3, 162 ATH10K_FW_IE_OTP_IMAGE = 4, 163 164 /* WMI "operations" interface version, 32 bit value. Supported from 165 * FW API 4 and above. 166 */ 167 ATH10K_FW_IE_WMI_OP_VERSION = 5, 168 169 /* HTT "operations" interface version, 32 bit value. Supported from 170 * FW API 5 and above. 171 */ 172 ATH10K_FW_IE_HTT_OP_VERSION = 6, 173 174 /* Code swap image for firmware binary */ 175 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 176 }; 177 178 enum ath10k_fw_wmi_op_version { 179 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 180 181 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 182 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 183 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 184 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 185 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 186 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 187 188 /* keep last */ 189 ATH10K_FW_WMI_OP_VERSION_MAX, 190 }; 191 192 enum ath10k_fw_htt_op_version { 193 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 194 195 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 196 197 /* also used in 10.2 and 10.2.4 branches */ 198 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 199 200 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 201 202 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 203 204 /* keep last */ 205 ATH10K_FW_HTT_OP_VERSION_MAX, 206 }; 207 208 enum ath10k_bd_ie_type { 209 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 210 ATH10K_BD_IE_BOARD = 0, 211 }; 212 213 enum ath10k_bd_ie_board_type { 214 ATH10K_BD_IE_BOARD_NAME = 0, 215 ATH10K_BD_IE_BOARD_DATA = 1, 216 }; 217 218 enum ath10k_hw_rev { 219 ATH10K_HW_QCA988X, 220 ATH10K_HW_QCA6174, 221 ATH10K_HW_QCA99X0, 222 ATH10K_HW_QCA9888, 223 ATH10K_HW_QCA9984, 224 ATH10K_HW_QCA9377, 225 ATH10K_HW_QCA4019, 226 ATH10K_HW_QCA9887, 227 }; 228 229 struct ath10k_hw_regs { 230 u32 rtc_soc_base_address; 231 u32 rtc_wmac_base_address; 232 u32 soc_core_base_address; 233 u32 ce_wrapper_base_address; 234 u32 ce0_base_address; 235 u32 ce1_base_address; 236 u32 ce2_base_address; 237 u32 ce3_base_address; 238 u32 ce4_base_address; 239 u32 ce5_base_address; 240 u32 ce6_base_address; 241 u32 ce7_base_address; 242 u32 soc_reset_control_si0_rst_mask; 243 u32 soc_reset_control_ce_rst_mask; 244 u32 soc_chip_id_address; 245 u32 scratch_3_address; 246 u32 fw_indicator_address; 247 u32 pcie_local_base_address; 248 u32 ce_wrap_intr_sum_host_msi_lsb; 249 u32 ce_wrap_intr_sum_host_msi_mask; 250 u32 pcie_intr_fw_mask; 251 u32 pcie_intr_ce_mask_all; 252 u32 pcie_intr_clr_address; 253 }; 254 255 extern const struct ath10k_hw_regs qca988x_regs; 256 extern const struct ath10k_hw_regs qca6174_regs; 257 extern const struct ath10k_hw_regs qca99x0_regs; 258 extern const struct ath10k_hw_regs qca4019_regs; 259 260 struct ath10k_hw_values { 261 u32 rtc_state_val_on; 262 u8 ce_count; 263 u8 msi_assign_ce_max; 264 u8 num_target_ce_config_wlan; 265 u16 ce_desc_meta_data_mask; 266 u8 ce_desc_meta_data_lsb; 267 }; 268 269 extern const struct ath10k_hw_values qca988x_values; 270 extern const struct ath10k_hw_values qca6174_values; 271 extern const struct ath10k_hw_values qca99x0_values; 272 extern const struct ath10k_hw_values qca9888_values; 273 extern const struct ath10k_hw_values qca4019_values; 274 275 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 276 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 277 278 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 279 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 280 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 281 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 282 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 283 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 284 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 285 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 286 287 /* Known peculiarities: 288 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 289 * - raw have FCS, nwifi doesn't 290 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 291 * param, llc/snap) are aligned to 4byte boundaries each */ 292 enum ath10k_hw_txrx_mode { 293 ATH10K_HW_TXRX_RAW = 0, 294 295 /* Native Wifi decap mode is used to align IP frames to 4-byte 296 * boundaries and avoid a very expensive re-alignment in mac80211. 297 */ 298 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 299 ATH10K_HW_TXRX_ETHERNET = 2, 300 301 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 302 ATH10K_HW_TXRX_MGMT = 3, 303 }; 304 305 enum ath10k_mcast2ucast_mode { 306 ATH10K_MCAST2UCAST_DISABLED = 0, 307 ATH10K_MCAST2UCAST_ENABLED = 1, 308 }; 309 310 enum ath10k_hw_rate_ofdm { 311 ATH10K_HW_RATE_OFDM_48M = 0, 312 ATH10K_HW_RATE_OFDM_24M, 313 ATH10K_HW_RATE_OFDM_12M, 314 ATH10K_HW_RATE_OFDM_6M, 315 ATH10K_HW_RATE_OFDM_54M, 316 ATH10K_HW_RATE_OFDM_36M, 317 ATH10K_HW_RATE_OFDM_18M, 318 ATH10K_HW_RATE_OFDM_9M, 319 }; 320 321 enum ath10k_hw_rate_cck { 322 ATH10K_HW_RATE_CCK_LP_11M = 0, 323 ATH10K_HW_RATE_CCK_LP_5_5M, 324 ATH10K_HW_RATE_CCK_LP_2M, 325 ATH10K_HW_RATE_CCK_LP_1M, 326 ATH10K_HW_RATE_CCK_SP_11M, 327 ATH10K_HW_RATE_CCK_SP_5_5M, 328 ATH10K_HW_RATE_CCK_SP_2M, 329 }; 330 331 enum ath10k_hw_rate_rev2_cck { 332 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 333 ATH10K_HW_RATE_REV2_CCK_LP_2M, 334 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 335 ATH10K_HW_RATE_REV2_CCK_LP_11M, 336 ATH10K_HW_RATE_REV2_CCK_SP_2M, 337 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 338 ATH10K_HW_RATE_REV2_CCK_SP_11M, 339 }; 340 341 enum ath10k_hw_cc_wraparound_type { 342 ATH10K_HW_CC_WRAP_DISABLED = 0, 343 344 /* This type is when the HW chip has a quirky Cycle Counter 345 * wraparound which resets to 0x7fffffff instead of 0. All 346 * other CC related counters (e.g. Rx Clear Count) are divided 347 * by 2 so they never wraparound themselves. 348 */ 349 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 350 351 /* Each hw counter wrapsaround independently. When the 352 * counter overflows the repestive counter is right shifted 353 * by 1, i.e reset to 0x7fffffff, and other counters will be 354 * running unaffected. In this type of wraparound, it should 355 * be possible to report accurate Rx busy time unlike the 356 * first type. 357 */ 358 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 359 }; 360 361 struct ath10k_hw_params { 362 u32 id; 363 u16 dev_id; 364 const char *name; 365 u32 patch_load_addr; 366 int uart_pin; 367 u32 otp_exe_param; 368 369 /* Type of hw cycle counter wraparound logic, for more info 370 * refer enum ath10k_hw_cc_wraparound_type. 371 */ 372 enum ath10k_hw_cc_wraparound_type cc_wraparound_type; 373 374 /* Some of chip expects fragment descriptor to be continuous 375 * memory for any TX operation. Set continuous_frag_desc flag 376 * for the hardware which have such requirement. 377 */ 378 bool continuous_frag_desc; 379 380 /* CCK hardware rate table mapping for the newer chipsets 381 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values 382 * are in a proper order with respect to the rate/preamble 383 */ 384 bool cck_rate_map_rev2; 385 386 u32 channel_counters_freq_hz; 387 388 /* Mgmt tx descriptors threshold for limiting probe response 389 * frames. 390 */ 391 u32 max_probe_resp_desc_thres; 392 393 u32 tx_chain_mask; 394 u32 rx_chain_mask; 395 u32 max_spatial_stream; 396 u32 cal_data_len; 397 398 struct ath10k_hw_params_fw { 399 const char *dir; 400 const char *board; 401 size_t board_size; 402 size_t board_ext_size; 403 } fw; 404 405 /* qca99x0 family chips deliver broadcast/multicast management 406 * frames encrypted and expect software do decryption. 407 */ 408 bool sw_decrypt_mcast_mgmt; 409 410 const struct ath10k_hw_ops *hw_ops; 411 412 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ 413 int decap_align_bytes; 414 }; 415 416 struct htt_rx_desc; 417 418 /* Defines needed for Rx descriptor abstraction */ 419 struct ath10k_hw_ops { 420 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 421 }; 422 423 extern const struct ath10k_hw_ops qca988x_ops; 424 extern const struct ath10k_hw_ops qca99x0_ops; 425 426 static inline int 427 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, 428 struct htt_rx_desc *rxd) 429 { 430 if (hw->hw_ops->rx_desc_get_l3_pad_bytes) 431 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd); 432 return 0; 433 } 434 435 /* Target specific defines for MAIN firmware */ 436 #define TARGET_NUM_VDEVS 8 437 #define TARGET_NUM_PEER_AST 2 438 #define TARGET_NUM_WDS_ENTRIES 32 439 #define TARGET_DMA_BURST_SIZE 0 440 #define TARGET_MAC_AGGR_DELIM 0 441 #define TARGET_AST_SKID_LIMIT 16 442 #define TARGET_NUM_STATIONS 16 443 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 444 (TARGET_NUM_VDEVS)) 445 #define TARGET_NUM_OFFLOAD_PEERS 0 446 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 447 #define TARGET_NUM_PEER_KEYS 2 448 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 449 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 450 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 451 #define TARGET_RX_TIMEOUT_LO_PRI 100 452 #define TARGET_RX_TIMEOUT_HI_PRI 40 453 454 #define TARGET_SCAN_MAX_PENDING_REQS 4 455 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 456 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 457 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 458 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 459 #define TARGET_NUM_MCAST_GROUPS 0 460 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 461 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 462 #define TARGET_TX_DBG_LOG_SIZE 1024 463 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 464 #define TARGET_VOW_CONFIG 0 465 #define TARGET_NUM_MSDU_DESC (1024 + 400) 466 #define TARGET_MAX_FRAG_ENTRIES 0 467 468 /* Target specific defines for 10.X firmware */ 469 #define TARGET_10X_NUM_VDEVS 16 470 #define TARGET_10X_NUM_PEER_AST 2 471 #define TARGET_10X_NUM_WDS_ENTRIES 32 472 #define TARGET_10X_DMA_BURST_SIZE 0 473 #define TARGET_10X_MAC_AGGR_DELIM 0 474 #define TARGET_10X_AST_SKID_LIMIT 128 475 #define TARGET_10X_NUM_STATIONS 128 476 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 477 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 478 (TARGET_10X_NUM_VDEVS)) 479 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 480 (TARGET_10X_NUM_VDEVS)) 481 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 482 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 483 #define TARGET_10X_NUM_PEER_KEYS 2 484 #define TARGET_10X_NUM_TIDS_MAX 256 485 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 486 (TARGET_10X_NUM_PEERS) * 2) 487 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 488 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 489 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 490 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 491 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 492 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 493 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 494 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 495 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 496 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 497 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 498 #define TARGET_10X_NUM_MCAST_GROUPS 0 499 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 500 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 501 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 502 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 503 #define TARGET_10X_VOW_CONFIG 0 504 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 505 #define TARGET_10X_MAX_FRAG_ENTRIES 0 506 507 /* 10.2 parameters */ 508 #define TARGET_10_2_DMA_BURST_SIZE 0 509 510 /* Target specific defines for WMI-TLV firmware */ 511 #define TARGET_TLV_NUM_VDEVS 4 512 #define TARGET_TLV_NUM_STATIONS 32 513 #define TARGET_TLV_NUM_PEERS 35 514 #define TARGET_TLV_NUM_TDLS_VDEVS 1 515 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 516 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 517 #define TARGET_TLV_NUM_WOW_PATTERNS 22 518 519 /* Diagnostic Window */ 520 #define CE_DIAG_PIPE 7 521 522 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 523 524 /* Target specific defines for 10.4 firmware */ 525 #define TARGET_10_4_NUM_VDEVS 16 526 #define TARGET_10_4_NUM_STATIONS 32 527 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 528 (TARGET_10_4_NUM_VDEVS)) 529 #define TARGET_10_4_ACTIVE_PEERS 0 530 531 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 532 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 533 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 534 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 535 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 536 #define TARGET_10_4_NUM_PEER_KEYS 2 537 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 538 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 539 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 540 #define TARGET_10_4_AST_SKID_LIMIT 32 541 542 /* 100 ms for video, best-effort, and background */ 543 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 544 545 /* 40 ms for voice */ 546 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 547 548 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 549 #define TARGET_10_4_SCAN_MAX_REQS 4 550 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 551 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 552 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 553 554 /* Note: mcast to ucast is disabled by default */ 555 #define TARGET_10_4_NUM_MCAST_GROUPS 0 556 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 557 #define TARGET_10_4_MCAST2UCAST_MODE 0 558 559 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 560 #define TARGET_10_4_NUM_WDS_ENTRIES 32 561 #define TARGET_10_4_DMA_BURST_SIZE 0 562 #define TARGET_10_4_MAC_AGGR_DELIM 0 563 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 564 #define TARGET_10_4_VOW_CONFIG 0 565 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 566 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 567 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 568 #define TARGET_10_4_SMART_ANT_CAP 0 569 #define TARGET_10_4_BK_MIN_FREE 0 570 #define TARGET_10_4_BE_MIN_FREE 0 571 #define TARGET_10_4_VI_MIN_FREE 0 572 #define TARGET_10_4_VO_MIN_FREE 0 573 #define TARGET_10_4_RX_BATCH_MODE 1 574 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 575 #define TARGET_10_4_ATF_CONFIG 0 576 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 577 #define TARGET_10_4_QWRAP_CONFIG 0 578 579 /* Number of Copy Engines supported */ 580 #define CE_COUNT ar->hw_values->ce_count 581 582 /* 583 * Granted MSIs are assigned as follows: 584 * Firmware uses the first 585 * Remaining MSIs, if any, are used by Copy Engines 586 * This mapping is known to both Target firmware and Host software. 587 * It may be changed as long as Host and Target are kept in sync. 588 */ 589 /* MSI for firmware (errors, etc.) */ 590 #define MSI_ASSIGN_FW 0 591 592 /* MSIs for Copy Engines */ 593 #define MSI_ASSIGN_CE_INITIAL 1 594 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 595 596 /* as of IP3.7.1 */ 597 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 598 599 #define RTC_STATE_V_LSB 0 600 #define RTC_STATE_V_MASK 0x00000007 601 #define RTC_STATE_ADDRESS 0x0000 602 #define PCIE_SOC_WAKE_V_MASK 0x00000001 603 #define PCIE_SOC_WAKE_ADDRESS 0x0004 604 #define PCIE_SOC_WAKE_RESET 0x00000000 605 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 606 607 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 608 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 609 #define MAC_COEX_BASE_ADDRESS 0x00006000 610 #define BT_COEX_BASE_ADDRESS 0x00007000 611 #define SOC_PCIE_BASE_ADDRESS 0x00008000 612 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 613 #define WLAN_UART_BASE_ADDRESS 0x0000c000 614 #define WLAN_SI_BASE_ADDRESS 0x00010000 615 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 616 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 617 #define WLAN_MAC_BASE_ADDRESS 0x00020000 618 #define EFUSE_BASE_ADDRESS 0x00030000 619 #define FPGA_REG_BASE_ADDRESS 0x00039000 620 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 621 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 622 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 623 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 624 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 625 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 626 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 627 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 628 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 629 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 630 #define DBI_BASE_ADDRESS 0x00060000 631 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 632 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 633 634 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 635 #define SOC_RESET_CONTROL_OFFSET 0x00000000 636 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 637 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 638 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 639 #define SOC_CPU_CLOCK_OFFSET 0x00000020 640 #define SOC_CPU_CLOCK_STANDARD_LSB 0 641 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 642 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 643 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 644 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 645 #define SOC_LPO_CAL_OFFSET 0x000000e0 646 #define SOC_LPO_CAL_ENABLE_LSB 20 647 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 648 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 649 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 650 651 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 652 #define SOC_CHIP_ID_REV_LSB 8 653 #define SOC_CHIP_ID_REV_MASK 0x00000f00 654 655 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 656 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 657 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 658 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 659 660 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 661 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 662 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 663 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 664 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 665 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 666 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 667 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 668 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 669 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 670 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 671 672 #define CLOCK_GPIO_OFFSET 0xffffffff 673 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 674 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 675 676 #define SI_CONFIG_OFFSET 0x00000000 677 #define SI_CONFIG_ERR_INT_LSB 19 678 #define SI_CONFIG_ERR_INT_MASK 0x00080000 679 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 680 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 681 #define SI_CONFIG_I2C_LSB 16 682 #define SI_CONFIG_I2C_MASK 0x00010000 683 #define SI_CONFIG_POS_SAMPLE_LSB 7 684 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 685 #define SI_CONFIG_INACTIVE_DATA_LSB 5 686 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 687 #define SI_CONFIG_INACTIVE_CLK_LSB 4 688 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 689 #define SI_CONFIG_DIVIDER_LSB 0 690 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 691 #define SI_CS_OFFSET 0x00000004 692 #define SI_CS_DONE_ERR_LSB 10 693 #define SI_CS_DONE_ERR_MASK 0x00000400 694 #define SI_CS_DONE_INT_LSB 9 695 #define SI_CS_DONE_INT_MASK 0x00000200 696 #define SI_CS_START_LSB 8 697 #define SI_CS_START_MASK 0x00000100 698 #define SI_CS_RX_CNT_LSB 4 699 #define SI_CS_RX_CNT_MASK 0x000000f0 700 #define SI_CS_TX_CNT_LSB 0 701 #define SI_CS_TX_CNT_MASK 0x0000000f 702 703 #define SI_TX_DATA0_OFFSET 0x00000008 704 #define SI_TX_DATA1_OFFSET 0x0000000c 705 #define SI_RX_DATA0_OFFSET 0x00000010 706 #define SI_RX_DATA1_OFFSET 0x00000014 707 708 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 709 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 710 #define CORE_CTRL_ADDRESS 0x0000 711 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 712 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 713 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 714 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 715 #define CPU_INTR_ADDRESS 0x0010 716 717 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 718 719 /* Firmware indications to the Host via SCRATCH_3 register. */ 720 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 721 #define FW_IND_EVENT_PENDING 1 722 #define FW_IND_INITIALIZED 2 723 #define FW_IND_HOST_READY 0x80000000 724 725 /* HOST_REG interrupt from firmware */ 726 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 727 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 728 729 #define DRAM_BASE_ADDRESS 0x00400000 730 731 #define PCIE_BAR_REG_ADDRESS 0x40030 732 733 #define MISSING 0 734 735 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 736 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 737 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 738 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 739 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 740 #define RESET_CONTROL_MBOX_RST_MASK MISSING 741 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 742 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 743 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 744 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 745 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 746 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 747 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 748 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 749 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 750 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 751 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 752 #define LOCAL_SCRATCH_OFFSET 0x18 753 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 754 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 755 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 756 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 757 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 758 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 759 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 760 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 761 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 762 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 763 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 764 #define MBOX_BASE_ADDRESS MISSING 765 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 766 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 767 #define INT_STATUS_ENABLE_CPU_LSB MISSING 768 #define INT_STATUS_ENABLE_CPU_MASK MISSING 769 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 770 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 771 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 772 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 773 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 774 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 775 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 776 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 777 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 778 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 779 #define INT_STATUS_ENABLE_ADDRESS MISSING 780 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 781 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 782 #define HOST_INT_STATUS_ADDRESS MISSING 783 #define CPU_INT_STATUS_ADDRESS MISSING 784 #define ERROR_INT_STATUS_ADDRESS MISSING 785 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 786 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 787 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 788 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 789 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 790 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 791 #define COUNT_DEC_ADDRESS MISSING 792 #define HOST_INT_STATUS_CPU_MASK MISSING 793 #define HOST_INT_STATUS_CPU_LSB MISSING 794 #define HOST_INT_STATUS_ERROR_MASK MISSING 795 #define HOST_INT_STATUS_ERROR_LSB MISSING 796 #define HOST_INT_STATUS_COUNTER_MASK MISSING 797 #define HOST_INT_STATUS_COUNTER_LSB MISSING 798 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 799 #define WINDOW_DATA_ADDRESS MISSING 800 #define WINDOW_READ_ADDR_ADDRESS MISSING 801 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 802 803 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 804 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 805 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 806 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 807 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 808 809 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 810 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 811 #define QCA9887_EEPROM_ADDR_HI_LSB 8 812 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 813 #define QCA9887_EEPROM_ADDR_LO_LSB 16 814 815 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 816 817 #endif /* _HW_H_ */ 818