1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HW_H_ 19 #define _HW_H_ 20 21 #include "targaddrs.h" 22 23 #define ATH10K_FW_DIR "ath10k" 24 25 #define QCA988X_2_0_DEVICE_ID (0x003c) 26 #define QCA6164_2_1_DEVICE_ID (0x0041) 27 #define QCA6174_2_1_DEVICE_ID (0x003e) 28 #define QCA99X0_2_0_DEVICE_ID (0x0040) 29 #define QCA9888_2_0_DEVICE_ID (0x0056) 30 #define QCA9984_1_0_DEVICE_ID (0x0046) 31 #define QCA9377_1_0_DEVICE_ID (0x0042) 32 #define QCA9887_1_0_DEVICE_ID (0x0050) 33 34 /* QCA988X 1.0 definitions (unsupported) */ 35 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 36 37 /* QCA988X 2.0 definitions */ 38 #define QCA988X_HW_2_0_VERSION 0x4100016c 39 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 40 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 41 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 43 44 /* QCA9887 1.0 definitions */ 45 #define QCA9887_HW_1_0_VERSION 0x4100016d 46 #define QCA9887_HW_1_0_CHIP_ID_REV 0 47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 48 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" 49 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 50 51 /* QCA6174 target BMI version signatures */ 52 #define QCA6174_HW_1_0_VERSION 0x05000000 53 #define QCA6174_HW_1_1_VERSION 0x05000001 54 #define QCA6174_HW_1_3_VERSION 0x05000003 55 #define QCA6174_HW_2_1_VERSION 0x05010000 56 #define QCA6174_HW_3_0_VERSION 0x05020000 57 #define QCA6174_HW_3_2_VERSION 0x05030000 58 59 /* QCA9377 target BMI version signatures */ 60 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 61 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 62 63 enum qca6174_pci_rev { 64 QCA6174_PCI_REV_1_1 = 0x11, 65 QCA6174_PCI_REV_1_3 = 0x13, 66 QCA6174_PCI_REV_2_0 = 0x20, 67 QCA6174_PCI_REV_3_0 = 0x30, 68 }; 69 70 enum qca6174_chip_id_rev { 71 QCA6174_HW_1_0_CHIP_ID_REV = 0, 72 QCA6174_HW_1_1_CHIP_ID_REV = 1, 73 QCA6174_HW_1_3_CHIP_ID_REV = 2, 74 QCA6174_HW_2_1_CHIP_ID_REV = 4, 75 QCA6174_HW_2_2_CHIP_ID_REV = 5, 76 QCA6174_HW_3_0_CHIP_ID_REV = 8, 77 QCA6174_HW_3_1_CHIP_ID_REV = 9, 78 QCA6174_HW_3_2_CHIP_ID_REV = 10, 79 }; 80 81 enum qca9377_chip_id_rev { 82 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 83 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 84 }; 85 86 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" 87 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 88 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 89 90 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" 91 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 92 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 93 94 /* QCA99X0 1.0 definitions (unsupported) */ 95 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 96 97 /* QCA99X0 2.0 definitions */ 98 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 99 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 100 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 101 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 102 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 103 104 /* QCA9984 1.0 defines */ 105 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 106 #define QCA9984_HW_DEV_TYPE 0xa 107 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 108 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 109 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" 110 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 111 112 /* QCA9888 2.0 defines */ 113 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 114 #define QCA9888_HW_DEV_TYPE 0xc 115 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 116 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 117 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" 118 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 119 120 /* QCA9377 1.0 definitions */ 121 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 122 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 123 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 124 125 /* QCA4019 1.0 definitions */ 126 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 127 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 128 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" 129 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 130 131 #define ATH10K_FW_FILE_BASE "firmware" 132 #define ATH10K_FW_API_MAX 6 133 #define ATH10K_FW_API_MIN 2 134 135 #define ATH10K_FW_API2_FILE "firmware-2.bin" 136 #define ATH10K_FW_API3_FILE "firmware-3.bin" 137 138 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 139 #define ATH10K_FW_API4_FILE "firmware-4.bin" 140 141 /* HTT id conflict fix for management frames over HTT */ 142 #define ATH10K_FW_API5_FILE "firmware-5.bin" 143 144 /* the firmware-6.bin blob */ 145 #define ATH10K_FW_API6_FILE "firmware-6.bin" 146 147 #define ATH10K_FW_UTF_FILE "utf.bin" 148 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 149 150 /* includes also the null byte */ 151 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 152 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 153 154 #define ATH10K_BOARD_API2_FILE "board-2.bin" 155 156 #define REG_DUMP_COUNT_QCA988X 60 157 158 struct ath10k_fw_ie { 159 __le32 id; 160 __le32 len; 161 u8 data[0]; 162 }; 163 164 enum ath10k_fw_ie_type { 165 ATH10K_FW_IE_FW_VERSION = 0, 166 ATH10K_FW_IE_TIMESTAMP = 1, 167 ATH10K_FW_IE_FEATURES = 2, 168 ATH10K_FW_IE_FW_IMAGE = 3, 169 ATH10K_FW_IE_OTP_IMAGE = 4, 170 171 /* WMI "operations" interface version, 32 bit value. Supported from 172 * FW API 4 and above. 173 */ 174 ATH10K_FW_IE_WMI_OP_VERSION = 5, 175 176 /* HTT "operations" interface version, 32 bit value. Supported from 177 * FW API 5 and above. 178 */ 179 ATH10K_FW_IE_HTT_OP_VERSION = 6, 180 181 /* Code swap image for firmware binary */ 182 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 183 }; 184 185 enum ath10k_fw_wmi_op_version { 186 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 187 188 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 189 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 190 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 191 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 192 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 193 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 194 195 /* keep last */ 196 ATH10K_FW_WMI_OP_VERSION_MAX, 197 }; 198 199 enum ath10k_fw_htt_op_version { 200 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 201 202 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 203 204 /* also used in 10.2 and 10.2.4 branches */ 205 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 206 207 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 208 209 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 210 211 /* keep last */ 212 ATH10K_FW_HTT_OP_VERSION_MAX, 213 }; 214 215 enum ath10k_bd_ie_type { 216 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 217 ATH10K_BD_IE_BOARD = 0, 218 }; 219 220 enum ath10k_bd_ie_board_type { 221 ATH10K_BD_IE_BOARD_NAME = 0, 222 ATH10K_BD_IE_BOARD_DATA = 1, 223 }; 224 225 enum ath10k_hw_rev { 226 ATH10K_HW_QCA988X, 227 ATH10K_HW_QCA6174, 228 ATH10K_HW_QCA99X0, 229 ATH10K_HW_QCA9888, 230 ATH10K_HW_QCA9984, 231 ATH10K_HW_QCA9377, 232 ATH10K_HW_QCA4019, 233 ATH10K_HW_QCA9887, 234 }; 235 236 struct ath10k_hw_regs { 237 u32 rtc_soc_base_address; 238 u32 rtc_wmac_base_address; 239 u32 soc_core_base_address; 240 u32 wlan_mac_base_address; 241 u32 ce_wrapper_base_address; 242 u32 ce0_base_address; 243 u32 ce1_base_address; 244 u32 ce2_base_address; 245 u32 ce3_base_address; 246 u32 ce4_base_address; 247 u32 ce5_base_address; 248 u32 ce6_base_address; 249 u32 ce7_base_address; 250 u32 soc_reset_control_si0_rst_mask; 251 u32 soc_reset_control_ce_rst_mask; 252 u32 soc_chip_id_address; 253 u32 scratch_3_address; 254 u32 fw_indicator_address; 255 u32 pcie_local_base_address; 256 u32 ce_wrap_intr_sum_host_msi_lsb; 257 u32 ce_wrap_intr_sum_host_msi_mask; 258 u32 pcie_intr_fw_mask; 259 u32 pcie_intr_ce_mask_all; 260 u32 pcie_intr_clr_address; 261 u32 cpu_pll_init_address; 262 u32 cpu_speed_address; 263 u32 core_clk_div_address; 264 }; 265 266 extern const struct ath10k_hw_regs qca988x_regs; 267 extern const struct ath10k_hw_regs qca6174_regs; 268 extern const struct ath10k_hw_regs qca99x0_regs; 269 extern const struct ath10k_hw_regs qca4019_regs; 270 271 struct ath10k_hw_values { 272 u32 rtc_state_val_on; 273 u8 ce_count; 274 u8 msi_assign_ce_max; 275 u8 num_target_ce_config_wlan; 276 u16 ce_desc_meta_data_mask; 277 u8 ce_desc_meta_data_lsb; 278 }; 279 280 extern const struct ath10k_hw_values qca988x_values; 281 extern const struct ath10k_hw_values qca6174_values; 282 extern const struct ath10k_hw_values qca99x0_values; 283 extern const struct ath10k_hw_values qca9888_values; 284 extern const struct ath10k_hw_values qca4019_values; 285 286 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 287 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 288 289 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 290 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 291 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 292 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 293 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 294 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 295 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 296 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 297 298 /* Known peculiarities: 299 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 300 * - raw have FCS, nwifi doesn't 301 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 302 * param, llc/snap) are aligned to 4byte boundaries each 303 */ 304 enum ath10k_hw_txrx_mode { 305 ATH10K_HW_TXRX_RAW = 0, 306 307 /* Native Wifi decap mode is used to align IP frames to 4-byte 308 * boundaries and avoid a very expensive re-alignment in mac80211. 309 */ 310 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 311 ATH10K_HW_TXRX_ETHERNET = 2, 312 313 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 314 ATH10K_HW_TXRX_MGMT = 3, 315 }; 316 317 enum ath10k_mcast2ucast_mode { 318 ATH10K_MCAST2UCAST_DISABLED = 0, 319 ATH10K_MCAST2UCAST_ENABLED = 1, 320 }; 321 322 enum ath10k_hw_rate_ofdm { 323 ATH10K_HW_RATE_OFDM_48M = 0, 324 ATH10K_HW_RATE_OFDM_24M, 325 ATH10K_HW_RATE_OFDM_12M, 326 ATH10K_HW_RATE_OFDM_6M, 327 ATH10K_HW_RATE_OFDM_54M, 328 ATH10K_HW_RATE_OFDM_36M, 329 ATH10K_HW_RATE_OFDM_18M, 330 ATH10K_HW_RATE_OFDM_9M, 331 }; 332 333 enum ath10k_hw_rate_cck { 334 ATH10K_HW_RATE_CCK_LP_11M = 0, 335 ATH10K_HW_RATE_CCK_LP_5_5M, 336 ATH10K_HW_RATE_CCK_LP_2M, 337 ATH10K_HW_RATE_CCK_LP_1M, 338 ATH10K_HW_RATE_CCK_SP_11M, 339 ATH10K_HW_RATE_CCK_SP_5_5M, 340 ATH10K_HW_RATE_CCK_SP_2M, 341 }; 342 343 enum ath10k_hw_rate_rev2_cck { 344 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 345 ATH10K_HW_RATE_REV2_CCK_LP_2M, 346 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 347 ATH10K_HW_RATE_REV2_CCK_LP_11M, 348 ATH10K_HW_RATE_REV2_CCK_SP_2M, 349 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 350 ATH10K_HW_RATE_REV2_CCK_SP_11M, 351 }; 352 353 enum ath10k_hw_cc_wraparound_type { 354 ATH10K_HW_CC_WRAP_DISABLED = 0, 355 356 /* This type is when the HW chip has a quirky Cycle Counter 357 * wraparound which resets to 0x7fffffff instead of 0. All 358 * other CC related counters (e.g. Rx Clear Count) are divided 359 * by 2 so they never wraparound themselves. 360 */ 361 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 362 363 /* Each hw counter wrapsaround independently. When the 364 * counter overflows the repestive counter is right shifted 365 * by 1, i.e reset to 0x7fffffff, and other counters will be 366 * running unaffected. In this type of wraparound, it should 367 * be possible to report accurate Rx busy time unlike the 368 * first type. 369 */ 370 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 371 }; 372 373 enum ath10k_hw_refclk_speed { 374 ATH10K_HW_REFCLK_UNKNOWN = -1, 375 ATH10K_HW_REFCLK_48_MHZ = 0, 376 ATH10K_HW_REFCLK_19_2_MHZ = 1, 377 ATH10K_HW_REFCLK_24_MHZ = 2, 378 ATH10K_HW_REFCLK_26_MHZ = 3, 379 ATH10K_HW_REFCLK_37_4_MHZ = 4, 380 ATH10K_HW_REFCLK_38_4_MHZ = 5, 381 ATH10K_HW_REFCLK_40_MHZ = 6, 382 ATH10K_HW_REFCLK_52_MHZ = 7, 383 384 /* must be the last one */ 385 ATH10K_HW_REFCLK_COUNT, 386 }; 387 388 struct ath10k_hw_clk_params { 389 u32 refclk; 390 u32 div; 391 u32 rnfrac; 392 u32 settle_time; 393 u32 refdiv; 394 u32 outdiv; 395 }; 396 397 struct ath10k_hw_params { 398 u32 id; 399 u16 dev_id; 400 const char *name; 401 u32 patch_load_addr; 402 int uart_pin; 403 u32 otp_exe_param; 404 405 /* Type of hw cycle counter wraparound logic, for more info 406 * refer enum ath10k_hw_cc_wraparound_type. 407 */ 408 enum ath10k_hw_cc_wraparound_type cc_wraparound_type; 409 410 /* Some of chip expects fragment descriptor to be continuous 411 * memory for any TX operation. Set continuous_frag_desc flag 412 * for the hardware which have such requirement. 413 */ 414 bool continuous_frag_desc; 415 416 /* CCK hardware rate table mapping for the newer chipsets 417 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values 418 * are in a proper order with respect to the rate/preamble 419 */ 420 bool cck_rate_map_rev2; 421 422 u32 channel_counters_freq_hz; 423 424 /* Mgmt tx descriptors threshold for limiting probe response 425 * frames. 426 */ 427 u32 max_probe_resp_desc_thres; 428 429 u32 tx_chain_mask; 430 u32 rx_chain_mask; 431 u32 max_spatial_stream; 432 u32 cal_data_len; 433 434 struct ath10k_hw_params_fw { 435 const char *dir; 436 const char *board; 437 size_t board_size; 438 size_t board_ext_size; 439 } fw; 440 441 /* qca99x0 family chips deliver broadcast/multicast management 442 * frames encrypted and expect software do decryption. 443 */ 444 bool sw_decrypt_mcast_mgmt; 445 446 const struct ath10k_hw_ops *hw_ops; 447 448 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ 449 int decap_align_bytes; 450 451 /* hw specific clock control parameters */ 452 const struct ath10k_hw_clk_params *hw_clk; 453 int target_cpu_freq; 454 455 /* Number of bytes to be discarded for each FFT sample */ 456 int spectral_bin_discard; 457 }; 458 459 struct htt_rx_desc; 460 461 /* Defines needed for Rx descriptor abstraction */ 462 struct ath10k_hw_ops { 463 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 464 void (*set_coverage_class)(struct ath10k *ar, s16 value); 465 int (*enable_pll_clk)(struct ath10k *ar); 466 }; 467 468 extern const struct ath10k_hw_ops qca988x_ops; 469 extern const struct ath10k_hw_ops qca99x0_ops; 470 extern const struct ath10k_hw_ops qca6174_ops; 471 472 extern const struct ath10k_hw_clk_params qca6174_clk[]; 473 474 static inline int 475 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, 476 struct htt_rx_desc *rxd) 477 { 478 if (hw->hw_ops->rx_desc_get_l3_pad_bytes) 479 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd); 480 return 0; 481 } 482 483 /* Target specific defines for MAIN firmware */ 484 #define TARGET_NUM_VDEVS 8 485 #define TARGET_NUM_PEER_AST 2 486 #define TARGET_NUM_WDS_ENTRIES 32 487 #define TARGET_DMA_BURST_SIZE 0 488 #define TARGET_MAC_AGGR_DELIM 0 489 #define TARGET_AST_SKID_LIMIT 16 490 #define TARGET_NUM_STATIONS 16 491 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 492 (TARGET_NUM_VDEVS)) 493 #define TARGET_NUM_OFFLOAD_PEERS 0 494 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 495 #define TARGET_NUM_PEER_KEYS 2 496 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 497 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 498 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 499 #define TARGET_RX_TIMEOUT_LO_PRI 100 500 #define TARGET_RX_TIMEOUT_HI_PRI 40 501 502 #define TARGET_SCAN_MAX_PENDING_REQS 4 503 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 504 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 505 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 506 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 507 #define TARGET_NUM_MCAST_GROUPS 0 508 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 509 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 510 #define TARGET_TX_DBG_LOG_SIZE 1024 511 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 512 #define TARGET_VOW_CONFIG 0 513 #define TARGET_NUM_MSDU_DESC (1024 + 400) 514 #define TARGET_MAX_FRAG_ENTRIES 0 515 516 /* Target specific defines for 10.X firmware */ 517 #define TARGET_10X_NUM_VDEVS 16 518 #define TARGET_10X_NUM_PEER_AST 2 519 #define TARGET_10X_NUM_WDS_ENTRIES 32 520 #define TARGET_10X_DMA_BURST_SIZE 0 521 #define TARGET_10X_MAC_AGGR_DELIM 0 522 #define TARGET_10X_AST_SKID_LIMIT 128 523 #define TARGET_10X_NUM_STATIONS 128 524 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 525 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 526 (TARGET_10X_NUM_VDEVS)) 527 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 528 (TARGET_10X_NUM_VDEVS)) 529 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 530 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 531 #define TARGET_10X_NUM_PEER_KEYS 2 532 #define TARGET_10X_NUM_TIDS_MAX 256 533 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 534 (TARGET_10X_NUM_PEERS) * 2) 535 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 536 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 537 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 538 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 539 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 540 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 541 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 542 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 543 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 544 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 545 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 546 #define TARGET_10X_NUM_MCAST_GROUPS 0 547 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 548 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 549 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 550 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 551 #define TARGET_10X_VOW_CONFIG 0 552 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 553 #define TARGET_10X_MAX_FRAG_ENTRIES 0 554 555 /* 10.2 parameters */ 556 #define TARGET_10_2_DMA_BURST_SIZE 0 557 558 /* Target specific defines for WMI-TLV firmware */ 559 #define TARGET_TLV_NUM_VDEVS 4 560 #define TARGET_TLV_NUM_STATIONS 32 561 #define TARGET_TLV_NUM_PEERS 33 562 #define TARGET_TLV_NUM_TDLS_VDEVS 1 563 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 564 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 565 #define TARGET_TLV_NUM_WOW_PATTERNS 22 566 567 /* Diagnostic Window */ 568 #define CE_DIAG_PIPE 7 569 570 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 571 572 /* Target specific defines for 10.4 firmware */ 573 #define TARGET_10_4_NUM_VDEVS 16 574 #define TARGET_10_4_NUM_STATIONS 32 575 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 576 (TARGET_10_4_NUM_VDEVS)) 577 #define TARGET_10_4_ACTIVE_PEERS 0 578 579 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 580 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 581 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 582 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 583 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 584 #define TARGET_10_4_NUM_PEER_KEYS 2 585 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 586 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 587 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 588 #define TARGET_10_4_AST_SKID_LIMIT 32 589 590 /* 100 ms for video, best-effort, and background */ 591 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 592 593 /* 40 ms for voice */ 594 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 595 596 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 597 #define TARGET_10_4_SCAN_MAX_REQS 4 598 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 599 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 600 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 601 602 /* Note: mcast to ucast is disabled by default */ 603 #define TARGET_10_4_NUM_MCAST_GROUPS 0 604 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 605 #define TARGET_10_4_MCAST2UCAST_MODE 0 606 607 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 608 #define TARGET_10_4_NUM_WDS_ENTRIES 32 609 #define TARGET_10_4_DMA_BURST_SIZE 0 610 #define TARGET_10_4_MAC_AGGR_DELIM 0 611 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 612 #define TARGET_10_4_VOW_CONFIG 0 613 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 614 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 615 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 616 #define TARGET_10_4_SMART_ANT_CAP 0 617 #define TARGET_10_4_BK_MIN_FREE 0 618 #define TARGET_10_4_BE_MIN_FREE 0 619 #define TARGET_10_4_VI_MIN_FREE 0 620 #define TARGET_10_4_VO_MIN_FREE 0 621 #define TARGET_10_4_RX_BATCH_MODE 1 622 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 623 #define TARGET_10_4_ATF_CONFIG 0 624 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 625 #define TARGET_10_4_QWRAP_CONFIG 0 626 627 /* Maximum number of Copy Engine's supported */ 628 #define CE_COUNT_MAX 12 629 630 /* Number of Copy Engines supported */ 631 #define CE_COUNT ar->hw_values->ce_count 632 633 /* 634 * Granted MSIs are assigned as follows: 635 * Firmware uses the first 636 * Remaining MSIs, if any, are used by Copy Engines 637 * This mapping is known to both Target firmware and Host software. 638 * It may be changed as long as Host and Target are kept in sync. 639 */ 640 /* MSI for firmware (errors, etc.) */ 641 #define MSI_ASSIGN_FW 0 642 643 /* MSIs for Copy Engines */ 644 #define MSI_ASSIGN_CE_INITIAL 1 645 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 646 647 /* as of IP3.7.1 */ 648 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 649 650 #define RTC_STATE_V_LSB 0 651 #define RTC_STATE_V_MASK 0x00000007 652 #define RTC_STATE_ADDRESS 0x0000 653 #define PCIE_SOC_WAKE_V_MASK 0x00000001 654 #define PCIE_SOC_WAKE_ADDRESS 0x0004 655 #define PCIE_SOC_WAKE_RESET 0x00000000 656 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 657 658 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 659 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 660 #define MAC_COEX_BASE_ADDRESS 0x00006000 661 #define BT_COEX_BASE_ADDRESS 0x00007000 662 #define SOC_PCIE_BASE_ADDRESS 0x00008000 663 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 664 #define WLAN_UART_BASE_ADDRESS 0x0000c000 665 #define WLAN_SI_BASE_ADDRESS 0x00010000 666 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 667 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 668 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address 669 #define EFUSE_BASE_ADDRESS 0x00030000 670 #define FPGA_REG_BASE_ADDRESS 0x00039000 671 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 672 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 673 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 674 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 675 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 676 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 677 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 678 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 679 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 680 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 681 #define DBI_BASE_ADDRESS 0x00060000 682 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 683 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 684 685 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 686 #define SOC_RESET_CONTROL_OFFSET 0x00000000 687 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 688 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 689 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 690 #define SOC_CPU_CLOCK_OFFSET 0x00000020 691 #define SOC_CPU_CLOCK_STANDARD_LSB 0 692 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 693 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 694 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 695 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 696 #define SOC_LPO_CAL_OFFSET 0x000000e0 697 #define SOC_LPO_CAL_ENABLE_LSB 20 698 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 699 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 700 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 701 702 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 703 #define SOC_CHIP_ID_REV_LSB 8 704 #define SOC_CHIP_ID_REV_MASK 0x00000f00 705 706 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 707 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 708 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 709 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 710 711 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 712 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 713 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 714 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 715 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 716 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 717 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 718 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 719 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 720 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 721 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 722 723 #define CLOCK_GPIO_OFFSET 0xffffffff 724 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 725 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 726 727 #define SI_CONFIG_OFFSET 0x00000000 728 #define SI_CONFIG_ERR_INT_LSB 19 729 #define SI_CONFIG_ERR_INT_MASK 0x00080000 730 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 731 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 732 #define SI_CONFIG_I2C_LSB 16 733 #define SI_CONFIG_I2C_MASK 0x00010000 734 #define SI_CONFIG_POS_SAMPLE_LSB 7 735 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 736 #define SI_CONFIG_INACTIVE_DATA_LSB 5 737 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 738 #define SI_CONFIG_INACTIVE_CLK_LSB 4 739 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 740 #define SI_CONFIG_DIVIDER_LSB 0 741 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 742 #define SI_CS_OFFSET 0x00000004 743 #define SI_CS_DONE_ERR_LSB 10 744 #define SI_CS_DONE_ERR_MASK 0x00000400 745 #define SI_CS_DONE_INT_LSB 9 746 #define SI_CS_DONE_INT_MASK 0x00000200 747 #define SI_CS_START_LSB 8 748 #define SI_CS_START_MASK 0x00000100 749 #define SI_CS_RX_CNT_LSB 4 750 #define SI_CS_RX_CNT_MASK 0x000000f0 751 #define SI_CS_TX_CNT_LSB 0 752 #define SI_CS_TX_CNT_MASK 0x0000000f 753 754 #define SI_TX_DATA0_OFFSET 0x00000008 755 #define SI_TX_DATA1_OFFSET 0x0000000c 756 #define SI_RX_DATA0_OFFSET 0x00000010 757 #define SI_RX_DATA1_OFFSET 0x00000014 758 759 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 760 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 761 #define CORE_CTRL_ADDRESS 0x0000 762 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 763 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 764 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 765 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 766 #define CPU_INTR_ADDRESS 0x0010 767 768 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 769 770 /* Firmware indications to the Host via SCRATCH_3 register. */ 771 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 772 #define FW_IND_EVENT_PENDING 1 773 #define FW_IND_INITIALIZED 2 774 #define FW_IND_HOST_READY 0x80000000 775 776 /* HOST_REG interrupt from firmware */ 777 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 778 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 779 780 #define DRAM_BASE_ADDRESS 0x00400000 781 782 #define PCIE_BAR_REG_ADDRESS 0x40030 783 784 #define MISSING 0 785 786 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 787 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 788 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 789 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 790 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 791 #define RESET_CONTROL_MBOX_RST_MASK MISSING 792 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 793 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 794 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 795 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 796 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 797 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 798 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 799 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 800 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 801 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 802 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 803 #define LOCAL_SCRATCH_OFFSET 0x18 804 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 805 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 806 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 807 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 808 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 809 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 810 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 811 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 812 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 813 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 814 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 815 #define MBOX_BASE_ADDRESS MISSING 816 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 817 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 818 #define INT_STATUS_ENABLE_CPU_LSB MISSING 819 #define INT_STATUS_ENABLE_CPU_MASK MISSING 820 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 821 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 822 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 823 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 824 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 825 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 826 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 827 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 828 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 829 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 830 #define INT_STATUS_ENABLE_ADDRESS MISSING 831 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 832 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 833 #define HOST_INT_STATUS_ADDRESS MISSING 834 #define CPU_INT_STATUS_ADDRESS MISSING 835 #define ERROR_INT_STATUS_ADDRESS MISSING 836 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 837 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 838 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 839 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 840 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 841 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 842 #define COUNT_DEC_ADDRESS MISSING 843 #define HOST_INT_STATUS_CPU_MASK MISSING 844 #define HOST_INT_STATUS_CPU_LSB MISSING 845 #define HOST_INT_STATUS_ERROR_MASK MISSING 846 #define HOST_INT_STATUS_ERROR_LSB MISSING 847 #define HOST_INT_STATUS_COUNTER_MASK MISSING 848 #define HOST_INT_STATUS_COUNTER_LSB MISSING 849 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 850 #define WINDOW_DATA_ADDRESS MISSING 851 #define WINDOW_READ_ADDR_ADDRESS MISSING 852 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 853 854 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 855 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 856 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 857 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 858 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 859 860 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 861 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 862 #define QCA9887_EEPROM_ADDR_HI_LSB 8 863 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 864 #define QCA9887_EEPROM_ADDR_LO_LSB 16 865 866 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 867 868 /* Register definitions for first generation ath10k cards. These cards include 869 * a mac thich has a register allocation similar to ath9k and at least some 870 * registers including the ones relevant for modifying the coverage class are 871 * identical to the ath9k definitions. 872 * These registers are usually managed by the ath10k firmware. However by 873 * overriding them it is possible to support coverage class modifications. 874 */ 875 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014 876 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF 877 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF 878 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0 879 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000 880 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16 881 882 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070 883 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF 884 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF 885 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0 886 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000 887 888 #define WAVE1_PHYCLK 0x801C 889 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F 890 #define WAVE1_PHYCLK_USEC_LSB 0 891 892 /* qca6174 PLL offset/mask */ 893 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114 894 #define SOC_CORE_CLK_CTRL_DIV_LSB 0 895 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 896 897 #define EFUSE_OFFSET 0x0000032c 898 #define EFUSE_XTAL_SEL_LSB 8 899 #define EFUSE_XTAL_SEL_MASK 0x00000700 900 901 #define BB_PLL_CONFIG_OFFSET 0x000002f4 902 #define BB_PLL_CONFIG_FRAC_LSB 0 903 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff 904 #define BB_PLL_CONFIG_OUTDIV_LSB 18 905 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 906 907 #define WLAN_PLL_SETTLE_OFFSET 0x0018 908 #define WLAN_PLL_SETTLE_TIME_LSB 0 909 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff 910 911 #define WLAN_PLL_CONTROL_OFFSET 0x0014 912 #define WLAN_PLL_CONTROL_DIV_LSB 0 913 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff 914 #define WLAN_PLL_CONTROL_REFDIV_LSB 10 915 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 916 #define WLAN_PLL_CONTROL_BYPASS_LSB 16 917 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 918 #define WLAN_PLL_CONTROL_NOPWD_LSB 18 919 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 920 921 #define RTC_SYNC_STATUS_OFFSET 0x0244 922 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 923 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 924 /* qca6174 PLL offset/mask end */ 925 926 #endif /* _HW_H_ */ 927