1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HW_H_ 19 #define _HW_H_ 20 21 #include "targaddrs.h" 22 23 #define ATH10K_FW_DIR "ath10k" 24 25 #define QCA988X_2_0_DEVICE_ID (0x003c) 26 #define QCA6164_2_1_DEVICE_ID (0x0041) 27 #define QCA6174_2_1_DEVICE_ID (0x003e) 28 #define QCA99X0_2_0_DEVICE_ID (0x0040) 29 #define QCA9888_2_0_DEVICE_ID (0x0056) 30 #define QCA9984_1_0_DEVICE_ID (0x0046) 31 #define QCA9377_1_0_DEVICE_ID (0x0042) 32 #define QCA9887_1_0_DEVICE_ID (0x0050) 33 34 /* QCA988X 1.0 definitions (unsupported) */ 35 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 36 37 /* QCA988X 2.0 definitions */ 38 #define QCA988X_HW_2_0_VERSION 0x4100016c 39 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 40 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 41 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 43 44 /* QCA9887 1.0 definitions */ 45 #define QCA9887_HW_1_0_VERSION 0x4100016d 46 #define QCA9887_HW_1_0_CHIP_ID_REV 0 47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 48 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" 49 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 50 51 /* QCA6174 target BMI version signatures */ 52 #define QCA6174_HW_1_0_VERSION 0x05000000 53 #define QCA6174_HW_1_1_VERSION 0x05000001 54 #define QCA6174_HW_1_3_VERSION 0x05000003 55 #define QCA6174_HW_2_1_VERSION 0x05010000 56 #define QCA6174_HW_3_0_VERSION 0x05020000 57 #define QCA6174_HW_3_2_VERSION 0x05030000 58 59 /* QCA9377 target BMI version signatures */ 60 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 61 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 62 63 enum qca6174_pci_rev { 64 QCA6174_PCI_REV_1_1 = 0x11, 65 QCA6174_PCI_REV_1_3 = 0x13, 66 QCA6174_PCI_REV_2_0 = 0x20, 67 QCA6174_PCI_REV_3_0 = 0x30, 68 }; 69 70 enum qca6174_chip_id_rev { 71 QCA6174_HW_1_0_CHIP_ID_REV = 0, 72 QCA6174_HW_1_1_CHIP_ID_REV = 1, 73 QCA6174_HW_1_3_CHIP_ID_REV = 2, 74 QCA6174_HW_2_1_CHIP_ID_REV = 4, 75 QCA6174_HW_2_2_CHIP_ID_REV = 5, 76 QCA6174_HW_3_0_CHIP_ID_REV = 8, 77 QCA6174_HW_3_1_CHIP_ID_REV = 9, 78 QCA6174_HW_3_2_CHIP_ID_REV = 10, 79 }; 80 81 enum qca9377_chip_id_rev { 82 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 83 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 84 }; 85 86 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" 87 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 88 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 89 90 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" 91 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 92 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 93 94 /* QCA99X0 1.0 definitions (unsupported) */ 95 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 96 97 /* QCA99X0 2.0 definitions */ 98 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 99 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 100 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 101 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 102 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 103 104 /* QCA9984 1.0 defines */ 105 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 106 #define QCA9984_HW_DEV_TYPE 0xa 107 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 108 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 109 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" 110 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 111 112 /* QCA9888 2.0 defines */ 113 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 114 #define QCA9888_HW_DEV_TYPE 0xc 115 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 116 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 117 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" 118 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 119 120 /* QCA9377 1.0 definitions */ 121 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 122 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 123 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 124 125 /* QCA4019 1.0 definitions */ 126 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 127 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 128 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" 129 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 130 131 #define ATH10K_FW_FILE_BASE "firmware" 132 #define ATH10K_FW_API_MAX 6 133 #define ATH10K_FW_API_MIN 2 134 135 #define ATH10K_FW_API2_FILE "firmware-2.bin" 136 #define ATH10K_FW_API3_FILE "firmware-3.bin" 137 138 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 139 #define ATH10K_FW_API4_FILE "firmware-4.bin" 140 141 /* HTT id conflict fix for management frames over HTT */ 142 #define ATH10K_FW_API5_FILE "firmware-5.bin" 143 144 /* the firmware-6.bin blob */ 145 #define ATH10K_FW_API6_FILE "firmware-6.bin" 146 147 #define ATH10K_FW_UTF_FILE "utf.bin" 148 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 149 150 /* includes also the null byte */ 151 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 152 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 153 154 #define ATH10K_BOARD_API2_FILE "board-2.bin" 155 156 #define REG_DUMP_COUNT_QCA988X 60 157 158 struct ath10k_fw_ie { 159 __le32 id; 160 __le32 len; 161 u8 data[0]; 162 }; 163 164 enum ath10k_fw_ie_type { 165 ATH10K_FW_IE_FW_VERSION = 0, 166 ATH10K_FW_IE_TIMESTAMP = 1, 167 ATH10K_FW_IE_FEATURES = 2, 168 ATH10K_FW_IE_FW_IMAGE = 3, 169 ATH10K_FW_IE_OTP_IMAGE = 4, 170 171 /* WMI "operations" interface version, 32 bit value. Supported from 172 * FW API 4 and above. 173 */ 174 ATH10K_FW_IE_WMI_OP_VERSION = 5, 175 176 /* HTT "operations" interface version, 32 bit value. Supported from 177 * FW API 5 and above. 178 */ 179 ATH10K_FW_IE_HTT_OP_VERSION = 6, 180 181 /* Code swap image for firmware binary */ 182 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 183 }; 184 185 enum ath10k_fw_wmi_op_version { 186 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 187 188 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 189 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 190 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 191 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 192 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 193 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 194 195 /* keep last */ 196 ATH10K_FW_WMI_OP_VERSION_MAX, 197 }; 198 199 enum ath10k_fw_htt_op_version { 200 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 201 202 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 203 204 /* also used in 10.2 and 10.2.4 branches */ 205 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 206 207 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 208 209 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 210 211 /* keep last */ 212 ATH10K_FW_HTT_OP_VERSION_MAX, 213 }; 214 215 enum ath10k_bd_ie_type { 216 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 217 ATH10K_BD_IE_BOARD = 0, 218 }; 219 220 enum ath10k_bd_ie_board_type { 221 ATH10K_BD_IE_BOARD_NAME = 0, 222 ATH10K_BD_IE_BOARD_DATA = 1, 223 }; 224 225 enum ath10k_hw_rev { 226 ATH10K_HW_QCA988X, 227 ATH10K_HW_QCA6174, 228 ATH10K_HW_QCA99X0, 229 ATH10K_HW_QCA9888, 230 ATH10K_HW_QCA9984, 231 ATH10K_HW_QCA9377, 232 ATH10K_HW_QCA4019, 233 ATH10K_HW_QCA9887, 234 }; 235 236 struct ath10k_hw_regs { 237 u32 rtc_soc_base_address; 238 u32 rtc_wmac_base_address; 239 u32 soc_core_base_address; 240 u32 wlan_mac_base_address; 241 u32 ce_wrapper_base_address; 242 u32 ce0_base_address; 243 u32 ce1_base_address; 244 u32 ce2_base_address; 245 u32 ce3_base_address; 246 u32 ce4_base_address; 247 u32 ce5_base_address; 248 u32 ce6_base_address; 249 u32 ce7_base_address; 250 u32 soc_reset_control_si0_rst_mask; 251 u32 soc_reset_control_ce_rst_mask; 252 u32 soc_chip_id_address; 253 u32 scratch_3_address; 254 u32 fw_indicator_address; 255 u32 pcie_local_base_address; 256 u32 ce_wrap_intr_sum_host_msi_lsb; 257 u32 ce_wrap_intr_sum_host_msi_mask; 258 u32 pcie_intr_fw_mask; 259 u32 pcie_intr_ce_mask_all; 260 u32 pcie_intr_clr_address; 261 u32 cpu_pll_init_address; 262 u32 cpu_speed_address; 263 u32 core_clk_div_address; 264 }; 265 266 extern const struct ath10k_hw_regs qca988x_regs; 267 extern const struct ath10k_hw_regs qca6174_regs; 268 extern const struct ath10k_hw_regs qca99x0_regs; 269 extern const struct ath10k_hw_regs qca4019_regs; 270 271 struct ath10k_hw_ce_regs_addr_map { 272 u32 msb; 273 u32 lsb; 274 u32 mask; 275 }; 276 277 struct ath10k_hw_ce_ctrl1 { 278 u32 addr; 279 u32 hw_mask; 280 u32 sw_mask; 281 u32 hw_wr_mask; 282 u32 sw_wr_mask; 283 u32 reset_mask; 284 u32 reset; 285 struct ath10k_hw_ce_regs_addr_map *src_ring; 286 struct ath10k_hw_ce_regs_addr_map *dst_ring; 287 struct ath10k_hw_ce_regs_addr_map *dmax; }; 288 289 struct ath10k_hw_ce_cmd_halt { 290 u32 status_reset; 291 u32 msb; 292 u32 mask; 293 struct ath10k_hw_ce_regs_addr_map *status; }; 294 295 struct ath10k_hw_ce_host_ie { 296 u32 copy_complete_reset; 297 struct ath10k_hw_ce_regs_addr_map *copy_complete; }; 298 299 struct ath10k_hw_ce_host_wm_regs { 300 u32 dstr_lmask; 301 u32 dstr_hmask; 302 u32 srcr_lmask; 303 u32 srcr_hmask; 304 u32 cc_mask; 305 u32 wm_mask; 306 u32 addr; 307 }; 308 309 struct ath10k_hw_ce_misc_regs { 310 u32 axi_err; 311 u32 dstr_add_err; 312 u32 srcr_len_err; 313 u32 dstr_mlen_vio; 314 u32 dstr_overflow; 315 u32 srcr_overflow; 316 u32 err_mask; 317 u32 addr; 318 }; 319 320 struct ath10k_hw_ce_dst_src_wm_regs { 321 u32 addr; 322 u32 low_rst; 323 u32 high_rst; 324 struct ath10k_hw_ce_regs_addr_map *wm_low; 325 struct ath10k_hw_ce_regs_addr_map *wm_high; }; 326 327 struct ath10k_hw_ce_regs { 328 u32 sr_base_addr; 329 u32 sr_size_addr; 330 u32 dr_base_addr; 331 u32 dr_size_addr; 332 u32 ce_cmd_addr; 333 u32 misc_ie_addr; 334 u32 sr_wr_index_addr; 335 u32 dst_wr_index_addr; 336 u32 current_srri_addr; 337 u32 current_drri_addr; 338 u32 ddr_addr_for_rri_low; 339 u32 ddr_addr_for_rri_high; 340 u32 ce_rri_low; 341 u32 ce_rri_high; 342 u32 host_ie_addr; 343 struct ath10k_hw_ce_host_wm_regs *wm_regs; 344 struct ath10k_hw_ce_misc_regs *misc_regs; 345 struct ath10k_hw_ce_ctrl1 *ctrl1_regs; 346 struct ath10k_hw_ce_cmd_halt *cmd_halt; 347 struct ath10k_hw_ce_host_ie *host_ie; 348 struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr; 349 struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; }; 350 351 struct ath10k_hw_values { 352 u32 rtc_state_val_on; 353 u8 ce_count; 354 u8 msi_assign_ce_max; 355 u8 num_target_ce_config_wlan; 356 u16 ce_desc_meta_data_mask; 357 u8 ce_desc_meta_data_lsb; 358 }; 359 360 extern const struct ath10k_hw_values qca988x_values; 361 extern const struct ath10k_hw_values qca6174_values; 362 extern const struct ath10k_hw_values qca99x0_values; 363 extern const struct ath10k_hw_values qca9888_values; 364 extern const struct ath10k_hw_values qca4019_values; 365 extern struct ath10k_hw_ce_regs qcax_ce_regs; 366 367 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 368 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 369 370 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 371 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 372 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 373 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 374 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 375 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 376 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 377 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 378 379 /* Known peculiarities: 380 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 381 * - raw have FCS, nwifi doesn't 382 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 383 * param, llc/snap) are aligned to 4byte boundaries each 384 */ 385 enum ath10k_hw_txrx_mode { 386 ATH10K_HW_TXRX_RAW = 0, 387 388 /* Native Wifi decap mode is used to align IP frames to 4-byte 389 * boundaries and avoid a very expensive re-alignment in mac80211. 390 */ 391 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 392 ATH10K_HW_TXRX_ETHERNET = 2, 393 394 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 395 ATH10K_HW_TXRX_MGMT = 3, 396 }; 397 398 enum ath10k_mcast2ucast_mode { 399 ATH10K_MCAST2UCAST_DISABLED = 0, 400 ATH10K_MCAST2UCAST_ENABLED = 1, 401 }; 402 403 enum ath10k_hw_rate_ofdm { 404 ATH10K_HW_RATE_OFDM_48M = 0, 405 ATH10K_HW_RATE_OFDM_24M, 406 ATH10K_HW_RATE_OFDM_12M, 407 ATH10K_HW_RATE_OFDM_6M, 408 ATH10K_HW_RATE_OFDM_54M, 409 ATH10K_HW_RATE_OFDM_36M, 410 ATH10K_HW_RATE_OFDM_18M, 411 ATH10K_HW_RATE_OFDM_9M, 412 }; 413 414 enum ath10k_hw_rate_cck { 415 ATH10K_HW_RATE_CCK_LP_11M = 0, 416 ATH10K_HW_RATE_CCK_LP_5_5M, 417 ATH10K_HW_RATE_CCK_LP_2M, 418 ATH10K_HW_RATE_CCK_LP_1M, 419 ATH10K_HW_RATE_CCK_SP_11M, 420 ATH10K_HW_RATE_CCK_SP_5_5M, 421 ATH10K_HW_RATE_CCK_SP_2M, 422 }; 423 424 enum ath10k_hw_rate_rev2_cck { 425 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 426 ATH10K_HW_RATE_REV2_CCK_LP_2M, 427 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 428 ATH10K_HW_RATE_REV2_CCK_LP_11M, 429 ATH10K_HW_RATE_REV2_CCK_SP_2M, 430 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 431 ATH10K_HW_RATE_REV2_CCK_SP_11M, 432 }; 433 434 enum ath10k_hw_cc_wraparound_type { 435 ATH10K_HW_CC_WRAP_DISABLED = 0, 436 437 /* This type is when the HW chip has a quirky Cycle Counter 438 * wraparound which resets to 0x7fffffff instead of 0. All 439 * other CC related counters (e.g. Rx Clear Count) are divided 440 * by 2 so they never wraparound themselves. 441 */ 442 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 443 444 /* Each hw counter wrapsaround independently. When the 445 * counter overflows the repestive counter is right shifted 446 * by 1, i.e reset to 0x7fffffff, and other counters will be 447 * running unaffected. In this type of wraparound, it should 448 * be possible to report accurate Rx busy time unlike the 449 * first type. 450 */ 451 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 452 }; 453 454 enum ath10k_hw_refclk_speed { 455 ATH10K_HW_REFCLK_UNKNOWN = -1, 456 ATH10K_HW_REFCLK_48_MHZ = 0, 457 ATH10K_HW_REFCLK_19_2_MHZ = 1, 458 ATH10K_HW_REFCLK_24_MHZ = 2, 459 ATH10K_HW_REFCLK_26_MHZ = 3, 460 ATH10K_HW_REFCLK_37_4_MHZ = 4, 461 ATH10K_HW_REFCLK_38_4_MHZ = 5, 462 ATH10K_HW_REFCLK_40_MHZ = 6, 463 ATH10K_HW_REFCLK_52_MHZ = 7, 464 465 /* must be the last one */ 466 ATH10K_HW_REFCLK_COUNT, 467 }; 468 469 struct ath10k_hw_clk_params { 470 u32 refclk; 471 u32 div; 472 u32 rnfrac; 473 u32 settle_time; 474 u32 refdiv; 475 u32 outdiv; 476 }; 477 478 struct ath10k_hw_params { 479 u32 id; 480 u16 dev_id; 481 const char *name; 482 u32 patch_load_addr; 483 int uart_pin; 484 u32 otp_exe_param; 485 486 /* Type of hw cycle counter wraparound logic, for more info 487 * refer enum ath10k_hw_cc_wraparound_type. 488 */ 489 enum ath10k_hw_cc_wraparound_type cc_wraparound_type; 490 491 /* Some of chip expects fragment descriptor to be continuous 492 * memory for any TX operation. Set continuous_frag_desc flag 493 * for the hardware which have such requirement. 494 */ 495 bool continuous_frag_desc; 496 497 /* CCK hardware rate table mapping for the newer chipsets 498 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values 499 * are in a proper order with respect to the rate/preamble 500 */ 501 bool cck_rate_map_rev2; 502 503 u32 channel_counters_freq_hz; 504 505 /* Mgmt tx descriptors threshold for limiting probe response 506 * frames. 507 */ 508 u32 max_probe_resp_desc_thres; 509 510 u32 tx_chain_mask; 511 u32 rx_chain_mask; 512 u32 max_spatial_stream; 513 u32 cal_data_len; 514 515 struct ath10k_hw_params_fw { 516 const char *dir; 517 const char *board; 518 size_t board_size; 519 size_t board_ext_size; 520 } fw; 521 522 /* qca99x0 family chips deliver broadcast/multicast management 523 * frames encrypted and expect software do decryption. 524 */ 525 bool sw_decrypt_mcast_mgmt; 526 527 const struct ath10k_hw_ops *hw_ops; 528 529 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ 530 int decap_align_bytes; 531 532 /* hw specific clock control parameters */ 533 const struct ath10k_hw_clk_params *hw_clk; 534 int target_cpu_freq; 535 536 /* Number of bytes to be discarded for each FFT sample */ 537 int spectral_bin_discard; 538 539 /* The board may have a restricted NSS for 160 or 80+80 vs what it 540 * can do for 80Mhz. 541 */ 542 int vht160_mcs_rx_highest; 543 int vht160_mcs_tx_highest; 544 }; 545 546 struct htt_rx_desc; 547 548 /* Defines needed for Rx descriptor abstraction */ 549 struct ath10k_hw_ops { 550 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 551 void (*set_coverage_class)(struct ath10k *ar, s16 value); 552 int (*enable_pll_clk)(struct ath10k *ar); 553 }; 554 555 extern const struct ath10k_hw_ops qca988x_ops; 556 extern const struct ath10k_hw_ops qca99x0_ops; 557 extern const struct ath10k_hw_ops qca6174_ops; 558 559 extern const struct ath10k_hw_clk_params qca6174_clk[]; 560 561 static inline int 562 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, 563 struct htt_rx_desc *rxd) 564 { 565 if (hw->hw_ops->rx_desc_get_l3_pad_bytes) 566 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd); 567 return 0; 568 } 569 570 /* Target specific defines for MAIN firmware */ 571 #define TARGET_NUM_VDEVS 8 572 #define TARGET_NUM_PEER_AST 2 573 #define TARGET_NUM_WDS_ENTRIES 32 574 #define TARGET_DMA_BURST_SIZE 0 575 #define TARGET_MAC_AGGR_DELIM 0 576 #define TARGET_AST_SKID_LIMIT 16 577 #define TARGET_NUM_STATIONS 16 578 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 579 (TARGET_NUM_VDEVS)) 580 #define TARGET_NUM_OFFLOAD_PEERS 0 581 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 582 #define TARGET_NUM_PEER_KEYS 2 583 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 584 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 585 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 586 #define TARGET_RX_TIMEOUT_LO_PRI 100 587 #define TARGET_RX_TIMEOUT_HI_PRI 40 588 589 #define TARGET_SCAN_MAX_PENDING_REQS 4 590 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 591 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 592 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 593 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 594 #define TARGET_NUM_MCAST_GROUPS 0 595 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 596 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 597 #define TARGET_TX_DBG_LOG_SIZE 1024 598 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 599 #define TARGET_VOW_CONFIG 0 600 #define TARGET_NUM_MSDU_DESC (1024 + 400) 601 #define TARGET_MAX_FRAG_ENTRIES 0 602 603 /* Target specific defines for 10.X firmware */ 604 #define TARGET_10X_NUM_VDEVS 16 605 #define TARGET_10X_NUM_PEER_AST 2 606 #define TARGET_10X_NUM_WDS_ENTRIES 32 607 #define TARGET_10X_DMA_BURST_SIZE 0 608 #define TARGET_10X_MAC_AGGR_DELIM 0 609 #define TARGET_10X_AST_SKID_LIMIT 128 610 #define TARGET_10X_NUM_STATIONS 128 611 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 612 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 613 (TARGET_10X_NUM_VDEVS)) 614 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 615 (TARGET_10X_NUM_VDEVS)) 616 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 617 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 618 #define TARGET_10X_NUM_PEER_KEYS 2 619 #define TARGET_10X_NUM_TIDS_MAX 256 620 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 621 (TARGET_10X_NUM_PEERS) * 2) 622 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 623 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 624 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 625 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 626 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 627 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 628 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 629 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 630 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 631 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 632 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 633 #define TARGET_10X_NUM_MCAST_GROUPS 0 634 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 635 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 636 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 637 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 638 #define TARGET_10X_VOW_CONFIG 0 639 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 640 #define TARGET_10X_MAX_FRAG_ENTRIES 0 641 642 /* 10.2 parameters */ 643 #define TARGET_10_2_DMA_BURST_SIZE 0 644 645 /* Target specific defines for WMI-TLV firmware */ 646 #define TARGET_TLV_NUM_VDEVS 4 647 #define TARGET_TLV_NUM_STATIONS 32 648 #define TARGET_TLV_NUM_PEERS 33 649 #define TARGET_TLV_NUM_TDLS_VDEVS 1 650 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 651 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 652 #define TARGET_TLV_NUM_WOW_PATTERNS 22 653 654 /* Diagnostic Window */ 655 #define CE_DIAG_PIPE 7 656 657 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 658 659 /* Target specific defines for 10.4 firmware */ 660 #define TARGET_10_4_NUM_VDEVS 16 661 #define TARGET_10_4_NUM_STATIONS 32 662 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 663 (TARGET_10_4_NUM_VDEVS)) 664 #define TARGET_10_4_ACTIVE_PEERS 0 665 666 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 667 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 668 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 669 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 670 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 671 #define TARGET_10_4_NUM_PEER_KEYS 2 672 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 673 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 674 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 675 #define TARGET_10_4_AST_SKID_LIMIT 32 676 677 /* 100 ms for video, best-effort, and background */ 678 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 679 680 /* 40 ms for voice */ 681 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 682 683 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 684 #define TARGET_10_4_SCAN_MAX_REQS 4 685 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 686 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 687 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 688 689 /* Note: mcast to ucast is disabled by default */ 690 #define TARGET_10_4_NUM_MCAST_GROUPS 0 691 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 692 #define TARGET_10_4_MCAST2UCAST_MODE 0 693 694 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 695 #define TARGET_10_4_NUM_WDS_ENTRIES 32 696 #define TARGET_10_4_DMA_BURST_SIZE 0 697 #define TARGET_10_4_MAC_AGGR_DELIM 0 698 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 699 #define TARGET_10_4_VOW_CONFIG 0 700 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 701 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 702 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 703 #define TARGET_10_4_SMART_ANT_CAP 0 704 #define TARGET_10_4_BK_MIN_FREE 0 705 #define TARGET_10_4_BE_MIN_FREE 0 706 #define TARGET_10_4_VI_MIN_FREE 0 707 #define TARGET_10_4_VO_MIN_FREE 0 708 #define TARGET_10_4_RX_BATCH_MODE 1 709 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 710 #define TARGET_10_4_ATF_CONFIG 0 711 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 712 #define TARGET_10_4_QWRAP_CONFIG 0 713 714 /* Maximum number of Copy Engine's supported */ 715 #define CE_COUNT_MAX 12 716 717 /* Number of Copy Engines supported */ 718 #define CE_COUNT ar->hw_values->ce_count 719 720 /* 721 * Granted MSIs are assigned as follows: 722 * Firmware uses the first 723 * Remaining MSIs, if any, are used by Copy Engines 724 * This mapping is known to both Target firmware and Host software. 725 * It may be changed as long as Host and Target are kept in sync. 726 */ 727 /* MSI for firmware (errors, etc.) */ 728 #define MSI_ASSIGN_FW 0 729 730 /* MSIs for Copy Engines */ 731 #define MSI_ASSIGN_CE_INITIAL 1 732 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 733 734 /* as of IP3.7.1 */ 735 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 736 737 #define RTC_STATE_V_LSB 0 738 #define RTC_STATE_V_MASK 0x00000007 739 #define RTC_STATE_ADDRESS 0x0000 740 #define PCIE_SOC_WAKE_V_MASK 0x00000001 741 #define PCIE_SOC_WAKE_ADDRESS 0x0004 742 #define PCIE_SOC_WAKE_RESET 0x00000000 743 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 744 745 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 746 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 747 #define MAC_COEX_BASE_ADDRESS 0x00006000 748 #define BT_COEX_BASE_ADDRESS 0x00007000 749 #define SOC_PCIE_BASE_ADDRESS 0x00008000 750 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 751 #define WLAN_UART_BASE_ADDRESS 0x0000c000 752 #define WLAN_SI_BASE_ADDRESS 0x00010000 753 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 754 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 755 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address 756 #define EFUSE_BASE_ADDRESS 0x00030000 757 #define FPGA_REG_BASE_ADDRESS 0x00039000 758 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 759 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 760 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 761 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 762 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 763 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 764 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 765 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 766 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 767 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 768 #define DBI_BASE_ADDRESS 0x00060000 769 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 770 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 771 772 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 773 #define SOC_RESET_CONTROL_OFFSET 0x00000000 774 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 775 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 776 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 777 #define SOC_CPU_CLOCK_OFFSET 0x00000020 778 #define SOC_CPU_CLOCK_STANDARD_LSB 0 779 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 780 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 781 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 782 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 783 #define SOC_LPO_CAL_OFFSET 0x000000e0 784 #define SOC_LPO_CAL_ENABLE_LSB 20 785 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 786 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 787 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 788 789 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 790 #define SOC_CHIP_ID_REV_LSB 8 791 #define SOC_CHIP_ID_REV_MASK 0x00000f00 792 793 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 794 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 795 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 796 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 797 798 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 799 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 800 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 801 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 802 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 803 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 804 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 805 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 806 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 807 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 808 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 809 810 #define CLOCK_GPIO_OFFSET 0xffffffff 811 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 812 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 813 814 #define SI_CONFIG_OFFSET 0x00000000 815 #define SI_CONFIG_ERR_INT_LSB 19 816 #define SI_CONFIG_ERR_INT_MASK 0x00080000 817 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 818 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 819 #define SI_CONFIG_I2C_LSB 16 820 #define SI_CONFIG_I2C_MASK 0x00010000 821 #define SI_CONFIG_POS_SAMPLE_LSB 7 822 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 823 #define SI_CONFIG_INACTIVE_DATA_LSB 5 824 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 825 #define SI_CONFIG_INACTIVE_CLK_LSB 4 826 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 827 #define SI_CONFIG_DIVIDER_LSB 0 828 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 829 #define SI_CS_OFFSET 0x00000004 830 #define SI_CS_DONE_ERR_LSB 10 831 #define SI_CS_DONE_ERR_MASK 0x00000400 832 #define SI_CS_DONE_INT_LSB 9 833 #define SI_CS_DONE_INT_MASK 0x00000200 834 #define SI_CS_START_LSB 8 835 #define SI_CS_START_MASK 0x00000100 836 #define SI_CS_RX_CNT_LSB 4 837 #define SI_CS_RX_CNT_MASK 0x000000f0 838 #define SI_CS_TX_CNT_LSB 0 839 #define SI_CS_TX_CNT_MASK 0x0000000f 840 841 #define SI_TX_DATA0_OFFSET 0x00000008 842 #define SI_TX_DATA1_OFFSET 0x0000000c 843 #define SI_RX_DATA0_OFFSET 0x00000010 844 #define SI_RX_DATA1_OFFSET 0x00000014 845 846 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 847 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 848 #define CORE_CTRL_ADDRESS 0x0000 849 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 850 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 851 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 852 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 853 #define CPU_INTR_ADDRESS 0x0010 854 855 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 856 857 /* Firmware indications to the Host via SCRATCH_3 register. */ 858 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 859 #define FW_IND_EVENT_PENDING 1 860 #define FW_IND_INITIALIZED 2 861 #define FW_IND_HOST_READY 0x80000000 862 863 /* HOST_REG interrupt from firmware */ 864 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 865 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 866 867 #define DRAM_BASE_ADDRESS 0x00400000 868 869 #define PCIE_BAR_REG_ADDRESS 0x40030 870 871 #define MISSING 0 872 873 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 874 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 875 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 876 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 877 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 878 #define RESET_CONTROL_MBOX_RST_MASK MISSING 879 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 880 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 881 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 882 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 883 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 884 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 885 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 886 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 887 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 888 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 889 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 890 #define LOCAL_SCRATCH_OFFSET 0x18 891 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 892 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 893 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 894 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 895 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 896 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 897 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 898 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 899 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 900 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 901 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 902 #define MBOX_BASE_ADDRESS MISSING 903 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 904 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 905 #define INT_STATUS_ENABLE_CPU_LSB MISSING 906 #define INT_STATUS_ENABLE_CPU_MASK MISSING 907 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 908 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 909 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 910 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 911 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 912 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 913 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 914 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 915 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 916 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 917 #define INT_STATUS_ENABLE_ADDRESS MISSING 918 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 919 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 920 #define HOST_INT_STATUS_ADDRESS MISSING 921 #define CPU_INT_STATUS_ADDRESS MISSING 922 #define ERROR_INT_STATUS_ADDRESS MISSING 923 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 924 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 925 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 926 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 927 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 928 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 929 #define COUNT_DEC_ADDRESS MISSING 930 #define HOST_INT_STATUS_CPU_MASK MISSING 931 #define HOST_INT_STATUS_CPU_LSB MISSING 932 #define HOST_INT_STATUS_ERROR_MASK MISSING 933 #define HOST_INT_STATUS_ERROR_LSB MISSING 934 #define HOST_INT_STATUS_COUNTER_MASK MISSING 935 #define HOST_INT_STATUS_COUNTER_LSB MISSING 936 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 937 #define WINDOW_DATA_ADDRESS MISSING 938 #define WINDOW_READ_ADDR_ADDRESS MISSING 939 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 940 941 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 942 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 943 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 944 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 945 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 946 947 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 948 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 949 #define QCA9887_EEPROM_ADDR_HI_LSB 8 950 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 951 #define QCA9887_EEPROM_ADDR_LO_LSB 16 952 953 #define MBOX_RESET_CONTROL_ADDRESS 0x00000000 954 #define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800 955 #define MBOX_HOST_INT_STATUS_ERROR_LSB 7 956 #define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080 957 #define MBOX_HOST_INT_STATUS_CPU_LSB 6 958 #define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040 959 #define MBOX_HOST_INT_STATUS_COUNTER_LSB 4 960 #define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010 961 #define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801 962 #define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802 963 #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB 2 964 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 965 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 966 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 967 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 968 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 969 #define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803 970 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0 971 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff 972 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805 973 #define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828 974 #define MBOX_INT_STATUS_ENABLE_ERROR_LSB 7 975 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080 976 #define MBOX_INT_STATUS_ENABLE_CPU_LSB 6 977 #define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040 978 #define MBOX_INT_STATUS_ENABLE_INT_LSB 5 979 #define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020 980 #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB 4 981 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 982 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0 983 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f 984 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819 985 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0 986 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 987 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a 988 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 989 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 990 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 991 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 992 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b 993 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 994 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 995 #define MBOX_COUNT_ADDRESS 0x00000820 996 #define MBOX_COUNT_DEC_ADDRESS 0x00000840 997 #define MBOX_WINDOW_DATA_ADDRESS 0x00000874 998 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878 999 #define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c 1000 #define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883 1001 #define MBOX_CPU_DBG_ADDRESS 0x00000884 1002 #define MBOX_RTC_BASE_ADDRESS 0x00000000 1003 #define MBOX_GPIO_BASE_ADDRESS 0x00005000 1004 #define MBOX_MBOX_BASE_ADDRESS 0x00008000 1005 1006 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 1007 1008 /* Register definitions for first generation ath10k cards. These cards include 1009 * a mac thich has a register allocation similar to ath9k and at least some 1010 * registers including the ones relevant for modifying the coverage class are 1011 * identical to the ath9k definitions. 1012 * These registers are usually managed by the ath10k firmware. However by 1013 * overriding them it is possible to support coverage class modifications. 1014 */ 1015 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014 1016 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF 1017 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF 1018 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0 1019 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000 1020 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16 1021 1022 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070 1023 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF 1024 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF 1025 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0 1026 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000 1027 1028 #define WAVE1_PHYCLK 0x801C 1029 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F 1030 #define WAVE1_PHYCLK_USEC_LSB 0 1031 1032 /* qca6174 PLL offset/mask */ 1033 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114 1034 #define SOC_CORE_CLK_CTRL_DIV_LSB 0 1035 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 1036 1037 #define EFUSE_OFFSET 0x0000032c 1038 #define EFUSE_XTAL_SEL_LSB 8 1039 #define EFUSE_XTAL_SEL_MASK 0x00000700 1040 1041 #define BB_PLL_CONFIG_OFFSET 0x000002f4 1042 #define BB_PLL_CONFIG_FRAC_LSB 0 1043 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff 1044 #define BB_PLL_CONFIG_OUTDIV_LSB 18 1045 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 1046 1047 #define WLAN_PLL_SETTLE_OFFSET 0x0018 1048 #define WLAN_PLL_SETTLE_TIME_LSB 0 1049 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff 1050 1051 #define WLAN_PLL_CONTROL_OFFSET 0x0014 1052 #define WLAN_PLL_CONTROL_DIV_LSB 0 1053 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff 1054 #define WLAN_PLL_CONTROL_REFDIV_LSB 10 1055 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 1056 #define WLAN_PLL_CONTROL_BYPASS_LSB 16 1057 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 1058 #define WLAN_PLL_CONTROL_NOPWD_LSB 18 1059 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 1060 1061 #define RTC_SYNC_STATUS_OFFSET 0x0244 1062 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 1063 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 1064 /* qca6174 PLL offset/mask end */ 1065 1066 #endif /* _HW_H_ */ 1067