xref: /openbmc/linux/drivers/net/wireless/ath/ath10k/hw.h (revision a2cce7a9)
1 /*
2  * Copyright (c) 2005-2011 Atheros Communications Inc.
3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  */
17 
18 #ifndef _HW_H_
19 #define _HW_H_
20 
21 #include "targaddrs.h"
22 
23 #define ATH10K_FW_DIR			"ath10k"
24 
25 /* QCA988X 1.0 definitions (unsupported) */
26 #define QCA988X_HW_1_0_CHIP_ID_REV	0x0
27 
28 /* QCA988X 2.0 definitions */
29 #define QCA988X_HW_2_0_VERSION		0x4100016c
30 #define QCA988X_HW_2_0_CHIP_ID_REV	0x2
31 #define QCA988X_HW_2_0_FW_DIR		ATH10K_FW_DIR "/QCA988X/hw2.0"
32 #define QCA988X_HW_2_0_FW_FILE		"firmware.bin"
33 #define QCA988X_HW_2_0_OTP_FILE		"otp.bin"
34 #define QCA988X_HW_2_0_BOARD_DATA_FILE	"board.bin"
35 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR	0x1234
36 
37 /* QCA6174 target BMI version signatures */
38 #define QCA6174_HW_1_0_VERSION		0x05000000
39 #define QCA6174_HW_1_1_VERSION		0x05000001
40 #define QCA6174_HW_1_3_VERSION		0x05000003
41 #define QCA6174_HW_2_1_VERSION		0x05010000
42 #define QCA6174_HW_3_0_VERSION		0x05020000
43 #define QCA6174_HW_3_2_VERSION		0x05030000
44 
45 enum qca6174_pci_rev {
46 	QCA6174_PCI_REV_1_1 = 0x11,
47 	QCA6174_PCI_REV_1_3 = 0x13,
48 	QCA6174_PCI_REV_2_0 = 0x20,
49 	QCA6174_PCI_REV_3_0 = 0x30,
50 };
51 
52 enum qca6174_chip_id_rev {
53 	QCA6174_HW_1_0_CHIP_ID_REV = 0,
54 	QCA6174_HW_1_1_CHIP_ID_REV = 1,
55 	QCA6174_HW_1_3_CHIP_ID_REV = 2,
56 	QCA6174_HW_2_1_CHIP_ID_REV = 4,
57 	QCA6174_HW_2_2_CHIP_ID_REV = 5,
58 	QCA6174_HW_3_0_CHIP_ID_REV = 8,
59 	QCA6174_HW_3_1_CHIP_ID_REV = 9,
60 	QCA6174_HW_3_2_CHIP_ID_REV = 10,
61 };
62 
63 #define QCA6174_HW_2_1_FW_DIR		"ath10k/QCA6174/hw2.1"
64 #define QCA6174_HW_2_1_FW_FILE		"firmware.bin"
65 #define QCA6174_HW_2_1_OTP_FILE		"otp.bin"
66 #define QCA6174_HW_2_1_BOARD_DATA_FILE	"board.bin"
67 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR	0x1234
68 
69 #define QCA6174_HW_3_0_FW_DIR		"ath10k/QCA6174/hw3.0"
70 #define QCA6174_HW_3_0_FW_FILE		"firmware.bin"
71 #define QCA6174_HW_3_0_OTP_FILE		"otp.bin"
72 #define QCA6174_HW_3_0_BOARD_DATA_FILE	"board.bin"
73 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR	0x1234
74 
75 /* QCA99X0 1.0 definitions (unsupported) */
76 #define QCA99X0_HW_1_0_CHIP_ID_REV     0x0
77 
78 /* QCA99X0 2.0 definitions */
79 #define QCA99X0_HW_2_0_DEV_VERSION     0x01000000
80 #define QCA99X0_HW_2_0_CHIP_ID_REV     0x1
81 #define QCA99X0_HW_2_0_FW_DIR          ATH10K_FW_DIR "/QCA99X0/hw2.0"
82 #define QCA99X0_HW_2_0_FW_FILE         "firmware.bin"
83 #define QCA99X0_HW_2_0_OTP_FILE        "otp.bin"
84 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
85 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR	0x1234
86 
87 #define ATH10K_FW_API2_FILE		"firmware-2.bin"
88 #define ATH10K_FW_API3_FILE		"firmware-3.bin"
89 
90 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */
91 #define ATH10K_FW_API4_FILE		"firmware-4.bin"
92 
93 /* HTT id conflict fix for management frames over HTT */
94 #define ATH10K_FW_API5_FILE		"firmware-5.bin"
95 
96 #define ATH10K_FW_UTF_FILE		"utf.bin"
97 
98 /* includes also the null byte */
99 #define ATH10K_FIRMWARE_MAGIC               "QCA-ATH10K"
100 
101 #define REG_DUMP_COUNT_QCA988X 60
102 
103 #define QCA988X_CAL_DATA_LEN		2116
104 
105 struct ath10k_fw_ie {
106 	__le32 id;
107 	__le32 len;
108 	u8 data[0];
109 };
110 
111 enum ath10k_fw_ie_type {
112 	ATH10K_FW_IE_FW_VERSION = 0,
113 	ATH10K_FW_IE_TIMESTAMP = 1,
114 	ATH10K_FW_IE_FEATURES = 2,
115 	ATH10K_FW_IE_FW_IMAGE = 3,
116 	ATH10K_FW_IE_OTP_IMAGE = 4,
117 
118 	/* WMI "operations" interface version, 32 bit value. Supported from
119 	 * FW API 4 and above.
120 	 */
121 	ATH10K_FW_IE_WMI_OP_VERSION = 5,
122 
123 	/* HTT "operations" interface version, 32 bit value. Supported from
124 	 * FW API 5 and above.
125 	 */
126 	ATH10K_FW_IE_HTT_OP_VERSION = 6,
127 
128 	/* Code swap image for firmware binary */
129 	ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7,
130 };
131 
132 enum ath10k_fw_wmi_op_version {
133 	ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
134 
135 	ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
136 	ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
137 	ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
138 	ATH10K_FW_WMI_OP_VERSION_TLV = 4,
139 	ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
140 	ATH10K_FW_WMI_OP_VERSION_10_4 = 6,
141 
142 	/* keep last */
143 	ATH10K_FW_WMI_OP_VERSION_MAX,
144 };
145 
146 enum ath10k_fw_htt_op_version {
147 	ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
148 
149 	ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
150 
151 	/* also used in 10.2 and 10.2.4 branches */
152 	ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
153 
154 	ATH10K_FW_HTT_OP_VERSION_TLV = 3,
155 
156 	ATH10K_FW_HTT_OP_VERSION_10_4 = 4,
157 
158 	/* keep last */
159 	ATH10K_FW_HTT_OP_VERSION_MAX,
160 };
161 
162 enum ath10k_hw_rev {
163 	ATH10K_HW_QCA988X,
164 	ATH10K_HW_QCA6174,
165 	ATH10K_HW_QCA99X0,
166 };
167 
168 struct ath10k_hw_regs {
169 	u32 rtc_state_cold_reset_mask;
170 	u32 rtc_soc_base_address;
171 	u32 rtc_wmac_base_address;
172 	u32 soc_core_base_address;
173 	u32 ce_wrapper_base_address;
174 	u32 ce0_base_address;
175 	u32 ce1_base_address;
176 	u32 ce2_base_address;
177 	u32 ce3_base_address;
178 	u32 ce4_base_address;
179 	u32 ce5_base_address;
180 	u32 ce6_base_address;
181 	u32 ce7_base_address;
182 	u32 soc_reset_control_si0_rst_mask;
183 	u32 soc_reset_control_ce_rst_mask;
184 	u32 soc_chip_id_address;
185 	u32 scratch_3_address;
186 	u32 fw_indicator_address;
187 	u32 pcie_local_base_address;
188 	u32 ce_wrap_intr_sum_host_msi_lsb;
189 	u32 ce_wrap_intr_sum_host_msi_mask;
190 	u32 pcie_intr_fw_mask;
191 	u32 pcie_intr_ce_mask_all;
192 	u32 pcie_intr_clr_address;
193 };
194 
195 extern const struct ath10k_hw_regs qca988x_regs;
196 extern const struct ath10k_hw_regs qca6174_regs;
197 extern const struct ath10k_hw_regs qca99x0_regs;
198 
199 struct ath10k_hw_values {
200 	u32 rtc_state_val_on;
201 	u8 ce_count;
202 	u8 msi_assign_ce_max;
203 	u8 num_target_ce_config_wlan;
204 	u16 ce_desc_meta_data_mask;
205 	u8 ce_desc_meta_data_lsb;
206 };
207 
208 extern const struct ath10k_hw_values qca988x_values;
209 extern const struct ath10k_hw_values qca6174_values;
210 extern const struct ath10k_hw_values qca99x0_values;
211 
212 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
213 				u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
214 
215 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
216 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
217 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
218 
219 /* Known pecularities:
220  *  - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
221  *  - raw have FCS, nwifi doesn't
222  *  - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
223  *    param, llc/snap) are aligned to 4byte boundaries each */
224 enum ath10k_hw_txrx_mode {
225 	ATH10K_HW_TXRX_RAW = 0,
226 
227 	/* Native Wifi decap mode is used to align IP frames to 4-byte
228 	 * boundaries and avoid a very expensive re-alignment in mac80211.
229 	 */
230 	ATH10K_HW_TXRX_NATIVE_WIFI = 1,
231 	ATH10K_HW_TXRX_ETHERNET = 2,
232 
233 	/* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
234 	ATH10K_HW_TXRX_MGMT = 3,
235 };
236 
237 enum ath10k_mcast2ucast_mode {
238 	ATH10K_MCAST2UCAST_DISABLED = 0,
239 	ATH10K_MCAST2UCAST_ENABLED = 1,
240 };
241 
242 struct ath10k_pktlog_hdr {
243 	__le16 flags;
244 	__le16 missed_cnt;
245 	__le16 log_type;
246 	__le16 size;
247 	__le32 timestamp;
248 	u8 payload[0];
249 } __packed;
250 
251 enum ath10k_hw_rate_ofdm {
252 	ATH10K_HW_RATE_OFDM_48M = 0,
253 	ATH10K_HW_RATE_OFDM_24M,
254 	ATH10K_HW_RATE_OFDM_12M,
255 	ATH10K_HW_RATE_OFDM_6M,
256 	ATH10K_HW_RATE_OFDM_54M,
257 	ATH10K_HW_RATE_OFDM_36M,
258 	ATH10K_HW_RATE_OFDM_18M,
259 	ATH10K_HW_RATE_OFDM_9M,
260 };
261 
262 enum ath10k_hw_rate_cck {
263 	ATH10K_HW_RATE_CCK_LP_11M = 0,
264 	ATH10K_HW_RATE_CCK_LP_5_5M,
265 	ATH10K_HW_RATE_CCK_LP_2M,
266 	ATH10K_HW_RATE_CCK_LP_1M,
267 	ATH10K_HW_RATE_CCK_SP_11M,
268 	ATH10K_HW_RATE_CCK_SP_5_5M,
269 	ATH10K_HW_RATE_CCK_SP_2M,
270 };
271 
272 /* Target specific defines for MAIN firmware */
273 #define TARGET_NUM_VDEVS			8
274 #define TARGET_NUM_PEER_AST			2
275 #define TARGET_NUM_WDS_ENTRIES			32
276 #define TARGET_DMA_BURST_SIZE			0
277 #define TARGET_MAC_AGGR_DELIM			0
278 #define TARGET_AST_SKID_LIMIT			16
279 #define TARGET_NUM_STATIONS			16
280 #define TARGET_NUM_PEERS			((TARGET_NUM_STATIONS) + \
281 						 (TARGET_NUM_VDEVS))
282 #define TARGET_NUM_OFFLOAD_PEERS		0
283 #define TARGET_NUM_OFFLOAD_REORDER_BUFS         0
284 #define TARGET_NUM_PEER_KEYS			2
285 #define TARGET_NUM_TIDS				((TARGET_NUM_PEERS) * 2)
286 #define TARGET_TX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
287 #define TARGET_RX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
288 #define TARGET_RX_TIMEOUT_LO_PRI		100
289 #define TARGET_RX_TIMEOUT_HI_PRI		40
290 
291 #define TARGET_SCAN_MAX_PENDING_REQS		4
292 #define TARGET_BMISS_OFFLOAD_MAX_VDEV		3
293 #define TARGET_ROAM_OFFLOAD_MAX_VDEV		3
294 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES	8
295 #define TARGET_GTK_OFFLOAD_MAX_VDEV		3
296 #define TARGET_NUM_MCAST_GROUPS			0
297 #define TARGET_NUM_MCAST_TABLE_ELEMS		0
298 #define TARGET_MCAST2UCAST_MODE			ATH10K_MCAST2UCAST_DISABLED
299 #define TARGET_TX_DBG_LOG_SIZE			1024
300 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
301 #define TARGET_VOW_CONFIG			0
302 #define TARGET_NUM_MSDU_DESC			(1024 + 400)
303 #define TARGET_MAX_FRAG_ENTRIES			0
304 
305 /* Target specific defines for 10.X firmware */
306 #define TARGET_10X_NUM_VDEVS			16
307 #define TARGET_10X_NUM_PEER_AST			2
308 #define TARGET_10X_NUM_WDS_ENTRIES		32
309 #define TARGET_10X_DMA_BURST_SIZE		0
310 #define TARGET_10X_MAC_AGGR_DELIM		0
311 #define TARGET_10X_AST_SKID_LIMIT		128
312 #define TARGET_10X_NUM_STATIONS			128
313 #define TARGET_10X_NUM_PEERS			((TARGET_10X_NUM_STATIONS) + \
314 						 (TARGET_10X_NUM_VDEVS))
315 #define TARGET_10X_NUM_OFFLOAD_PEERS		0
316 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS	0
317 #define TARGET_10X_NUM_PEER_KEYS		2
318 #define TARGET_10X_NUM_TIDS_MAX			256
319 #define TARGET_10X_NUM_TIDS			min((TARGET_10X_NUM_TIDS_MAX), \
320 						    (TARGET_10X_NUM_PEERS) * 2)
321 #define TARGET_10X_TX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
322 #define TARGET_10X_RX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
323 #define TARGET_10X_RX_TIMEOUT_LO_PRI		100
324 #define TARGET_10X_RX_TIMEOUT_HI_PRI		40
325 #define TARGET_10X_SCAN_MAX_PENDING_REQS	4
326 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV	2
327 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV	2
328 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES	8
329 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV		3
330 #define TARGET_10X_NUM_MCAST_GROUPS		0
331 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS	0
332 #define TARGET_10X_MCAST2UCAST_MODE		ATH10K_MCAST2UCAST_DISABLED
333 #define TARGET_10X_TX_DBG_LOG_SIZE		1024
334 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
335 #define TARGET_10X_VOW_CONFIG			0
336 #define TARGET_10X_NUM_MSDU_DESC		(1024 + 400)
337 #define TARGET_10X_MAX_FRAG_ENTRIES		0
338 
339 /* 10.2 parameters */
340 #define TARGET_10_2_DMA_BURST_SIZE		1
341 
342 /* Target specific defines for WMI-TLV firmware */
343 #define TARGET_TLV_NUM_VDEVS			4
344 #define TARGET_TLV_NUM_STATIONS			32
345 #define TARGET_TLV_NUM_PEERS			35
346 #define TARGET_TLV_NUM_TDLS_VDEVS		1
347 #define TARGET_TLV_NUM_TIDS			((TARGET_TLV_NUM_PEERS) * 2)
348 #define TARGET_TLV_NUM_MSDU_DESC		(1024 + 32)
349 #define TARGET_TLV_NUM_WOW_PATTERNS		22
350 
351 /* Diagnostic Window */
352 #define CE_DIAG_PIPE	7
353 
354 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
355 
356 /* Target specific defines for 10.4 firmware */
357 #define TARGET_10_4_NUM_VDEVS			16
358 #define TARGET_10_4_NUM_STATIONS		32
359 #define TARGET_10_4_NUM_PEERS			((TARGET_10_4_NUM_STATIONS) + \
360 						 (TARGET_10_4_NUM_VDEVS))
361 #define TARGET_10_4_ACTIVE_PEERS		0
362 
363 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX	512
364 #define TARGET_10_4_QCACHE_ACTIVE_PEERS		50
365 #define TARGET_10_4_NUM_OFFLOAD_PEERS		0
366 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS	0
367 #define TARGET_10_4_NUM_PEER_KEYS		2
368 #define TARGET_10_4_TGT_NUM_TIDS		((TARGET_10_4_NUM_PEERS) * 2)
369 #define TARGET_10_4_AST_SKID_LIMIT		32
370 #define TARGET_10_4_TX_CHAIN_MASK		(BIT(0) | BIT(1) | \
371 						 BIT(2) | BIT(3))
372 #define TARGET_10_4_RX_CHAIN_MASK		(BIT(0) | BIT(1) | \
373 						 BIT(2) | BIT(3))
374 
375 /* 100 ms for video, best-effort, and background */
376 #define TARGET_10_4_RX_TIMEOUT_LO_PRI		100
377 
378 /* 40 ms for voice */
379 #define TARGET_10_4_RX_TIMEOUT_HI_PRI		40
380 
381 #define TARGET_10_4_RX_DECAP_MODE		ATH10K_HW_TXRX_NATIVE_WIFI
382 #define TARGET_10_4_SCAN_MAX_REQS		4
383 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV	3
384 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV	3
385 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES   8
386 
387 /* Note: mcast to ucast is disabled by default */
388 #define TARGET_10_4_NUM_MCAST_GROUPS		0
389 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS	0
390 #define TARGET_10_4_MCAST2UCAST_MODE		0
391 
392 #define TARGET_10_4_TX_DBG_LOG_SIZE		1024
393 #define TARGET_10_4_NUM_WDS_ENTRIES		32
394 #define TARGET_10_4_DMA_BURST_SIZE		1
395 #define TARGET_10_4_MAC_AGGR_DELIM		0
396 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
397 #define TARGET_10_4_VOW_CONFIG			0
398 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV	3
399 #define TARGET_10_4_NUM_MSDU_DESC		(1024 + 400)
400 #define TARGET_10_4_11AC_TX_MAX_FRAGS		2
401 #define TARGET_10_4_MAX_PEER_EXT_STATS		16
402 #define TARGET_10_4_SMART_ANT_CAP		0
403 #define TARGET_10_4_BK_MIN_FREE			0
404 #define TARGET_10_4_BE_MIN_FREE			0
405 #define TARGET_10_4_VI_MIN_FREE			0
406 #define TARGET_10_4_VO_MIN_FREE			0
407 #define TARGET_10_4_RX_BATCH_MODE		1
408 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG	0
409 #define TARGET_10_4_ATF_CONFIG			0
410 #define TARGET_10_4_IPHDR_PAD_CONFIG		1
411 #define TARGET_10_4_QWRAP_CONFIG		0
412 
413 /* Number of Copy Engines supported */
414 #define CE_COUNT ar->hw_values->ce_count
415 
416 /*
417  * Total number of PCIe MSI interrupts requested for all interrupt sources.
418  * PCIe standard forces this to be a power of 2.
419  * Some Host OS's limit MSI requests that can be granted to 8
420  * so for now we abide by this limit and avoid requesting more
421  * than that.
422  */
423 #define MSI_NUM_REQUEST_LOG2	3
424 #define MSI_NUM_REQUEST		(1<<MSI_NUM_REQUEST_LOG2)
425 
426 /*
427  * Granted MSIs are assigned as follows:
428  * Firmware uses the first
429  * Remaining MSIs, if any, are used by Copy Engines
430  * This mapping is known to both Target firmware and Host software.
431  * It may be changed as long as Host and Target are kept in sync.
432  */
433 /* MSI for firmware (errors, etc.) */
434 #define MSI_ASSIGN_FW		0
435 
436 /* MSIs for Copy Engines */
437 #define MSI_ASSIGN_CE_INITIAL	1
438 #define MSI_ASSIGN_CE_MAX	ar->hw_values->msi_assign_ce_max
439 
440 /* as of IP3.7.1 */
441 #define RTC_STATE_V_ON				ar->hw_values->rtc_state_val_on
442 
443 #define RTC_STATE_COLD_RESET_MASK		ar->regs->rtc_state_cold_reset_mask
444 #define RTC_STATE_V_LSB				0
445 #define RTC_STATE_V_MASK			0x00000007
446 #define RTC_STATE_ADDRESS			0x0000
447 #define PCIE_SOC_WAKE_V_MASK			0x00000001
448 #define PCIE_SOC_WAKE_ADDRESS			0x0004
449 #define PCIE_SOC_WAKE_RESET			0x00000000
450 #define SOC_GLOBAL_RESET_ADDRESS		0x0008
451 
452 #define RTC_SOC_BASE_ADDRESS			ar->regs->rtc_soc_base_address
453 #define RTC_WMAC_BASE_ADDRESS			ar->regs->rtc_wmac_base_address
454 #define MAC_COEX_BASE_ADDRESS			0x00006000
455 #define BT_COEX_BASE_ADDRESS			0x00007000
456 #define SOC_PCIE_BASE_ADDRESS			0x00008000
457 #define SOC_CORE_BASE_ADDRESS			ar->regs->soc_core_base_address
458 #define WLAN_UART_BASE_ADDRESS			0x0000c000
459 #define WLAN_SI_BASE_ADDRESS			0x00010000
460 #define WLAN_GPIO_BASE_ADDRESS			0x00014000
461 #define WLAN_ANALOG_INTF_BASE_ADDRESS		0x0001c000
462 #define WLAN_MAC_BASE_ADDRESS			0x00020000
463 #define EFUSE_BASE_ADDRESS			0x00030000
464 #define FPGA_REG_BASE_ADDRESS			0x00039000
465 #define WLAN_UART2_BASE_ADDRESS			0x00054c00
466 #define CE_WRAPPER_BASE_ADDRESS			ar->regs->ce_wrapper_base_address
467 #define CE0_BASE_ADDRESS			ar->regs->ce0_base_address
468 #define CE1_BASE_ADDRESS			ar->regs->ce1_base_address
469 #define CE2_BASE_ADDRESS			ar->regs->ce2_base_address
470 #define CE3_BASE_ADDRESS			ar->regs->ce3_base_address
471 #define CE4_BASE_ADDRESS			ar->regs->ce4_base_address
472 #define CE5_BASE_ADDRESS			ar->regs->ce5_base_address
473 #define CE6_BASE_ADDRESS			ar->regs->ce6_base_address
474 #define CE7_BASE_ADDRESS			ar->regs->ce7_base_address
475 #define DBI_BASE_ADDRESS			0x00060000
476 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS	0x0006c000
477 #define PCIE_LOCAL_BASE_ADDRESS		ar->regs->pcie_local_base_address
478 
479 #define SOC_RESET_CONTROL_ADDRESS		0x00000000
480 #define SOC_RESET_CONTROL_OFFSET		0x00000000
481 #define SOC_RESET_CONTROL_SI0_RST_MASK		ar->regs->soc_reset_control_si0_rst_mask
482 #define SOC_RESET_CONTROL_CE_RST_MASK		ar->regs->soc_reset_control_ce_rst_mask
483 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK	0x00000040
484 #define SOC_CPU_CLOCK_OFFSET			0x00000020
485 #define SOC_CPU_CLOCK_STANDARD_LSB		0
486 #define SOC_CPU_CLOCK_STANDARD_MASK		0x00000003
487 #define SOC_CLOCK_CONTROL_OFFSET		0x00000028
488 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK		0x00000001
489 #define SOC_SYSTEM_SLEEP_OFFSET			0x000000c4
490 #define SOC_LPO_CAL_OFFSET			0x000000e0
491 #define SOC_LPO_CAL_ENABLE_LSB			20
492 #define SOC_LPO_CAL_ENABLE_MASK			0x00100000
493 #define SOC_LF_TIMER_CONTROL0_ADDRESS		0x00000050
494 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK	0x00000004
495 
496 #define SOC_CHIP_ID_ADDRESS			ar->regs->soc_chip_id_address
497 #define SOC_CHIP_ID_REV_LSB			8
498 #define SOC_CHIP_ID_REV_MASK			0x00000f00
499 
500 #define WLAN_RESET_CONTROL_COLD_RST_MASK	0x00000008
501 #define WLAN_RESET_CONTROL_WARM_RST_MASK	0x00000004
502 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB		0
503 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK		0x00000001
504 
505 #define WLAN_GPIO_PIN0_ADDRESS			0x00000028
506 #define WLAN_GPIO_PIN0_CONFIG_MASK		0x00007800
507 #define WLAN_GPIO_PIN1_ADDRESS			0x0000002c
508 #define WLAN_GPIO_PIN1_CONFIG_MASK		0x00007800
509 #define WLAN_GPIO_PIN10_ADDRESS			0x00000050
510 #define WLAN_GPIO_PIN11_ADDRESS			0x00000054
511 #define WLAN_GPIO_PIN12_ADDRESS			0x00000058
512 #define WLAN_GPIO_PIN13_ADDRESS			0x0000005c
513 
514 #define CLOCK_GPIO_OFFSET			0xffffffff
515 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB		0
516 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK		0
517 
518 #define SI_CONFIG_OFFSET			0x00000000
519 #define SI_CONFIG_BIDIR_OD_DATA_LSB		18
520 #define SI_CONFIG_BIDIR_OD_DATA_MASK		0x00040000
521 #define SI_CONFIG_I2C_LSB			16
522 #define SI_CONFIG_I2C_MASK			0x00010000
523 #define SI_CONFIG_POS_SAMPLE_LSB		7
524 #define SI_CONFIG_POS_SAMPLE_MASK		0x00000080
525 #define SI_CONFIG_INACTIVE_DATA_LSB		5
526 #define SI_CONFIG_INACTIVE_DATA_MASK		0x00000020
527 #define SI_CONFIG_INACTIVE_CLK_LSB		4
528 #define SI_CONFIG_INACTIVE_CLK_MASK		0x00000010
529 #define SI_CONFIG_DIVIDER_LSB			0
530 #define SI_CONFIG_DIVIDER_MASK			0x0000000f
531 #define SI_CS_OFFSET				0x00000004
532 #define SI_CS_DONE_ERR_MASK			0x00000400
533 #define SI_CS_DONE_INT_MASK			0x00000200
534 #define SI_CS_START_LSB				8
535 #define SI_CS_START_MASK			0x00000100
536 #define SI_CS_RX_CNT_LSB			4
537 #define SI_CS_RX_CNT_MASK			0x000000f0
538 #define SI_CS_TX_CNT_LSB			0
539 #define SI_CS_TX_CNT_MASK			0x0000000f
540 
541 #define SI_TX_DATA0_OFFSET			0x00000008
542 #define SI_TX_DATA1_OFFSET			0x0000000c
543 #define SI_RX_DATA0_OFFSET			0x00000010
544 #define SI_RX_DATA1_OFFSET			0x00000014
545 
546 #define CORE_CTRL_CPU_INTR_MASK			0x00002000
547 #define CORE_CTRL_PCIE_REG_31_MASK		0x00000800
548 #define CORE_CTRL_ADDRESS			0x0000
549 #define PCIE_INTR_ENABLE_ADDRESS		0x0008
550 #define PCIE_INTR_CAUSE_ADDRESS			0x000c
551 #define PCIE_INTR_CLR_ADDRESS			ar->regs->pcie_intr_clr_address
552 #define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address
553 #define CPU_INTR_ADDRESS			0x0010
554 
555 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
556 
557 /* Firmware indications to the Host via SCRATCH_3 register. */
558 #define FW_INDICATOR_ADDRESS			ar->regs->fw_indicator_address
559 #define FW_IND_EVENT_PENDING			1
560 #define FW_IND_INITIALIZED			2
561 
562 /* HOST_REG interrupt from firmware */
563 #define PCIE_INTR_FIRMWARE_MASK			ar->regs->pcie_intr_fw_mask
564 #define PCIE_INTR_CE_MASK_ALL			ar->regs->pcie_intr_ce_mask_all
565 
566 #define DRAM_BASE_ADDRESS			0x00400000
567 
568 #define PCIE_BAR_REG_ADDRESS			0x40030
569 
570 #define MISSING 0
571 
572 #define SYSTEM_SLEEP_OFFSET			SOC_SYSTEM_SLEEP_OFFSET
573 #define WLAN_SYSTEM_SLEEP_OFFSET		SOC_SYSTEM_SLEEP_OFFSET
574 #define WLAN_RESET_CONTROL_OFFSET		SOC_RESET_CONTROL_OFFSET
575 #define CLOCK_CONTROL_OFFSET			SOC_CLOCK_CONTROL_OFFSET
576 #define CLOCK_CONTROL_SI0_CLK_MASK		SOC_CLOCK_CONTROL_SI0_CLK_MASK
577 #define RESET_CONTROL_MBOX_RST_MASK		MISSING
578 #define RESET_CONTROL_SI0_RST_MASK		SOC_RESET_CONTROL_SI0_RST_MASK
579 #define GPIO_BASE_ADDRESS			WLAN_GPIO_BASE_ADDRESS
580 #define GPIO_PIN0_OFFSET			WLAN_GPIO_PIN0_ADDRESS
581 #define GPIO_PIN1_OFFSET			WLAN_GPIO_PIN1_ADDRESS
582 #define GPIO_PIN0_CONFIG_MASK			WLAN_GPIO_PIN0_CONFIG_MASK
583 #define GPIO_PIN1_CONFIG_MASK			WLAN_GPIO_PIN1_CONFIG_MASK
584 #define SI_BASE_ADDRESS				WLAN_SI_BASE_ADDRESS
585 #define SCRATCH_BASE_ADDRESS			SOC_CORE_BASE_ADDRESS
586 #define LOCAL_SCRATCH_OFFSET			0x18
587 #define CPU_CLOCK_OFFSET			SOC_CPU_CLOCK_OFFSET
588 #define LPO_CAL_OFFSET				SOC_LPO_CAL_OFFSET
589 #define GPIO_PIN10_OFFSET			WLAN_GPIO_PIN10_ADDRESS
590 #define GPIO_PIN11_OFFSET			WLAN_GPIO_PIN11_ADDRESS
591 #define GPIO_PIN12_OFFSET			WLAN_GPIO_PIN12_ADDRESS
592 #define GPIO_PIN13_OFFSET			WLAN_GPIO_PIN13_ADDRESS
593 #define CPU_CLOCK_STANDARD_LSB			SOC_CPU_CLOCK_STANDARD_LSB
594 #define CPU_CLOCK_STANDARD_MASK			SOC_CPU_CLOCK_STANDARD_MASK
595 #define LPO_CAL_ENABLE_LSB			SOC_LPO_CAL_ENABLE_LSB
596 #define LPO_CAL_ENABLE_MASK			SOC_LPO_CAL_ENABLE_MASK
597 #define ANALOG_INTF_BASE_ADDRESS		WLAN_ANALOG_INTF_BASE_ADDRESS
598 #define MBOX_BASE_ADDRESS			MISSING
599 #define INT_STATUS_ENABLE_ERROR_LSB		MISSING
600 #define INT_STATUS_ENABLE_ERROR_MASK		MISSING
601 #define INT_STATUS_ENABLE_CPU_LSB		MISSING
602 #define INT_STATUS_ENABLE_CPU_MASK		MISSING
603 #define INT_STATUS_ENABLE_COUNTER_LSB		MISSING
604 #define INT_STATUS_ENABLE_COUNTER_MASK		MISSING
605 #define INT_STATUS_ENABLE_MBOX_DATA_LSB		MISSING
606 #define INT_STATUS_ENABLE_MBOX_DATA_MASK	MISSING
607 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB	MISSING
608 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK	MISSING
609 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB	MISSING
610 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK	MISSING
611 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB	MISSING
612 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK	MISSING
613 #define INT_STATUS_ENABLE_ADDRESS		MISSING
614 #define CPU_INT_STATUS_ENABLE_BIT_LSB		MISSING
615 #define CPU_INT_STATUS_ENABLE_BIT_MASK		MISSING
616 #define HOST_INT_STATUS_ADDRESS			MISSING
617 #define CPU_INT_STATUS_ADDRESS			MISSING
618 #define ERROR_INT_STATUS_ADDRESS		MISSING
619 #define ERROR_INT_STATUS_WAKEUP_MASK		MISSING
620 #define ERROR_INT_STATUS_WAKEUP_LSB		MISSING
621 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK	MISSING
622 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB	MISSING
623 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK	MISSING
624 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB	MISSING
625 #define COUNT_DEC_ADDRESS			MISSING
626 #define HOST_INT_STATUS_CPU_MASK		MISSING
627 #define HOST_INT_STATUS_CPU_LSB			MISSING
628 #define HOST_INT_STATUS_ERROR_MASK		MISSING
629 #define HOST_INT_STATUS_ERROR_LSB		MISSING
630 #define HOST_INT_STATUS_COUNTER_MASK		MISSING
631 #define HOST_INT_STATUS_COUNTER_LSB		MISSING
632 #define RX_LOOKAHEAD_VALID_ADDRESS		MISSING
633 #define WINDOW_DATA_ADDRESS			MISSING
634 #define WINDOW_READ_ADDR_ADDRESS		MISSING
635 #define WINDOW_WRITE_ADDR_ADDRESS		MISSING
636 
637 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
638 
639 #endif /* _HW_H_ */
640