1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _HW_H_ 9 #define _HW_H_ 10 11 #include "targaddrs.h" 12 13 enum ath10k_bus { 14 ATH10K_BUS_PCI, 15 ATH10K_BUS_AHB, 16 ATH10K_BUS_SDIO, 17 ATH10K_BUS_USB, 18 ATH10K_BUS_SNOC, 19 }; 20 21 #define ATH10K_FW_DIR "ath10k" 22 23 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac) 24 #define QCA988X_2_0_DEVICE_ID (0x003c) 25 #define QCA6164_2_1_DEVICE_ID (0x0041) 26 #define QCA6174_2_1_DEVICE_ID (0x003e) 27 #define QCA6174_3_2_DEVICE_ID (0x0042) 28 #define QCA99X0_2_0_DEVICE_ID (0x0040) 29 #define QCA9888_2_0_DEVICE_ID (0x0056) 30 #define QCA9984_1_0_DEVICE_ID (0x0046) 31 #define QCA9377_1_0_DEVICE_ID (0x0042) 32 #define QCA9887_1_0_DEVICE_ID (0x0050) 33 34 /* QCA988X 1.0 definitions (unsupported) */ 35 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 36 37 /* QCA988X 2.0 definitions */ 38 #define QCA988X_HW_2_0_VERSION 0x4100016c 39 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 40 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 41 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 43 44 /* QCA9887 1.0 definitions */ 45 #define QCA9887_HW_1_0_VERSION 0x4100016d 46 #define QCA9887_HW_1_0_CHIP_ID_REV 0 47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 48 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" 49 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 50 51 /* QCA6174 target BMI version signatures */ 52 #define QCA6174_HW_1_0_VERSION 0x05000000 53 #define QCA6174_HW_1_1_VERSION 0x05000001 54 #define QCA6174_HW_1_3_VERSION 0x05000003 55 #define QCA6174_HW_2_1_VERSION 0x05010000 56 #define QCA6174_HW_3_0_VERSION 0x05020000 57 #define QCA6174_HW_3_2_VERSION 0x05030000 58 59 /* QCA9377 target BMI version signatures */ 60 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 61 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 62 63 enum qca6174_pci_rev { 64 QCA6174_PCI_REV_1_1 = 0x11, 65 QCA6174_PCI_REV_1_3 = 0x13, 66 QCA6174_PCI_REV_2_0 = 0x20, 67 QCA6174_PCI_REV_3_0 = 0x30, 68 }; 69 70 enum qca6174_chip_id_rev { 71 QCA6174_HW_1_0_CHIP_ID_REV = 0, 72 QCA6174_HW_1_1_CHIP_ID_REV = 1, 73 QCA6174_HW_1_3_CHIP_ID_REV = 2, 74 QCA6174_HW_2_1_CHIP_ID_REV = 4, 75 QCA6174_HW_2_2_CHIP_ID_REV = 5, 76 QCA6174_HW_3_0_CHIP_ID_REV = 8, 77 QCA6174_HW_3_1_CHIP_ID_REV = 9, 78 QCA6174_HW_3_2_CHIP_ID_REV = 10, 79 }; 80 81 enum qca9377_chip_id_rev { 82 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 83 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 84 }; 85 86 #define QCA6174_HW_2_1_FW_DIR ATH10K_FW_DIR "/QCA6174/hw2.1" 87 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 88 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 89 90 #define QCA6174_HW_3_0_FW_DIR ATH10K_FW_DIR "/QCA6174/hw3.0" 91 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 92 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 93 94 /* QCA99X0 1.0 definitions (unsupported) */ 95 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 96 97 /* QCA99X0 2.0 definitions */ 98 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 99 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 100 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 101 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 102 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 103 104 /* QCA9984 1.0 defines */ 105 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 106 #define QCA9984_HW_DEV_TYPE 0xa 107 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 108 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 109 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" 110 #define QCA9984_HW_1_0_EBOARD_DATA_FILE "eboard.bin" 111 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 112 113 /* QCA9888 2.0 defines */ 114 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 115 #define QCA9888_HW_DEV_TYPE 0xc 116 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 117 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 118 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" 119 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 120 121 /* QCA9377 1.0 definitions */ 122 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 123 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 124 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 125 126 /* QCA4019 1.0 definitions */ 127 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 128 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 129 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" 130 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 131 132 /* WCN3990 1.0 definitions */ 133 #define WCN3990_HW_1_0_DEV_VERSION ATH10K_HW_WCN3990 134 #define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw1.0" 135 136 #define ATH10K_FW_FILE_BASE "firmware" 137 #define ATH10K_FW_API_MAX 6 138 #define ATH10K_FW_API_MIN 2 139 140 #define ATH10K_FW_API2_FILE "firmware-2.bin" 141 #define ATH10K_FW_API3_FILE "firmware-3.bin" 142 143 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 144 #define ATH10K_FW_API4_FILE "firmware-4.bin" 145 146 /* HTT id conflict fix for management frames over HTT */ 147 #define ATH10K_FW_API5_FILE "firmware-5.bin" 148 149 /* the firmware-6.bin blob */ 150 #define ATH10K_FW_API6_FILE "firmware-6.bin" 151 152 #define ATH10K_FW_UTF_FILE "utf.bin" 153 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 154 155 #define ATH10K_FW_UTF_FILE_BASE "utf" 156 157 /* includes also the null byte */ 158 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 159 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 160 161 #define ATH10K_BOARD_API2_FILE "board-2.bin" 162 163 #define REG_DUMP_COUNT_QCA988X 60 164 165 struct ath10k_fw_ie { 166 __le32 id; 167 __le32 len; 168 u8 data[]; 169 }; 170 171 enum ath10k_fw_ie_type { 172 ATH10K_FW_IE_FW_VERSION = 0, 173 ATH10K_FW_IE_TIMESTAMP = 1, 174 ATH10K_FW_IE_FEATURES = 2, 175 ATH10K_FW_IE_FW_IMAGE = 3, 176 ATH10K_FW_IE_OTP_IMAGE = 4, 177 178 /* WMI "operations" interface version, 32 bit value. Supported from 179 * FW API 4 and above. 180 */ 181 ATH10K_FW_IE_WMI_OP_VERSION = 5, 182 183 /* HTT "operations" interface version, 32 bit value. Supported from 184 * FW API 5 and above. 185 */ 186 ATH10K_FW_IE_HTT_OP_VERSION = 6, 187 188 /* Code swap image for firmware binary */ 189 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 190 }; 191 192 enum ath10k_fw_wmi_op_version { 193 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 194 195 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 196 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 197 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 198 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 199 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 200 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 201 202 /* keep last */ 203 ATH10K_FW_WMI_OP_VERSION_MAX, 204 }; 205 206 enum ath10k_fw_htt_op_version { 207 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 208 209 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 210 211 /* also used in 10.2 and 10.2.4 branches */ 212 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 213 214 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 215 216 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 217 218 /* keep last */ 219 ATH10K_FW_HTT_OP_VERSION_MAX, 220 }; 221 222 enum ath10k_bd_ie_type { 223 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 224 ATH10K_BD_IE_BOARD = 0, 225 ATH10K_BD_IE_BOARD_EXT = 1, 226 }; 227 228 enum ath10k_bd_ie_board_type { 229 ATH10K_BD_IE_BOARD_NAME = 0, 230 ATH10K_BD_IE_BOARD_DATA = 1, 231 }; 232 233 enum ath10k_hw_rev { 234 ATH10K_HW_QCA988X, 235 ATH10K_HW_QCA6174, 236 ATH10K_HW_QCA99X0, 237 ATH10K_HW_QCA9888, 238 ATH10K_HW_QCA9984, 239 ATH10K_HW_QCA9377, 240 ATH10K_HW_QCA4019, 241 ATH10K_HW_QCA9887, 242 ATH10K_HW_WCN3990, 243 }; 244 245 struct ath10k_hw_regs { 246 u32 rtc_soc_base_address; 247 u32 rtc_wmac_base_address; 248 u32 soc_core_base_address; 249 u32 wlan_mac_base_address; 250 u32 ce_wrapper_base_address; 251 u32 ce0_base_address; 252 u32 ce1_base_address; 253 u32 ce2_base_address; 254 u32 ce3_base_address; 255 u32 ce4_base_address; 256 u32 ce5_base_address; 257 u32 ce6_base_address; 258 u32 ce7_base_address; 259 u32 ce8_base_address; 260 u32 ce9_base_address; 261 u32 ce10_base_address; 262 u32 ce11_base_address; 263 u32 soc_reset_control_si0_rst_mask; 264 u32 soc_reset_control_ce_rst_mask; 265 u32 soc_chip_id_address; 266 u32 scratch_3_address; 267 u32 fw_indicator_address; 268 u32 pcie_local_base_address; 269 u32 ce_wrap_intr_sum_host_msi_lsb; 270 u32 ce_wrap_intr_sum_host_msi_mask; 271 u32 pcie_intr_fw_mask; 272 u32 pcie_intr_ce_mask_all; 273 u32 pcie_intr_clr_address; 274 u32 cpu_pll_init_address; 275 u32 cpu_speed_address; 276 u32 core_clk_div_address; 277 }; 278 279 extern const struct ath10k_hw_regs qca988x_regs; 280 extern const struct ath10k_hw_regs qca6174_regs; 281 extern const struct ath10k_hw_regs qca99x0_regs; 282 extern const struct ath10k_hw_regs qca4019_regs; 283 extern const struct ath10k_hw_regs wcn3990_regs; 284 285 struct ath10k_hw_ce_regs_addr_map { 286 u32 msb; 287 u32 lsb; 288 u32 mask; 289 }; 290 291 struct ath10k_hw_ce_ctrl1 { 292 u32 addr; 293 u32 hw_mask; 294 u32 sw_mask; 295 u32 hw_wr_mask; 296 u32 sw_wr_mask; 297 u32 reset_mask; 298 u32 reset; 299 struct ath10k_hw_ce_regs_addr_map *src_ring; 300 struct ath10k_hw_ce_regs_addr_map *dst_ring; 301 struct ath10k_hw_ce_regs_addr_map *dmax; }; 302 303 struct ath10k_hw_ce_cmd_halt { 304 u32 status_reset; 305 u32 msb; 306 u32 mask; 307 struct ath10k_hw_ce_regs_addr_map *status; }; 308 309 struct ath10k_hw_ce_host_ie { 310 u32 copy_complete_reset; 311 struct ath10k_hw_ce_regs_addr_map *copy_complete; }; 312 313 struct ath10k_hw_ce_host_wm_regs { 314 u32 dstr_lmask; 315 u32 dstr_hmask; 316 u32 srcr_lmask; 317 u32 srcr_hmask; 318 u32 cc_mask; 319 u32 wm_mask; 320 u32 addr; 321 }; 322 323 struct ath10k_hw_ce_misc_regs { 324 u32 axi_err; 325 u32 dstr_add_err; 326 u32 srcr_len_err; 327 u32 dstr_mlen_vio; 328 u32 dstr_overflow; 329 u32 srcr_overflow; 330 u32 err_mask; 331 u32 addr; 332 }; 333 334 struct ath10k_hw_ce_dst_src_wm_regs { 335 u32 addr; 336 u32 low_rst; 337 u32 high_rst; 338 struct ath10k_hw_ce_regs_addr_map *wm_low; 339 struct ath10k_hw_ce_regs_addr_map *wm_high; }; 340 341 struct ath10k_hw_ce_ctrl1_upd { 342 u32 shift; 343 u32 mask; 344 u32 enable; 345 }; 346 347 struct ath10k_hw_ce_regs { 348 u32 sr_base_addr_lo; 349 u32 sr_base_addr_hi; 350 u32 sr_size_addr; 351 u32 dr_base_addr_lo; 352 u32 dr_base_addr_hi; 353 u32 dr_size_addr; 354 u32 ce_cmd_addr; 355 u32 misc_ie_addr; 356 u32 sr_wr_index_addr; 357 u32 dst_wr_index_addr; 358 u32 current_srri_addr; 359 u32 current_drri_addr; 360 u32 ddr_addr_for_rri_low; 361 u32 ddr_addr_for_rri_high; 362 u32 ce_rri_low; 363 u32 ce_rri_high; 364 u32 host_ie_addr; 365 struct ath10k_hw_ce_host_wm_regs *wm_regs; 366 struct ath10k_hw_ce_misc_regs *misc_regs; 367 struct ath10k_hw_ce_ctrl1 *ctrl1_regs; 368 struct ath10k_hw_ce_cmd_halt *cmd_halt; 369 struct ath10k_hw_ce_host_ie *host_ie; 370 struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr; 371 struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; 372 struct ath10k_hw_ce_ctrl1_upd *upd; 373 }; 374 375 struct ath10k_hw_values { 376 u32 rtc_state_val_on; 377 u8 ce_count; 378 u8 msi_assign_ce_max; 379 u8 num_target_ce_config_wlan; 380 u16 ce_desc_meta_data_mask; 381 u8 ce_desc_meta_data_lsb; 382 u32 rfkill_pin; 383 u32 rfkill_cfg; 384 bool rfkill_on_level; 385 }; 386 387 extern const struct ath10k_hw_values qca988x_values; 388 extern const struct ath10k_hw_values qca6174_values; 389 extern const struct ath10k_hw_values qca99x0_values; 390 extern const struct ath10k_hw_values qca9888_values; 391 extern const struct ath10k_hw_values qca4019_values; 392 extern const struct ath10k_hw_values wcn3990_values; 393 extern const struct ath10k_hw_ce_regs wcn3990_ce_regs; 394 extern const struct ath10k_hw_ce_regs qcax_ce_regs; 395 396 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 397 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 398 399 int ath10k_hw_diag_fast_download(struct ath10k *ar, 400 u32 address, 401 const void *buffer, 402 u32 length); 403 404 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 405 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 406 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 407 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 408 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 409 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 410 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 411 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 412 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990) 413 414 /* Known peculiarities: 415 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 416 * - raw have FCS, nwifi doesn't 417 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 418 * param, llc/snap) are aligned to 4byte boundaries each 419 */ 420 enum ath10k_hw_txrx_mode { 421 ATH10K_HW_TXRX_RAW = 0, 422 423 /* Native Wifi decap mode is used to align IP frames to 4-byte 424 * boundaries and avoid a very expensive re-alignment in mac80211. 425 */ 426 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 427 ATH10K_HW_TXRX_ETHERNET = 2, 428 429 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 430 ATH10K_HW_TXRX_MGMT = 3, 431 }; 432 433 enum ath10k_mcast2ucast_mode { 434 ATH10K_MCAST2UCAST_DISABLED = 0, 435 ATH10K_MCAST2UCAST_ENABLED = 1, 436 }; 437 438 enum ath10k_hw_rate_ofdm { 439 ATH10K_HW_RATE_OFDM_48M = 0, 440 ATH10K_HW_RATE_OFDM_24M, 441 ATH10K_HW_RATE_OFDM_12M, 442 ATH10K_HW_RATE_OFDM_6M, 443 ATH10K_HW_RATE_OFDM_54M, 444 ATH10K_HW_RATE_OFDM_36M, 445 ATH10K_HW_RATE_OFDM_18M, 446 ATH10K_HW_RATE_OFDM_9M, 447 }; 448 449 enum ath10k_hw_rate_cck { 450 ATH10K_HW_RATE_CCK_LP_11M = 0, 451 ATH10K_HW_RATE_CCK_LP_5_5M, 452 ATH10K_HW_RATE_CCK_LP_2M, 453 ATH10K_HW_RATE_CCK_LP_1M, 454 ATH10K_HW_RATE_CCK_SP_11M, 455 ATH10K_HW_RATE_CCK_SP_5_5M, 456 ATH10K_HW_RATE_CCK_SP_2M, 457 }; 458 459 enum ath10k_hw_rate_rev2_cck { 460 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 461 ATH10K_HW_RATE_REV2_CCK_LP_2M, 462 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 463 ATH10K_HW_RATE_REV2_CCK_LP_11M, 464 ATH10K_HW_RATE_REV2_CCK_SP_2M, 465 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 466 ATH10K_HW_RATE_REV2_CCK_SP_11M, 467 }; 468 469 enum ath10k_hw_cc_wraparound_type { 470 ATH10K_HW_CC_WRAP_DISABLED = 0, 471 472 /* This type is when the HW chip has a quirky Cycle Counter 473 * wraparound which resets to 0x7fffffff instead of 0. All 474 * other CC related counters (e.g. Rx Clear Count) are divided 475 * by 2 so they never wraparound themselves. 476 */ 477 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 478 479 /* Each hw counter wrapsaround independently. When the 480 * counter overflows the repestive counter is right shifted 481 * by 1, i.e reset to 0x7fffffff, and other counters will be 482 * running unaffected. In this type of wraparound, it should 483 * be possible to report accurate Rx busy time unlike the 484 * first type. 485 */ 486 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 487 }; 488 489 enum ath10k_hw_refclk_speed { 490 ATH10K_HW_REFCLK_UNKNOWN = -1, 491 ATH10K_HW_REFCLK_48_MHZ = 0, 492 ATH10K_HW_REFCLK_19_2_MHZ = 1, 493 ATH10K_HW_REFCLK_24_MHZ = 2, 494 ATH10K_HW_REFCLK_26_MHZ = 3, 495 ATH10K_HW_REFCLK_37_4_MHZ = 4, 496 ATH10K_HW_REFCLK_38_4_MHZ = 5, 497 ATH10K_HW_REFCLK_40_MHZ = 6, 498 ATH10K_HW_REFCLK_52_MHZ = 7, 499 500 /* must be the last one */ 501 ATH10K_HW_REFCLK_COUNT, 502 }; 503 504 struct ath10k_hw_clk_params { 505 u32 refclk; 506 u32 div; 507 u32 rnfrac; 508 u32 settle_time; 509 u32 refdiv; 510 u32 outdiv; 511 }; 512 513 struct ath10k_hw_params { 514 u32 id; 515 u16 dev_id; 516 enum ath10k_bus bus; 517 const char *name; 518 u32 patch_load_addr; 519 int uart_pin; 520 u32 otp_exe_param; 521 522 /* Type of hw cycle counter wraparound logic, for more info 523 * refer enum ath10k_hw_cc_wraparound_type. 524 */ 525 enum ath10k_hw_cc_wraparound_type cc_wraparound_type; 526 527 /* Some of chip expects fragment descriptor to be continuous 528 * memory for any TX operation. Set continuous_frag_desc flag 529 * for the hardware which have such requirement. 530 */ 531 bool continuous_frag_desc; 532 533 /* CCK hardware rate table mapping for the newer chipsets 534 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values 535 * are in a proper order with respect to the rate/preamble 536 */ 537 bool cck_rate_map_rev2; 538 539 u32 channel_counters_freq_hz; 540 541 /* Mgmt tx descriptors threshold for limiting probe response 542 * frames. 543 */ 544 u32 max_probe_resp_desc_thres; 545 546 u32 tx_chain_mask; 547 u32 rx_chain_mask; 548 u32 max_spatial_stream; 549 u32 cal_data_len; 550 551 struct ath10k_hw_params_fw { 552 const char *dir; 553 const char *board; 554 size_t board_size; 555 const char *eboard; 556 size_t ext_board_size; 557 size_t board_ext_size; 558 } fw; 559 560 /* qca99x0 family chips deliver broadcast/multicast management 561 * frames encrypted and expect software do decryption. 562 */ 563 bool sw_decrypt_mcast_mgmt; 564 565 const struct ath10k_hw_ops *hw_ops; 566 567 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ 568 int decap_align_bytes; 569 570 /* hw specific clock control parameters */ 571 const struct ath10k_hw_clk_params *hw_clk; 572 int target_cpu_freq; 573 574 /* Number of bytes to be discarded for each FFT sample */ 575 int spectral_bin_discard; 576 577 /* The board may have a restricted NSS for 160 or 80+80 vs what it 578 * can do for 80Mhz. 579 */ 580 int vht160_mcs_rx_highest; 581 int vht160_mcs_tx_highest; 582 583 /* Number of ciphers supported (i.e First N) in cipher_suites array */ 584 int n_cipher_suites; 585 586 u32 num_peers; 587 u32 ast_skid_limit; 588 u32 num_wds_entries; 589 590 /* Targets supporting physical addressing capability above 32-bits */ 591 bool target_64bit; 592 593 /* Target rx ring fill level */ 594 u32 rx_ring_fill_level; 595 596 /* target supporting shadow register for ce write */ 597 bool shadow_reg_support; 598 599 /* target supporting retention restore on ddr */ 600 bool rri_on_ddr; 601 602 /* Number of bytes to be the offset for each FFT sample */ 603 int spectral_bin_offset; 604 605 /* targets which require hw filter reset during boot up, 606 * to avoid it sending spurious acks. 607 */ 608 bool hw_filter_reset_required; 609 610 /* target supporting fw download via diag ce */ 611 bool fw_diag_ce_download; 612 613 /* target supporting fw download via large size BMI */ 614 bool bmi_large_size_download; 615 616 /* need to set uart pin if disable uart print, workaround for a 617 * firmware bug 618 */ 619 bool uart_pin_workaround; 620 621 /* Workaround for the credit size calculation */ 622 bool credit_size_workaround; 623 624 /* tx stats support over pktlog */ 625 bool tx_stats_over_pktlog; 626 627 /* provides bitrates for sta_statistics using WMI_TLV_PEER_STATS_INFO_EVENTID */ 628 bool supports_peer_stats_info; 629 630 bool dynamic_sar_support; 631 }; 632 633 struct htt_rx_desc; 634 struct htt_resp; 635 struct htt_data_tx_completion_ext; 636 637 /* Defines needed for Rx descriptor abstraction */ 638 struct ath10k_hw_ops { 639 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 640 void (*set_coverage_class)(struct ath10k *ar, s16 value); 641 int (*enable_pll_clk)(struct ath10k *ar); 642 bool (*rx_desc_get_msdu_limit_error)(struct htt_rx_desc *rxd); 643 int (*tx_data_rssi_pad_bytes)(struct htt_resp *htt); 644 int (*is_rssi_enable)(struct htt_resp *resp); 645 }; 646 647 extern const struct ath10k_hw_ops qca988x_ops; 648 extern const struct ath10k_hw_ops qca99x0_ops; 649 extern const struct ath10k_hw_ops qca6174_ops; 650 extern const struct ath10k_hw_ops qca6174_sdio_ops; 651 extern const struct ath10k_hw_ops wcn3990_ops; 652 653 extern const struct ath10k_hw_clk_params qca6174_clk[]; 654 655 static inline int 656 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, 657 struct htt_rx_desc *rxd) 658 { 659 if (hw->hw_ops->rx_desc_get_l3_pad_bytes) 660 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd); 661 return 0; 662 } 663 664 static inline bool 665 ath10k_rx_desc_msdu_limit_error(struct ath10k_hw_params *hw, 666 struct htt_rx_desc *rxd) 667 { 668 if (hw->hw_ops->rx_desc_get_msdu_limit_error) 669 return hw->hw_ops->rx_desc_get_msdu_limit_error(rxd); 670 return false; 671 } 672 673 static inline int 674 ath10k_tx_data_rssi_get_pad_bytes(struct ath10k_hw_params *hw, 675 struct htt_resp *htt) 676 { 677 if (hw->hw_ops->tx_data_rssi_pad_bytes) 678 return hw->hw_ops->tx_data_rssi_pad_bytes(htt); 679 return 0; 680 } 681 682 static inline int 683 ath10k_is_rssi_enable(struct ath10k_hw_params *hw, 684 struct htt_resp *resp) 685 { 686 if (hw->hw_ops->is_rssi_enable) 687 return hw->hw_ops->is_rssi_enable(resp); 688 return 0; 689 } 690 691 /* Target specific defines for MAIN firmware */ 692 #define TARGET_NUM_VDEVS 8 693 #define TARGET_NUM_PEER_AST 2 694 #define TARGET_NUM_WDS_ENTRIES 32 695 #define TARGET_DMA_BURST_SIZE 0 696 #define TARGET_MAC_AGGR_DELIM 0 697 #define TARGET_AST_SKID_LIMIT 16 698 #define TARGET_NUM_STATIONS 16 699 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 700 (TARGET_NUM_VDEVS)) 701 #define TARGET_NUM_OFFLOAD_PEERS 0 702 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 703 #define TARGET_NUM_PEER_KEYS 2 704 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 705 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 706 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 707 #define TARGET_RX_TIMEOUT_LO_PRI 100 708 #define TARGET_RX_TIMEOUT_HI_PRI 40 709 710 #define TARGET_SCAN_MAX_PENDING_REQS 4 711 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 712 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 713 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 714 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 715 #define TARGET_NUM_MCAST_GROUPS 0 716 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 717 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 718 #define TARGET_TX_DBG_LOG_SIZE 1024 719 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 720 #define TARGET_VOW_CONFIG 0 721 #define TARGET_NUM_MSDU_DESC (1024 + 400) 722 #define TARGET_MAX_FRAG_ENTRIES 0 723 724 /* Target specific defines for 10.X firmware */ 725 #define TARGET_10X_NUM_VDEVS 16 726 #define TARGET_10X_NUM_PEER_AST 2 727 #define TARGET_10X_NUM_WDS_ENTRIES 32 728 #define TARGET_10X_DMA_BURST_SIZE 0 729 #define TARGET_10X_MAC_AGGR_DELIM 0 730 #define TARGET_10X_AST_SKID_LIMIT 128 731 #define TARGET_10X_NUM_STATIONS 128 732 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 733 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 734 (TARGET_10X_NUM_VDEVS)) 735 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 736 (TARGET_10X_NUM_VDEVS)) 737 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 738 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 739 #define TARGET_10X_NUM_PEER_KEYS 2 740 #define TARGET_10X_NUM_TIDS_MAX 256 741 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 742 (TARGET_10X_NUM_PEERS) * 2) 743 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 744 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 745 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 746 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 747 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 748 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 749 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 750 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 751 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 752 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 753 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 754 #define TARGET_10X_NUM_MCAST_GROUPS 0 755 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 756 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 757 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 758 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 759 #define TARGET_10X_VOW_CONFIG 0 760 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 761 #define TARGET_10X_MAX_FRAG_ENTRIES 0 762 763 /* 10.2 parameters */ 764 #define TARGET_10_2_DMA_BURST_SIZE 0 765 766 /* Target specific defines for WMI-TLV firmware */ 767 #define TARGET_TLV_NUM_VDEVS 4 768 #define TARGET_TLV_NUM_STATIONS 32 769 #define TARGET_TLV_NUM_PEERS 33 770 #define TARGET_TLV_NUM_TDLS_VDEVS 1 771 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 772 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 773 #define TARGET_TLV_NUM_MSDU_DESC_HL 1024 774 #define TARGET_TLV_NUM_WOW_PATTERNS 22 775 #define TARGET_TLV_MGMT_NUM_MSDU_DESC (50) 776 777 /* Target specific defines for WMI-HL-1.0 firmware */ 778 #define TARGET_HL_TLV_NUM_PEERS 33 779 #define TARGET_HL_TLV_AST_SKID_LIMIT 16 780 #define TARGET_HL_TLV_NUM_WDS_ENTRIES 2 781 782 /* Target specific defines for QCA9377 high latency firmware */ 783 #define TARGET_QCA9377_HL_NUM_PEERS 15 784 785 /* Diagnostic Window */ 786 #define CE_DIAG_PIPE 7 787 788 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 789 790 /* Target specific defines for 10.4 firmware */ 791 #define TARGET_10_4_NUM_VDEVS 16 792 #define TARGET_10_4_NUM_STATIONS 32 793 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 794 (TARGET_10_4_NUM_VDEVS)) 795 #define TARGET_10_4_ACTIVE_PEERS 0 796 797 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 798 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 799 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 800 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 801 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 802 #define TARGET_10_4_NUM_PEER_KEYS 2 803 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 804 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 805 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 806 #define TARGET_10_4_AST_SKID_LIMIT 32 807 808 /* 100 ms for video, best-effort, and background */ 809 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 810 811 /* 40 ms for voice */ 812 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 813 814 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 815 #define TARGET_10_4_SCAN_MAX_REQS 4 816 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 817 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 818 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 819 820 /* Note: mcast to ucast is disabled by default */ 821 #define TARGET_10_4_NUM_MCAST_GROUPS 0 822 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 823 #define TARGET_10_4_MCAST2UCAST_MODE 0 824 825 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 826 #define TARGET_10_4_NUM_WDS_ENTRIES 32 827 #define TARGET_10_4_DMA_BURST_SIZE 1 828 #define TARGET_10_4_MAC_AGGR_DELIM 0 829 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 830 #define TARGET_10_4_VOW_CONFIG 0 831 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 832 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 833 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 834 #define TARGET_10_4_SMART_ANT_CAP 0 835 #define TARGET_10_4_BK_MIN_FREE 0 836 #define TARGET_10_4_BE_MIN_FREE 0 837 #define TARGET_10_4_VI_MIN_FREE 0 838 #define TARGET_10_4_VO_MIN_FREE 0 839 #define TARGET_10_4_RX_BATCH_MODE 1 840 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 841 #define TARGET_10_4_ATF_CONFIG 0 842 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 843 #define TARGET_10_4_QWRAP_CONFIG 0 844 845 /* TDLS config */ 846 #define TARGET_10_4_NUM_TDLS_VDEVS 1 847 #define TARGET_10_4_NUM_TDLS_BUFFER_STA 1 848 #define TARGET_10_4_NUM_TDLS_SLEEP_STA 1 849 850 /* Maximum number of Copy Engine's supported */ 851 #define CE_COUNT_MAX 12 852 853 /* Number of Copy Engines supported */ 854 #define CE_COUNT ar->hw_values->ce_count 855 856 /* 857 * Granted MSIs are assigned as follows: 858 * Firmware uses the first 859 * Remaining MSIs, if any, are used by Copy Engines 860 * This mapping is known to both Target firmware and Host software. 861 * It may be changed as long as Host and Target are kept in sync. 862 */ 863 /* MSI for firmware (errors, etc.) */ 864 #define MSI_ASSIGN_FW 0 865 866 /* MSIs for Copy Engines */ 867 #define MSI_ASSIGN_CE_INITIAL 1 868 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 869 870 /* as of IP3.7.1 */ 871 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 872 873 #define RTC_STATE_V_LSB 0 874 #define RTC_STATE_V_MASK 0x00000007 875 #define RTC_STATE_ADDRESS 0x0000 876 #define PCIE_SOC_WAKE_V_MASK 0x00000001 877 #define PCIE_SOC_WAKE_ADDRESS 0x0004 878 #define PCIE_SOC_WAKE_RESET 0x00000000 879 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 880 881 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 882 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 883 #define MAC_COEX_BASE_ADDRESS 0x00006000 884 #define BT_COEX_BASE_ADDRESS 0x00007000 885 #define SOC_PCIE_BASE_ADDRESS 0x00008000 886 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 887 #define WLAN_UART_BASE_ADDRESS 0x0000c000 888 #define WLAN_SI_BASE_ADDRESS 0x00010000 889 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 890 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 891 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address 892 #define EFUSE_BASE_ADDRESS 0x00030000 893 #define FPGA_REG_BASE_ADDRESS 0x00039000 894 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 895 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 896 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 897 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 898 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 899 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 900 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 901 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 902 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 903 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 904 #define DBI_BASE_ADDRESS 0x00060000 905 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 906 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 907 908 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 909 #define SOC_RESET_CONTROL_OFFSET 0x00000000 910 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 911 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 912 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 913 #define SOC_CPU_CLOCK_OFFSET 0x00000020 914 #define SOC_CPU_CLOCK_STANDARD_LSB 0 915 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 916 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 917 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 918 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 919 #define SOC_LPO_CAL_OFFSET 0x000000e0 920 #define SOC_LPO_CAL_ENABLE_LSB 20 921 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 922 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 923 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 924 925 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 926 #define SOC_CHIP_ID_REV_LSB 8 927 #define SOC_CHIP_ID_REV_MASK 0x00000f00 928 929 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 930 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 931 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 932 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 933 934 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 935 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 936 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 937 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 938 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 939 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 940 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 941 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 942 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 943 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 944 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 945 946 #define CLOCK_GPIO_OFFSET 0xffffffff 947 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 948 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 949 950 #define SI_CONFIG_OFFSET 0x00000000 951 #define SI_CONFIG_ERR_INT_LSB 19 952 #define SI_CONFIG_ERR_INT_MASK 0x00080000 953 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 954 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 955 #define SI_CONFIG_I2C_LSB 16 956 #define SI_CONFIG_I2C_MASK 0x00010000 957 #define SI_CONFIG_POS_SAMPLE_LSB 7 958 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 959 #define SI_CONFIG_INACTIVE_DATA_LSB 5 960 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 961 #define SI_CONFIG_INACTIVE_CLK_LSB 4 962 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 963 #define SI_CONFIG_DIVIDER_LSB 0 964 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 965 #define SI_CS_OFFSET 0x00000004 966 #define SI_CS_DONE_ERR_LSB 10 967 #define SI_CS_DONE_ERR_MASK 0x00000400 968 #define SI_CS_DONE_INT_LSB 9 969 #define SI_CS_DONE_INT_MASK 0x00000200 970 #define SI_CS_START_LSB 8 971 #define SI_CS_START_MASK 0x00000100 972 #define SI_CS_RX_CNT_LSB 4 973 #define SI_CS_RX_CNT_MASK 0x000000f0 974 #define SI_CS_TX_CNT_LSB 0 975 #define SI_CS_TX_CNT_MASK 0x0000000f 976 977 #define SI_TX_DATA0_OFFSET 0x00000008 978 #define SI_TX_DATA1_OFFSET 0x0000000c 979 #define SI_RX_DATA0_OFFSET 0x00000010 980 #define SI_RX_DATA1_OFFSET 0x00000014 981 982 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 983 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 984 #define CORE_CTRL_ADDRESS 0x0000 985 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 986 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 987 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 988 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 989 #define CPU_INTR_ADDRESS 0x0010 990 #define FW_RAM_CONFIG_ADDRESS 0x0018 991 992 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 993 994 /* Firmware indications to the Host via SCRATCH_3 register. */ 995 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 996 #define FW_IND_EVENT_PENDING 1 997 #define FW_IND_INITIALIZED 2 998 #define FW_IND_HOST_READY 0x80000000 999 1000 /* HOST_REG interrupt from firmware */ 1001 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 1002 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 1003 1004 #define DRAM_BASE_ADDRESS 0x00400000 1005 1006 #define PCIE_BAR_REG_ADDRESS 0x40030 1007 1008 #define MISSING 0 1009 1010 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 1011 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 1012 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 1013 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 1014 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 1015 #define RESET_CONTROL_MBOX_RST_MASK MISSING 1016 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 1017 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 1018 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 1019 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 1020 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 1021 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 1022 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 1023 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 1024 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 1025 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 1026 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 1027 #define LOCAL_SCRATCH_OFFSET 0x18 1028 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 1029 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 1030 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 1031 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 1032 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 1033 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 1034 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 1035 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 1036 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 1037 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 1038 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 1039 #define MBOX_BASE_ADDRESS MISSING 1040 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 1041 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 1042 #define INT_STATUS_ENABLE_CPU_LSB MISSING 1043 #define INT_STATUS_ENABLE_CPU_MASK MISSING 1044 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 1045 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 1046 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 1047 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 1048 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 1049 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 1050 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 1051 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 1052 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 1053 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 1054 #define INT_STATUS_ENABLE_ADDRESS MISSING 1055 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 1056 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 1057 #define HOST_INT_STATUS_ADDRESS MISSING 1058 #define CPU_INT_STATUS_ADDRESS MISSING 1059 #define ERROR_INT_STATUS_ADDRESS MISSING 1060 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 1061 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 1062 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 1063 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 1064 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 1065 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 1066 #define COUNT_DEC_ADDRESS MISSING 1067 #define HOST_INT_STATUS_CPU_MASK MISSING 1068 #define HOST_INT_STATUS_CPU_LSB MISSING 1069 #define HOST_INT_STATUS_ERROR_MASK MISSING 1070 #define HOST_INT_STATUS_ERROR_LSB MISSING 1071 #define HOST_INT_STATUS_COUNTER_MASK MISSING 1072 #define HOST_INT_STATUS_COUNTER_LSB MISSING 1073 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 1074 #define WINDOW_DATA_ADDRESS MISSING 1075 #define WINDOW_READ_ADDR_ADDRESS MISSING 1076 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 1077 1078 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 1079 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 1080 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 1081 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 1082 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 1083 1084 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 1085 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 1086 #define QCA9887_EEPROM_ADDR_HI_LSB 8 1087 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 1088 #define QCA9887_EEPROM_ADDR_LO_LSB 16 1089 1090 #define MBOX_RESET_CONTROL_ADDRESS 0x00000000 1091 #define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800 1092 #define MBOX_HOST_INT_STATUS_ERROR_LSB 7 1093 #define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080 1094 #define MBOX_HOST_INT_STATUS_CPU_LSB 6 1095 #define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040 1096 #define MBOX_HOST_INT_STATUS_COUNTER_LSB 4 1097 #define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010 1098 #define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801 1099 #define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802 1100 #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB 2 1101 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 1102 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 1103 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 1104 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 1105 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 1106 #define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803 1107 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0 1108 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff 1109 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805 1110 #define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828 1111 #define MBOX_INT_STATUS_ENABLE_ERROR_LSB 7 1112 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080 1113 #define MBOX_INT_STATUS_ENABLE_CPU_LSB 6 1114 #define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040 1115 #define MBOX_INT_STATUS_ENABLE_INT_LSB 5 1116 #define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020 1117 #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB 4 1118 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 1119 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0 1120 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f 1121 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819 1122 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0 1123 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1124 #define MBOX_CPU_STATUS_ENABLE_ASSERT_MASK 0x00000001 1125 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a 1126 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 1127 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 1128 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 1129 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 1130 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b 1131 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 1132 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1133 #define MBOX_COUNT_ADDRESS 0x00000820 1134 #define MBOX_COUNT_DEC_ADDRESS 0x00000840 1135 #define MBOX_WINDOW_DATA_ADDRESS 0x00000874 1136 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878 1137 #define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c 1138 #define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883 1139 #define MBOX_CPU_DBG_ADDRESS 0x00000884 1140 #define MBOX_RTC_BASE_ADDRESS 0x00000000 1141 #define MBOX_GPIO_BASE_ADDRESS 0x00005000 1142 #define MBOX_MBOX_BASE_ADDRESS 0x00008000 1143 1144 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 1145 1146 /* Register definitions for first generation ath10k cards. These cards include 1147 * a mac thich has a register allocation similar to ath9k and at least some 1148 * registers including the ones relevant for modifying the coverage class are 1149 * identical to the ath9k definitions. 1150 * These registers are usually managed by the ath10k firmware. However by 1151 * overriding them it is possible to support coverage class modifications. 1152 */ 1153 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014 1154 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF 1155 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF 1156 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0 1157 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000 1158 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16 1159 1160 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070 1161 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF 1162 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF 1163 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0 1164 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000 1165 1166 #define WAVE1_PHYCLK 0x801C 1167 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F 1168 #define WAVE1_PHYCLK_USEC_LSB 0 1169 1170 /* qca6174 PLL offset/mask */ 1171 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114 1172 #define SOC_CORE_CLK_CTRL_DIV_LSB 0 1173 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 1174 1175 #define EFUSE_OFFSET 0x0000032c 1176 #define EFUSE_XTAL_SEL_LSB 8 1177 #define EFUSE_XTAL_SEL_MASK 0x00000700 1178 1179 #define BB_PLL_CONFIG_OFFSET 0x000002f4 1180 #define BB_PLL_CONFIG_FRAC_LSB 0 1181 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff 1182 #define BB_PLL_CONFIG_OUTDIV_LSB 18 1183 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 1184 1185 #define WLAN_PLL_SETTLE_OFFSET 0x0018 1186 #define WLAN_PLL_SETTLE_TIME_LSB 0 1187 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff 1188 1189 #define WLAN_PLL_CONTROL_OFFSET 0x0014 1190 #define WLAN_PLL_CONTROL_DIV_LSB 0 1191 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff 1192 #define WLAN_PLL_CONTROL_REFDIV_LSB 10 1193 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 1194 #define WLAN_PLL_CONTROL_BYPASS_LSB 16 1195 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 1196 #define WLAN_PLL_CONTROL_NOPWD_LSB 18 1197 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 1198 1199 #define RTC_SYNC_STATUS_OFFSET 0x0244 1200 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 1201 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 1202 /* qca6174 PLL offset/mask end */ 1203 1204 /* CPU_ADDR_MSB is a register, bit[3:0] is to specify which memory 1205 * region is accessed. The memory region size is 1M. 1206 * If host wants to access 0xX12345 at target, then CPU_ADDR_MSB[3:0] 1207 * is 0xX. 1208 * The following MACROs are defined to get the 0xX and the size limit. 1209 */ 1210 #define CPU_ADDR_MSB_REGION_MASK GENMASK(23, 20) 1211 #define CPU_ADDR_MSB_REGION_VAL(X) FIELD_GET(CPU_ADDR_MSB_REGION_MASK, X) 1212 #define REGION_ACCESS_SIZE_LIMIT 0x100000 1213 #define REGION_ACCESS_SIZE_MASK (REGION_ACCESS_SIZE_LIMIT - 1) 1214 1215 #endif /* _HW_H_ */ 1216