1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HW_H_ 20 #define _HW_H_ 21 22 #include "targaddrs.h" 23 24 enum ath10k_bus { 25 ATH10K_BUS_PCI, 26 ATH10K_BUS_AHB, 27 ATH10K_BUS_SDIO, 28 ATH10K_BUS_USB, 29 ATH10K_BUS_SNOC, 30 }; 31 32 #define ATH10K_FW_DIR "ath10k" 33 34 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac) 35 #define QCA988X_2_0_DEVICE_ID (0x003c) 36 #define QCA6164_2_1_DEVICE_ID (0x0041) 37 #define QCA6174_2_1_DEVICE_ID (0x003e) 38 #define QCA99X0_2_0_DEVICE_ID (0x0040) 39 #define QCA9888_2_0_DEVICE_ID (0x0056) 40 #define QCA9984_1_0_DEVICE_ID (0x0046) 41 #define QCA9377_1_0_DEVICE_ID (0x0042) 42 #define QCA9887_1_0_DEVICE_ID (0x0050) 43 44 /* QCA988X 1.0 definitions (unsupported) */ 45 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 46 47 /* QCA988X 2.0 definitions */ 48 #define QCA988X_HW_2_0_VERSION 0x4100016c 49 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 50 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 51 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 52 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 53 54 /* QCA9887 1.0 definitions */ 55 #define QCA9887_HW_1_0_VERSION 0x4100016d 56 #define QCA9887_HW_1_0_CHIP_ID_REV 0 57 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 58 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" 59 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 60 61 /* QCA6174 target BMI version signatures */ 62 #define QCA6174_HW_1_0_VERSION 0x05000000 63 #define QCA6174_HW_1_1_VERSION 0x05000001 64 #define QCA6174_HW_1_3_VERSION 0x05000003 65 #define QCA6174_HW_2_1_VERSION 0x05010000 66 #define QCA6174_HW_3_0_VERSION 0x05020000 67 #define QCA6174_HW_3_2_VERSION 0x05030000 68 69 /* QCA9377 target BMI version signatures */ 70 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 71 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 72 73 enum qca6174_pci_rev { 74 QCA6174_PCI_REV_1_1 = 0x11, 75 QCA6174_PCI_REV_1_3 = 0x13, 76 QCA6174_PCI_REV_2_0 = 0x20, 77 QCA6174_PCI_REV_3_0 = 0x30, 78 }; 79 80 enum qca6174_chip_id_rev { 81 QCA6174_HW_1_0_CHIP_ID_REV = 0, 82 QCA6174_HW_1_1_CHIP_ID_REV = 1, 83 QCA6174_HW_1_3_CHIP_ID_REV = 2, 84 QCA6174_HW_2_1_CHIP_ID_REV = 4, 85 QCA6174_HW_2_2_CHIP_ID_REV = 5, 86 QCA6174_HW_3_0_CHIP_ID_REV = 8, 87 QCA6174_HW_3_1_CHIP_ID_REV = 9, 88 QCA6174_HW_3_2_CHIP_ID_REV = 10, 89 }; 90 91 enum qca9377_chip_id_rev { 92 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 93 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 94 }; 95 96 #define QCA6174_HW_2_1_FW_DIR ATH10K_FW_DIR "/QCA6174/hw2.1" 97 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 98 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 99 100 #define QCA6174_HW_3_0_FW_DIR ATH10K_FW_DIR "/QCA6174/hw3.0" 101 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 102 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 103 104 /* QCA99X0 1.0 definitions (unsupported) */ 105 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 106 107 /* QCA99X0 2.0 definitions */ 108 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 109 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 110 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 111 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 112 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 113 114 /* QCA9984 1.0 defines */ 115 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 116 #define QCA9984_HW_DEV_TYPE 0xa 117 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 118 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 119 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" 120 #define QCA9984_HW_1_0_EBOARD_DATA_FILE "eboard.bin" 121 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 122 123 /* QCA9888 2.0 defines */ 124 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 125 #define QCA9888_HW_DEV_TYPE 0xc 126 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 127 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 128 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" 129 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 130 131 /* QCA9377 1.0 definitions */ 132 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 133 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 134 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 135 136 /* QCA4019 1.0 definitions */ 137 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 138 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 139 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" 140 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 141 142 /* WCN3990 1.0 definitions */ 143 #define WCN3990_HW_1_0_DEV_VERSION ATH10K_HW_WCN3990 144 #define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw1.0" 145 146 #define ATH10K_FW_FILE_BASE "firmware" 147 #define ATH10K_FW_API_MAX 6 148 #define ATH10K_FW_API_MIN 2 149 150 #define ATH10K_FW_API2_FILE "firmware-2.bin" 151 #define ATH10K_FW_API3_FILE "firmware-3.bin" 152 153 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 154 #define ATH10K_FW_API4_FILE "firmware-4.bin" 155 156 /* HTT id conflict fix for management frames over HTT */ 157 #define ATH10K_FW_API5_FILE "firmware-5.bin" 158 159 /* the firmware-6.bin blob */ 160 #define ATH10K_FW_API6_FILE "firmware-6.bin" 161 162 #define ATH10K_FW_UTF_FILE "utf.bin" 163 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 164 165 /* includes also the null byte */ 166 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 167 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 168 169 #define ATH10K_BOARD_API2_FILE "board-2.bin" 170 171 #define REG_DUMP_COUNT_QCA988X 60 172 173 struct ath10k_fw_ie { 174 __le32 id; 175 __le32 len; 176 u8 data[0]; 177 }; 178 179 enum ath10k_fw_ie_type { 180 ATH10K_FW_IE_FW_VERSION = 0, 181 ATH10K_FW_IE_TIMESTAMP = 1, 182 ATH10K_FW_IE_FEATURES = 2, 183 ATH10K_FW_IE_FW_IMAGE = 3, 184 ATH10K_FW_IE_OTP_IMAGE = 4, 185 186 /* WMI "operations" interface version, 32 bit value. Supported from 187 * FW API 4 and above. 188 */ 189 ATH10K_FW_IE_WMI_OP_VERSION = 5, 190 191 /* HTT "operations" interface version, 32 bit value. Supported from 192 * FW API 5 and above. 193 */ 194 ATH10K_FW_IE_HTT_OP_VERSION = 6, 195 196 /* Code swap image for firmware binary */ 197 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 198 }; 199 200 enum ath10k_fw_wmi_op_version { 201 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 202 203 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 204 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 205 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 206 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 207 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 208 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 209 210 /* keep last */ 211 ATH10K_FW_WMI_OP_VERSION_MAX, 212 }; 213 214 enum ath10k_fw_htt_op_version { 215 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 216 217 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 218 219 /* also used in 10.2 and 10.2.4 branches */ 220 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 221 222 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 223 224 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 225 226 /* keep last */ 227 ATH10K_FW_HTT_OP_VERSION_MAX, 228 }; 229 230 enum ath10k_bd_ie_type { 231 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 232 ATH10K_BD_IE_BOARD = 0, 233 ATH10K_BD_IE_BOARD_EXT = 1, 234 }; 235 236 enum ath10k_bd_ie_board_type { 237 ATH10K_BD_IE_BOARD_NAME = 0, 238 ATH10K_BD_IE_BOARD_DATA = 1, 239 }; 240 241 enum ath10k_hw_rev { 242 ATH10K_HW_QCA988X, 243 ATH10K_HW_QCA6174, 244 ATH10K_HW_QCA99X0, 245 ATH10K_HW_QCA9888, 246 ATH10K_HW_QCA9984, 247 ATH10K_HW_QCA9377, 248 ATH10K_HW_QCA4019, 249 ATH10K_HW_QCA9887, 250 ATH10K_HW_WCN3990, 251 }; 252 253 struct ath10k_hw_regs { 254 u32 rtc_soc_base_address; 255 u32 rtc_wmac_base_address; 256 u32 soc_core_base_address; 257 u32 wlan_mac_base_address; 258 u32 ce_wrapper_base_address; 259 u32 ce0_base_address; 260 u32 ce1_base_address; 261 u32 ce2_base_address; 262 u32 ce3_base_address; 263 u32 ce4_base_address; 264 u32 ce5_base_address; 265 u32 ce6_base_address; 266 u32 ce7_base_address; 267 u32 ce8_base_address; 268 u32 ce9_base_address; 269 u32 ce10_base_address; 270 u32 ce11_base_address; 271 u32 soc_reset_control_si0_rst_mask; 272 u32 soc_reset_control_ce_rst_mask; 273 u32 soc_chip_id_address; 274 u32 scratch_3_address; 275 u32 fw_indicator_address; 276 u32 pcie_local_base_address; 277 u32 ce_wrap_intr_sum_host_msi_lsb; 278 u32 ce_wrap_intr_sum_host_msi_mask; 279 u32 pcie_intr_fw_mask; 280 u32 pcie_intr_ce_mask_all; 281 u32 pcie_intr_clr_address; 282 u32 cpu_pll_init_address; 283 u32 cpu_speed_address; 284 u32 core_clk_div_address; 285 }; 286 287 extern const struct ath10k_hw_regs qca988x_regs; 288 extern const struct ath10k_hw_regs qca6174_regs; 289 extern const struct ath10k_hw_regs qca99x0_regs; 290 extern const struct ath10k_hw_regs qca4019_regs; 291 extern const struct ath10k_hw_regs wcn3990_regs; 292 293 struct ath10k_hw_ce_regs_addr_map { 294 u32 msb; 295 u32 lsb; 296 u32 mask; 297 }; 298 299 struct ath10k_hw_ce_ctrl1 { 300 u32 addr; 301 u32 hw_mask; 302 u32 sw_mask; 303 u32 hw_wr_mask; 304 u32 sw_wr_mask; 305 u32 reset_mask; 306 u32 reset; 307 struct ath10k_hw_ce_regs_addr_map *src_ring; 308 struct ath10k_hw_ce_regs_addr_map *dst_ring; 309 struct ath10k_hw_ce_regs_addr_map *dmax; }; 310 311 struct ath10k_hw_ce_cmd_halt { 312 u32 status_reset; 313 u32 msb; 314 u32 mask; 315 struct ath10k_hw_ce_regs_addr_map *status; }; 316 317 struct ath10k_hw_ce_host_ie { 318 u32 copy_complete_reset; 319 struct ath10k_hw_ce_regs_addr_map *copy_complete; }; 320 321 struct ath10k_hw_ce_host_wm_regs { 322 u32 dstr_lmask; 323 u32 dstr_hmask; 324 u32 srcr_lmask; 325 u32 srcr_hmask; 326 u32 cc_mask; 327 u32 wm_mask; 328 u32 addr; 329 }; 330 331 struct ath10k_hw_ce_misc_regs { 332 u32 axi_err; 333 u32 dstr_add_err; 334 u32 srcr_len_err; 335 u32 dstr_mlen_vio; 336 u32 dstr_overflow; 337 u32 srcr_overflow; 338 u32 err_mask; 339 u32 addr; 340 }; 341 342 struct ath10k_hw_ce_dst_src_wm_regs { 343 u32 addr; 344 u32 low_rst; 345 u32 high_rst; 346 struct ath10k_hw_ce_regs_addr_map *wm_low; 347 struct ath10k_hw_ce_regs_addr_map *wm_high; }; 348 349 struct ath10k_hw_ce_ctrl1_upd { 350 u32 shift; 351 u32 mask; 352 u32 enable; 353 }; 354 355 struct ath10k_hw_ce_regs { 356 u32 sr_base_addr; 357 u32 sr_size_addr; 358 u32 dr_base_addr; 359 u32 dr_size_addr; 360 u32 ce_cmd_addr; 361 u32 misc_ie_addr; 362 u32 sr_wr_index_addr; 363 u32 dst_wr_index_addr; 364 u32 current_srri_addr; 365 u32 current_drri_addr; 366 u32 ddr_addr_for_rri_low; 367 u32 ddr_addr_for_rri_high; 368 u32 ce_rri_low; 369 u32 ce_rri_high; 370 u32 host_ie_addr; 371 struct ath10k_hw_ce_host_wm_regs *wm_regs; 372 struct ath10k_hw_ce_misc_regs *misc_regs; 373 struct ath10k_hw_ce_ctrl1 *ctrl1_regs; 374 struct ath10k_hw_ce_cmd_halt *cmd_halt; 375 struct ath10k_hw_ce_host_ie *host_ie; 376 struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr; 377 struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; 378 struct ath10k_hw_ce_ctrl1_upd *upd; 379 }; 380 381 struct ath10k_hw_values { 382 u32 rtc_state_val_on; 383 u8 ce_count; 384 u8 msi_assign_ce_max; 385 u8 num_target_ce_config_wlan; 386 u16 ce_desc_meta_data_mask; 387 u8 ce_desc_meta_data_lsb; 388 }; 389 390 extern const struct ath10k_hw_values qca988x_values; 391 extern const struct ath10k_hw_values qca6174_values; 392 extern const struct ath10k_hw_values qca99x0_values; 393 extern const struct ath10k_hw_values qca9888_values; 394 extern const struct ath10k_hw_values qca4019_values; 395 extern const struct ath10k_hw_values wcn3990_values; 396 extern const struct ath10k_hw_ce_regs wcn3990_ce_regs; 397 extern const struct ath10k_hw_ce_regs qcax_ce_regs; 398 399 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 400 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 401 402 int ath10k_hw_diag_fast_download(struct ath10k *ar, 403 u32 address, 404 const void *buffer, 405 u32 length); 406 407 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 408 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 409 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 410 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 411 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 412 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 413 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 414 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 415 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990) 416 417 /* Known peculiarities: 418 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 419 * - raw have FCS, nwifi doesn't 420 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 421 * param, llc/snap) are aligned to 4byte boundaries each 422 */ 423 enum ath10k_hw_txrx_mode { 424 ATH10K_HW_TXRX_RAW = 0, 425 426 /* Native Wifi decap mode is used to align IP frames to 4-byte 427 * boundaries and avoid a very expensive re-alignment in mac80211. 428 */ 429 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 430 ATH10K_HW_TXRX_ETHERNET = 2, 431 432 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 433 ATH10K_HW_TXRX_MGMT = 3, 434 }; 435 436 enum ath10k_mcast2ucast_mode { 437 ATH10K_MCAST2UCAST_DISABLED = 0, 438 ATH10K_MCAST2UCAST_ENABLED = 1, 439 }; 440 441 enum ath10k_hw_rate_ofdm { 442 ATH10K_HW_RATE_OFDM_48M = 0, 443 ATH10K_HW_RATE_OFDM_24M, 444 ATH10K_HW_RATE_OFDM_12M, 445 ATH10K_HW_RATE_OFDM_6M, 446 ATH10K_HW_RATE_OFDM_54M, 447 ATH10K_HW_RATE_OFDM_36M, 448 ATH10K_HW_RATE_OFDM_18M, 449 ATH10K_HW_RATE_OFDM_9M, 450 }; 451 452 enum ath10k_hw_rate_cck { 453 ATH10K_HW_RATE_CCK_LP_11M = 0, 454 ATH10K_HW_RATE_CCK_LP_5_5M, 455 ATH10K_HW_RATE_CCK_LP_2M, 456 ATH10K_HW_RATE_CCK_LP_1M, 457 ATH10K_HW_RATE_CCK_SP_11M, 458 ATH10K_HW_RATE_CCK_SP_5_5M, 459 ATH10K_HW_RATE_CCK_SP_2M, 460 }; 461 462 enum ath10k_hw_rate_rev2_cck { 463 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 464 ATH10K_HW_RATE_REV2_CCK_LP_2M, 465 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 466 ATH10K_HW_RATE_REV2_CCK_LP_11M, 467 ATH10K_HW_RATE_REV2_CCK_SP_2M, 468 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 469 ATH10K_HW_RATE_REV2_CCK_SP_11M, 470 }; 471 472 enum ath10k_hw_cc_wraparound_type { 473 ATH10K_HW_CC_WRAP_DISABLED = 0, 474 475 /* This type is when the HW chip has a quirky Cycle Counter 476 * wraparound which resets to 0x7fffffff instead of 0. All 477 * other CC related counters (e.g. Rx Clear Count) are divided 478 * by 2 so they never wraparound themselves. 479 */ 480 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 481 482 /* Each hw counter wrapsaround independently. When the 483 * counter overflows the repestive counter is right shifted 484 * by 1, i.e reset to 0x7fffffff, and other counters will be 485 * running unaffected. In this type of wraparound, it should 486 * be possible to report accurate Rx busy time unlike the 487 * first type. 488 */ 489 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 490 }; 491 492 enum ath10k_hw_refclk_speed { 493 ATH10K_HW_REFCLK_UNKNOWN = -1, 494 ATH10K_HW_REFCLK_48_MHZ = 0, 495 ATH10K_HW_REFCLK_19_2_MHZ = 1, 496 ATH10K_HW_REFCLK_24_MHZ = 2, 497 ATH10K_HW_REFCLK_26_MHZ = 3, 498 ATH10K_HW_REFCLK_37_4_MHZ = 4, 499 ATH10K_HW_REFCLK_38_4_MHZ = 5, 500 ATH10K_HW_REFCLK_40_MHZ = 6, 501 ATH10K_HW_REFCLK_52_MHZ = 7, 502 503 /* must be the last one */ 504 ATH10K_HW_REFCLK_COUNT, 505 }; 506 507 struct ath10k_hw_clk_params { 508 u32 refclk; 509 u32 div; 510 u32 rnfrac; 511 u32 settle_time; 512 u32 refdiv; 513 u32 outdiv; 514 }; 515 516 struct ath10k_hw_params { 517 u32 id; 518 u16 dev_id; 519 enum ath10k_bus bus; 520 const char *name; 521 u32 patch_load_addr; 522 int uart_pin; 523 u32 otp_exe_param; 524 525 /* Type of hw cycle counter wraparound logic, for more info 526 * refer enum ath10k_hw_cc_wraparound_type. 527 */ 528 enum ath10k_hw_cc_wraparound_type cc_wraparound_type; 529 530 /* Some of chip expects fragment descriptor to be continuous 531 * memory for any TX operation. Set continuous_frag_desc flag 532 * for the hardware which have such requirement. 533 */ 534 bool continuous_frag_desc; 535 536 /* CCK hardware rate table mapping for the newer chipsets 537 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values 538 * are in a proper order with respect to the rate/preamble 539 */ 540 bool cck_rate_map_rev2; 541 542 u32 channel_counters_freq_hz; 543 544 /* Mgmt tx descriptors threshold for limiting probe response 545 * frames. 546 */ 547 u32 max_probe_resp_desc_thres; 548 549 u32 tx_chain_mask; 550 u32 rx_chain_mask; 551 u32 max_spatial_stream; 552 u32 cal_data_len; 553 554 struct ath10k_hw_params_fw { 555 const char *dir; 556 const char *board; 557 size_t board_size; 558 const char *eboard; 559 size_t ext_board_size; 560 size_t board_ext_size; 561 } fw; 562 563 /* qca99x0 family chips deliver broadcast/multicast management 564 * frames encrypted and expect software do decryption. 565 */ 566 bool sw_decrypt_mcast_mgmt; 567 568 const struct ath10k_hw_ops *hw_ops; 569 570 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ 571 int decap_align_bytes; 572 573 /* hw specific clock control parameters */ 574 const struct ath10k_hw_clk_params *hw_clk; 575 int target_cpu_freq; 576 577 /* Number of bytes to be discarded for each FFT sample */ 578 int spectral_bin_discard; 579 580 /* The board may have a restricted NSS for 160 or 80+80 vs what it 581 * can do for 80Mhz. 582 */ 583 int vht160_mcs_rx_highest; 584 int vht160_mcs_tx_highest; 585 586 /* Number of ciphers supported (i.e First N) in cipher_suites array */ 587 int n_cipher_suites; 588 589 u32 num_peers; 590 u32 ast_skid_limit; 591 u32 num_wds_entries; 592 593 /* Targets supporting physical addressing capability above 32-bits */ 594 bool target_64bit; 595 596 /* Target rx ring fill level */ 597 u32 rx_ring_fill_level; 598 599 /* target supporting per ce IRQ */ 600 bool per_ce_irq; 601 602 /* target supporting shadow register for ce write */ 603 bool shadow_reg_support; 604 605 /* target supporting retention restore on ddr */ 606 bool rri_on_ddr; 607 608 /* Number of bytes to be the offset for each FFT sample */ 609 int spectral_bin_offset; 610 611 /* targets which require hw filter reset during boot up, 612 * to avoid it sending spurious acks. 613 */ 614 bool hw_filter_reset_required; 615 616 /* target supporting fw download via diag ce */ 617 bool fw_diag_ce_download; 618 }; 619 620 struct htt_rx_desc; 621 622 /* Defines needed for Rx descriptor abstraction */ 623 struct ath10k_hw_ops { 624 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 625 void (*set_coverage_class)(struct ath10k *ar, s16 value); 626 int (*enable_pll_clk)(struct ath10k *ar); 627 }; 628 629 extern const struct ath10k_hw_ops qca988x_ops; 630 extern const struct ath10k_hw_ops qca99x0_ops; 631 extern const struct ath10k_hw_ops qca6174_ops; 632 extern const struct ath10k_hw_ops wcn3990_ops; 633 634 extern const struct ath10k_hw_clk_params qca6174_clk[]; 635 636 static inline int 637 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, 638 struct htt_rx_desc *rxd) 639 { 640 if (hw->hw_ops->rx_desc_get_l3_pad_bytes) 641 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd); 642 return 0; 643 } 644 645 /* Target specific defines for MAIN firmware */ 646 #define TARGET_NUM_VDEVS 8 647 #define TARGET_NUM_PEER_AST 2 648 #define TARGET_NUM_WDS_ENTRIES 32 649 #define TARGET_DMA_BURST_SIZE 0 650 #define TARGET_MAC_AGGR_DELIM 0 651 #define TARGET_AST_SKID_LIMIT 16 652 #define TARGET_NUM_STATIONS 16 653 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 654 (TARGET_NUM_VDEVS)) 655 #define TARGET_NUM_OFFLOAD_PEERS 0 656 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 657 #define TARGET_NUM_PEER_KEYS 2 658 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 659 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 660 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 661 #define TARGET_RX_TIMEOUT_LO_PRI 100 662 #define TARGET_RX_TIMEOUT_HI_PRI 40 663 664 #define TARGET_SCAN_MAX_PENDING_REQS 4 665 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 666 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 667 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 668 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 669 #define TARGET_NUM_MCAST_GROUPS 0 670 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 671 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 672 #define TARGET_TX_DBG_LOG_SIZE 1024 673 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 674 #define TARGET_VOW_CONFIG 0 675 #define TARGET_NUM_MSDU_DESC (1024 + 400) 676 #define TARGET_MAX_FRAG_ENTRIES 0 677 678 /* Target specific defines for 10.X firmware */ 679 #define TARGET_10X_NUM_VDEVS 16 680 #define TARGET_10X_NUM_PEER_AST 2 681 #define TARGET_10X_NUM_WDS_ENTRIES 32 682 #define TARGET_10X_DMA_BURST_SIZE 0 683 #define TARGET_10X_MAC_AGGR_DELIM 0 684 #define TARGET_10X_AST_SKID_LIMIT 128 685 #define TARGET_10X_NUM_STATIONS 128 686 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 687 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 688 (TARGET_10X_NUM_VDEVS)) 689 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 690 (TARGET_10X_NUM_VDEVS)) 691 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 692 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 693 #define TARGET_10X_NUM_PEER_KEYS 2 694 #define TARGET_10X_NUM_TIDS_MAX 256 695 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 696 (TARGET_10X_NUM_PEERS) * 2) 697 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 698 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 699 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 700 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 701 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 702 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 703 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 704 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 705 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 706 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 707 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 708 #define TARGET_10X_NUM_MCAST_GROUPS 0 709 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 710 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 711 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 712 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 713 #define TARGET_10X_VOW_CONFIG 0 714 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 715 #define TARGET_10X_MAX_FRAG_ENTRIES 0 716 717 /* 10.2 parameters */ 718 #define TARGET_10_2_DMA_BURST_SIZE 0 719 720 /* Target specific defines for WMI-TLV firmware */ 721 #define TARGET_TLV_NUM_VDEVS 4 722 #define TARGET_TLV_NUM_STATIONS 32 723 #define TARGET_TLV_NUM_PEERS 33 724 #define TARGET_TLV_NUM_TDLS_VDEVS 1 725 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 726 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 727 #define TARGET_TLV_NUM_WOW_PATTERNS 22 728 #define TARGET_TLV_MGMT_NUM_MSDU_DESC (50) 729 730 /* Target specific defines for WMI-HL-1.0 firmware */ 731 #define TARGET_HL_10_TLV_NUM_PEERS 14 732 #define TARGET_HL_10_TLV_AST_SKID_LIMIT 6 733 #define TARGET_HL_10_TLV_NUM_WDS_ENTRIES 2 734 735 /* Diagnostic Window */ 736 #define CE_DIAG_PIPE 7 737 738 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 739 740 /* Target specific defines for 10.4 firmware */ 741 #define TARGET_10_4_NUM_VDEVS 16 742 #define TARGET_10_4_NUM_STATIONS 32 743 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 744 (TARGET_10_4_NUM_VDEVS)) 745 #define TARGET_10_4_ACTIVE_PEERS 0 746 747 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 748 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 749 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 750 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 751 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 752 #define TARGET_10_4_NUM_PEER_KEYS 2 753 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 754 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 755 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 756 #define TARGET_10_4_AST_SKID_LIMIT 32 757 758 /* 100 ms for video, best-effort, and background */ 759 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 760 761 /* 40 ms for voice */ 762 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 763 764 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 765 #define TARGET_10_4_SCAN_MAX_REQS 4 766 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 767 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 768 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 769 770 /* Note: mcast to ucast is disabled by default */ 771 #define TARGET_10_4_NUM_MCAST_GROUPS 0 772 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 773 #define TARGET_10_4_MCAST2UCAST_MODE 0 774 775 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 776 #define TARGET_10_4_NUM_WDS_ENTRIES 32 777 #define TARGET_10_4_DMA_BURST_SIZE 0 778 #define TARGET_10_4_MAC_AGGR_DELIM 0 779 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 780 #define TARGET_10_4_VOW_CONFIG 0 781 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 782 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 783 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 784 #define TARGET_10_4_SMART_ANT_CAP 0 785 #define TARGET_10_4_BK_MIN_FREE 0 786 #define TARGET_10_4_BE_MIN_FREE 0 787 #define TARGET_10_4_VI_MIN_FREE 0 788 #define TARGET_10_4_VO_MIN_FREE 0 789 #define TARGET_10_4_RX_BATCH_MODE 1 790 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 791 #define TARGET_10_4_ATF_CONFIG 0 792 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 793 #define TARGET_10_4_QWRAP_CONFIG 0 794 795 /* TDLS config */ 796 #define TARGET_10_4_NUM_TDLS_VDEVS 1 797 #define TARGET_10_4_NUM_TDLS_BUFFER_STA 1 798 #define TARGET_10_4_NUM_TDLS_SLEEP_STA 1 799 800 /* Maximum number of Copy Engine's supported */ 801 #define CE_COUNT_MAX 12 802 803 /* Number of Copy Engines supported */ 804 #define CE_COUNT ar->hw_values->ce_count 805 806 /* 807 * Granted MSIs are assigned as follows: 808 * Firmware uses the first 809 * Remaining MSIs, if any, are used by Copy Engines 810 * This mapping is known to both Target firmware and Host software. 811 * It may be changed as long as Host and Target are kept in sync. 812 */ 813 /* MSI for firmware (errors, etc.) */ 814 #define MSI_ASSIGN_FW 0 815 816 /* MSIs for Copy Engines */ 817 #define MSI_ASSIGN_CE_INITIAL 1 818 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 819 820 /* as of IP3.7.1 */ 821 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 822 823 #define RTC_STATE_V_LSB 0 824 #define RTC_STATE_V_MASK 0x00000007 825 #define RTC_STATE_ADDRESS 0x0000 826 #define PCIE_SOC_WAKE_V_MASK 0x00000001 827 #define PCIE_SOC_WAKE_ADDRESS 0x0004 828 #define PCIE_SOC_WAKE_RESET 0x00000000 829 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 830 831 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 832 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 833 #define MAC_COEX_BASE_ADDRESS 0x00006000 834 #define BT_COEX_BASE_ADDRESS 0x00007000 835 #define SOC_PCIE_BASE_ADDRESS 0x00008000 836 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 837 #define WLAN_UART_BASE_ADDRESS 0x0000c000 838 #define WLAN_SI_BASE_ADDRESS 0x00010000 839 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 840 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 841 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address 842 #define EFUSE_BASE_ADDRESS 0x00030000 843 #define FPGA_REG_BASE_ADDRESS 0x00039000 844 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 845 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 846 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 847 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 848 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 849 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 850 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 851 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 852 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 853 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 854 #define DBI_BASE_ADDRESS 0x00060000 855 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 856 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 857 858 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 859 #define SOC_RESET_CONTROL_OFFSET 0x00000000 860 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 861 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 862 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 863 #define SOC_CPU_CLOCK_OFFSET 0x00000020 864 #define SOC_CPU_CLOCK_STANDARD_LSB 0 865 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 866 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 867 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 868 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 869 #define SOC_LPO_CAL_OFFSET 0x000000e0 870 #define SOC_LPO_CAL_ENABLE_LSB 20 871 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 872 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 873 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 874 875 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 876 #define SOC_CHIP_ID_REV_LSB 8 877 #define SOC_CHIP_ID_REV_MASK 0x00000f00 878 879 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 880 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 881 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 882 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 883 884 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 885 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 886 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 887 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 888 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 889 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 890 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 891 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 892 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 893 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 894 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 895 896 #define CLOCK_GPIO_OFFSET 0xffffffff 897 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 898 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 899 900 #define SI_CONFIG_OFFSET 0x00000000 901 #define SI_CONFIG_ERR_INT_LSB 19 902 #define SI_CONFIG_ERR_INT_MASK 0x00080000 903 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 904 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 905 #define SI_CONFIG_I2C_LSB 16 906 #define SI_CONFIG_I2C_MASK 0x00010000 907 #define SI_CONFIG_POS_SAMPLE_LSB 7 908 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 909 #define SI_CONFIG_INACTIVE_DATA_LSB 5 910 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 911 #define SI_CONFIG_INACTIVE_CLK_LSB 4 912 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 913 #define SI_CONFIG_DIVIDER_LSB 0 914 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 915 #define SI_CS_OFFSET 0x00000004 916 #define SI_CS_DONE_ERR_LSB 10 917 #define SI_CS_DONE_ERR_MASK 0x00000400 918 #define SI_CS_DONE_INT_LSB 9 919 #define SI_CS_DONE_INT_MASK 0x00000200 920 #define SI_CS_START_LSB 8 921 #define SI_CS_START_MASK 0x00000100 922 #define SI_CS_RX_CNT_LSB 4 923 #define SI_CS_RX_CNT_MASK 0x000000f0 924 #define SI_CS_TX_CNT_LSB 0 925 #define SI_CS_TX_CNT_MASK 0x0000000f 926 927 #define SI_TX_DATA0_OFFSET 0x00000008 928 #define SI_TX_DATA1_OFFSET 0x0000000c 929 #define SI_RX_DATA0_OFFSET 0x00000010 930 #define SI_RX_DATA1_OFFSET 0x00000014 931 932 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 933 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 934 #define CORE_CTRL_ADDRESS 0x0000 935 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 936 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 937 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 938 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 939 #define CPU_INTR_ADDRESS 0x0010 940 #define FW_RAM_CONFIG_ADDRESS 0x0018 941 942 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 943 944 /* Firmware indications to the Host via SCRATCH_3 register. */ 945 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 946 #define FW_IND_EVENT_PENDING 1 947 #define FW_IND_INITIALIZED 2 948 #define FW_IND_HOST_READY 0x80000000 949 950 /* HOST_REG interrupt from firmware */ 951 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 952 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 953 954 #define DRAM_BASE_ADDRESS 0x00400000 955 956 #define PCIE_BAR_REG_ADDRESS 0x40030 957 958 #define MISSING 0 959 960 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 961 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 962 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 963 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 964 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 965 #define RESET_CONTROL_MBOX_RST_MASK MISSING 966 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 967 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 968 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 969 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 970 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 971 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 972 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 973 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 974 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 975 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 976 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 977 #define LOCAL_SCRATCH_OFFSET 0x18 978 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 979 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 980 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 981 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 982 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 983 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 984 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 985 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 986 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 987 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 988 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 989 #define MBOX_BASE_ADDRESS MISSING 990 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 991 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 992 #define INT_STATUS_ENABLE_CPU_LSB MISSING 993 #define INT_STATUS_ENABLE_CPU_MASK MISSING 994 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 995 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 996 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 997 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 998 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 999 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 1000 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 1001 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 1002 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 1003 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 1004 #define INT_STATUS_ENABLE_ADDRESS MISSING 1005 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 1006 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 1007 #define HOST_INT_STATUS_ADDRESS MISSING 1008 #define CPU_INT_STATUS_ADDRESS MISSING 1009 #define ERROR_INT_STATUS_ADDRESS MISSING 1010 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 1011 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 1012 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 1013 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 1014 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 1015 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 1016 #define COUNT_DEC_ADDRESS MISSING 1017 #define HOST_INT_STATUS_CPU_MASK MISSING 1018 #define HOST_INT_STATUS_CPU_LSB MISSING 1019 #define HOST_INT_STATUS_ERROR_MASK MISSING 1020 #define HOST_INT_STATUS_ERROR_LSB MISSING 1021 #define HOST_INT_STATUS_COUNTER_MASK MISSING 1022 #define HOST_INT_STATUS_COUNTER_LSB MISSING 1023 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 1024 #define WINDOW_DATA_ADDRESS MISSING 1025 #define WINDOW_READ_ADDR_ADDRESS MISSING 1026 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 1027 1028 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 1029 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 1030 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 1031 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 1032 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 1033 1034 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 1035 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 1036 #define QCA9887_EEPROM_ADDR_HI_LSB 8 1037 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 1038 #define QCA9887_EEPROM_ADDR_LO_LSB 16 1039 1040 #define MBOX_RESET_CONTROL_ADDRESS 0x00000000 1041 #define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800 1042 #define MBOX_HOST_INT_STATUS_ERROR_LSB 7 1043 #define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080 1044 #define MBOX_HOST_INT_STATUS_CPU_LSB 6 1045 #define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040 1046 #define MBOX_HOST_INT_STATUS_COUNTER_LSB 4 1047 #define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010 1048 #define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801 1049 #define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802 1050 #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB 2 1051 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 1052 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 1053 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 1054 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 1055 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 1056 #define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803 1057 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0 1058 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff 1059 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805 1060 #define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828 1061 #define MBOX_INT_STATUS_ENABLE_ERROR_LSB 7 1062 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080 1063 #define MBOX_INT_STATUS_ENABLE_CPU_LSB 6 1064 #define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040 1065 #define MBOX_INT_STATUS_ENABLE_INT_LSB 5 1066 #define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020 1067 #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB 4 1068 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 1069 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0 1070 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f 1071 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819 1072 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0 1073 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1074 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a 1075 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 1076 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 1077 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 1078 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 1079 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b 1080 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 1081 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1082 #define MBOX_COUNT_ADDRESS 0x00000820 1083 #define MBOX_COUNT_DEC_ADDRESS 0x00000840 1084 #define MBOX_WINDOW_DATA_ADDRESS 0x00000874 1085 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878 1086 #define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c 1087 #define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883 1088 #define MBOX_CPU_DBG_ADDRESS 0x00000884 1089 #define MBOX_RTC_BASE_ADDRESS 0x00000000 1090 #define MBOX_GPIO_BASE_ADDRESS 0x00005000 1091 #define MBOX_MBOX_BASE_ADDRESS 0x00008000 1092 1093 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 1094 1095 /* Register definitions for first generation ath10k cards. These cards include 1096 * a mac thich has a register allocation similar to ath9k and at least some 1097 * registers including the ones relevant for modifying the coverage class are 1098 * identical to the ath9k definitions. 1099 * These registers are usually managed by the ath10k firmware. However by 1100 * overriding them it is possible to support coverage class modifications. 1101 */ 1102 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014 1103 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF 1104 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF 1105 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0 1106 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000 1107 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16 1108 1109 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070 1110 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF 1111 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF 1112 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0 1113 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000 1114 1115 #define WAVE1_PHYCLK 0x801C 1116 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F 1117 #define WAVE1_PHYCLK_USEC_LSB 0 1118 1119 /* qca6174 PLL offset/mask */ 1120 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114 1121 #define SOC_CORE_CLK_CTRL_DIV_LSB 0 1122 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 1123 1124 #define EFUSE_OFFSET 0x0000032c 1125 #define EFUSE_XTAL_SEL_LSB 8 1126 #define EFUSE_XTAL_SEL_MASK 0x00000700 1127 1128 #define BB_PLL_CONFIG_OFFSET 0x000002f4 1129 #define BB_PLL_CONFIG_FRAC_LSB 0 1130 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff 1131 #define BB_PLL_CONFIG_OUTDIV_LSB 18 1132 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 1133 1134 #define WLAN_PLL_SETTLE_OFFSET 0x0018 1135 #define WLAN_PLL_SETTLE_TIME_LSB 0 1136 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff 1137 1138 #define WLAN_PLL_CONTROL_OFFSET 0x0014 1139 #define WLAN_PLL_CONTROL_DIV_LSB 0 1140 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff 1141 #define WLAN_PLL_CONTROL_REFDIV_LSB 10 1142 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 1143 #define WLAN_PLL_CONTROL_BYPASS_LSB 16 1144 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 1145 #define WLAN_PLL_CONTROL_NOPWD_LSB 18 1146 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 1147 1148 #define RTC_SYNC_STATUS_OFFSET 0x0244 1149 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 1150 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 1151 /* qca6174 PLL offset/mask end */ 1152 1153 /* CPU_ADDR_MSB is a register, bit[3:0] is to specify which memory 1154 * region is accessed. The memory region size is 1M. 1155 * If host wants to access 0xX12345 at target, then CPU_ADDR_MSB[3:0] 1156 * is 0xX. 1157 * The following MACROs are defined to get the 0xX and the size limit. 1158 */ 1159 #define CPU_ADDR_MSB_REGION_MASK GENMASK(23, 20) 1160 #define CPU_ADDR_MSB_REGION_VAL(X) FIELD_GET(CPU_ADDR_MSB_REGION_MASK, X) 1161 #define REGION_ACCESS_SIZE_LIMIT 0x100000 1162 #define REGION_ACCESS_SIZE_MASK (REGION_ACCESS_SIZE_LIMIT - 1) 1163 1164 #endif /* _HW_H_ */ 1165