1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HW_H_ 19 #define _HW_H_ 20 21 #include "targaddrs.h" 22 23 #define ATH10K_FW_DIR "ath10k" 24 25 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac) 26 #define QCA988X_2_0_DEVICE_ID (0x003c) 27 #define QCA6164_2_1_DEVICE_ID (0x0041) 28 #define QCA6174_2_1_DEVICE_ID (0x003e) 29 #define QCA99X0_2_0_DEVICE_ID (0x0040) 30 #define QCA9888_2_0_DEVICE_ID (0x0056) 31 #define QCA9984_1_0_DEVICE_ID (0x0046) 32 #define QCA9377_1_0_DEVICE_ID (0x0042) 33 #define QCA9887_1_0_DEVICE_ID (0x0050) 34 35 /* QCA988X 1.0 definitions (unsupported) */ 36 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 37 38 /* QCA988X 2.0 definitions */ 39 #define QCA988X_HW_2_0_VERSION 0x4100016c 40 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 41 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 42 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 43 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 44 45 /* QCA9887 1.0 definitions */ 46 #define QCA9887_HW_1_0_VERSION 0x4100016d 47 #define QCA9887_HW_1_0_CHIP_ID_REV 0 48 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 49 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" 50 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 51 52 /* QCA6174 target BMI version signatures */ 53 #define QCA6174_HW_1_0_VERSION 0x05000000 54 #define QCA6174_HW_1_1_VERSION 0x05000001 55 #define QCA6174_HW_1_3_VERSION 0x05000003 56 #define QCA6174_HW_2_1_VERSION 0x05010000 57 #define QCA6174_HW_3_0_VERSION 0x05020000 58 #define QCA6174_HW_3_2_VERSION 0x05030000 59 60 /* QCA9377 target BMI version signatures */ 61 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 62 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 63 64 enum qca6174_pci_rev { 65 QCA6174_PCI_REV_1_1 = 0x11, 66 QCA6174_PCI_REV_1_3 = 0x13, 67 QCA6174_PCI_REV_2_0 = 0x20, 68 QCA6174_PCI_REV_3_0 = 0x30, 69 }; 70 71 enum qca6174_chip_id_rev { 72 QCA6174_HW_1_0_CHIP_ID_REV = 0, 73 QCA6174_HW_1_1_CHIP_ID_REV = 1, 74 QCA6174_HW_1_3_CHIP_ID_REV = 2, 75 QCA6174_HW_2_1_CHIP_ID_REV = 4, 76 QCA6174_HW_2_2_CHIP_ID_REV = 5, 77 QCA6174_HW_3_0_CHIP_ID_REV = 8, 78 QCA6174_HW_3_1_CHIP_ID_REV = 9, 79 QCA6174_HW_3_2_CHIP_ID_REV = 10, 80 }; 81 82 enum qca9377_chip_id_rev { 83 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 84 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 85 }; 86 87 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" 88 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 89 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 90 91 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" 92 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 93 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 94 95 /* QCA99X0 1.0 definitions (unsupported) */ 96 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 97 98 /* QCA99X0 2.0 definitions */ 99 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 100 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 101 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 102 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 103 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 104 105 /* QCA9984 1.0 defines */ 106 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 107 #define QCA9984_HW_DEV_TYPE 0xa 108 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 109 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 110 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" 111 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 112 113 /* QCA9888 2.0 defines */ 114 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 115 #define QCA9888_HW_DEV_TYPE 0xc 116 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 117 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 118 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" 119 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 120 121 /* QCA9377 1.0 definitions */ 122 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 123 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 124 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 125 126 /* QCA4019 1.0 definitions */ 127 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 128 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 129 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" 130 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 131 132 /* WCN3990 1.0 definitions */ 133 #define WCN3990_HW_1_0_DEV_VERSION ATH10K_HW_WCN3990 134 #define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw3.0" 135 136 #define ATH10K_FW_FILE_BASE "firmware" 137 #define ATH10K_FW_API_MAX 6 138 #define ATH10K_FW_API_MIN 2 139 140 #define ATH10K_FW_API2_FILE "firmware-2.bin" 141 #define ATH10K_FW_API3_FILE "firmware-3.bin" 142 143 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 144 #define ATH10K_FW_API4_FILE "firmware-4.bin" 145 146 /* HTT id conflict fix for management frames over HTT */ 147 #define ATH10K_FW_API5_FILE "firmware-5.bin" 148 149 /* the firmware-6.bin blob */ 150 #define ATH10K_FW_API6_FILE "firmware-6.bin" 151 152 #define ATH10K_FW_UTF_FILE "utf.bin" 153 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 154 155 /* includes also the null byte */ 156 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 157 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 158 159 #define ATH10K_BOARD_API2_FILE "board-2.bin" 160 161 #define REG_DUMP_COUNT_QCA988X 60 162 163 struct ath10k_fw_ie { 164 __le32 id; 165 __le32 len; 166 u8 data[0]; 167 }; 168 169 enum ath10k_fw_ie_type { 170 ATH10K_FW_IE_FW_VERSION = 0, 171 ATH10K_FW_IE_TIMESTAMP = 1, 172 ATH10K_FW_IE_FEATURES = 2, 173 ATH10K_FW_IE_FW_IMAGE = 3, 174 ATH10K_FW_IE_OTP_IMAGE = 4, 175 176 /* WMI "operations" interface version, 32 bit value. Supported from 177 * FW API 4 and above. 178 */ 179 ATH10K_FW_IE_WMI_OP_VERSION = 5, 180 181 /* HTT "operations" interface version, 32 bit value. Supported from 182 * FW API 5 and above. 183 */ 184 ATH10K_FW_IE_HTT_OP_VERSION = 6, 185 186 /* Code swap image for firmware binary */ 187 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 188 }; 189 190 enum ath10k_fw_wmi_op_version { 191 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 192 193 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 194 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 195 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 196 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 197 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 198 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 199 200 /* keep last */ 201 ATH10K_FW_WMI_OP_VERSION_MAX, 202 }; 203 204 enum ath10k_fw_htt_op_version { 205 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 206 207 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 208 209 /* also used in 10.2 and 10.2.4 branches */ 210 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 211 212 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 213 214 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 215 216 /* keep last */ 217 ATH10K_FW_HTT_OP_VERSION_MAX, 218 }; 219 220 enum ath10k_bd_ie_type { 221 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 222 ATH10K_BD_IE_BOARD = 0, 223 }; 224 225 enum ath10k_bd_ie_board_type { 226 ATH10K_BD_IE_BOARD_NAME = 0, 227 ATH10K_BD_IE_BOARD_DATA = 1, 228 }; 229 230 enum ath10k_hw_rev { 231 ATH10K_HW_QCA988X, 232 ATH10K_HW_QCA6174, 233 ATH10K_HW_QCA99X0, 234 ATH10K_HW_QCA9888, 235 ATH10K_HW_QCA9984, 236 ATH10K_HW_QCA9377, 237 ATH10K_HW_QCA4019, 238 ATH10K_HW_QCA9887, 239 ATH10K_HW_WCN3990, 240 }; 241 242 struct ath10k_hw_regs { 243 u32 rtc_soc_base_address; 244 u32 rtc_wmac_base_address; 245 u32 soc_core_base_address; 246 u32 wlan_mac_base_address; 247 u32 ce_wrapper_base_address; 248 u32 ce0_base_address; 249 u32 ce1_base_address; 250 u32 ce2_base_address; 251 u32 ce3_base_address; 252 u32 ce4_base_address; 253 u32 ce5_base_address; 254 u32 ce6_base_address; 255 u32 ce7_base_address; 256 u32 ce8_base_address; 257 u32 ce9_base_address; 258 u32 ce10_base_address; 259 u32 ce11_base_address; 260 u32 soc_reset_control_si0_rst_mask; 261 u32 soc_reset_control_ce_rst_mask; 262 u32 soc_chip_id_address; 263 u32 scratch_3_address; 264 u32 fw_indicator_address; 265 u32 pcie_local_base_address; 266 u32 ce_wrap_intr_sum_host_msi_lsb; 267 u32 ce_wrap_intr_sum_host_msi_mask; 268 u32 pcie_intr_fw_mask; 269 u32 pcie_intr_ce_mask_all; 270 u32 pcie_intr_clr_address; 271 u32 cpu_pll_init_address; 272 u32 cpu_speed_address; 273 u32 core_clk_div_address; 274 }; 275 276 extern const struct ath10k_hw_regs qca988x_regs; 277 extern const struct ath10k_hw_regs qca6174_regs; 278 extern const struct ath10k_hw_regs qca99x0_regs; 279 extern const struct ath10k_hw_regs qca4019_regs; 280 extern const struct ath10k_hw_regs wcn3990_regs; 281 282 struct ath10k_hw_ce_regs_addr_map { 283 u32 msb; 284 u32 lsb; 285 u32 mask; 286 }; 287 288 struct ath10k_hw_ce_ctrl1 { 289 u32 addr; 290 u32 hw_mask; 291 u32 sw_mask; 292 u32 hw_wr_mask; 293 u32 sw_wr_mask; 294 u32 reset_mask; 295 u32 reset; 296 struct ath10k_hw_ce_regs_addr_map *src_ring; 297 struct ath10k_hw_ce_regs_addr_map *dst_ring; 298 struct ath10k_hw_ce_regs_addr_map *dmax; }; 299 300 struct ath10k_hw_ce_cmd_halt { 301 u32 status_reset; 302 u32 msb; 303 u32 mask; 304 struct ath10k_hw_ce_regs_addr_map *status; }; 305 306 struct ath10k_hw_ce_host_ie { 307 u32 copy_complete_reset; 308 struct ath10k_hw_ce_regs_addr_map *copy_complete; }; 309 310 struct ath10k_hw_ce_host_wm_regs { 311 u32 dstr_lmask; 312 u32 dstr_hmask; 313 u32 srcr_lmask; 314 u32 srcr_hmask; 315 u32 cc_mask; 316 u32 wm_mask; 317 u32 addr; 318 }; 319 320 struct ath10k_hw_ce_misc_regs { 321 u32 axi_err; 322 u32 dstr_add_err; 323 u32 srcr_len_err; 324 u32 dstr_mlen_vio; 325 u32 dstr_overflow; 326 u32 srcr_overflow; 327 u32 err_mask; 328 u32 addr; 329 }; 330 331 struct ath10k_hw_ce_dst_src_wm_regs { 332 u32 addr; 333 u32 low_rst; 334 u32 high_rst; 335 struct ath10k_hw_ce_regs_addr_map *wm_low; 336 struct ath10k_hw_ce_regs_addr_map *wm_high; }; 337 338 struct ath10k_hw_ce_regs { 339 u32 sr_base_addr; 340 u32 sr_size_addr; 341 u32 dr_base_addr; 342 u32 dr_size_addr; 343 u32 ce_cmd_addr; 344 u32 misc_ie_addr; 345 u32 sr_wr_index_addr; 346 u32 dst_wr_index_addr; 347 u32 current_srri_addr; 348 u32 current_drri_addr; 349 u32 ddr_addr_for_rri_low; 350 u32 ddr_addr_for_rri_high; 351 u32 ce_rri_low; 352 u32 ce_rri_high; 353 u32 host_ie_addr; 354 struct ath10k_hw_ce_host_wm_regs *wm_regs; 355 struct ath10k_hw_ce_misc_regs *misc_regs; 356 struct ath10k_hw_ce_ctrl1 *ctrl1_regs; 357 struct ath10k_hw_ce_cmd_halt *cmd_halt; 358 struct ath10k_hw_ce_host_ie *host_ie; 359 struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr; 360 struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; }; 361 362 struct ath10k_hw_values { 363 u32 rtc_state_val_on; 364 u8 ce_count; 365 u8 msi_assign_ce_max; 366 u8 num_target_ce_config_wlan; 367 u16 ce_desc_meta_data_mask; 368 u8 ce_desc_meta_data_lsb; 369 }; 370 371 extern const struct ath10k_hw_values qca988x_values; 372 extern const struct ath10k_hw_values qca6174_values; 373 extern const struct ath10k_hw_values qca99x0_values; 374 extern const struct ath10k_hw_values qca9888_values; 375 extern const struct ath10k_hw_values qca4019_values; 376 extern const struct ath10k_hw_values wcn3990_values; 377 extern const struct ath10k_hw_ce_regs wcn3990_ce_regs; 378 extern const struct ath10k_hw_ce_regs qcax_ce_regs; 379 380 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 381 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 382 383 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 384 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 385 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 386 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 387 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 388 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 389 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 390 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 391 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990) 392 393 /* Known peculiarities: 394 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 395 * - raw have FCS, nwifi doesn't 396 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 397 * param, llc/snap) are aligned to 4byte boundaries each 398 */ 399 enum ath10k_hw_txrx_mode { 400 ATH10K_HW_TXRX_RAW = 0, 401 402 /* Native Wifi decap mode is used to align IP frames to 4-byte 403 * boundaries and avoid a very expensive re-alignment in mac80211. 404 */ 405 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 406 ATH10K_HW_TXRX_ETHERNET = 2, 407 408 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 409 ATH10K_HW_TXRX_MGMT = 3, 410 }; 411 412 enum ath10k_mcast2ucast_mode { 413 ATH10K_MCAST2UCAST_DISABLED = 0, 414 ATH10K_MCAST2UCAST_ENABLED = 1, 415 }; 416 417 enum ath10k_hw_rate_ofdm { 418 ATH10K_HW_RATE_OFDM_48M = 0, 419 ATH10K_HW_RATE_OFDM_24M, 420 ATH10K_HW_RATE_OFDM_12M, 421 ATH10K_HW_RATE_OFDM_6M, 422 ATH10K_HW_RATE_OFDM_54M, 423 ATH10K_HW_RATE_OFDM_36M, 424 ATH10K_HW_RATE_OFDM_18M, 425 ATH10K_HW_RATE_OFDM_9M, 426 }; 427 428 enum ath10k_hw_rate_cck { 429 ATH10K_HW_RATE_CCK_LP_11M = 0, 430 ATH10K_HW_RATE_CCK_LP_5_5M, 431 ATH10K_HW_RATE_CCK_LP_2M, 432 ATH10K_HW_RATE_CCK_LP_1M, 433 ATH10K_HW_RATE_CCK_SP_11M, 434 ATH10K_HW_RATE_CCK_SP_5_5M, 435 ATH10K_HW_RATE_CCK_SP_2M, 436 }; 437 438 enum ath10k_hw_rate_rev2_cck { 439 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 440 ATH10K_HW_RATE_REV2_CCK_LP_2M, 441 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 442 ATH10K_HW_RATE_REV2_CCK_LP_11M, 443 ATH10K_HW_RATE_REV2_CCK_SP_2M, 444 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 445 ATH10K_HW_RATE_REV2_CCK_SP_11M, 446 }; 447 448 enum ath10k_hw_cc_wraparound_type { 449 ATH10K_HW_CC_WRAP_DISABLED = 0, 450 451 /* This type is when the HW chip has a quirky Cycle Counter 452 * wraparound which resets to 0x7fffffff instead of 0. All 453 * other CC related counters (e.g. Rx Clear Count) are divided 454 * by 2 so they never wraparound themselves. 455 */ 456 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 457 458 /* Each hw counter wrapsaround independently. When the 459 * counter overflows the repestive counter is right shifted 460 * by 1, i.e reset to 0x7fffffff, and other counters will be 461 * running unaffected. In this type of wraparound, it should 462 * be possible to report accurate Rx busy time unlike the 463 * first type. 464 */ 465 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 466 }; 467 468 enum ath10k_hw_refclk_speed { 469 ATH10K_HW_REFCLK_UNKNOWN = -1, 470 ATH10K_HW_REFCLK_48_MHZ = 0, 471 ATH10K_HW_REFCLK_19_2_MHZ = 1, 472 ATH10K_HW_REFCLK_24_MHZ = 2, 473 ATH10K_HW_REFCLK_26_MHZ = 3, 474 ATH10K_HW_REFCLK_37_4_MHZ = 4, 475 ATH10K_HW_REFCLK_38_4_MHZ = 5, 476 ATH10K_HW_REFCLK_40_MHZ = 6, 477 ATH10K_HW_REFCLK_52_MHZ = 7, 478 479 /* must be the last one */ 480 ATH10K_HW_REFCLK_COUNT, 481 }; 482 483 struct ath10k_hw_clk_params { 484 u32 refclk; 485 u32 div; 486 u32 rnfrac; 487 u32 settle_time; 488 u32 refdiv; 489 u32 outdiv; 490 }; 491 492 struct ath10k_hw_params { 493 u32 id; 494 u16 dev_id; 495 const char *name; 496 u32 patch_load_addr; 497 int uart_pin; 498 u32 otp_exe_param; 499 500 /* Type of hw cycle counter wraparound logic, for more info 501 * refer enum ath10k_hw_cc_wraparound_type. 502 */ 503 enum ath10k_hw_cc_wraparound_type cc_wraparound_type; 504 505 /* Some of chip expects fragment descriptor to be continuous 506 * memory for any TX operation. Set continuous_frag_desc flag 507 * for the hardware which have such requirement. 508 */ 509 bool continuous_frag_desc; 510 511 /* CCK hardware rate table mapping for the newer chipsets 512 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values 513 * are in a proper order with respect to the rate/preamble 514 */ 515 bool cck_rate_map_rev2; 516 517 u32 channel_counters_freq_hz; 518 519 /* Mgmt tx descriptors threshold for limiting probe response 520 * frames. 521 */ 522 u32 max_probe_resp_desc_thres; 523 524 u32 tx_chain_mask; 525 u32 rx_chain_mask; 526 u32 max_spatial_stream; 527 u32 cal_data_len; 528 529 struct ath10k_hw_params_fw { 530 const char *dir; 531 const char *board; 532 size_t board_size; 533 size_t board_ext_size; 534 } fw; 535 536 /* qca99x0 family chips deliver broadcast/multicast management 537 * frames encrypted and expect software do decryption. 538 */ 539 bool sw_decrypt_mcast_mgmt; 540 541 const struct ath10k_hw_ops *hw_ops; 542 543 /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ 544 int decap_align_bytes; 545 546 /* hw specific clock control parameters */ 547 const struct ath10k_hw_clk_params *hw_clk; 548 int target_cpu_freq; 549 550 /* Number of bytes to be discarded for each FFT sample */ 551 int spectral_bin_discard; 552 553 /* The board may have a restricted NSS for 160 or 80+80 vs what it 554 * can do for 80Mhz. 555 */ 556 int vht160_mcs_rx_highest; 557 int vht160_mcs_tx_highest; 558 559 /* Number of ciphers supported (i.e First N) in cipher_suites array */ 560 int n_cipher_suites; 561 562 u32 num_peers; 563 u32 ast_skid_limit; 564 u32 num_wds_entries; 565 566 /* Targets supporting physical addressing capability above 32-bits */ 567 bool target_64bit; 568 569 /* Target rx ring fill level */ 570 u32 rx_ring_fill_level; 571 }; 572 573 struct htt_rx_desc; 574 575 /* Defines needed for Rx descriptor abstraction */ 576 struct ath10k_hw_ops { 577 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 578 void (*set_coverage_class)(struct ath10k *ar, s16 value); 579 int (*enable_pll_clk)(struct ath10k *ar); 580 }; 581 582 extern const struct ath10k_hw_ops qca988x_ops; 583 extern const struct ath10k_hw_ops qca99x0_ops; 584 extern const struct ath10k_hw_ops qca6174_ops; 585 extern const struct ath10k_hw_ops wcn3990_ops; 586 587 extern const struct ath10k_hw_clk_params qca6174_clk[]; 588 589 static inline int 590 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, 591 struct htt_rx_desc *rxd) 592 { 593 if (hw->hw_ops->rx_desc_get_l3_pad_bytes) 594 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd); 595 return 0; 596 } 597 598 /* Target specific defines for MAIN firmware */ 599 #define TARGET_NUM_VDEVS 8 600 #define TARGET_NUM_PEER_AST 2 601 #define TARGET_NUM_WDS_ENTRIES 32 602 #define TARGET_DMA_BURST_SIZE 0 603 #define TARGET_MAC_AGGR_DELIM 0 604 #define TARGET_AST_SKID_LIMIT 16 605 #define TARGET_NUM_STATIONS 16 606 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 607 (TARGET_NUM_VDEVS)) 608 #define TARGET_NUM_OFFLOAD_PEERS 0 609 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 610 #define TARGET_NUM_PEER_KEYS 2 611 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 612 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 613 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 614 #define TARGET_RX_TIMEOUT_LO_PRI 100 615 #define TARGET_RX_TIMEOUT_HI_PRI 40 616 617 #define TARGET_SCAN_MAX_PENDING_REQS 4 618 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 619 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 620 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 621 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 622 #define TARGET_NUM_MCAST_GROUPS 0 623 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 624 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 625 #define TARGET_TX_DBG_LOG_SIZE 1024 626 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 627 #define TARGET_VOW_CONFIG 0 628 #define TARGET_NUM_MSDU_DESC (1024 + 400) 629 #define TARGET_MAX_FRAG_ENTRIES 0 630 631 /* Target specific defines for 10.X firmware */ 632 #define TARGET_10X_NUM_VDEVS 16 633 #define TARGET_10X_NUM_PEER_AST 2 634 #define TARGET_10X_NUM_WDS_ENTRIES 32 635 #define TARGET_10X_DMA_BURST_SIZE 0 636 #define TARGET_10X_MAC_AGGR_DELIM 0 637 #define TARGET_10X_AST_SKID_LIMIT 128 638 #define TARGET_10X_NUM_STATIONS 128 639 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 640 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 641 (TARGET_10X_NUM_VDEVS)) 642 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 643 (TARGET_10X_NUM_VDEVS)) 644 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 645 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 646 #define TARGET_10X_NUM_PEER_KEYS 2 647 #define TARGET_10X_NUM_TIDS_MAX 256 648 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 649 (TARGET_10X_NUM_PEERS) * 2) 650 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 651 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 652 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 653 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 654 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 655 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 656 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 657 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 658 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 659 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 660 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 661 #define TARGET_10X_NUM_MCAST_GROUPS 0 662 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 663 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 664 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 665 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 666 #define TARGET_10X_VOW_CONFIG 0 667 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 668 #define TARGET_10X_MAX_FRAG_ENTRIES 0 669 670 /* 10.2 parameters */ 671 #define TARGET_10_2_DMA_BURST_SIZE 0 672 673 /* Target specific defines for WMI-TLV firmware */ 674 #define TARGET_TLV_NUM_VDEVS 4 675 #define TARGET_TLV_NUM_STATIONS 32 676 #define TARGET_TLV_NUM_PEERS 33 677 #define TARGET_TLV_NUM_TDLS_VDEVS 1 678 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 679 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 680 #define TARGET_TLV_NUM_WOW_PATTERNS 22 681 682 /* Target specific defines for WMI-HL-1.0 firmware */ 683 #define TARGET_HL_10_TLV_NUM_PEERS 14 684 #define TARGET_HL_10_TLV_AST_SKID_LIMIT 6 685 #define TARGET_HL_10_TLV_NUM_WDS_ENTRIES 2 686 687 /* Diagnostic Window */ 688 #define CE_DIAG_PIPE 7 689 690 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 691 692 /* Target specific defines for 10.4 firmware */ 693 #define TARGET_10_4_NUM_VDEVS 16 694 #define TARGET_10_4_NUM_STATIONS 32 695 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 696 (TARGET_10_4_NUM_VDEVS)) 697 #define TARGET_10_4_ACTIVE_PEERS 0 698 699 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 700 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 701 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 702 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 703 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 704 #define TARGET_10_4_NUM_PEER_KEYS 2 705 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 706 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 707 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 708 #define TARGET_10_4_AST_SKID_LIMIT 32 709 710 /* 100 ms for video, best-effort, and background */ 711 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 712 713 /* 40 ms for voice */ 714 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 715 716 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 717 #define TARGET_10_4_SCAN_MAX_REQS 4 718 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 719 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 720 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 721 722 /* Note: mcast to ucast is disabled by default */ 723 #define TARGET_10_4_NUM_MCAST_GROUPS 0 724 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 725 #define TARGET_10_4_MCAST2UCAST_MODE 0 726 727 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 728 #define TARGET_10_4_NUM_WDS_ENTRIES 32 729 #define TARGET_10_4_DMA_BURST_SIZE 0 730 #define TARGET_10_4_MAC_AGGR_DELIM 0 731 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 732 #define TARGET_10_4_VOW_CONFIG 0 733 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 734 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 735 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 736 #define TARGET_10_4_SMART_ANT_CAP 0 737 #define TARGET_10_4_BK_MIN_FREE 0 738 #define TARGET_10_4_BE_MIN_FREE 0 739 #define TARGET_10_4_VI_MIN_FREE 0 740 #define TARGET_10_4_VO_MIN_FREE 0 741 #define TARGET_10_4_RX_BATCH_MODE 1 742 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 743 #define TARGET_10_4_ATF_CONFIG 0 744 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 745 #define TARGET_10_4_QWRAP_CONFIG 0 746 747 /* TDLS config */ 748 #define TARGET_10_4_NUM_TDLS_VDEVS 1 749 #define TARGET_10_4_NUM_TDLS_BUFFER_STA 1 750 #define TARGET_10_4_NUM_TDLS_SLEEP_STA 1 751 752 /* Maximum number of Copy Engine's supported */ 753 #define CE_COUNT_MAX 12 754 755 /* Number of Copy Engines supported */ 756 #define CE_COUNT ar->hw_values->ce_count 757 758 /* 759 * Granted MSIs are assigned as follows: 760 * Firmware uses the first 761 * Remaining MSIs, if any, are used by Copy Engines 762 * This mapping is known to both Target firmware and Host software. 763 * It may be changed as long as Host and Target are kept in sync. 764 */ 765 /* MSI for firmware (errors, etc.) */ 766 #define MSI_ASSIGN_FW 0 767 768 /* MSIs for Copy Engines */ 769 #define MSI_ASSIGN_CE_INITIAL 1 770 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 771 772 /* as of IP3.7.1 */ 773 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 774 775 #define RTC_STATE_V_LSB 0 776 #define RTC_STATE_V_MASK 0x00000007 777 #define RTC_STATE_ADDRESS 0x0000 778 #define PCIE_SOC_WAKE_V_MASK 0x00000001 779 #define PCIE_SOC_WAKE_ADDRESS 0x0004 780 #define PCIE_SOC_WAKE_RESET 0x00000000 781 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 782 783 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 784 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 785 #define MAC_COEX_BASE_ADDRESS 0x00006000 786 #define BT_COEX_BASE_ADDRESS 0x00007000 787 #define SOC_PCIE_BASE_ADDRESS 0x00008000 788 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 789 #define WLAN_UART_BASE_ADDRESS 0x0000c000 790 #define WLAN_SI_BASE_ADDRESS 0x00010000 791 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 792 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 793 #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address 794 #define EFUSE_BASE_ADDRESS 0x00030000 795 #define FPGA_REG_BASE_ADDRESS 0x00039000 796 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 797 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 798 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 799 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 800 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 801 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 802 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 803 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 804 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 805 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 806 #define DBI_BASE_ADDRESS 0x00060000 807 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 808 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 809 810 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 811 #define SOC_RESET_CONTROL_OFFSET 0x00000000 812 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 813 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 814 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 815 #define SOC_CPU_CLOCK_OFFSET 0x00000020 816 #define SOC_CPU_CLOCK_STANDARD_LSB 0 817 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 818 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 819 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 820 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 821 #define SOC_LPO_CAL_OFFSET 0x000000e0 822 #define SOC_LPO_CAL_ENABLE_LSB 20 823 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 824 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 825 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 826 827 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 828 #define SOC_CHIP_ID_REV_LSB 8 829 #define SOC_CHIP_ID_REV_MASK 0x00000f00 830 831 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 832 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 833 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 834 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 835 836 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 837 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 838 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 839 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 840 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 841 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 842 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 843 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 844 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 845 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 846 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 847 848 #define CLOCK_GPIO_OFFSET 0xffffffff 849 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 850 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 851 852 #define SI_CONFIG_OFFSET 0x00000000 853 #define SI_CONFIG_ERR_INT_LSB 19 854 #define SI_CONFIG_ERR_INT_MASK 0x00080000 855 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 856 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 857 #define SI_CONFIG_I2C_LSB 16 858 #define SI_CONFIG_I2C_MASK 0x00010000 859 #define SI_CONFIG_POS_SAMPLE_LSB 7 860 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 861 #define SI_CONFIG_INACTIVE_DATA_LSB 5 862 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 863 #define SI_CONFIG_INACTIVE_CLK_LSB 4 864 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 865 #define SI_CONFIG_DIVIDER_LSB 0 866 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 867 #define SI_CS_OFFSET 0x00000004 868 #define SI_CS_DONE_ERR_LSB 10 869 #define SI_CS_DONE_ERR_MASK 0x00000400 870 #define SI_CS_DONE_INT_LSB 9 871 #define SI_CS_DONE_INT_MASK 0x00000200 872 #define SI_CS_START_LSB 8 873 #define SI_CS_START_MASK 0x00000100 874 #define SI_CS_RX_CNT_LSB 4 875 #define SI_CS_RX_CNT_MASK 0x000000f0 876 #define SI_CS_TX_CNT_LSB 0 877 #define SI_CS_TX_CNT_MASK 0x0000000f 878 879 #define SI_TX_DATA0_OFFSET 0x00000008 880 #define SI_TX_DATA1_OFFSET 0x0000000c 881 #define SI_RX_DATA0_OFFSET 0x00000010 882 #define SI_RX_DATA1_OFFSET 0x00000014 883 884 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 885 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 886 #define CORE_CTRL_ADDRESS 0x0000 887 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 888 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 889 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 890 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 891 #define CPU_INTR_ADDRESS 0x0010 892 #define FW_RAM_CONFIG_ADDRESS 0x0018 893 894 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 895 896 /* Firmware indications to the Host via SCRATCH_3 register. */ 897 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 898 #define FW_IND_EVENT_PENDING 1 899 #define FW_IND_INITIALIZED 2 900 #define FW_IND_HOST_READY 0x80000000 901 902 /* HOST_REG interrupt from firmware */ 903 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 904 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 905 906 #define DRAM_BASE_ADDRESS 0x00400000 907 908 #define PCIE_BAR_REG_ADDRESS 0x40030 909 910 #define MISSING 0 911 912 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 913 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 914 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 915 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 916 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 917 #define RESET_CONTROL_MBOX_RST_MASK MISSING 918 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 919 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 920 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 921 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 922 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 923 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 924 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 925 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 926 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 927 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 928 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 929 #define LOCAL_SCRATCH_OFFSET 0x18 930 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 931 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 932 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 933 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 934 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 935 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 936 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 937 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 938 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 939 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 940 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 941 #define MBOX_BASE_ADDRESS MISSING 942 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 943 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 944 #define INT_STATUS_ENABLE_CPU_LSB MISSING 945 #define INT_STATUS_ENABLE_CPU_MASK MISSING 946 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 947 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 948 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 949 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 950 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 951 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 952 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 953 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 954 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 955 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 956 #define INT_STATUS_ENABLE_ADDRESS MISSING 957 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 958 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 959 #define HOST_INT_STATUS_ADDRESS MISSING 960 #define CPU_INT_STATUS_ADDRESS MISSING 961 #define ERROR_INT_STATUS_ADDRESS MISSING 962 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 963 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 964 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 965 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 966 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 967 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 968 #define COUNT_DEC_ADDRESS MISSING 969 #define HOST_INT_STATUS_CPU_MASK MISSING 970 #define HOST_INT_STATUS_CPU_LSB MISSING 971 #define HOST_INT_STATUS_ERROR_MASK MISSING 972 #define HOST_INT_STATUS_ERROR_LSB MISSING 973 #define HOST_INT_STATUS_COUNTER_MASK MISSING 974 #define HOST_INT_STATUS_COUNTER_LSB MISSING 975 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 976 #define WINDOW_DATA_ADDRESS MISSING 977 #define WINDOW_READ_ADDR_ADDRESS MISSING 978 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 979 980 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 981 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 982 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 983 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 984 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 985 986 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 987 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 988 #define QCA9887_EEPROM_ADDR_HI_LSB 8 989 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 990 #define QCA9887_EEPROM_ADDR_LO_LSB 16 991 992 #define MBOX_RESET_CONTROL_ADDRESS 0x00000000 993 #define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800 994 #define MBOX_HOST_INT_STATUS_ERROR_LSB 7 995 #define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080 996 #define MBOX_HOST_INT_STATUS_CPU_LSB 6 997 #define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040 998 #define MBOX_HOST_INT_STATUS_COUNTER_LSB 4 999 #define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010 1000 #define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801 1001 #define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802 1002 #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB 2 1003 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 1004 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 1005 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 1006 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 1007 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 1008 #define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803 1009 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0 1010 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff 1011 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805 1012 #define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828 1013 #define MBOX_INT_STATUS_ENABLE_ERROR_LSB 7 1014 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080 1015 #define MBOX_INT_STATUS_ENABLE_CPU_LSB 6 1016 #define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040 1017 #define MBOX_INT_STATUS_ENABLE_INT_LSB 5 1018 #define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020 1019 #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB 4 1020 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 1021 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0 1022 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f 1023 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819 1024 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0 1025 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1026 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a 1027 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 1028 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 1029 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 1030 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 1031 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b 1032 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 1033 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff 1034 #define MBOX_COUNT_ADDRESS 0x00000820 1035 #define MBOX_COUNT_DEC_ADDRESS 0x00000840 1036 #define MBOX_WINDOW_DATA_ADDRESS 0x00000874 1037 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878 1038 #define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c 1039 #define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883 1040 #define MBOX_CPU_DBG_ADDRESS 0x00000884 1041 #define MBOX_RTC_BASE_ADDRESS 0x00000000 1042 #define MBOX_GPIO_BASE_ADDRESS 0x00005000 1043 #define MBOX_MBOX_BASE_ADDRESS 0x00008000 1044 1045 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 1046 1047 /* Register definitions for first generation ath10k cards. These cards include 1048 * a mac thich has a register allocation similar to ath9k and at least some 1049 * registers including the ones relevant for modifying the coverage class are 1050 * identical to the ath9k definitions. 1051 * These registers are usually managed by the ath10k firmware. However by 1052 * overriding them it is possible to support coverage class modifications. 1053 */ 1054 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014 1055 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF 1056 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF 1057 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0 1058 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000 1059 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16 1060 1061 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070 1062 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF 1063 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF 1064 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0 1065 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000 1066 1067 #define WAVE1_PHYCLK 0x801C 1068 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F 1069 #define WAVE1_PHYCLK_USEC_LSB 0 1070 1071 /* qca6174 PLL offset/mask */ 1072 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114 1073 #define SOC_CORE_CLK_CTRL_DIV_LSB 0 1074 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 1075 1076 #define EFUSE_OFFSET 0x0000032c 1077 #define EFUSE_XTAL_SEL_LSB 8 1078 #define EFUSE_XTAL_SEL_MASK 0x00000700 1079 1080 #define BB_PLL_CONFIG_OFFSET 0x000002f4 1081 #define BB_PLL_CONFIG_FRAC_LSB 0 1082 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff 1083 #define BB_PLL_CONFIG_OUTDIV_LSB 18 1084 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 1085 1086 #define WLAN_PLL_SETTLE_OFFSET 0x0018 1087 #define WLAN_PLL_SETTLE_TIME_LSB 0 1088 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff 1089 1090 #define WLAN_PLL_CONTROL_OFFSET 0x0014 1091 #define WLAN_PLL_CONTROL_DIV_LSB 0 1092 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff 1093 #define WLAN_PLL_CONTROL_REFDIV_LSB 10 1094 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 1095 #define WLAN_PLL_CONTROL_BYPASS_LSB 16 1096 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 1097 #define WLAN_PLL_CONTROL_NOPWD_LSB 18 1098 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 1099 1100 #define RTC_SYNC_STATUS_OFFSET 0x0244 1101 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 1102 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 1103 /* qca6174 PLL offset/mask end */ 1104 1105 #endif /* _HW_H_ */ 1106