xref: /openbmc/linux/drivers/net/wireless/ath/ath10k/hw.h (revision 4f205687)
1 /*
2  * Copyright (c) 2005-2011 Atheros Communications Inc.
3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  */
17 
18 #ifndef _HW_H_
19 #define _HW_H_
20 
21 #include "targaddrs.h"
22 
23 #define ATH10K_FW_DIR			"ath10k"
24 
25 #define QCA988X_2_0_DEVICE_ID   (0x003c)
26 #define QCA6164_2_1_DEVICE_ID   (0x0041)
27 #define QCA6174_2_1_DEVICE_ID   (0x003e)
28 #define QCA99X0_2_0_DEVICE_ID   (0x0040)
29 #define QCA9377_1_0_DEVICE_ID   (0x0042)
30 
31 /* QCA988X 1.0 definitions (unsupported) */
32 #define QCA988X_HW_1_0_CHIP_ID_REV	0x0
33 
34 /* QCA988X 2.0 definitions */
35 #define QCA988X_HW_2_0_VERSION		0x4100016c
36 #define QCA988X_HW_2_0_CHIP_ID_REV	0x2
37 #define QCA988X_HW_2_0_FW_DIR		ATH10K_FW_DIR "/QCA988X/hw2.0"
38 #define QCA988X_HW_2_0_BOARD_DATA_FILE	"board.bin"
39 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR	0x1234
40 
41 /* QCA6174 target BMI version signatures */
42 #define QCA6174_HW_1_0_VERSION		0x05000000
43 #define QCA6174_HW_1_1_VERSION		0x05000001
44 #define QCA6174_HW_1_3_VERSION		0x05000003
45 #define QCA6174_HW_2_1_VERSION		0x05010000
46 #define QCA6174_HW_3_0_VERSION		0x05020000
47 #define QCA6174_HW_3_2_VERSION		0x05030000
48 
49 /* QCA9377 target BMI version signatures */
50 #define QCA9377_HW_1_0_DEV_VERSION	0x05020000
51 #define QCA9377_HW_1_1_DEV_VERSION	0x05020001
52 
53 enum qca6174_pci_rev {
54 	QCA6174_PCI_REV_1_1 = 0x11,
55 	QCA6174_PCI_REV_1_3 = 0x13,
56 	QCA6174_PCI_REV_2_0 = 0x20,
57 	QCA6174_PCI_REV_3_0 = 0x30,
58 };
59 
60 enum qca6174_chip_id_rev {
61 	QCA6174_HW_1_0_CHIP_ID_REV = 0,
62 	QCA6174_HW_1_1_CHIP_ID_REV = 1,
63 	QCA6174_HW_1_3_CHIP_ID_REV = 2,
64 	QCA6174_HW_2_1_CHIP_ID_REV = 4,
65 	QCA6174_HW_2_2_CHIP_ID_REV = 5,
66 	QCA6174_HW_3_0_CHIP_ID_REV = 8,
67 	QCA6174_HW_3_1_CHIP_ID_REV = 9,
68 	QCA6174_HW_3_2_CHIP_ID_REV = 10,
69 };
70 
71 enum qca9377_chip_id_rev {
72 	QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
73 	QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
74 };
75 
76 #define QCA6174_HW_2_1_FW_DIR		"ath10k/QCA6174/hw2.1"
77 #define QCA6174_HW_2_1_BOARD_DATA_FILE	"board.bin"
78 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR	0x1234
79 
80 #define QCA6174_HW_3_0_FW_DIR		"ath10k/QCA6174/hw3.0"
81 #define QCA6174_HW_3_0_BOARD_DATA_FILE	"board.bin"
82 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR	0x1234
83 
84 /* QCA99X0 1.0 definitions (unsupported) */
85 #define QCA99X0_HW_1_0_CHIP_ID_REV     0x0
86 
87 /* QCA99X0 2.0 definitions */
88 #define QCA99X0_HW_2_0_DEV_VERSION     0x01000000
89 #define QCA99X0_HW_2_0_CHIP_ID_REV     0x1
90 #define QCA99X0_HW_2_0_FW_DIR          ATH10K_FW_DIR "/QCA99X0/hw2.0"
91 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
92 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR	0x1234
93 
94 /* QCA9377 1.0 definitions */
95 #define QCA9377_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA9377/hw1.0"
96 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin"
97 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR	0x1234
98 
99 /* QCA4019 1.0 definitions */
100 #define QCA4019_HW_1_0_DEV_VERSION     0x01000000
101 #define QCA4019_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA4019/hw1.0"
102 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin"
103 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR  0x1234
104 
105 #define ATH10K_FW_API2_FILE		"firmware-2.bin"
106 #define ATH10K_FW_API3_FILE		"firmware-3.bin"
107 
108 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */
109 #define ATH10K_FW_API4_FILE		"firmware-4.bin"
110 
111 /* HTT id conflict fix for management frames over HTT */
112 #define ATH10K_FW_API5_FILE		"firmware-5.bin"
113 
114 #define ATH10K_FW_UTF_FILE		"utf.bin"
115 #define ATH10K_FW_UTF_API2_FILE		"utf-2.bin"
116 
117 /* includes also the null byte */
118 #define ATH10K_FIRMWARE_MAGIC               "QCA-ATH10K"
119 #define ATH10K_BOARD_MAGIC                  "QCA-ATH10K-BOARD"
120 
121 #define ATH10K_BOARD_API2_FILE         "board-2.bin"
122 
123 #define REG_DUMP_COUNT_QCA988X 60
124 
125 struct ath10k_fw_ie {
126 	__le32 id;
127 	__le32 len;
128 	u8 data[0];
129 };
130 
131 enum ath10k_fw_ie_type {
132 	ATH10K_FW_IE_FW_VERSION = 0,
133 	ATH10K_FW_IE_TIMESTAMP = 1,
134 	ATH10K_FW_IE_FEATURES = 2,
135 	ATH10K_FW_IE_FW_IMAGE = 3,
136 	ATH10K_FW_IE_OTP_IMAGE = 4,
137 
138 	/* WMI "operations" interface version, 32 bit value. Supported from
139 	 * FW API 4 and above.
140 	 */
141 	ATH10K_FW_IE_WMI_OP_VERSION = 5,
142 
143 	/* HTT "operations" interface version, 32 bit value. Supported from
144 	 * FW API 5 and above.
145 	 */
146 	ATH10K_FW_IE_HTT_OP_VERSION = 6,
147 
148 	/* Code swap image for firmware binary */
149 	ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7,
150 };
151 
152 enum ath10k_fw_wmi_op_version {
153 	ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
154 
155 	ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
156 	ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
157 	ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
158 	ATH10K_FW_WMI_OP_VERSION_TLV = 4,
159 	ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
160 	ATH10K_FW_WMI_OP_VERSION_10_4 = 6,
161 
162 	/* keep last */
163 	ATH10K_FW_WMI_OP_VERSION_MAX,
164 };
165 
166 enum ath10k_fw_htt_op_version {
167 	ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
168 
169 	ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
170 
171 	/* also used in 10.2 and 10.2.4 branches */
172 	ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
173 
174 	ATH10K_FW_HTT_OP_VERSION_TLV = 3,
175 
176 	ATH10K_FW_HTT_OP_VERSION_10_4 = 4,
177 
178 	/* keep last */
179 	ATH10K_FW_HTT_OP_VERSION_MAX,
180 };
181 
182 enum ath10k_bd_ie_type {
183 	/* contains sub IEs of enum ath10k_bd_ie_board_type */
184 	ATH10K_BD_IE_BOARD = 0,
185 };
186 
187 enum ath10k_bd_ie_board_type {
188 	ATH10K_BD_IE_BOARD_NAME = 0,
189 	ATH10K_BD_IE_BOARD_DATA = 1,
190 };
191 
192 enum ath10k_hw_rev {
193 	ATH10K_HW_QCA988X,
194 	ATH10K_HW_QCA6174,
195 	ATH10K_HW_QCA99X0,
196 	ATH10K_HW_QCA9377,
197 	ATH10K_HW_QCA4019,
198 };
199 
200 struct ath10k_hw_regs {
201 	u32 rtc_state_cold_reset_mask;
202 	u32 rtc_soc_base_address;
203 	u32 rtc_wmac_base_address;
204 	u32 soc_core_base_address;
205 	u32 ce_wrapper_base_address;
206 	u32 ce0_base_address;
207 	u32 ce1_base_address;
208 	u32 ce2_base_address;
209 	u32 ce3_base_address;
210 	u32 ce4_base_address;
211 	u32 ce5_base_address;
212 	u32 ce6_base_address;
213 	u32 ce7_base_address;
214 	u32 soc_reset_control_si0_rst_mask;
215 	u32 soc_reset_control_ce_rst_mask;
216 	u32 soc_chip_id_address;
217 	u32 scratch_3_address;
218 	u32 fw_indicator_address;
219 	u32 pcie_local_base_address;
220 	u32 ce_wrap_intr_sum_host_msi_lsb;
221 	u32 ce_wrap_intr_sum_host_msi_mask;
222 	u32 pcie_intr_fw_mask;
223 	u32 pcie_intr_ce_mask_all;
224 	u32 pcie_intr_clr_address;
225 };
226 
227 extern const struct ath10k_hw_regs qca988x_regs;
228 extern const struct ath10k_hw_regs qca6174_regs;
229 extern const struct ath10k_hw_regs qca99x0_regs;
230 extern const struct ath10k_hw_regs qca4019_regs;
231 
232 struct ath10k_hw_values {
233 	u32 rtc_state_val_on;
234 	u8 ce_count;
235 	u8 msi_assign_ce_max;
236 	u8 num_target_ce_config_wlan;
237 	u16 ce_desc_meta_data_mask;
238 	u8 ce_desc_meta_data_lsb;
239 };
240 
241 extern const struct ath10k_hw_values qca988x_values;
242 extern const struct ath10k_hw_values qca6174_values;
243 extern const struct ath10k_hw_values qca99x0_values;
244 extern const struct ath10k_hw_values qca4019_values;
245 
246 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
247 				u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
248 
249 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
250 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
251 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
252 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
253 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
254 
255 /* Known pecularities:
256  *  - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
257  *  - raw have FCS, nwifi doesn't
258  *  - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
259  *    param, llc/snap) are aligned to 4byte boundaries each */
260 enum ath10k_hw_txrx_mode {
261 	ATH10K_HW_TXRX_RAW = 0,
262 
263 	/* Native Wifi decap mode is used to align IP frames to 4-byte
264 	 * boundaries and avoid a very expensive re-alignment in mac80211.
265 	 */
266 	ATH10K_HW_TXRX_NATIVE_WIFI = 1,
267 	ATH10K_HW_TXRX_ETHERNET = 2,
268 
269 	/* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
270 	ATH10K_HW_TXRX_MGMT = 3,
271 };
272 
273 enum ath10k_mcast2ucast_mode {
274 	ATH10K_MCAST2UCAST_DISABLED = 0,
275 	ATH10K_MCAST2UCAST_ENABLED = 1,
276 };
277 
278 struct ath10k_pktlog_hdr {
279 	__le16 flags;
280 	__le16 missed_cnt;
281 	__le16 log_type;
282 	__le16 size;
283 	__le32 timestamp;
284 	u8 payload[0];
285 } __packed;
286 
287 struct ath10k_pktlog_10_4_hdr {
288 	__le16 flags;
289 	__le16 missed_cnt;
290 	__le16 log_type;
291 	__le16 size;
292 	__le32 timestamp;
293 	__le32 type_specific_data;
294 	u8 payload[0];
295 } __packed;
296 
297 enum ath10k_hw_rate_ofdm {
298 	ATH10K_HW_RATE_OFDM_48M = 0,
299 	ATH10K_HW_RATE_OFDM_24M,
300 	ATH10K_HW_RATE_OFDM_12M,
301 	ATH10K_HW_RATE_OFDM_6M,
302 	ATH10K_HW_RATE_OFDM_54M,
303 	ATH10K_HW_RATE_OFDM_36M,
304 	ATH10K_HW_RATE_OFDM_18M,
305 	ATH10K_HW_RATE_OFDM_9M,
306 };
307 
308 enum ath10k_hw_rate_cck {
309 	ATH10K_HW_RATE_CCK_LP_11M = 0,
310 	ATH10K_HW_RATE_CCK_LP_5_5M,
311 	ATH10K_HW_RATE_CCK_LP_2M,
312 	ATH10K_HW_RATE_CCK_LP_1M,
313 	ATH10K_HW_RATE_CCK_SP_11M,
314 	ATH10K_HW_RATE_CCK_SP_5_5M,
315 	ATH10K_HW_RATE_CCK_SP_2M,
316 };
317 
318 enum ath10k_hw_4addr_pad {
319 	ATH10K_HW_4ADDR_PAD_AFTER,
320 	ATH10K_HW_4ADDR_PAD_BEFORE,
321 };
322 
323 /* Target specific defines for MAIN firmware */
324 #define TARGET_NUM_VDEVS			8
325 #define TARGET_NUM_PEER_AST			2
326 #define TARGET_NUM_WDS_ENTRIES			32
327 #define TARGET_DMA_BURST_SIZE			0
328 #define TARGET_MAC_AGGR_DELIM			0
329 #define TARGET_AST_SKID_LIMIT			16
330 #define TARGET_NUM_STATIONS			16
331 #define TARGET_NUM_PEERS			((TARGET_NUM_STATIONS) + \
332 						 (TARGET_NUM_VDEVS))
333 #define TARGET_NUM_OFFLOAD_PEERS		0
334 #define TARGET_NUM_OFFLOAD_REORDER_BUFS         0
335 #define TARGET_NUM_PEER_KEYS			2
336 #define TARGET_NUM_TIDS				((TARGET_NUM_PEERS) * 2)
337 #define TARGET_TX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
338 #define TARGET_RX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
339 #define TARGET_RX_TIMEOUT_LO_PRI		100
340 #define TARGET_RX_TIMEOUT_HI_PRI		40
341 
342 #define TARGET_SCAN_MAX_PENDING_REQS		4
343 #define TARGET_BMISS_OFFLOAD_MAX_VDEV		3
344 #define TARGET_ROAM_OFFLOAD_MAX_VDEV		3
345 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES	8
346 #define TARGET_GTK_OFFLOAD_MAX_VDEV		3
347 #define TARGET_NUM_MCAST_GROUPS			0
348 #define TARGET_NUM_MCAST_TABLE_ELEMS		0
349 #define TARGET_MCAST2UCAST_MODE			ATH10K_MCAST2UCAST_DISABLED
350 #define TARGET_TX_DBG_LOG_SIZE			1024
351 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
352 #define TARGET_VOW_CONFIG			0
353 #define TARGET_NUM_MSDU_DESC			(1024 + 400)
354 #define TARGET_MAX_FRAG_ENTRIES			0
355 
356 /* Target specific defines for 10.X firmware */
357 #define TARGET_10X_NUM_VDEVS			16
358 #define TARGET_10X_NUM_PEER_AST			2
359 #define TARGET_10X_NUM_WDS_ENTRIES		32
360 #define TARGET_10X_DMA_BURST_SIZE		0
361 #define TARGET_10X_MAC_AGGR_DELIM		0
362 #define TARGET_10X_AST_SKID_LIMIT		128
363 #define TARGET_10X_NUM_STATIONS			128
364 #define TARGET_10X_TX_STATS_NUM_STATIONS	118
365 #define TARGET_10X_NUM_PEERS			((TARGET_10X_NUM_STATIONS) + \
366 						 (TARGET_10X_NUM_VDEVS))
367 #define TARGET_10X_TX_STATS_NUM_PEERS		((TARGET_10X_TX_STATS_NUM_STATIONS) + \
368 						 (TARGET_10X_NUM_VDEVS))
369 #define TARGET_10X_NUM_OFFLOAD_PEERS		0
370 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS	0
371 #define TARGET_10X_NUM_PEER_KEYS		2
372 #define TARGET_10X_NUM_TIDS_MAX			256
373 #define TARGET_10X_NUM_TIDS			min((TARGET_10X_NUM_TIDS_MAX), \
374 						    (TARGET_10X_NUM_PEERS) * 2)
375 #define TARGET_10X_TX_STATS_NUM_TIDS		min((TARGET_10X_NUM_TIDS_MAX), \
376 						    (TARGET_10X_TX_STATS_NUM_PEERS) * 2)
377 #define TARGET_10X_TX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
378 #define TARGET_10X_RX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
379 #define TARGET_10X_RX_TIMEOUT_LO_PRI		100
380 #define TARGET_10X_RX_TIMEOUT_HI_PRI		40
381 #define TARGET_10X_SCAN_MAX_PENDING_REQS	4
382 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV	2
383 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV	2
384 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES	8
385 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV		3
386 #define TARGET_10X_NUM_MCAST_GROUPS		0
387 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS	0
388 #define TARGET_10X_MCAST2UCAST_MODE		ATH10K_MCAST2UCAST_DISABLED
389 #define TARGET_10X_TX_DBG_LOG_SIZE		1024
390 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
391 #define TARGET_10X_VOW_CONFIG			0
392 #define TARGET_10X_NUM_MSDU_DESC		(1024 + 400)
393 #define TARGET_10X_MAX_FRAG_ENTRIES		0
394 
395 /* 10.2 parameters */
396 #define TARGET_10_2_DMA_BURST_SIZE		0
397 
398 /* Target specific defines for WMI-TLV firmware */
399 #define TARGET_TLV_NUM_VDEVS			4
400 #define TARGET_TLV_NUM_STATIONS			32
401 #define TARGET_TLV_NUM_PEERS			35
402 #define TARGET_TLV_NUM_TDLS_VDEVS		1
403 #define TARGET_TLV_NUM_TIDS			((TARGET_TLV_NUM_PEERS) * 2)
404 #define TARGET_TLV_NUM_MSDU_DESC		(1024 + 32)
405 #define TARGET_TLV_NUM_WOW_PATTERNS		22
406 
407 /* Diagnostic Window */
408 #define CE_DIAG_PIPE	7
409 
410 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
411 
412 /* Target specific defines for 10.4 firmware */
413 #define TARGET_10_4_NUM_VDEVS			16
414 #define TARGET_10_4_NUM_STATIONS		32
415 #define TARGET_10_4_NUM_PEERS			((TARGET_10_4_NUM_STATIONS) + \
416 						 (TARGET_10_4_NUM_VDEVS))
417 #define TARGET_10_4_ACTIVE_PEERS		0
418 
419 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX	512
420 #define TARGET_10_4_QCACHE_ACTIVE_PEERS		50
421 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC	35
422 #define TARGET_10_4_NUM_OFFLOAD_PEERS		0
423 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS	0
424 #define TARGET_10_4_NUM_PEER_KEYS		2
425 #define TARGET_10_4_TGT_NUM_TIDS		((TARGET_10_4_NUM_PEERS) * 2)
426 #define TARGET_10_4_NUM_MSDU_DESC		(1024 + 400)
427 #define TARGET_10_4_NUM_MSDU_DESC_PFC		2500
428 #define TARGET_10_4_AST_SKID_LIMIT		32
429 
430 /* 100 ms for video, best-effort, and background */
431 #define TARGET_10_4_RX_TIMEOUT_LO_PRI		100
432 
433 /* 40 ms for voice */
434 #define TARGET_10_4_RX_TIMEOUT_HI_PRI		40
435 
436 #define TARGET_10_4_RX_DECAP_MODE		ATH10K_HW_TXRX_NATIVE_WIFI
437 #define TARGET_10_4_SCAN_MAX_REQS		4
438 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV	3
439 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV	3
440 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES   8
441 
442 /* Note: mcast to ucast is disabled by default */
443 #define TARGET_10_4_NUM_MCAST_GROUPS		0
444 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS	0
445 #define TARGET_10_4_MCAST2UCAST_MODE		0
446 
447 #define TARGET_10_4_TX_DBG_LOG_SIZE		1024
448 #define TARGET_10_4_NUM_WDS_ENTRIES		32
449 #define TARGET_10_4_DMA_BURST_SIZE		0
450 #define TARGET_10_4_MAC_AGGR_DELIM		0
451 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
452 #define TARGET_10_4_VOW_CONFIG			0
453 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV	3
454 #define TARGET_10_4_11AC_TX_MAX_FRAGS		2
455 #define TARGET_10_4_MAX_PEER_EXT_STATS		16
456 #define TARGET_10_4_SMART_ANT_CAP		0
457 #define TARGET_10_4_BK_MIN_FREE			0
458 #define TARGET_10_4_BE_MIN_FREE			0
459 #define TARGET_10_4_VI_MIN_FREE			0
460 #define TARGET_10_4_VO_MIN_FREE			0
461 #define TARGET_10_4_RX_BATCH_MODE		1
462 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG	0
463 #define TARGET_10_4_ATF_CONFIG			0
464 #define TARGET_10_4_IPHDR_PAD_CONFIG		1
465 #define TARGET_10_4_QWRAP_CONFIG		0
466 
467 /* Number of Copy Engines supported */
468 #define CE_COUNT ar->hw_values->ce_count
469 
470 /*
471  * Granted MSIs are assigned as follows:
472  * Firmware uses the first
473  * Remaining MSIs, if any, are used by Copy Engines
474  * This mapping is known to both Target firmware and Host software.
475  * It may be changed as long as Host and Target are kept in sync.
476  */
477 /* MSI for firmware (errors, etc.) */
478 #define MSI_ASSIGN_FW		0
479 
480 /* MSIs for Copy Engines */
481 #define MSI_ASSIGN_CE_INITIAL	1
482 #define MSI_ASSIGN_CE_MAX	ar->hw_values->msi_assign_ce_max
483 
484 /* as of IP3.7.1 */
485 #define RTC_STATE_V_ON				ar->hw_values->rtc_state_val_on
486 
487 #define RTC_STATE_COLD_RESET_MASK		ar->regs->rtc_state_cold_reset_mask
488 #define RTC_STATE_V_LSB				0
489 #define RTC_STATE_V_MASK			0x00000007
490 #define RTC_STATE_ADDRESS			0x0000
491 #define PCIE_SOC_WAKE_V_MASK			0x00000001
492 #define PCIE_SOC_WAKE_ADDRESS			0x0004
493 #define PCIE_SOC_WAKE_RESET			0x00000000
494 #define SOC_GLOBAL_RESET_ADDRESS		0x0008
495 
496 #define RTC_SOC_BASE_ADDRESS			ar->regs->rtc_soc_base_address
497 #define RTC_WMAC_BASE_ADDRESS			ar->regs->rtc_wmac_base_address
498 #define MAC_COEX_BASE_ADDRESS			0x00006000
499 #define BT_COEX_BASE_ADDRESS			0x00007000
500 #define SOC_PCIE_BASE_ADDRESS			0x00008000
501 #define SOC_CORE_BASE_ADDRESS			ar->regs->soc_core_base_address
502 #define WLAN_UART_BASE_ADDRESS			0x0000c000
503 #define WLAN_SI_BASE_ADDRESS			0x00010000
504 #define WLAN_GPIO_BASE_ADDRESS			0x00014000
505 #define WLAN_ANALOG_INTF_BASE_ADDRESS		0x0001c000
506 #define WLAN_MAC_BASE_ADDRESS			0x00020000
507 #define EFUSE_BASE_ADDRESS			0x00030000
508 #define FPGA_REG_BASE_ADDRESS			0x00039000
509 #define WLAN_UART2_BASE_ADDRESS			0x00054c00
510 #define CE_WRAPPER_BASE_ADDRESS			ar->regs->ce_wrapper_base_address
511 #define CE0_BASE_ADDRESS			ar->regs->ce0_base_address
512 #define CE1_BASE_ADDRESS			ar->regs->ce1_base_address
513 #define CE2_BASE_ADDRESS			ar->regs->ce2_base_address
514 #define CE3_BASE_ADDRESS			ar->regs->ce3_base_address
515 #define CE4_BASE_ADDRESS			ar->regs->ce4_base_address
516 #define CE5_BASE_ADDRESS			ar->regs->ce5_base_address
517 #define CE6_BASE_ADDRESS			ar->regs->ce6_base_address
518 #define CE7_BASE_ADDRESS			ar->regs->ce7_base_address
519 #define DBI_BASE_ADDRESS			0x00060000
520 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS	0x0006c000
521 #define PCIE_LOCAL_BASE_ADDRESS		ar->regs->pcie_local_base_address
522 
523 #define SOC_RESET_CONTROL_ADDRESS		0x00000000
524 #define SOC_RESET_CONTROL_OFFSET		0x00000000
525 #define SOC_RESET_CONTROL_SI0_RST_MASK		ar->regs->soc_reset_control_si0_rst_mask
526 #define SOC_RESET_CONTROL_CE_RST_MASK		ar->regs->soc_reset_control_ce_rst_mask
527 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK	0x00000040
528 #define SOC_CPU_CLOCK_OFFSET			0x00000020
529 #define SOC_CPU_CLOCK_STANDARD_LSB		0
530 #define SOC_CPU_CLOCK_STANDARD_MASK		0x00000003
531 #define SOC_CLOCK_CONTROL_OFFSET		0x00000028
532 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK		0x00000001
533 #define SOC_SYSTEM_SLEEP_OFFSET			0x000000c4
534 #define SOC_LPO_CAL_OFFSET			0x000000e0
535 #define SOC_LPO_CAL_ENABLE_LSB			20
536 #define SOC_LPO_CAL_ENABLE_MASK			0x00100000
537 #define SOC_LF_TIMER_CONTROL0_ADDRESS		0x00000050
538 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK	0x00000004
539 
540 #define SOC_CHIP_ID_ADDRESS			ar->regs->soc_chip_id_address
541 #define SOC_CHIP_ID_REV_LSB			8
542 #define SOC_CHIP_ID_REV_MASK			0x00000f00
543 
544 #define WLAN_RESET_CONTROL_COLD_RST_MASK	0x00000008
545 #define WLAN_RESET_CONTROL_WARM_RST_MASK	0x00000004
546 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB		0
547 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK		0x00000001
548 
549 #define WLAN_GPIO_PIN0_ADDRESS			0x00000028
550 #define WLAN_GPIO_PIN0_CONFIG_MASK		0x00007800
551 #define WLAN_GPIO_PIN1_ADDRESS			0x0000002c
552 #define WLAN_GPIO_PIN1_CONFIG_MASK		0x00007800
553 #define WLAN_GPIO_PIN10_ADDRESS			0x00000050
554 #define WLAN_GPIO_PIN11_ADDRESS			0x00000054
555 #define WLAN_GPIO_PIN12_ADDRESS			0x00000058
556 #define WLAN_GPIO_PIN13_ADDRESS			0x0000005c
557 
558 #define CLOCK_GPIO_OFFSET			0xffffffff
559 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB		0
560 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK		0
561 
562 #define SI_CONFIG_OFFSET			0x00000000
563 #define SI_CONFIG_BIDIR_OD_DATA_LSB		18
564 #define SI_CONFIG_BIDIR_OD_DATA_MASK		0x00040000
565 #define SI_CONFIG_I2C_LSB			16
566 #define SI_CONFIG_I2C_MASK			0x00010000
567 #define SI_CONFIG_POS_SAMPLE_LSB		7
568 #define SI_CONFIG_POS_SAMPLE_MASK		0x00000080
569 #define SI_CONFIG_INACTIVE_DATA_LSB		5
570 #define SI_CONFIG_INACTIVE_DATA_MASK		0x00000020
571 #define SI_CONFIG_INACTIVE_CLK_LSB		4
572 #define SI_CONFIG_INACTIVE_CLK_MASK		0x00000010
573 #define SI_CONFIG_DIVIDER_LSB			0
574 #define SI_CONFIG_DIVIDER_MASK			0x0000000f
575 #define SI_CS_OFFSET				0x00000004
576 #define SI_CS_DONE_ERR_MASK			0x00000400
577 #define SI_CS_DONE_INT_MASK			0x00000200
578 #define SI_CS_START_LSB				8
579 #define SI_CS_START_MASK			0x00000100
580 #define SI_CS_RX_CNT_LSB			4
581 #define SI_CS_RX_CNT_MASK			0x000000f0
582 #define SI_CS_TX_CNT_LSB			0
583 #define SI_CS_TX_CNT_MASK			0x0000000f
584 
585 #define SI_TX_DATA0_OFFSET			0x00000008
586 #define SI_TX_DATA1_OFFSET			0x0000000c
587 #define SI_RX_DATA0_OFFSET			0x00000010
588 #define SI_RX_DATA1_OFFSET			0x00000014
589 
590 #define CORE_CTRL_CPU_INTR_MASK			0x00002000
591 #define CORE_CTRL_PCIE_REG_31_MASK		0x00000800
592 #define CORE_CTRL_ADDRESS			0x0000
593 #define PCIE_INTR_ENABLE_ADDRESS		0x0008
594 #define PCIE_INTR_CAUSE_ADDRESS			0x000c
595 #define PCIE_INTR_CLR_ADDRESS			ar->regs->pcie_intr_clr_address
596 #define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address
597 #define CPU_INTR_ADDRESS			0x0010
598 
599 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
600 
601 /* Firmware indications to the Host via SCRATCH_3 register. */
602 #define FW_INDICATOR_ADDRESS			ar->regs->fw_indicator_address
603 #define FW_IND_EVENT_PENDING			1
604 #define FW_IND_INITIALIZED			2
605 #define FW_IND_HOST_READY			0x80000000
606 
607 /* HOST_REG interrupt from firmware */
608 #define PCIE_INTR_FIRMWARE_MASK			ar->regs->pcie_intr_fw_mask
609 #define PCIE_INTR_CE_MASK_ALL			ar->regs->pcie_intr_ce_mask_all
610 
611 #define DRAM_BASE_ADDRESS			0x00400000
612 
613 #define PCIE_BAR_REG_ADDRESS			0x40030
614 
615 #define MISSING 0
616 
617 #define SYSTEM_SLEEP_OFFSET			SOC_SYSTEM_SLEEP_OFFSET
618 #define WLAN_SYSTEM_SLEEP_OFFSET		SOC_SYSTEM_SLEEP_OFFSET
619 #define WLAN_RESET_CONTROL_OFFSET		SOC_RESET_CONTROL_OFFSET
620 #define CLOCK_CONTROL_OFFSET			SOC_CLOCK_CONTROL_OFFSET
621 #define CLOCK_CONTROL_SI0_CLK_MASK		SOC_CLOCK_CONTROL_SI0_CLK_MASK
622 #define RESET_CONTROL_MBOX_RST_MASK		MISSING
623 #define RESET_CONTROL_SI0_RST_MASK		SOC_RESET_CONTROL_SI0_RST_MASK
624 #define GPIO_BASE_ADDRESS			WLAN_GPIO_BASE_ADDRESS
625 #define GPIO_PIN0_OFFSET			WLAN_GPIO_PIN0_ADDRESS
626 #define GPIO_PIN1_OFFSET			WLAN_GPIO_PIN1_ADDRESS
627 #define GPIO_PIN0_CONFIG_MASK			WLAN_GPIO_PIN0_CONFIG_MASK
628 #define GPIO_PIN1_CONFIG_MASK			WLAN_GPIO_PIN1_CONFIG_MASK
629 #define SI_BASE_ADDRESS				WLAN_SI_BASE_ADDRESS
630 #define SCRATCH_BASE_ADDRESS			SOC_CORE_BASE_ADDRESS
631 #define LOCAL_SCRATCH_OFFSET			0x18
632 #define CPU_CLOCK_OFFSET			SOC_CPU_CLOCK_OFFSET
633 #define LPO_CAL_OFFSET				SOC_LPO_CAL_OFFSET
634 #define GPIO_PIN10_OFFSET			WLAN_GPIO_PIN10_ADDRESS
635 #define GPIO_PIN11_OFFSET			WLAN_GPIO_PIN11_ADDRESS
636 #define GPIO_PIN12_OFFSET			WLAN_GPIO_PIN12_ADDRESS
637 #define GPIO_PIN13_OFFSET			WLAN_GPIO_PIN13_ADDRESS
638 #define CPU_CLOCK_STANDARD_LSB			SOC_CPU_CLOCK_STANDARD_LSB
639 #define CPU_CLOCK_STANDARD_MASK			SOC_CPU_CLOCK_STANDARD_MASK
640 #define LPO_CAL_ENABLE_LSB			SOC_LPO_CAL_ENABLE_LSB
641 #define LPO_CAL_ENABLE_MASK			SOC_LPO_CAL_ENABLE_MASK
642 #define ANALOG_INTF_BASE_ADDRESS		WLAN_ANALOG_INTF_BASE_ADDRESS
643 #define MBOX_BASE_ADDRESS			MISSING
644 #define INT_STATUS_ENABLE_ERROR_LSB		MISSING
645 #define INT_STATUS_ENABLE_ERROR_MASK		MISSING
646 #define INT_STATUS_ENABLE_CPU_LSB		MISSING
647 #define INT_STATUS_ENABLE_CPU_MASK		MISSING
648 #define INT_STATUS_ENABLE_COUNTER_LSB		MISSING
649 #define INT_STATUS_ENABLE_COUNTER_MASK		MISSING
650 #define INT_STATUS_ENABLE_MBOX_DATA_LSB		MISSING
651 #define INT_STATUS_ENABLE_MBOX_DATA_MASK	MISSING
652 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB	MISSING
653 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK	MISSING
654 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB	MISSING
655 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK	MISSING
656 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB	MISSING
657 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK	MISSING
658 #define INT_STATUS_ENABLE_ADDRESS		MISSING
659 #define CPU_INT_STATUS_ENABLE_BIT_LSB		MISSING
660 #define CPU_INT_STATUS_ENABLE_BIT_MASK		MISSING
661 #define HOST_INT_STATUS_ADDRESS			MISSING
662 #define CPU_INT_STATUS_ADDRESS			MISSING
663 #define ERROR_INT_STATUS_ADDRESS		MISSING
664 #define ERROR_INT_STATUS_WAKEUP_MASK		MISSING
665 #define ERROR_INT_STATUS_WAKEUP_LSB		MISSING
666 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK	MISSING
667 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB	MISSING
668 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK	MISSING
669 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB	MISSING
670 #define COUNT_DEC_ADDRESS			MISSING
671 #define HOST_INT_STATUS_CPU_MASK		MISSING
672 #define HOST_INT_STATUS_CPU_LSB			MISSING
673 #define HOST_INT_STATUS_ERROR_MASK		MISSING
674 #define HOST_INT_STATUS_ERROR_LSB		MISSING
675 #define HOST_INT_STATUS_COUNTER_MASK		MISSING
676 #define HOST_INT_STATUS_COUNTER_LSB		MISSING
677 #define RX_LOOKAHEAD_VALID_ADDRESS		MISSING
678 #define WINDOW_DATA_ADDRESS			MISSING
679 #define WINDOW_READ_ADDR_ADDRESS		MISSING
680 #define WINDOW_WRITE_ADDR_ADDRESS		MISSING
681 
682 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
683 
684 #endif /* _HW_H_ */
685