1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HW_H_ 19 #define _HW_H_ 20 21 #include "targaddrs.h" 22 23 #define ATH10K_FW_DIR "ath10k" 24 25 #define QCA988X_2_0_DEVICE_ID (0x003c) 26 #define QCA6164_2_1_DEVICE_ID (0x0041) 27 #define QCA6174_2_1_DEVICE_ID (0x003e) 28 #define QCA99X0_2_0_DEVICE_ID (0x0040) 29 #define QCA9888_2_0_DEVICE_ID (0x0056) 30 #define QCA9984_1_0_DEVICE_ID (0x0046) 31 #define QCA9377_1_0_DEVICE_ID (0x0042) 32 #define QCA9887_1_0_DEVICE_ID (0x0050) 33 34 /* QCA988X 1.0 definitions (unsupported) */ 35 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 36 37 /* QCA988X 2.0 definitions */ 38 #define QCA988X_HW_2_0_VERSION 0x4100016c 39 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 40 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 41 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 43 44 /* QCA9887 1.0 definitions */ 45 #define QCA9887_HW_1_0_VERSION 0x4100016d 46 #define QCA9887_HW_1_0_CHIP_ID_REV 0 47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" 48 #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" 49 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 50 51 /* QCA6174 target BMI version signatures */ 52 #define QCA6174_HW_1_0_VERSION 0x05000000 53 #define QCA6174_HW_1_1_VERSION 0x05000001 54 #define QCA6174_HW_1_3_VERSION 0x05000003 55 #define QCA6174_HW_2_1_VERSION 0x05010000 56 #define QCA6174_HW_3_0_VERSION 0x05020000 57 #define QCA6174_HW_3_2_VERSION 0x05030000 58 59 /* QCA9377 target BMI version signatures */ 60 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 61 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 62 63 enum qca6174_pci_rev { 64 QCA6174_PCI_REV_1_1 = 0x11, 65 QCA6174_PCI_REV_1_3 = 0x13, 66 QCA6174_PCI_REV_2_0 = 0x20, 67 QCA6174_PCI_REV_3_0 = 0x30, 68 }; 69 70 enum qca6174_chip_id_rev { 71 QCA6174_HW_1_0_CHIP_ID_REV = 0, 72 QCA6174_HW_1_1_CHIP_ID_REV = 1, 73 QCA6174_HW_1_3_CHIP_ID_REV = 2, 74 QCA6174_HW_2_1_CHIP_ID_REV = 4, 75 QCA6174_HW_2_2_CHIP_ID_REV = 5, 76 QCA6174_HW_3_0_CHIP_ID_REV = 8, 77 QCA6174_HW_3_1_CHIP_ID_REV = 9, 78 QCA6174_HW_3_2_CHIP_ID_REV = 10, 79 }; 80 81 enum qca9377_chip_id_rev { 82 QCA9377_HW_1_0_CHIP_ID_REV = 0x0, 83 QCA9377_HW_1_1_CHIP_ID_REV = 0x1, 84 }; 85 86 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" 87 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 88 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 89 90 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" 91 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 92 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 93 94 /* QCA99X0 1.0 definitions (unsupported) */ 95 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 96 97 /* QCA99X0 2.0 definitions */ 98 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 99 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 100 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" 101 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" 102 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 103 104 /* QCA9984 1.0 defines */ 105 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 106 #define QCA9984_HW_DEV_TYPE 0xa 107 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 108 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" 109 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" 110 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 111 112 /* QCA9888 2.0 defines */ 113 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 114 #define QCA9888_HW_DEV_TYPE 0xc 115 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 116 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" 117 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" 118 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 119 120 /* QCA9377 1.0 definitions */ 121 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" 122 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" 123 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 124 125 /* QCA4019 1.0 definitions */ 126 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 127 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" 128 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" 129 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 130 131 #define ATH10K_FW_API2_FILE "firmware-2.bin" 132 #define ATH10K_FW_API3_FILE "firmware-3.bin" 133 134 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 135 #define ATH10K_FW_API4_FILE "firmware-4.bin" 136 137 /* HTT id conflict fix for management frames over HTT */ 138 #define ATH10K_FW_API5_FILE "firmware-5.bin" 139 140 #define ATH10K_FW_UTF_FILE "utf.bin" 141 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" 142 143 /* includes also the null byte */ 144 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 145 #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" 146 147 #define ATH10K_BOARD_API2_FILE "board-2.bin" 148 149 #define REG_DUMP_COUNT_QCA988X 60 150 151 struct ath10k_fw_ie { 152 __le32 id; 153 __le32 len; 154 u8 data[0]; 155 }; 156 157 enum ath10k_fw_ie_type { 158 ATH10K_FW_IE_FW_VERSION = 0, 159 ATH10K_FW_IE_TIMESTAMP = 1, 160 ATH10K_FW_IE_FEATURES = 2, 161 ATH10K_FW_IE_FW_IMAGE = 3, 162 ATH10K_FW_IE_OTP_IMAGE = 4, 163 164 /* WMI "operations" interface version, 32 bit value. Supported from 165 * FW API 4 and above. 166 */ 167 ATH10K_FW_IE_WMI_OP_VERSION = 5, 168 169 /* HTT "operations" interface version, 32 bit value. Supported from 170 * FW API 5 and above. 171 */ 172 ATH10K_FW_IE_HTT_OP_VERSION = 6, 173 174 /* Code swap image for firmware binary */ 175 ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, 176 }; 177 178 enum ath10k_fw_wmi_op_version { 179 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 180 181 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 182 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 183 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 184 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 185 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 186 ATH10K_FW_WMI_OP_VERSION_10_4 = 6, 187 188 /* keep last */ 189 ATH10K_FW_WMI_OP_VERSION_MAX, 190 }; 191 192 enum ath10k_fw_htt_op_version { 193 ATH10K_FW_HTT_OP_VERSION_UNSET = 0, 194 195 ATH10K_FW_HTT_OP_VERSION_MAIN = 1, 196 197 /* also used in 10.2 and 10.2.4 branches */ 198 ATH10K_FW_HTT_OP_VERSION_10_1 = 2, 199 200 ATH10K_FW_HTT_OP_VERSION_TLV = 3, 201 202 ATH10K_FW_HTT_OP_VERSION_10_4 = 4, 203 204 /* keep last */ 205 ATH10K_FW_HTT_OP_VERSION_MAX, 206 }; 207 208 enum ath10k_bd_ie_type { 209 /* contains sub IEs of enum ath10k_bd_ie_board_type */ 210 ATH10K_BD_IE_BOARD = 0, 211 }; 212 213 enum ath10k_bd_ie_board_type { 214 ATH10K_BD_IE_BOARD_NAME = 0, 215 ATH10K_BD_IE_BOARD_DATA = 1, 216 }; 217 218 enum ath10k_hw_rev { 219 ATH10K_HW_QCA988X, 220 ATH10K_HW_QCA6174, 221 ATH10K_HW_QCA99X0, 222 ATH10K_HW_QCA9888, 223 ATH10K_HW_QCA9984, 224 ATH10K_HW_QCA9377, 225 ATH10K_HW_QCA4019, 226 ATH10K_HW_QCA9887, 227 }; 228 229 struct ath10k_hw_regs { 230 u32 rtc_soc_base_address; 231 u32 rtc_wmac_base_address; 232 u32 soc_core_base_address; 233 u32 ce_wrapper_base_address; 234 u32 ce0_base_address; 235 u32 ce1_base_address; 236 u32 ce2_base_address; 237 u32 ce3_base_address; 238 u32 ce4_base_address; 239 u32 ce5_base_address; 240 u32 ce6_base_address; 241 u32 ce7_base_address; 242 u32 soc_reset_control_si0_rst_mask; 243 u32 soc_reset_control_ce_rst_mask; 244 u32 soc_chip_id_address; 245 u32 scratch_3_address; 246 u32 fw_indicator_address; 247 u32 pcie_local_base_address; 248 u32 ce_wrap_intr_sum_host_msi_lsb; 249 u32 ce_wrap_intr_sum_host_msi_mask; 250 u32 pcie_intr_fw_mask; 251 u32 pcie_intr_ce_mask_all; 252 u32 pcie_intr_clr_address; 253 }; 254 255 extern const struct ath10k_hw_regs qca988x_regs; 256 extern const struct ath10k_hw_regs qca6174_regs; 257 extern const struct ath10k_hw_regs qca99x0_regs; 258 extern const struct ath10k_hw_regs qca4019_regs; 259 260 struct ath10k_hw_values { 261 u32 rtc_state_val_on; 262 u8 ce_count; 263 u8 msi_assign_ce_max; 264 u8 num_target_ce_config_wlan; 265 u16 ce_desc_meta_data_mask; 266 u8 ce_desc_meta_data_lsb; 267 }; 268 269 extern const struct ath10k_hw_values qca988x_values; 270 extern const struct ath10k_hw_values qca6174_values; 271 extern const struct ath10k_hw_values qca99x0_values; 272 extern const struct ath10k_hw_values qca9888_values; 273 extern const struct ath10k_hw_values qca4019_values; 274 275 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 276 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); 277 278 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 279 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) 280 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 281 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) 282 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) 283 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) 284 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) 285 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) 286 287 /* Known pecularities: 288 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 289 * - raw have FCS, nwifi doesn't 290 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 291 * param, llc/snap) are aligned to 4byte boundaries each */ 292 enum ath10k_hw_txrx_mode { 293 ATH10K_HW_TXRX_RAW = 0, 294 295 /* Native Wifi decap mode is used to align IP frames to 4-byte 296 * boundaries and avoid a very expensive re-alignment in mac80211. 297 */ 298 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 299 ATH10K_HW_TXRX_ETHERNET = 2, 300 301 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 302 ATH10K_HW_TXRX_MGMT = 3, 303 }; 304 305 enum ath10k_mcast2ucast_mode { 306 ATH10K_MCAST2UCAST_DISABLED = 0, 307 ATH10K_MCAST2UCAST_ENABLED = 1, 308 }; 309 310 enum ath10k_hw_rate_ofdm { 311 ATH10K_HW_RATE_OFDM_48M = 0, 312 ATH10K_HW_RATE_OFDM_24M, 313 ATH10K_HW_RATE_OFDM_12M, 314 ATH10K_HW_RATE_OFDM_6M, 315 ATH10K_HW_RATE_OFDM_54M, 316 ATH10K_HW_RATE_OFDM_36M, 317 ATH10K_HW_RATE_OFDM_18M, 318 ATH10K_HW_RATE_OFDM_9M, 319 }; 320 321 enum ath10k_hw_rate_cck { 322 ATH10K_HW_RATE_CCK_LP_11M = 0, 323 ATH10K_HW_RATE_CCK_LP_5_5M, 324 ATH10K_HW_RATE_CCK_LP_2M, 325 ATH10K_HW_RATE_CCK_LP_1M, 326 ATH10K_HW_RATE_CCK_SP_11M, 327 ATH10K_HW_RATE_CCK_SP_5_5M, 328 ATH10K_HW_RATE_CCK_SP_2M, 329 }; 330 331 enum ath10k_hw_rate_rev2_cck { 332 ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, 333 ATH10K_HW_RATE_REV2_CCK_LP_2M, 334 ATH10K_HW_RATE_REV2_CCK_LP_5_5M, 335 ATH10K_HW_RATE_REV2_CCK_LP_11M, 336 ATH10K_HW_RATE_REV2_CCK_SP_2M, 337 ATH10K_HW_RATE_REV2_CCK_SP_5_5M, 338 ATH10K_HW_RATE_REV2_CCK_SP_11M, 339 }; 340 341 enum ath10k_hw_4addr_pad { 342 ATH10K_HW_4ADDR_PAD_AFTER, 343 ATH10K_HW_4ADDR_PAD_BEFORE, 344 }; 345 346 enum ath10k_hw_cc_wraparound_type { 347 ATH10K_HW_CC_WRAP_DISABLED = 0, 348 349 /* This type is when the HW chip has a quirky Cycle Counter 350 * wraparound which resets to 0x7fffffff instead of 0. All 351 * other CC related counters (e.g. Rx Clear Count) are divided 352 * by 2 so they never wraparound themselves. 353 */ 354 ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, 355 356 /* Each hw counter wrapsaround independently. When the 357 * counter overflows the repestive counter is right shifted 358 * by 1, i.e reset to 0x7fffffff, and other counters will be 359 * running unaffected. In this type of wraparound, it should 360 * be possible to report accurate Rx busy time unlike the 361 * first type. 362 */ 363 ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, 364 }; 365 366 /* Target specific defines for MAIN firmware */ 367 #define TARGET_NUM_VDEVS 8 368 #define TARGET_NUM_PEER_AST 2 369 #define TARGET_NUM_WDS_ENTRIES 32 370 #define TARGET_DMA_BURST_SIZE 0 371 #define TARGET_MAC_AGGR_DELIM 0 372 #define TARGET_AST_SKID_LIMIT 16 373 #define TARGET_NUM_STATIONS 16 374 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 375 (TARGET_NUM_VDEVS)) 376 #define TARGET_NUM_OFFLOAD_PEERS 0 377 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 378 #define TARGET_NUM_PEER_KEYS 2 379 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 380 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 381 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 382 #define TARGET_RX_TIMEOUT_LO_PRI 100 383 #define TARGET_RX_TIMEOUT_HI_PRI 40 384 385 #define TARGET_SCAN_MAX_PENDING_REQS 4 386 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 387 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 388 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 389 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 390 #define TARGET_NUM_MCAST_GROUPS 0 391 #define TARGET_NUM_MCAST_TABLE_ELEMS 0 392 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 393 #define TARGET_TX_DBG_LOG_SIZE 1024 394 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 395 #define TARGET_VOW_CONFIG 0 396 #define TARGET_NUM_MSDU_DESC (1024 + 400) 397 #define TARGET_MAX_FRAG_ENTRIES 0 398 399 /* Target specific defines for 10.X firmware */ 400 #define TARGET_10X_NUM_VDEVS 16 401 #define TARGET_10X_NUM_PEER_AST 2 402 #define TARGET_10X_NUM_WDS_ENTRIES 32 403 #define TARGET_10X_DMA_BURST_SIZE 0 404 #define TARGET_10X_MAC_AGGR_DELIM 0 405 #define TARGET_10X_AST_SKID_LIMIT 128 406 #define TARGET_10X_NUM_STATIONS 128 407 #define TARGET_10X_TX_STATS_NUM_STATIONS 118 408 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 409 (TARGET_10X_NUM_VDEVS)) 410 #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ 411 (TARGET_10X_NUM_VDEVS)) 412 #define TARGET_10X_NUM_OFFLOAD_PEERS 0 413 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 414 #define TARGET_10X_NUM_PEER_KEYS 2 415 #define TARGET_10X_NUM_TIDS_MAX 256 416 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 417 (TARGET_10X_NUM_PEERS) * 2) 418 #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 419 (TARGET_10X_TX_STATS_NUM_PEERS) * 2) 420 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 421 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 422 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 423 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 424 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 425 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 426 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 427 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 428 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 429 #define TARGET_10X_NUM_MCAST_GROUPS 0 430 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 431 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 432 #define TARGET_10X_TX_DBG_LOG_SIZE 1024 433 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 434 #define TARGET_10X_VOW_CONFIG 0 435 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 436 #define TARGET_10X_MAX_FRAG_ENTRIES 0 437 438 /* 10.2 parameters */ 439 #define TARGET_10_2_DMA_BURST_SIZE 0 440 441 /* Target specific defines for WMI-TLV firmware */ 442 #define TARGET_TLV_NUM_VDEVS 4 443 #define TARGET_TLV_NUM_STATIONS 32 444 #define TARGET_TLV_NUM_PEERS 35 445 #define TARGET_TLV_NUM_TDLS_VDEVS 1 446 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 447 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 448 #define TARGET_TLV_NUM_WOW_PATTERNS 22 449 450 /* Diagnostic Window */ 451 #define CE_DIAG_PIPE 7 452 453 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan 454 455 /* Target specific defines for 10.4 firmware */ 456 #define TARGET_10_4_NUM_VDEVS 16 457 #define TARGET_10_4_NUM_STATIONS 32 458 #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ 459 (TARGET_10_4_NUM_VDEVS)) 460 #define TARGET_10_4_ACTIVE_PEERS 0 461 462 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 463 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 464 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 465 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 466 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 467 #define TARGET_10_4_NUM_PEER_KEYS 2 468 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) 469 #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) 470 #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 471 #define TARGET_10_4_AST_SKID_LIMIT 32 472 473 /* 100 ms for video, best-effort, and background */ 474 #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 475 476 /* 40 ms for voice */ 477 #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 478 479 #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 480 #define TARGET_10_4_SCAN_MAX_REQS 4 481 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 482 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 483 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 484 485 /* Note: mcast to ucast is disabled by default */ 486 #define TARGET_10_4_NUM_MCAST_GROUPS 0 487 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 488 #define TARGET_10_4_MCAST2UCAST_MODE 0 489 490 #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 491 #define TARGET_10_4_NUM_WDS_ENTRIES 32 492 #define TARGET_10_4_DMA_BURST_SIZE 0 493 #define TARGET_10_4_MAC_AGGR_DELIM 0 494 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 495 #define TARGET_10_4_VOW_CONFIG 0 496 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 497 #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 498 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 499 #define TARGET_10_4_SMART_ANT_CAP 0 500 #define TARGET_10_4_BK_MIN_FREE 0 501 #define TARGET_10_4_BE_MIN_FREE 0 502 #define TARGET_10_4_VI_MIN_FREE 0 503 #define TARGET_10_4_VO_MIN_FREE 0 504 #define TARGET_10_4_RX_BATCH_MODE 1 505 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 506 #define TARGET_10_4_ATF_CONFIG 0 507 #define TARGET_10_4_IPHDR_PAD_CONFIG 1 508 #define TARGET_10_4_QWRAP_CONFIG 0 509 510 /* Number of Copy Engines supported */ 511 #define CE_COUNT ar->hw_values->ce_count 512 513 /* 514 * Granted MSIs are assigned as follows: 515 * Firmware uses the first 516 * Remaining MSIs, if any, are used by Copy Engines 517 * This mapping is known to both Target firmware and Host software. 518 * It may be changed as long as Host and Target are kept in sync. 519 */ 520 /* MSI for firmware (errors, etc.) */ 521 #define MSI_ASSIGN_FW 0 522 523 /* MSIs for Copy Engines */ 524 #define MSI_ASSIGN_CE_INITIAL 1 525 #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max 526 527 /* as of IP3.7.1 */ 528 #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on 529 530 #define RTC_STATE_V_LSB 0 531 #define RTC_STATE_V_MASK 0x00000007 532 #define RTC_STATE_ADDRESS 0x0000 533 #define PCIE_SOC_WAKE_V_MASK 0x00000001 534 #define PCIE_SOC_WAKE_ADDRESS 0x0004 535 #define PCIE_SOC_WAKE_RESET 0x00000000 536 #define SOC_GLOBAL_RESET_ADDRESS 0x0008 537 538 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 539 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 540 #define MAC_COEX_BASE_ADDRESS 0x00006000 541 #define BT_COEX_BASE_ADDRESS 0x00007000 542 #define SOC_PCIE_BASE_ADDRESS 0x00008000 543 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 544 #define WLAN_UART_BASE_ADDRESS 0x0000c000 545 #define WLAN_SI_BASE_ADDRESS 0x00010000 546 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 547 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 548 #define WLAN_MAC_BASE_ADDRESS 0x00020000 549 #define EFUSE_BASE_ADDRESS 0x00030000 550 #define FPGA_REG_BASE_ADDRESS 0x00039000 551 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 552 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 553 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address 554 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address 555 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address 556 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address 557 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address 558 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address 559 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address 560 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address 561 #define DBI_BASE_ADDRESS 0x00060000 562 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 563 #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address 564 565 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 566 #define SOC_RESET_CONTROL_OFFSET 0x00000000 567 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 568 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 569 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 570 #define SOC_CPU_CLOCK_OFFSET 0x00000020 571 #define SOC_CPU_CLOCK_STANDARD_LSB 0 572 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 573 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 574 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 575 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 576 #define SOC_LPO_CAL_OFFSET 0x000000e0 577 #define SOC_LPO_CAL_ENABLE_LSB 20 578 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 579 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 580 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 581 582 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 583 #define SOC_CHIP_ID_REV_LSB 8 584 #define SOC_CHIP_ID_REV_MASK 0x00000f00 585 586 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 587 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 588 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 589 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 590 591 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 592 #define WLAN_GPIO_PIN0_CONFIG_LSB 11 593 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 594 #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 595 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 596 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 597 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 598 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 599 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 600 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 601 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 602 603 #define CLOCK_GPIO_OFFSET 0xffffffff 604 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 605 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 606 607 #define SI_CONFIG_OFFSET 0x00000000 608 #define SI_CONFIG_ERR_INT_LSB 19 609 #define SI_CONFIG_ERR_INT_MASK 0x00080000 610 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 611 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 612 #define SI_CONFIG_I2C_LSB 16 613 #define SI_CONFIG_I2C_MASK 0x00010000 614 #define SI_CONFIG_POS_SAMPLE_LSB 7 615 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 616 #define SI_CONFIG_INACTIVE_DATA_LSB 5 617 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 618 #define SI_CONFIG_INACTIVE_CLK_LSB 4 619 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 620 #define SI_CONFIG_DIVIDER_LSB 0 621 #define SI_CONFIG_DIVIDER_MASK 0x0000000f 622 #define SI_CS_OFFSET 0x00000004 623 #define SI_CS_DONE_ERR_LSB 10 624 #define SI_CS_DONE_ERR_MASK 0x00000400 625 #define SI_CS_DONE_INT_LSB 9 626 #define SI_CS_DONE_INT_MASK 0x00000200 627 #define SI_CS_START_LSB 8 628 #define SI_CS_START_MASK 0x00000100 629 #define SI_CS_RX_CNT_LSB 4 630 #define SI_CS_RX_CNT_MASK 0x000000f0 631 #define SI_CS_TX_CNT_LSB 0 632 #define SI_CS_TX_CNT_MASK 0x0000000f 633 634 #define SI_TX_DATA0_OFFSET 0x00000008 635 #define SI_TX_DATA1_OFFSET 0x0000000c 636 #define SI_RX_DATA0_OFFSET 0x00000010 637 #define SI_RX_DATA1_OFFSET 0x00000014 638 639 #define CORE_CTRL_CPU_INTR_MASK 0x00002000 640 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 641 #define CORE_CTRL_ADDRESS 0x0000 642 #define PCIE_INTR_ENABLE_ADDRESS 0x0008 643 #define PCIE_INTR_CAUSE_ADDRESS 0x000c 644 #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address 645 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 646 #define CPU_INTR_ADDRESS 0x0010 647 648 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) 649 650 /* Firmware indications to the Host via SCRATCH_3 register. */ 651 #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address 652 #define FW_IND_EVENT_PENDING 1 653 #define FW_IND_INITIALIZED 2 654 #define FW_IND_HOST_READY 0x80000000 655 656 /* HOST_REG interrupt from firmware */ 657 #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask 658 #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all 659 660 #define DRAM_BASE_ADDRESS 0x00400000 661 662 #define PCIE_BAR_REG_ADDRESS 0x40030 663 664 #define MISSING 0 665 666 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 667 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 668 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 669 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 670 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 671 #define RESET_CONTROL_MBOX_RST_MASK MISSING 672 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 673 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 674 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 675 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 676 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 677 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 678 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 679 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 680 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 681 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 682 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 683 #define LOCAL_SCRATCH_OFFSET 0x18 684 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 685 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 686 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 687 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 688 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 689 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 690 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 691 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 692 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 693 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 694 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 695 #define MBOX_BASE_ADDRESS MISSING 696 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 697 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 698 #define INT_STATUS_ENABLE_CPU_LSB MISSING 699 #define INT_STATUS_ENABLE_CPU_MASK MISSING 700 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 701 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 702 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 703 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 704 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 705 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 706 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 707 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 708 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 709 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 710 #define INT_STATUS_ENABLE_ADDRESS MISSING 711 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 712 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 713 #define HOST_INT_STATUS_ADDRESS MISSING 714 #define CPU_INT_STATUS_ADDRESS MISSING 715 #define ERROR_INT_STATUS_ADDRESS MISSING 716 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 717 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 718 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 719 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 720 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 721 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 722 #define COUNT_DEC_ADDRESS MISSING 723 #define HOST_INT_STATUS_CPU_MASK MISSING 724 #define HOST_INT_STATUS_CPU_LSB MISSING 725 #define HOST_INT_STATUS_ERROR_MASK MISSING 726 #define HOST_INT_STATUS_ERROR_LSB MISSING 727 #define HOST_INT_STATUS_COUNTER_MASK MISSING 728 #define HOST_INT_STATUS_COUNTER_LSB MISSING 729 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 730 #define WINDOW_DATA_ADDRESS MISSING 731 #define WINDOW_READ_ADDR_ADDRESS MISSING 732 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 733 734 #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 735 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 736 #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 737 #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 738 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 739 740 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 741 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 742 #define QCA9887_EEPROM_ADDR_HI_LSB 8 743 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 744 #define QCA9887_EEPROM_ADDR_LO_LSB 16 745 746 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 747 748 #endif /* _HW_H_ */ 749