xref: /openbmc/linux/drivers/net/wireless/ath/ath10k/hw.c (revision 5d0e4d78)
1 /*
2  * Copyright (c) 2014-2015 Qualcomm Atheros, Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <linux/types.h>
18 #include <linux/bitops.h>
19 #include "core.h"
20 #include "hw.h"
21 #include "hif.h"
22 #include "wmi-ops.h"
23 #include "bmi.h"
24 
25 const struct ath10k_hw_regs qca988x_regs = {
26 	.rtc_soc_base_address		= 0x00004000,
27 	.rtc_wmac_base_address		= 0x00005000,
28 	.soc_core_base_address		= 0x00009000,
29 	.wlan_mac_base_address		= 0x00020000,
30 	.ce_wrapper_base_address	= 0x00057000,
31 	.ce0_base_address		= 0x00057400,
32 	.ce1_base_address		= 0x00057800,
33 	.ce2_base_address		= 0x00057c00,
34 	.ce3_base_address		= 0x00058000,
35 	.ce4_base_address		= 0x00058400,
36 	.ce5_base_address		= 0x00058800,
37 	.ce6_base_address		= 0x00058c00,
38 	.ce7_base_address		= 0x00059000,
39 	.soc_reset_control_si0_rst_mask	= 0x00000001,
40 	.soc_reset_control_ce_rst_mask	= 0x00040000,
41 	.soc_chip_id_address		= 0x000000ec,
42 	.scratch_3_address		= 0x00000030,
43 	.fw_indicator_address		= 0x00009030,
44 	.pcie_local_base_address	= 0x00080000,
45 	.ce_wrap_intr_sum_host_msi_lsb	= 0x00000008,
46 	.ce_wrap_intr_sum_host_msi_mask	= 0x0000ff00,
47 	.pcie_intr_fw_mask		= 0x00000400,
48 	.pcie_intr_ce_mask_all		= 0x0007f800,
49 	.pcie_intr_clr_address		= 0x00000014,
50 };
51 
52 const struct ath10k_hw_regs qca6174_regs = {
53 	.rtc_soc_base_address			= 0x00000800,
54 	.rtc_wmac_base_address			= 0x00001000,
55 	.soc_core_base_address			= 0x0003a000,
56 	.wlan_mac_base_address			= 0x00010000,
57 	.ce_wrapper_base_address		= 0x00034000,
58 	.ce0_base_address			= 0x00034400,
59 	.ce1_base_address			= 0x00034800,
60 	.ce2_base_address			= 0x00034c00,
61 	.ce3_base_address			= 0x00035000,
62 	.ce4_base_address			= 0x00035400,
63 	.ce5_base_address			= 0x00035800,
64 	.ce6_base_address			= 0x00035c00,
65 	.ce7_base_address			= 0x00036000,
66 	.soc_reset_control_si0_rst_mask		= 0x00000000,
67 	.soc_reset_control_ce_rst_mask		= 0x00000001,
68 	.soc_chip_id_address			= 0x000000f0,
69 	.scratch_3_address			= 0x00000028,
70 	.fw_indicator_address			= 0x0003a028,
71 	.pcie_local_base_address		= 0x00080000,
72 	.ce_wrap_intr_sum_host_msi_lsb		= 0x00000008,
73 	.ce_wrap_intr_sum_host_msi_mask		= 0x0000ff00,
74 	.pcie_intr_fw_mask			= 0x00000400,
75 	.pcie_intr_ce_mask_all			= 0x0007f800,
76 	.pcie_intr_clr_address			= 0x00000014,
77 	.cpu_pll_init_address			= 0x00404020,
78 	.cpu_speed_address			= 0x00404024,
79 	.core_clk_div_address			= 0x00404028,
80 };
81 
82 const struct ath10k_hw_regs qca99x0_regs = {
83 	.rtc_soc_base_address			= 0x00080000,
84 	.rtc_wmac_base_address			= 0x00000000,
85 	.soc_core_base_address			= 0x00082000,
86 	.wlan_mac_base_address			= 0x00030000,
87 	.ce_wrapper_base_address		= 0x0004d000,
88 	.ce0_base_address			= 0x0004a000,
89 	.ce1_base_address			= 0x0004a400,
90 	.ce2_base_address			= 0x0004a800,
91 	.ce3_base_address			= 0x0004ac00,
92 	.ce4_base_address			= 0x0004b000,
93 	.ce5_base_address			= 0x0004b400,
94 	.ce6_base_address			= 0x0004b800,
95 	.ce7_base_address			= 0x0004bc00,
96 	/* Note: qca99x0 supports upto 12 Copy Engines. Other than address of
97 	 * CE0 and CE1 no other copy engine is directly referred in the code.
98 	 * It is not really necessary to assign address for newly supported
99 	 * CEs in this address table.
100 	 *	Copy Engine		Address
101 	 *	CE8			0x0004c000
102 	 *	CE9			0x0004c400
103 	 *	CE10			0x0004c800
104 	 *	CE11			0x0004cc00
105 	 */
106 	.soc_reset_control_si0_rst_mask		= 0x00000001,
107 	.soc_reset_control_ce_rst_mask		= 0x00000100,
108 	.soc_chip_id_address			= 0x000000ec,
109 	.scratch_3_address			= 0x00040050,
110 	.fw_indicator_address			= 0x00040050,
111 	.pcie_local_base_address		= 0x00000000,
112 	.ce_wrap_intr_sum_host_msi_lsb		= 0x0000000c,
113 	.ce_wrap_intr_sum_host_msi_mask		= 0x00fff000,
114 	.pcie_intr_fw_mask			= 0x00100000,
115 	.pcie_intr_ce_mask_all			= 0x000fff00,
116 	.pcie_intr_clr_address			= 0x00000010,
117 };
118 
119 const struct ath10k_hw_regs qca4019_regs = {
120 	.rtc_soc_base_address                   = 0x00080000,
121 	.soc_core_base_address                  = 0x00082000,
122 	.wlan_mac_base_address                  = 0x00030000,
123 	.ce_wrapper_base_address                = 0x0004d000,
124 	.ce0_base_address                       = 0x0004a000,
125 	.ce1_base_address                       = 0x0004a400,
126 	.ce2_base_address                       = 0x0004a800,
127 	.ce3_base_address                       = 0x0004ac00,
128 	.ce4_base_address                       = 0x0004b000,
129 	.ce5_base_address                       = 0x0004b400,
130 	.ce6_base_address                       = 0x0004b800,
131 	.ce7_base_address                       = 0x0004bc00,
132 	/* qca4019 supports upto 12 copy engines. Since base address
133 	 * of ce8 to ce11 are not directly referred in the code,
134 	 * no need have them in separate members in this table.
135 	 *      Copy Engine             Address
136 	 *      CE8                     0x0004c000
137 	 *      CE9                     0x0004c400
138 	 *      CE10                    0x0004c800
139 	 *      CE11                    0x0004cc00
140 	 */
141 	.soc_reset_control_si0_rst_mask         = 0x00000001,
142 	.soc_reset_control_ce_rst_mask          = 0x00000100,
143 	.soc_chip_id_address                    = 0x000000ec,
144 	.fw_indicator_address                   = 0x0004f00c,
145 	.ce_wrap_intr_sum_host_msi_lsb          = 0x0000000c,
146 	.ce_wrap_intr_sum_host_msi_mask         = 0x00fff000,
147 	.pcie_intr_fw_mask                      = 0x00100000,
148 	.pcie_intr_ce_mask_all                  = 0x000fff00,
149 	.pcie_intr_clr_address                  = 0x00000010,
150 };
151 
152 const struct ath10k_hw_values qca988x_values = {
153 	.rtc_state_val_on		= 3,
154 	.ce_count			= 8,
155 	.msi_assign_ce_max		= 7,
156 	.num_target_ce_config_wlan	= 7,
157 	.ce_desc_meta_data_mask		= 0xFFFC,
158 	.ce_desc_meta_data_lsb		= 2,
159 };
160 
161 const struct ath10k_hw_values qca6174_values = {
162 	.rtc_state_val_on		= 3,
163 	.ce_count			= 8,
164 	.msi_assign_ce_max		= 7,
165 	.num_target_ce_config_wlan	= 7,
166 	.ce_desc_meta_data_mask		= 0xFFFC,
167 	.ce_desc_meta_data_lsb		= 2,
168 };
169 
170 const struct ath10k_hw_values qca99x0_values = {
171 	.rtc_state_val_on		= 5,
172 	.ce_count			= 12,
173 	.msi_assign_ce_max		= 12,
174 	.num_target_ce_config_wlan	= 10,
175 	.ce_desc_meta_data_mask		= 0xFFF0,
176 	.ce_desc_meta_data_lsb		= 4,
177 };
178 
179 const struct ath10k_hw_values qca9888_values = {
180 	.rtc_state_val_on		= 3,
181 	.ce_count			= 12,
182 	.msi_assign_ce_max		= 12,
183 	.num_target_ce_config_wlan	= 10,
184 	.ce_desc_meta_data_mask		= 0xFFF0,
185 	.ce_desc_meta_data_lsb		= 4,
186 };
187 
188 const struct ath10k_hw_values qca4019_values = {
189 	.ce_count                       = 12,
190 	.num_target_ce_config_wlan      = 10,
191 	.ce_desc_meta_data_mask         = 0xFFF0,
192 	.ce_desc_meta_data_lsb          = 4,
193 };
194 
195 static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {
196 	.msb	= 0x00000010,
197 	.lsb	= 0x00000010,
198 	.mask	= GENMASK(16, 16),
199 };
200 
201 static struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = {
202 	.msb	= 0x00000011,
203 	.lsb	= 0x00000011,
204 	.mask	= GENMASK(17, 17),
205 };
206 
207 static struct ath10k_hw_ce_regs_addr_map qcax_dmax = {
208 	.msb	= 0x0000000f,
209 	.lsb	= 0x00000000,
210 	.mask	= GENMASK(15, 0),
211 };
212 
213 static struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = {
214 	.addr		= 0x00000010,
215 	.hw_mask	= 0x0007ffff,
216 	.sw_mask	= 0x0007ffff,
217 	.hw_wr_mask	= 0x00000000,
218 	.sw_wr_mask	= 0x0007ffff,
219 	.reset_mask	= 0xffffffff,
220 	.reset		= 0x00000080,
221 	.src_ring	= &qcax_src_ring,
222 	.dst_ring	= &qcax_dst_ring,
223 	.dmax		= &qcax_dmax,
224 };
225 
226 static struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = {
227 	.msb	= 0x00000003,
228 	.lsb	= 0x00000003,
229 	.mask	= GENMASK(3, 3),
230 };
231 
232 static struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = {
233 	.msb		= 0x00000000,
234 	.mask		= GENMASK(0, 0),
235 	.status_reset	= 0x00000000,
236 	.status		= &qcax_cmd_halt_status,
237 };
238 
239 static struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = {
240 	.msb	= 0x00000000,
241 	.lsb	= 0x00000000,
242 	.mask	= GENMASK(0, 0),
243 };
244 
245 static struct ath10k_hw_ce_host_ie qcax_host_ie = {
246 	.copy_complete_reset	= 0x00000000,
247 	.copy_complete		= &qcax_host_ie_cc,
248 };
249 
250 static struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = {
251 	.dstr_lmask	= 0x00000010,
252 	.dstr_hmask	= 0x00000008,
253 	.srcr_lmask	= 0x00000004,
254 	.srcr_hmask	= 0x00000002,
255 	.cc_mask	= 0x00000001,
256 	.wm_mask	= 0x0000001E,
257 	.addr		= 0x00000030,
258 };
259 
260 static struct ath10k_hw_ce_misc_regs qcax_misc_reg = {
261 	.axi_err	= 0x00000400,
262 	.dstr_add_err	= 0x00000200,
263 	.srcr_len_err	= 0x00000100,
264 	.dstr_mlen_vio	= 0x00000080,
265 	.dstr_overflow	= 0x00000040,
266 	.srcr_overflow	= 0x00000020,
267 	.err_mask	= 0x000007E0,
268 	.addr		= 0x00000038,
269 };
270 
271 static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = {
272 	.msb    = 0x0000001f,
273 	.lsb	= 0x00000010,
274 	.mask	= GENMASK(31, 16),
275 };
276 
277 static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = {
278 	.msb	= 0x0000000f,
279 	.lsb	= 0x00000000,
280 	.mask	= GENMASK(15, 0),
281 };
282 
283 static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = {
284 	.addr		= 0x0000004c,
285 	.low_rst	= 0x00000000,
286 	.high_rst	= 0x00000000,
287 	.wm_low		= &qcax_src_wm_low,
288 	.wm_high        = &qcax_src_wm_high,
289 };
290 
291 static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = {
292 	.lsb	= 0x00000010,
293 	.mask	= GENMASK(31, 16),
294 };
295 
296 static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = {
297 	.msb	= 0x0000000f,
298 	.lsb	= 0x00000000,
299 	.mask	= GENMASK(15, 0),
300 };
301 
302 static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = {
303 	.addr		= 0x00000050,
304 	.low_rst	= 0x00000000,
305 	.high_rst	= 0x00000000,
306 	.wm_low		= &qcax_dst_wm_low,
307 	.wm_high	= &qcax_dst_wm_high,
308 };
309 
310 struct ath10k_hw_ce_regs qcax_ce_regs = {
311 	.sr_base_addr		= 0x00000000,
312 	.sr_size_addr		= 0x00000004,
313 	.dr_base_addr		= 0x00000008,
314 	.dr_size_addr		= 0x0000000c,
315 	.ce_cmd_addr		= 0x00000018,
316 	.misc_ie_addr		= 0x00000034,
317 	.sr_wr_index_addr	= 0x0000003c,
318 	.dst_wr_index_addr	= 0x00000040,
319 	.current_srri_addr	= 0x00000044,
320 	.current_drri_addr	= 0x00000048,
321 	.host_ie_addr		= 0x0000002c,
322 	.ctrl1_regs		= &qcax_ctrl1,
323 	.cmd_halt		= &qcax_cmd_halt,
324 	.host_ie		= &qcax_host_ie,
325 	.wm_regs		= &qcax_wm_reg,
326 	.misc_regs		= &qcax_misc_reg,
327 	.wm_srcr		= &qcax_wm_src_ring,
328 	.wm_dstr                = &qcax_wm_dst_ring,
329 };
330 
331 const struct ath10k_hw_clk_params qca6174_clk[ATH10K_HW_REFCLK_COUNT] = {
332 	{
333 		.refclk = 48000000,
334 		.div = 0xe,
335 		.rnfrac = 0x2aaa8,
336 		.settle_time = 2400,
337 		.refdiv = 0,
338 		.outdiv = 1,
339 	},
340 	{
341 		.refclk = 19200000,
342 		.div = 0x24,
343 		.rnfrac = 0x2aaa8,
344 		.settle_time = 960,
345 		.refdiv = 0,
346 		.outdiv = 1,
347 	},
348 	{
349 		.refclk = 24000000,
350 		.div = 0x1d,
351 		.rnfrac = 0x15551,
352 		.settle_time = 1200,
353 		.refdiv = 0,
354 		.outdiv = 1,
355 	},
356 	{
357 		.refclk = 26000000,
358 		.div = 0x1b,
359 		.rnfrac = 0x4ec4,
360 		.settle_time = 1300,
361 		.refdiv = 0,
362 		.outdiv = 1,
363 	},
364 	{
365 		.refclk = 37400000,
366 		.div = 0x12,
367 		.rnfrac = 0x34b49,
368 		.settle_time = 1870,
369 		.refdiv = 0,
370 		.outdiv = 1,
371 	},
372 	{
373 		.refclk = 38400000,
374 		.div = 0x12,
375 		.rnfrac = 0x15551,
376 		.settle_time = 1920,
377 		.refdiv = 0,
378 		.outdiv = 1,
379 	},
380 	{
381 		.refclk = 40000000,
382 		.div = 0x12,
383 		.rnfrac = 0x26665,
384 		.settle_time = 2000,
385 		.refdiv = 0,
386 		.outdiv = 1,
387 	},
388 	{
389 		.refclk = 52000000,
390 		.div = 0x1b,
391 		.rnfrac = 0x4ec4,
392 		.settle_time = 2600,
393 		.refdiv = 0,
394 		.outdiv = 1,
395 	},
396 };
397 
398 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
399 				u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
400 {
401 	u32 cc_fix = 0;
402 	u32 rcc_fix = 0;
403 	enum ath10k_hw_cc_wraparound_type wraparound_type;
404 
405 	survey->filled |= SURVEY_INFO_TIME |
406 			  SURVEY_INFO_TIME_BUSY;
407 
408 	wraparound_type = ar->hw_params.cc_wraparound_type;
409 
410 	if (cc < cc_prev || rcc < rcc_prev) {
411 		switch (wraparound_type) {
412 		case ATH10K_HW_CC_WRAP_SHIFTED_ALL:
413 			if (cc < cc_prev) {
414 				cc_fix = 0x7fffffff;
415 				survey->filled &= ~SURVEY_INFO_TIME_BUSY;
416 			}
417 			break;
418 		case ATH10K_HW_CC_WRAP_SHIFTED_EACH:
419 			if (cc < cc_prev)
420 				cc_fix = 0x7fffffff;
421 
422 			if (rcc < rcc_prev)
423 				rcc_fix = 0x7fffffff;
424 			break;
425 		case ATH10K_HW_CC_WRAP_DISABLED:
426 			break;
427 		}
428 	}
429 
430 	cc -= cc_prev - cc_fix;
431 	rcc -= rcc_prev - rcc_fix;
432 
433 	survey->time = CCNT_TO_MSEC(ar, cc);
434 	survey->time_busy = CCNT_TO_MSEC(ar, rcc);
435 }
436 
437 /* The firmware does not support setting the coverage class. Instead this
438  * function monitors and modifies the corresponding MAC registers.
439  */
440 static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar,
441 						 s16 value)
442 {
443 	u32 slottime_reg;
444 	u32 slottime;
445 	u32 timeout_reg;
446 	u32 ack_timeout;
447 	u32 cts_timeout;
448 	u32 phyclk_reg;
449 	u32 phyclk;
450 	u64 fw_dbglog_mask;
451 	u32 fw_dbglog_level;
452 
453 	mutex_lock(&ar->conf_mutex);
454 
455 	/* Only modify registers if the core is started. */
456 	if ((ar->state != ATH10K_STATE_ON) &&
457 	    (ar->state != ATH10K_STATE_RESTARTED))
458 		goto unlock;
459 
460 	/* Retrieve the current values of the two registers that need to be
461 	 * adjusted.
462 	 */
463 	slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
464 					     WAVE1_PCU_GBL_IFS_SLOT);
465 	timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
466 					    WAVE1_PCU_ACK_CTS_TIMEOUT);
467 	phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
468 					   WAVE1_PHYCLK);
469 	phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1;
470 
471 	if (value < 0)
472 		value = ar->fw_coverage.coverage_class;
473 
474 	/* Break out if the coverage class and registers have the expected
475 	 * value.
476 	 */
477 	if (value == ar->fw_coverage.coverage_class &&
478 	    slottime_reg == ar->fw_coverage.reg_slottime_conf &&
479 	    timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf &&
480 	    phyclk_reg == ar->fw_coverage.reg_phyclk)
481 		goto unlock;
482 
483 	/* Store new initial register values from the firmware. */
484 	if (slottime_reg != ar->fw_coverage.reg_slottime_conf)
485 		ar->fw_coverage.reg_slottime_orig = slottime_reg;
486 	if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf)
487 		ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg;
488 	ar->fw_coverage.reg_phyclk = phyclk_reg;
489 
490 	/* Calculat new value based on the (original) firmware calculation. */
491 	slottime_reg = ar->fw_coverage.reg_slottime_orig;
492 	timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig;
493 
494 	/* Do some sanity checks on the slottime register. */
495 	if (slottime_reg % phyclk) {
496 		ath10k_warn(ar,
497 			    "failed to set coverage class: expected integer microsecond value in register\n");
498 
499 		goto store_regs;
500 	}
501 
502 	slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
503 	slottime = slottime / phyclk;
504 	if (slottime != 9 && slottime != 20) {
505 		ath10k_warn(ar,
506 			    "failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n",
507 			    slottime);
508 
509 		goto store_regs;
510 	}
511 
512 	/* Recalculate the register values by adding the additional propagation
513 	 * delay (3us per coverage class).
514 	 */
515 
516 	slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
517 	slottime += value * 3 * phyclk;
518 	slottime = min_t(u32, slottime, WAVE1_PCU_GBL_IFS_SLOT_MAX);
519 	slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT);
520 	slottime_reg = (slottime_reg & ~WAVE1_PCU_GBL_IFS_SLOT_MASK) | slottime;
521 
522 	/* Update ack timeout (lower halfword). */
523 	ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
524 	ack_timeout += 3 * value * phyclk;
525 	ack_timeout = min_t(u32, ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
526 	ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
527 
528 	/* Update cts timeout (upper halfword). */
529 	cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
530 	cts_timeout += 3 * value * phyclk;
531 	cts_timeout = min_t(u32, cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
532 	cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
533 
534 	timeout_reg = ack_timeout | cts_timeout;
535 
536 	ath10k_hif_write32(ar,
537 			   WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_GBL_IFS_SLOT,
538 			   slottime_reg);
539 	ath10k_hif_write32(ar,
540 			   WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_ACK_CTS_TIMEOUT,
541 			   timeout_reg);
542 
543 	/* Ensure we have a debug level of WARN set for the case that the
544 	 * coverage class is larger than 0. This is important as we need to
545 	 * set the registers again if the firmware does an internal reset and
546 	 * this way we will be notified of the event.
547 	 */
548 	fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar);
549 	fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar);
550 
551 	if (value > 0) {
552 		if (fw_dbglog_level > ATH10K_DBGLOG_LEVEL_WARN)
553 			fw_dbglog_level = ATH10K_DBGLOG_LEVEL_WARN;
554 		fw_dbglog_mask = ~0;
555 	}
556 
557 	ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level);
558 
559 store_regs:
560 	/* After an error we will not retry setting the coverage class. */
561 	spin_lock_bh(&ar->data_lock);
562 	ar->fw_coverage.coverage_class = value;
563 	spin_unlock_bh(&ar->data_lock);
564 
565 	ar->fw_coverage.reg_slottime_conf = slottime_reg;
566 	ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg;
567 
568 unlock:
569 	mutex_unlock(&ar->conf_mutex);
570 }
571 
572 /**
573  * ath10k_hw_qca6174_enable_pll_clock() - enable the qca6174 hw pll clock
574  * @ar: the ath10k blob
575  *
576  * This function is very hardware specific, the clock initialization
577  * steps is very sensitive and could lead to unknown crash, so they
578  * should be done in sequence.
579  *
580  * *** Be aware if you planned to refactor them. ***
581  *
582  * Return: 0 if successfully enable the pll, otherwise EINVAL
583  */
584 static int ath10k_hw_qca6174_enable_pll_clock(struct ath10k *ar)
585 {
586 	int ret, wait_limit;
587 	u32 clk_div_addr, pll_init_addr, speed_addr;
588 	u32 addr, reg_val, mem_val;
589 	struct ath10k_hw_params *hw;
590 	const struct ath10k_hw_clk_params *hw_clk;
591 
592 	hw = &ar->hw_params;
593 
594 	if (ar->regs->core_clk_div_address == 0 ||
595 	    ar->regs->cpu_pll_init_address == 0 ||
596 	    ar->regs->cpu_speed_address == 0)
597 		return -EINVAL;
598 
599 	clk_div_addr = ar->regs->core_clk_div_address;
600 	pll_init_addr = ar->regs->cpu_pll_init_address;
601 	speed_addr = ar->regs->cpu_speed_address;
602 
603 	/* Read efuse register to find out the right hw clock configuration */
604 	addr = (RTC_SOC_BASE_ADDRESS | EFUSE_OFFSET);
605 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
606 	if (ret)
607 		return -EINVAL;
608 
609 	/* sanitize if the hw refclk index is out of the boundary */
610 	if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT)
611 		return -EINVAL;
612 
613 	hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)];
614 
615 	/* Set the rnfrac and outdiv params to bb_pll register */
616 	addr = (RTC_SOC_BASE_ADDRESS | BB_PLL_CONFIG_OFFSET);
617 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
618 	if (ret)
619 		return -EINVAL;
620 
621 	reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK);
622 	reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) |
623 		    SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV));
624 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
625 	if (ret)
626 		return -EINVAL;
627 
628 	/* Set the correct settle time value to pll_settle register */
629 	addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_SETTLE_OFFSET);
630 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
631 	if (ret)
632 		return -EINVAL;
633 
634 	reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK;
635 	reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME);
636 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
637 	if (ret)
638 		return -EINVAL;
639 
640 	/* Set the clock_ctrl div to core_clk_ctrl register */
641 	addr = (RTC_SOC_BASE_ADDRESS | SOC_CORE_CLK_CTRL_OFFSET);
642 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
643 	if (ret)
644 		return -EINVAL;
645 
646 	reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK;
647 	reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV);
648 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
649 	if (ret)
650 		return -EINVAL;
651 
652 	/* Set the clock_div register */
653 	mem_val = 1;
654 	ret = ath10k_bmi_write_memory(ar, clk_div_addr, &mem_val,
655 				      sizeof(mem_val));
656 	if (ret)
657 		return -EINVAL;
658 
659 	/* Configure the pll_control register */
660 	addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);
661 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
662 	if (ret)
663 		return -EINVAL;
664 
665 	reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) |
666 		    SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) |
667 		    SM(1, WLAN_PLL_CONTROL_NOPWD));
668 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
669 	if (ret)
670 		return -EINVAL;
671 
672 	/* busy wait (max 1s) the rtc_sync status register indicate ready */
673 	wait_limit = 100000;
674 	addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET);
675 	do {
676 		ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
677 		if (ret)
678 			return -EINVAL;
679 
680 		if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
681 			break;
682 
683 		wait_limit--;
684 		udelay(10);
685 
686 	} while (wait_limit > 0);
687 
688 	if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
689 		return -EINVAL;
690 
691 	/* Unset the pll_bypass in pll_control register */
692 	addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);
693 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
694 	if (ret)
695 		return -EINVAL;
696 
697 	reg_val &= ~WLAN_PLL_CONTROL_BYPASS_MASK;
698 	reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS);
699 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
700 	if (ret)
701 		return -EINVAL;
702 
703 	/* busy wait (max 1s) the rtc_sync status register indicate ready */
704 	wait_limit = 100000;
705 	addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET);
706 	do {
707 		ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
708 		if (ret)
709 			return -EINVAL;
710 
711 		if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
712 			break;
713 
714 		wait_limit--;
715 		udelay(10);
716 
717 	} while (wait_limit > 0);
718 
719 	if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
720 		return -EINVAL;
721 
722 	/* Enable the hardware cpu clock register */
723 	addr = (RTC_SOC_BASE_ADDRESS | SOC_CPU_CLOCK_OFFSET);
724 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
725 	if (ret)
726 		return -EINVAL;
727 
728 	reg_val &= ~SOC_CPU_CLOCK_STANDARD_MASK;
729 	reg_val |= SM(1, SOC_CPU_CLOCK_STANDARD);
730 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
731 	if (ret)
732 		return -EINVAL;
733 
734 	/* unset the nopwd from pll_control register */
735 	addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);
736 	ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
737 	if (ret)
738 		return -EINVAL;
739 
740 	reg_val &= ~WLAN_PLL_CONTROL_NOPWD_MASK;
741 	ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
742 	if (ret)
743 		return -EINVAL;
744 
745 	/* enable the pll_init register */
746 	mem_val = 1;
747 	ret = ath10k_bmi_write_memory(ar, pll_init_addr, &mem_val,
748 				      sizeof(mem_val));
749 	if (ret)
750 		return -EINVAL;
751 
752 	/* set the target clock frequency to speed register */
753 	ret = ath10k_bmi_write_memory(ar, speed_addr, &hw->target_cpu_freq,
754 				      sizeof(hw->target_cpu_freq));
755 	if (ret)
756 		return -EINVAL;
757 
758 	return 0;
759 }
760 
761 const struct ath10k_hw_ops qca988x_ops = {
762 	.set_coverage_class = ath10k_hw_qca988x_set_coverage_class,
763 };
764 
765 static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd)
766 {
767 	return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1),
768 		  RX_MSDU_END_INFO1_L3_HDR_PAD);
769 }
770 
771 const struct ath10k_hw_ops qca99x0_ops = {
772 	.rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
773 };
774 
775 const struct ath10k_hw_ops qca6174_ops = {
776 	.set_coverage_class = ath10k_hw_qca988x_set_coverage_class,
777 	.enable_pll_clk = ath10k_hw_qca6174_enable_pll_clock,
778 };
779