1 /* 2 * Copyright (c) 2014-2015 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/types.h> 18 #include <linux/bitops.h> 19 #include "core.h" 20 #include "hw.h" 21 #include "hif.h" 22 #include "wmi-ops.h" 23 #include "bmi.h" 24 25 const struct ath10k_hw_regs qca988x_regs = { 26 .rtc_soc_base_address = 0x00004000, 27 .rtc_wmac_base_address = 0x00005000, 28 .soc_core_base_address = 0x00009000, 29 .wlan_mac_base_address = 0x00020000, 30 .ce_wrapper_base_address = 0x00057000, 31 .ce0_base_address = 0x00057400, 32 .ce1_base_address = 0x00057800, 33 .ce2_base_address = 0x00057c00, 34 .ce3_base_address = 0x00058000, 35 .ce4_base_address = 0x00058400, 36 .ce5_base_address = 0x00058800, 37 .ce6_base_address = 0x00058c00, 38 .ce7_base_address = 0x00059000, 39 .soc_reset_control_si0_rst_mask = 0x00000001, 40 .soc_reset_control_ce_rst_mask = 0x00040000, 41 .soc_chip_id_address = 0x000000ec, 42 .scratch_3_address = 0x00000030, 43 .fw_indicator_address = 0x00009030, 44 .pcie_local_base_address = 0x00080000, 45 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008, 46 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00, 47 .pcie_intr_fw_mask = 0x00000400, 48 .pcie_intr_ce_mask_all = 0x0007f800, 49 .pcie_intr_clr_address = 0x00000014, 50 }; 51 52 const struct ath10k_hw_regs qca6174_regs = { 53 .rtc_soc_base_address = 0x00000800, 54 .rtc_wmac_base_address = 0x00001000, 55 .soc_core_base_address = 0x0003a000, 56 .wlan_mac_base_address = 0x00010000, 57 .ce_wrapper_base_address = 0x00034000, 58 .ce0_base_address = 0x00034400, 59 .ce1_base_address = 0x00034800, 60 .ce2_base_address = 0x00034c00, 61 .ce3_base_address = 0x00035000, 62 .ce4_base_address = 0x00035400, 63 .ce5_base_address = 0x00035800, 64 .ce6_base_address = 0x00035c00, 65 .ce7_base_address = 0x00036000, 66 .soc_reset_control_si0_rst_mask = 0x00000000, 67 .soc_reset_control_ce_rst_mask = 0x00000001, 68 .soc_chip_id_address = 0x000000f0, 69 .scratch_3_address = 0x00000028, 70 .fw_indicator_address = 0x0003a028, 71 .pcie_local_base_address = 0x00080000, 72 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008, 73 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00, 74 .pcie_intr_fw_mask = 0x00000400, 75 .pcie_intr_ce_mask_all = 0x0007f800, 76 .pcie_intr_clr_address = 0x00000014, 77 .cpu_pll_init_address = 0x00404020, 78 .cpu_speed_address = 0x00404024, 79 .core_clk_div_address = 0x00404028, 80 }; 81 82 const struct ath10k_hw_regs qca99x0_regs = { 83 .rtc_soc_base_address = 0x00080000, 84 .rtc_wmac_base_address = 0x00000000, 85 .soc_core_base_address = 0x00082000, 86 .wlan_mac_base_address = 0x00030000, 87 .ce_wrapper_base_address = 0x0004d000, 88 .ce0_base_address = 0x0004a000, 89 .ce1_base_address = 0x0004a400, 90 .ce2_base_address = 0x0004a800, 91 .ce3_base_address = 0x0004ac00, 92 .ce4_base_address = 0x0004b000, 93 .ce5_base_address = 0x0004b400, 94 .ce6_base_address = 0x0004b800, 95 .ce7_base_address = 0x0004bc00, 96 /* Note: qca99x0 supports upto 12 Copy Engines. Other than address of 97 * CE0 and CE1 no other copy engine is directly referred in the code. 98 * It is not really necessary to assign address for newly supported 99 * CEs in this address table. 100 * Copy Engine Address 101 * CE8 0x0004c000 102 * CE9 0x0004c400 103 * CE10 0x0004c800 104 * CE11 0x0004cc00 105 */ 106 .soc_reset_control_si0_rst_mask = 0x00000001, 107 .soc_reset_control_ce_rst_mask = 0x00000100, 108 .soc_chip_id_address = 0x000000ec, 109 .scratch_3_address = 0x00040050, 110 .fw_indicator_address = 0x00040050, 111 .pcie_local_base_address = 0x00000000, 112 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c, 113 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000, 114 .pcie_intr_fw_mask = 0x00100000, 115 .pcie_intr_ce_mask_all = 0x000fff00, 116 .pcie_intr_clr_address = 0x00000010, 117 }; 118 119 const struct ath10k_hw_regs qca4019_regs = { 120 .rtc_soc_base_address = 0x00080000, 121 .soc_core_base_address = 0x00082000, 122 .wlan_mac_base_address = 0x00030000, 123 .ce_wrapper_base_address = 0x0004d000, 124 .ce0_base_address = 0x0004a000, 125 .ce1_base_address = 0x0004a400, 126 .ce2_base_address = 0x0004a800, 127 .ce3_base_address = 0x0004ac00, 128 .ce4_base_address = 0x0004b000, 129 .ce5_base_address = 0x0004b400, 130 .ce6_base_address = 0x0004b800, 131 .ce7_base_address = 0x0004bc00, 132 /* qca4019 supports upto 12 copy engines. Since base address 133 * of ce8 to ce11 are not directly referred in the code, 134 * no need have them in separate members in this table. 135 * Copy Engine Address 136 * CE8 0x0004c000 137 * CE9 0x0004c400 138 * CE10 0x0004c800 139 * CE11 0x0004cc00 140 */ 141 .soc_reset_control_si0_rst_mask = 0x00000001, 142 .soc_reset_control_ce_rst_mask = 0x00000100, 143 .soc_chip_id_address = 0x000000ec, 144 .fw_indicator_address = 0x0004f00c, 145 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c, 146 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000, 147 .pcie_intr_fw_mask = 0x00100000, 148 .pcie_intr_ce_mask_all = 0x000fff00, 149 .pcie_intr_clr_address = 0x00000010, 150 }; 151 152 const struct ath10k_hw_values qca988x_values = { 153 .rtc_state_val_on = 3, 154 .ce_count = 8, 155 .msi_assign_ce_max = 7, 156 .num_target_ce_config_wlan = 7, 157 .ce_desc_meta_data_mask = 0xFFFC, 158 .ce_desc_meta_data_lsb = 2, 159 }; 160 161 const struct ath10k_hw_values qca6174_values = { 162 .rtc_state_val_on = 3, 163 .ce_count = 8, 164 .msi_assign_ce_max = 7, 165 .num_target_ce_config_wlan = 7, 166 .ce_desc_meta_data_mask = 0xFFFC, 167 .ce_desc_meta_data_lsb = 2, 168 }; 169 170 const struct ath10k_hw_values qca99x0_values = { 171 .rtc_state_val_on = 5, 172 .ce_count = 12, 173 .msi_assign_ce_max = 12, 174 .num_target_ce_config_wlan = 10, 175 .ce_desc_meta_data_mask = 0xFFF0, 176 .ce_desc_meta_data_lsb = 4, 177 }; 178 179 const struct ath10k_hw_values qca9888_values = { 180 .rtc_state_val_on = 3, 181 .ce_count = 12, 182 .msi_assign_ce_max = 12, 183 .num_target_ce_config_wlan = 10, 184 .ce_desc_meta_data_mask = 0xFFF0, 185 .ce_desc_meta_data_lsb = 4, 186 }; 187 188 const struct ath10k_hw_values qca4019_values = { 189 .ce_count = 12, 190 .num_target_ce_config_wlan = 10, 191 .ce_desc_meta_data_mask = 0xFFF0, 192 .ce_desc_meta_data_lsb = 4, 193 }; 194 195 const struct ath10k_hw_regs wcn3990_regs = { 196 .rtc_soc_base_address = 0x00000000, 197 .rtc_wmac_base_address = 0x00000000, 198 .soc_core_base_address = 0x00000000, 199 .ce_wrapper_base_address = 0x0024C000, 200 .ce0_base_address = 0x00240000, 201 .ce1_base_address = 0x00241000, 202 .ce2_base_address = 0x00242000, 203 .ce3_base_address = 0x00243000, 204 .ce4_base_address = 0x00244000, 205 .ce5_base_address = 0x00245000, 206 .ce6_base_address = 0x00246000, 207 .ce7_base_address = 0x00247000, 208 .ce8_base_address = 0x00248000, 209 .ce9_base_address = 0x00249000, 210 .ce10_base_address = 0x0024A000, 211 .ce11_base_address = 0x0024B000, 212 .soc_chip_id_address = 0x000000f0, 213 .soc_reset_control_si0_rst_mask = 0x00000001, 214 .soc_reset_control_ce_rst_mask = 0x00000100, 215 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c, 216 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000, 217 .pcie_intr_fw_mask = 0x00100000, 218 }; 219 220 static struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = { 221 .msb = 0x00000010, 222 .lsb = 0x00000010, 223 .mask = GENMASK(17, 17), 224 }; 225 226 static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = { 227 .msb = 0x00000012, 228 .lsb = 0x00000012, 229 .mask = GENMASK(18, 18), 230 }; 231 232 static struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = { 233 .msb = 0x00000000, 234 .lsb = 0x00000000, 235 .mask = GENMASK(15, 0), 236 }; 237 238 static struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = { 239 .addr = 0x00000018, 240 .src_ring = &wcn3990_src_ring, 241 .dst_ring = &wcn3990_dst_ring, 242 .dmax = &wcn3990_dmax, 243 }; 244 245 static struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = { 246 .mask = GENMASK(0, 0), 247 }; 248 249 static struct ath10k_hw_ce_host_ie wcn3990_host_ie = { 250 .copy_complete = &wcn3990_host_ie_cc, 251 }; 252 253 static struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = { 254 .dstr_lmask = 0x00000010, 255 .dstr_hmask = 0x00000008, 256 .srcr_lmask = 0x00000004, 257 .srcr_hmask = 0x00000002, 258 .cc_mask = 0x00000001, 259 .wm_mask = 0x0000001E, 260 .addr = 0x00000030, 261 }; 262 263 static struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = { 264 .axi_err = 0x00000100, 265 .dstr_add_err = 0x00000200, 266 .srcr_len_err = 0x00000100, 267 .dstr_mlen_vio = 0x00000080, 268 .dstr_overflow = 0x00000040, 269 .srcr_overflow = 0x00000020, 270 .err_mask = 0x000003E0, 271 .addr = 0x00000038, 272 }; 273 274 static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = { 275 .msb = 0x00000000, 276 .lsb = 0x00000010, 277 .mask = GENMASK(31, 16), 278 }; 279 280 static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = { 281 .msb = 0x0000000f, 282 .lsb = 0x00000000, 283 .mask = GENMASK(15, 0), 284 }; 285 286 static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = { 287 .addr = 0x0000004c, 288 .low_rst = 0x00000000, 289 .high_rst = 0x00000000, 290 .wm_low = &wcn3990_src_wm_low, 291 .wm_high = &wcn3990_src_wm_high, 292 }; 293 294 static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = { 295 .lsb = 0x00000010, 296 .mask = GENMASK(31, 16), 297 }; 298 299 static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = { 300 .msb = 0x0000000f, 301 .lsb = 0x00000000, 302 .mask = GENMASK(15, 0), 303 }; 304 305 static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = { 306 .addr = 0x00000050, 307 .low_rst = 0x00000000, 308 .high_rst = 0x00000000, 309 .wm_low = &wcn3990_dst_wm_low, 310 .wm_high = &wcn3990_dst_wm_high, 311 }; 312 313 struct ath10k_hw_ce_regs wcn3990_ce_regs = { 314 .sr_base_addr = 0x00000000, 315 .sr_size_addr = 0x00000008, 316 .dr_base_addr = 0x0000000c, 317 .dr_size_addr = 0x00000014, 318 .misc_ie_addr = 0x00000034, 319 .sr_wr_index_addr = 0x0000003c, 320 .dst_wr_index_addr = 0x00000040, 321 .current_srri_addr = 0x00000044, 322 .current_drri_addr = 0x00000048, 323 .ddr_addr_for_rri_low = 0x00000004, 324 .ddr_addr_for_rri_high = 0x00000008, 325 .ce_rri_low = 0x0024C004, 326 .ce_rri_high = 0x0024C008, 327 .host_ie_addr = 0x0000002c, 328 .ctrl1_regs = &wcn3990_ctrl1, 329 .host_ie = &wcn3990_host_ie, 330 .wm_regs = &wcn3990_wm_reg, 331 .misc_regs = &wcn3990_misc_reg, 332 .wm_srcr = &wcn3990_wm_src_ring, 333 .wm_dstr = &wcn3990_wm_dst_ring, 334 }; 335 336 const struct ath10k_hw_values wcn3990_values = { 337 .rtc_state_val_on = 5, 338 .ce_count = 12, 339 .msi_assign_ce_max = 12, 340 .num_target_ce_config_wlan = 12, 341 .ce_desc_meta_data_mask = 0xFFF0, 342 .ce_desc_meta_data_lsb = 4, 343 }; 344 345 static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = { 346 .msb = 0x00000010, 347 .lsb = 0x00000010, 348 .mask = GENMASK(16, 16), 349 }; 350 351 static struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = { 352 .msb = 0x00000011, 353 .lsb = 0x00000011, 354 .mask = GENMASK(17, 17), 355 }; 356 357 static struct ath10k_hw_ce_regs_addr_map qcax_dmax = { 358 .msb = 0x0000000f, 359 .lsb = 0x00000000, 360 .mask = GENMASK(15, 0), 361 }; 362 363 static struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = { 364 .addr = 0x00000010, 365 .hw_mask = 0x0007ffff, 366 .sw_mask = 0x0007ffff, 367 .hw_wr_mask = 0x00000000, 368 .sw_wr_mask = 0x0007ffff, 369 .reset_mask = 0xffffffff, 370 .reset = 0x00000080, 371 .src_ring = &qcax_src_ring, 372 .dst_ring = &qcax_dst_ring, 373 .dmax = &qcax_dmax, 374 }; 375 376 static struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = { 377 .msb = 0x00000003, 378 .lsb = 0x00000003, 379 .mask = GENMASK(3, 3), 380 }; 381 382 static struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = { 383 .msb = 0x00000000, 384 .mask = GENMASK(0, 0), 385 .status_reset = 0x00000000, 386 .status = &qcax_cmd_halt_status, 387 }; 388 389 static struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = { 390 .msb = 0x00000000, 391 .lsb = 0x00000000, 392 .mask = GENMASK(0, 0), 393 }; 394 395 static struct ath10k_hw_ce_host_ie qcax_host_ie = { 396 .copy_complete_reset = 0x00000000, 397 .copy_complete = &qcax_host_ie_cc, 398 }; 399 400 static struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = { 401 .dstr_lmask = 0x00000010, 402 .dstr_hmask = 0x00000008, 403 .srcr_lmask = 0x00000004, 404 .srcr_hmask = 0x00000002, 405 .cc_mask = 0x00000001, 406 .wm_mask = 0x0000001E, 407 .addr = 0x00000030, 408 }; 409 410 static struct ath10k_hw_ce_misc_regs qcax_misc_reg = { 411 .axi_err = 0x00000400, 412 .dstr_add_err = 0x00000200, 413 .srcr_len_err = 0x00000100, 414 .dstr_mlen_vio = 0x00000080, 415 .dstr_overflow = 0x00000040, 416 .srcr_overflow = 0x00000020, 417 .err_mask = 0x000007E0, 418 .addr = 0x00000038, 419 }; 420 421 static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = { 422 .msb = 0x0000001f, 423 .lsb = 0x00000010, 424 .mask = GENMASK(31, 16), 425 }; 426 427 static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = { 428 .msb = 0x0000000f, 429 .lsb = 0x00000000, 430 .mask = GENMASK(15, 0), 431 }; 432 433 static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = { 434 .addr = 0x0000004c, 435 .low_rst = 0x00000000, 436 .high_rst = 0x00000000, 437 .wm_low = &qcax_src_wm_low, 438 .wm_high = &qcax_src_wm_high, 439 }; 440 441 static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = { 442 .lsb = 0x00000010, 443 .mask = GENMASK(31, 16), 444 }; 445 446 static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = { 447 .msb = 0x0000000f, 448 .lsb = 0x00000000, 449 .mask = GENMASK(15, 0), 450 }; 451 452 static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = { 453 .addr = 0x00000050, 454 .low_rst = 0x00000000, 455 .high_rst = 0x00000000, 456 .wm_low = &qcax_dst_wm_low, 457 .wm_high = &qcax_dst_wm_high, 458 }; 459 460 struct ath10k_hw_ce_regs qcax_ce_regs = { 461 .sr_base_addr = 0x00000000, 462 .sr_size_addr = 0x00000004, 463 .dr_base_addr = 0x00000008, 464 .dr_size_addr = 0x0000000c, 465 .ce_cmd_addr = 0x00000018, 466 .misc_ie_addr = 0x00000034, 467 .sr_wr_index_addr = 0x0000003c, 468 .dst_wr_index_addr = 0x00000040, 469 .current_srri_addr = 0x00000044, 470 .current_drri_addr = 0x00000048, 471 .host_ie_addr = 0x0000002c, 472 .ctrl1_regs = &qcax_ctrl1, 473 .cmd_halt = &qcax_cmd_halt, 474 .host_ie = &qcax_host_ie, 475 .wm_regs = &qcax_wm_reg, 476 .misc_regs = &qcax_misc_reg, 477 .wm_srcr = &qcax_wm_src_ring, 478 .wm_dstr = &qcax_wm_dst_ring, 479 }; 480 481 const struct ath10k_hw_clk_params qca6174_clk[ATH10K_HW_REFCLK_COUNT] = { 482 { 483 .refclk = 48000000, 484 .div = 0xe, 485 .rnfrac = 0x2aaa8, 486 .settle_time = 2400, 487 .refdiv = 0, 488 .outdiv = 1, 489 }, 490 { 491 .refclk = 19200000, 492 .div = 0x24, 493 .rnfrac = 0x2aaa8, 494 .settle_time = 960, 495 .refdiv = 0, 496 .outdiv = 1, 497 }, 498 { 499 .refclk = 24000000, 500 .div = 0x1d, 501 .rnfrac = 0x15551, 502 .settle_time = 1200, 503 .refdiv = 0, 504 .outdiv = 1, 505 }, 506 { 507 .refclk = 26000000, 508 .div = 0x1b, 509 .rnfrac = 0x4ec4, 510 .settle_time = 1300, 511 .refdiv = 0, 512 .outdiv = 1, 513 }, 514 { 515 .refclk = 37400000, 516 .div = 0x12, 517 .rnfrac = 0x34b49, 518 .settle_time = 1870, 519 .refdiv = 0, 520 .outdiv = 1, 521 }, 522 { 523 .refclk = 38400000, 524 .div = 0x12, 525 .rnfrac = 0x15551, 526 .settle_time = 1920, 527 .refdiv = 0, 528 .outdiv = 1, 529 }, 530 { 531 .refclk = 40000000, 532 .div = 0x12, 533 .rnfrac = 0x26665, 534 .settle_time = 2000, 535 .refdiv = 0, 536 .outdiv = 1, 537 }, 538 { 539 .refclk = 52000000, 540 .div = 0x1b, 541 .rnfrac = 0x4ec4, 542 .settle_time = 2600, 543 .refdiv = 0, 544 .outdiv = 1, 545 }, 546 }; 547 548 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 549 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev) 550 { 551 u32 cc_fix = 0; 552 u32 rcc_fix = 0; 553 enum ath10k_hw_cc_wraparound_type wraparound_type; 554 555 survey->filled |= SURVEY_INFO_TIME | 556 SURVEY_INFO_TIME_BUSY; 557 558 wraparound_type = ar->hw_params.cc_wraparound_type; 559 560 if (cc < cc_prev || rcc < rcc_prev) { 561 switch (wraparound_type) { 562 case ATH10K_HW_CC_WRAP_SHIFTED_ALL: 563 if (cc < cc_prev) { 564 cc_fix = 0x7fffffff; 565 survey->filled &= ~SURVEY_INFO_TIME_BUSY; 566 } 567 break; 568 case ATH10K_HW_CC_WRAP_SHIFTED_EACH: 569 if (cc < cc_prev) 570 cc_fix = 0x7fffffff; 571 572 if (rcc < rcc_prev) 573 rcc_fix = 0x7fffffff; 574 break; 575 case ATH10K_HW_CC_WRAP_DISABLED: 576 break; 577 } 578 } 579 580 cc -= cc_prev - cc_fix; 581 rcc -= rcc_prev - rcc_fix; 582 583 survey->time = CCNT_TO_MSEC(ar, cc); 584 survey->time_busy = CCNT_TO_MSEC(ar, rcc); 585 } 586 587 /* The firmware does not support setting the coverage class. Instead this 588 * function monitors and modifies the corresponding MAC registers. 589 */ 590 static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar, 591 s16 value) 592 { 593 u32 slottime_reg; 594 u32 slottime; 595 u32 timeout_reg; 596 u32 ack_timeout; 597 u32 cts_timeout; 598 u32 phyclk_reg; 599 u32 phyclk; 600 u64 fw_dbglog_mask; 601 u32 fw_dbglog_level; 602 603 mutex_lock(&ar->conf_mutex); 604 605 /* Only modify registers if the core is started. */ 606 if ((ar->state != ATH10K_STATE_ON) && 607 (ar->state != ATH10K_STATE_RESTARTED)) 608 goto unlock; 609 610 /* Retrieve the current values of the two registers that need to be 611 * adjusted. 612 */ 613 slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS + 614 WAVE1_PCU_GBL_IFS_SLOT); 615 timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS + 616 WAVE1_PCU_ACK_CTS_TIMEOUT); 617 phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS + 618 WAVE1_PHYCLK); 619 phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1; 620 621 if (value < 0) 622 value = ar->fw_coverage.coverage_class; 623 624 /* Break out if the coverage class and registers have the expected 625 * value. 626 */ 627 if (value == ar->fw_coverage.coverage_class && 628 slottime_reg == ar->fw_coverage.reg_slottime_conf && 629 timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf && 630 phyclk_reg == ar->fw_coverage.reg_phyclk) 631 goto unlock; 632 633 /* Store new initial register values from the firmware. */ 634 if (slottime_reg != ar->fw_coverage.reg_slottime_conf) 635 ar->fw_coverage.reg_slottime_orig = slottime_reg; 636 if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf) 637 ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg; 638 ar->fw_coverage.reg_phyclk = phyclk_reg; 639 640 /* Calculat new value based on the (original) firmware calculation. */ 641 slottime_reg = ar->fw_coverage.reg_slottime_orig; 642 timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig; 643 644 /* Do some sanity checks on the slottime register. */ 645 if (slottime_reg % phyclk) { 646 ath10k_warn(ar, 647 "failed to set coverage class: expected integer microsecond value in register\n"); 648 649 goto store_regs; 650 } 651 652 slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT); 653 slottime = slottime / phyclk; 654 if (slottime != 9 && slottime != 20) { 655 ath10k_warn(ar, 656 "failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n", 657 slottime); 658 659 goto store_regs; 660 } 661 662 /* Recalculate the register values by adding the additional propagation 663 * delay (3us per coverage class). 664 */ 665 666 slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT); 667 slottime += value * 3 * phyclk; 668 slottime = min_t(u32, slottime, WAVE1_PCU_GBL_IFS_SLOT_MAX); 669 slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT); 670 slottime_reg = (slottime_reg & ~WAVE1_PCU_GBL_IFS_SLOT_MASK) | slottime; 671 672 /* Update ack timeout (lower halfword). */ 673 ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK); 674 ack_timeout += 3 * value * phyclk; 675 ack_timeout = min_t(u32, ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX); 676 ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK); 677 678 /* Update cts timeout (upper halfword). */ 679 cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS); 680 cts_timeout += 3 * value * phyclk; 681 cts_timeout = min_t(u32, cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX); 682 cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS); 683 684 timeout_reg = ack_timeout | cts_timeout; 685 686 ath10k_hif_write32(ar, 687 WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_GBL_IFS_SLOT, 688 slottime_reg); 689 ath10k_hif_write32(ar, 690 WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_ACK_CTS_TIMEOUT, 691 timeout_reg); 692 693 /* Ensure we have a debug level of WARN set for the case that the 694 * coverage class is larger than 0. This is important as we need to 695 * set the registers again if the firmware does an internal reset and 696 * this way we will be notified of the event. 697 */ 698 fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar); 699 fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar); 700 701 if (value > 0) { 702 if (fw_dbglog_level > ATH10K_DBGLOG_LEVEL_WARN) 703 fw_dbglog_level = ATH10K_DBGLOG_LEVEL_WARN; 704 fw_dbglog_mask = ~0; 705 } 706 707 ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level); 708 709 store_regs: 710 /* After an error we will not retry setting the coverage class. */ 711 spin_lock_bh(&ar->data_lock); 712 ar->fw_coverage.coverage_class = value; 713 spin_unlock_bh(&ar->data_lock); 714 715 ar->fw_coverage.reg_slottime_conf = slottime_reg; 716 ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg; 717 718 unlock: 719 mutex_unlock(&ar->conf_mutex); 720 } 721 722 /** 723 * ath10k_hw_qca6174_enable_pll_clock() - enable the qca6174 hw pll clock 724 * @ar: the ath10k blob 725 * 726 * This function is very hardware specific, the clock initialization 727 * steps is very sensitive and could lead to unknown crash, so they 728 * should be done in sequence. 729 * 730 * *** Be aware if you planned to refactor them. *** 731 * 732 * Return: 0 if successfully enable the pll, otherwise EINVAL 733 */ 734 static int ath10k_hw_qca6174_enable_pll_clock(struct ath10k *ar) 735 { 736 int ret, wait_limit; 737 u32 clk_div_addr, pll_init_addr, speed_addr; 738 u32 addr, reg_val, mem_val; 739 struct ath10k_hw_params *hw; 740 const struct ath10k_hw_clk_params *hw_clk; 741 742 hw = &ar->hw_params; 743 744 if (ar->regs->core_clk_div_address == 0 || 745 ar->regs->cpu_pll_init_address == 0 || 746 ar->regs->cpu_speed_address == 0) 747 return -EINVAL; 748 749 clk_div_addr = ar->regs->core_clk_div_address; 750 pll_init_addr = ar->regs->cpu_pll_init_address; 751 speed_addr = ar->regs->cpu_speed_address; 752 753 /* Read efuse register to find out the right hw clock configuration */ 754 addr = (RTC_SOC_BASE_ADDRESS | EFUSE_OFFSET); 755 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 756 if (ret) 757 return -EINVAL; 758 759 /* sanitize if the hw refclk index is out of the boundary */ 760 if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT) 761 return -EINVAL; 762 763 hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)]; 764 765 /* Set the rnfrac and outdiv params to bb_pll register */ 766 addr = (RTC_SOC_BASE_ADDRESS | BB_PLL_CONFIG_OFFSET); 767 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 768 if (ret) 769 return -EINVAL; 770 771 reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK); 772 reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) | 773 SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV)); 774 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 775 if (ret) 776 return -EINVAL; 777 778 /* Set the correct settle time value to pll_settle register */ 779 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_SETTLE_OFFSET); 780 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 781 if (ret) 782 return -EINVAL; 783 784 reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK; 785 reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME); 786 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 787 if (ret) 788 return -EINVAL; 789 790 /* Set the clock_ctrl div to core_clk_ctrl register */ 791 addr = (RTC_SOC_BASE_ADDRESS | SOC_CORE_CLK_CTRL_OFFSET); 792 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 793 if (ret) 794 return -EINVAL; 795 796 reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK; 797 reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV); 798 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 799 if (ret) 800 return -EINVAL; 801 802 /* Set the clock_div register */ 803 mem_val = 1; 804 ret = ath10k_bmi_write_memory(ar, clk_div_addr, &mem_val, 805 sizeof(mem_val)); 806 if (ret) 807 return -EINVAL; 808 809 /* Configure the pll_control register */ 810 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET); 811 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 812 if (ret) 813 return -EINVAL; 814 815 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | 816 SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) | 817 SM(1, WLAN_PLL_CONTROL_NOPWD)); 818 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 819 if (ret) 820 return -EINVAL; 821 822 /* busy wait (max 1s) the rtc_sync status register indicate ready */ 823 wait_limit = 100000; 824 addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET); 825 do { 826 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 827 if (ret) 828 return -EINVAL; 829 830 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) 831 break; 832 833 wait_limit--; 834 udelay(10); 835 836 } while (wait_limit > 0); 837 838 if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) 839 return -EINVAL; 840 841 /* Unset the pll_bypass in pll_control register */ 842 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET); 843 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 844 if (ret) 845 return -EINVAL; 846 847 reg_val &= ~WLAN_PLL_CONTROL_BYPASS_MASK; 848 reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS); 849 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 850 if (ret) 851 return -EINVAL; 852 853 /* busy wait (max 1s) the rtc_sync status register indicate ready */ 854 wait_limit = 100000; 855 addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET); 856 do { 857 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 858 if (ret) 859 return -EINVAL; 860 861 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) 862 break; 863 864 wait_limit--; 865 udelay(10); 866 867 } while (wait_limit > 0); 868 869 if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) 870 return -EINVAL; 871 872 /* Enable the hardware cpu clock register */ 873 addr = (RTC_SOC_BASE_ADDRESS | SOC_CPU_CLOCK_OFFSET); 874 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 875 if (ret) 876 return -EINVAL; 877 878 reg_val &= ~SOC_CPU_CLOCK_STANDARD_MASK; 879 reg_val |= SM(1, SOC_CPU_CLOCK_STANDARD); 880 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 881 if (ret) 882 return -EINVAL; 883 884 /* unset the nopwd from pll_control register */ 885 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET); 886 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 887 if (ret) 888 return -EINVAL; 889 890 reg_val &= ~WLAN_PLL_CONTROL_NOPWD_MASK; 891 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 892 if (ret) 893 return -EINVAL; 894 895 /* enable the pll_init register */ 896 mem_val = 1; 897 ret = ath10k_bmi_write_memory(ar, pll_init_addr, &mem_val, 898 sizeof(mem_val)); 899 if (ret) 900 return -EINVAL; 901 902 /* set the target clock frequency to speed register */ 903 ret = ath10k_bmi_write_memory(ar, speed_addr, &hw->target_cpu_freq, 904 sizeof(hw->target_cpu_freq)); 905 if (ret) 906 return -EINVAL; 907 908 return 0; 909 } 910 911 const struct ath10k_hw_ops qca988x_ops = { 912 .set_coverage_class = ath10k_hw_qca988x_set_coverage_class, 913 }; 914 915 static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd) 916 { 917 return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1), 918 RX_MSDU_END_INFO1_L3_HDR_PAD); 919 } 920 921 const struct ath10k_hw_ops qca99x0_ops = { 922 .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes, 923 }; 924 925 const struct ath10k_hw_ops qca6174_ops = { 926 .set_coverage_class = ath10k_hw_qca988x_set_coverage_class, 927 .enable_pll_clk = ath10k_hw_qca6174_enable_pll_clock, 928 }; 929