1 /* 2 * Copyright (c) 2014-2017 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/types.h> 18 #include <linux/bitops.h> 19 #include "core.h" 20 #include "hw.h" 21 #include "hif.h" 22 #include "wmi-ops.h" 23 #include "bmi.h" 24 25 const struct ath10k_hw_regs qca988x_regs = { 26 .rtc_soc_base_address = 0x00004000, 27 .rtc_wmac_base_address = 0x00005000, 28 .soc_core_base_address = 0x00009000, 29 .wlan_mac_base_address = 0x00020000, 30 .ce_wrapper_base_address = 0x00057000, 31 .ce0_base_address = 0x00057400, 32 .ce1_base_address = 0x00057800, 33 .ce2_base_address = 0x00057c00, 34 .ce3_base_address = 0x00058000, 35 .ce4_base_address = 0x00058400, 36 .ce5_base_address = 0x00058800, 37 .ce6_base_address = 0x00058c00, 38 .ce7_base_address = 0x00059000, 39 .soc_reset_control_si0_rst_mask = 0x00000001, 40 .soc_reset_control_ce_rst_mask = 0x00040000, 41 .soc_chip_id_address = 0x000000ec, 42 .scratch_3_address = 0x00000030, 43 .fw_indicator_address = 0x00009030, 44 .pcie_local_base_address = 0x00080000, 45 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008, 46 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00, 47 .pcie_intr_fw_mask = 0x00000400, 48 .pcie_intr_ce_mask_all = 0x0007f800, 49 .pcie_intr_clr_address = 0x00000014, 50 }; 51 52 const struct ath10k_hw_regs qca6174_regs = { 53 .rtc_soc_base_address = 0x00000800, 54 .rtc_wmac_base_address = 0x00001000, 55 .soc_core_base_address = 0x0003a000, 56 .wlan_mac_base_address = 0x00010000, 57 .ce_wrapper_base_address = 0x00034000, 58 .ce0_base_address = 0x00034400, 59 .ce1_base_address = 0x00034800, 60 .ce2_base_address = 0x00034c00, 61 .ce3_base_address = 0x00035000, 62 .ce4_base_address = 0x00035400, 63 .ce5_base_address = 0x00035800, 64 .ce6_base_address = 0x00035c00, 65 .ce7_base_address = 0x00036000, 66 .soc_reset_control_si0_rst_mask = 0x00000000, 67 .soc_reset_control_ce_rst_mask = 0x00000001, 68 .soc_chip_id_address = 0x000000f0, 69 .scratch_3_address = 0x00000028, 70 .fw_indicator_address = 0x0003a028, 71 .pcie_local_base_address = 0x00080000, 72 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008, 73 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00, 74 .pcie_intr_fw_mask = 0x00000400, 75 .pcie_intr_ce_mask_all = 0x0007f800, 76 .pcie_intr_clr_address = 0x00000014, 77 .cpu_pll_init_address = 0x00404020, 78 .cpu_speed_address = 0x00404024, 79 .core_clk_div_address = 0x00404028, 80 }; 81 82 const struct ath10k_hw_regs qca99x0_regs = { 83 .rtc_soc_base_address = 0x00080000, 84 .rtc_wmac_base_address = 0x00000000, 85 .soc_core_base_address = 0x00082000, 86 .wlan_mac_base_address = 0x00030000, 87 .ce_wrapper_base_address = 0x0004d000, 88 .ce0_base_address = 0x0004a000, 89 .ce1_base_address = 0x0004a400, 90 .ce2_base_address = 0x0004a800, 91 .ce3_base_address = 0x0004ac00, 92 .ce4_base_address = 0x0004b000, 93 .ce5_base_address = 0x0004b400, 94 .ce6_base_address = 0x0004b800, 95 .ce7_base_address = 0x0004bc00, 96 /* Note: qca99x0 supports upto 12 Copy Engines. Other than address of 97 * CE0 and CE1 no other copy engine is directly referred in the code. 98 * It is not really necessary to assign address for newly supported 99 * CEs in this address table. 100 * Copy Engine Address 101 * CE8 0x0004c000 102 * CE9 0x0004c400 103 * CE10 0x0004c800 104 * CE11 0x0004cc00 105 */ 106 .soc_reset_control_si0_rst_mask = 0x00000001, 107 .soc_reset_control_ce_rst_mask = 0x00000100, 108 .soc_chip_id_address = 0x000000ec, 109 .scratch_3_address = 0x00040050, 110 .fw_indicator_address = 0x00040050, 111 .pcie_local_base_address = 0x00000000, 112 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c, 113 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000, 114 .pcie_intr_fw_mask = 0x00100000, 115 .pcie_intr_ce_mask_all = 0x000fff00, 116 .pcie_intr_clr_address = 0x00000010, 117 }; 118 119 const struct ath10k_hw_regs qca4019_regs = { 120 .rtc_soc_base_address = 0x00080000, 121 .soc_core_base_address = 0x00082000, 122 .wlan_mac_base_address = 0x00030000, 123 .ce_wrapper_base_address = 0x0004d000, 124 .ce0_base_address = 0x0004a000, 125 .ce1_base_address = 0x0004a400, 126 .ce2_base_address = 0x0004a800, 127 .ce3_base_address = 0x0004ac00, 128 .ce4_base_address = 0x0004b000, 129 .ce5_base_address = 0x0004b400, 130 .ce6_base_address = 0x0004b800, 131 .ce7_base_address = 0x0004bc00, 132 /* qca4019 supports upto 12 copy engines. Since base address 133 * of ce8 to ce11 are not directly referred in the code, 134 * no need have them in separate members in this table. 135 * Copy Engine Address 136 * CE8 0x0004c000 137 * CE9 0x0004c400 138 * CE10 0x0004c800 139 * CE11 0x0004cc00 140 */ 141 .soc_reset_control_si0_rst_mask = 0x00000001, 142 .soc_reset_control_ce_rst_mask = 0x00000100, 143 .soc_chip_id_address = 0x000000ec, 144 .fw_indicator_address = 0x0004f00c, 145 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c, 146 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000, 147 .pcie_intr_fw_mask = 0x00100000, 148 .pcie_intr_ce_mask_all = 0x000fff00, 149 .pcie_intr_clr_address = 0x00000010, 150 }; 151 152 const struct ath10k_hw_values qca988x_values = { 153 .rtc_state_val_on = 3, 154 .ce_count = 8, 155 .msi_assign_ce_max = 7, 156 .num_target_ce_config_wlan = 7, 157 .ce_desc_meta_data_mask = 0xFFFC, 158 .ce_desc_meta_data_lsb = 2, 159 }; 160 161 const struct ath10k_hw_values qca6174_values = { 162 .rtc_state_val_on = 3, 163 .ce_count = 8, 164 .msi_assign_ce_max = 7, 165 .num_target_ce_config_wlan = 7, 166 .ce_desc_meta_data_mask = 0xFFFC, 167 .ce_desc_meta_data_lsb = 2, 168 }; 169 170 const struct ath10k_hw_values qca99x0_values = { 171 .rtc_state_val_on = 5, 172 .ce_count = 12, 173 .msi_assign_ce_max = 12, 174 .num_target_ce_config_wlan = 10, 175 .ce_desc_meta_data_mask = 0xFFF0, 176 .ce_desc_meta_data_lsb = 4, 177 }; 178 179 const struct ath10k_hw_values qca9888_values = { 180 .rtc_state_val_on = 3, 181 .ce_count = 12, 182 .msi_assign_ce_max = 12, 183 .num_target_ce_config_wlan = 10, 184 .ce_desc_meta_data_mask = 0xFFF0, 185 .ce_desc_meta_data_lsb = 4, 186 }; 187 188 const struct ath10k_hw_values qca4019_values = { 189 .ce_count = 12, 190 .num_target_ce_config_wlan = 10, 191 .ce_desc_meta_data_mask = 0xFFF0, 192 .ce_desc_meta_data_lsb = 4, 193 }; 194 195 const struct ath10k_hw_regs wcn3990_regs = { 196 .rtc_soc_base_address = 0x00000000, 197 .rtc_wmac_base_address = 0x00000000, 198 .soc_core_base_address = 0x00000000, 199 .ce_wrapper_base_address = 0x0024C000, 200 .ce0_base_address = 0x00240000, 201 .ce1_base_address = 0x00241000, 202 .ce2_base_address = 0x00242000, 203 .ce3_base_address = 0x00243000, 204 .ce4_base_address = 0x00244000, 205 .ce5_base_address = 0x00245000, 206 .ce6_base_address = 0x00246000, 207 .ce7_base_address = 0x00247000, 208 .ce8_base_address = 0x00248000, 209 .ce9_base_address = 0x00249000, 210 .ce10_base_address = 0x0024A000, 211 .ce11_base_address = 0x0024B000, 212 .soc_chip_id_address = 0x000000f0, 213 .soc_reset_control_si0_rst_mask = 0x00000001, 214 .soc_reset_control_ce_rst_mask = 0x00000100, 215 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c, 216 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000, 217 .pcie_intr_fw_mask = 0x00100000, 218 }; 219 220 static struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = { 221 .msb = 0x00000010, 222 .lsb = 0x00000010, 223 .mask = GENMASK(17, 17), 224 }; 225 226 static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = { 227 .msb = 0x00000012, 228 .lsb = 0x00000012, 229 .mask = GENMASK(18, 18), 230 }; 231 232 static struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = { 233 .msb = 0x00000000, 234 .lsb = 0x00000000, 235 .mask = GENMASK(15, 0), 236 }; 237 238 static struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = { 239 .addr = 0x00000018, 240 .src_ring = &wcn3990_src_ring, 241 .dst_ring = &wcn3990_dst_ring, 242 .dmax = &wcn3990_dmax, 243 }; 244 245 static struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = { 246 .mask = GENMASK(0, 0), 247 }; 248 249 static struct ath10k_hw_ce_host_ie wcn3990_host_ie = { 250 .copy_complete = &wcn3990_host_ie_cc, 251 }; 252 253 static struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = { 254 .dstr_lmask = 0x00000010, 255 .dstr_hmask = 0x00000008, 256 .srcr_lmask = 0x00000004, 257 .srcr_hmask = 0x00000002, 258 .cc_mask = 0x00000001, 259 .wm_mask = 0x0000001E, 260 .addr = 0x00000030, 261 }; 262 263 static struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = { 264 .axi_err = 0x00000100, 265 .dstr_add_err = 0x00000200, 266 .srcr_len_err = 0x00000100, 267 .dstr_mlen_vio = 0x00000080, 268 .dstr_overflow = 0x00000040, 269 .srcr_overflow = 0x00000020, 270 .err_mask = 0x000003E0, 271 .addr = 0x00000038, 272 }; 273 274 static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = { 275 .msb = 0x00000000, 276 .lsb = 0x00000010, 277 .mask = GENMASK(31, 16), 278 }; 279 280 static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = { 281 .msb = 0x0000000f, 282 .lsb = 0x00000000, 283 .mask = GENMASK(15, 0), 284 }; 285 286 static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = { 287 .addr = 0x0000004c, 288 .low_rst = 0x00000000, 289 .high_rst = 0x00000000, 290 .wm_low = &wcn3990_src_wm_low, 291 .wm_high = &wcn3990_src_wm_high, 292 }; 293 294 static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = { 295 .lsb = 0x00000010, 296 .mask = GENMASK(31, 16), 297 }; 298 299 static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = { 300 .msb = 0x0000000f, 301 .lsb = 0x00000000, 302 .mask = GENMASK(15, 0), 303 }; 304 305 static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = { 306 .addr = 0x00000050, 307 .low_rst = 0x00000000, 308 .high_rst = 0x00000000, 309 .wm_low = &wcn3990_dst_wm_low, 310 .wm_high = &wcn3990_dst_wm_high, 311 }; 312 313 static struct ath10k_hw_ce_ctrl1_upd wcn3990_ctrl1_upd = { 314 .shift = 19, 315 .mask = 0x00080000, 316 .enable = 0x00000000, 317 }; 318 319 const struct ath10k_hw_ce_regs wcn3990_ce_regs = { 320 .sr_base_addr = 0x00000000, 321 .sr_size_addr = 0x00000008, 322 .dr_base_addr = 0x0000000c, 323 .dr_size_addr = 0x00000014, 324 .misc_ie_addr = 0x00000034, 325 .sr_wr_index_addr = 0x0000003c, 326 .dst_wr_index_addr = 0x00000040, 327 .current_srri_addr = 0x00000044, 328 .current_drri_addr = 0x00000048, 329 .ce_rri_low = 0x0024C004, 330 .ce_rri_high = 0x0024C008, 331 .host_ie_addr = 0x0000002c, 332 .ctrl1_regs = &wcn3990_ctrl1, 333 .host_ie = &wcn3990_host_ie, 334 .wm_regs = &wcn3990_wm_reg, 335 .misc_regs = &wcn3990_misc_reg, 336 .wm_srcr = &wcn3990_wm_src_ring, 337 .wm_dstr = &wcn3990_wm_dst_ring, 338 .upd = &wcn3990_ctrl1_upd, 339 }; 340 341 const struct ath10k_hw_values wcn3990_values = { 342 .rtc_state_val_on = 5, 343 .ce_count = 12, 344 .msi_assign_ce_max = 12, 345 .num_target_ce_config_wlan = 12, 346 .ce_desc_meta_data_mask = 0xFFF0, 347 .ce_desc_meta_data_lsb = 4, 348 }; 349 350 static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = { 351 .msb = 0x00000010, 352 .lsb = 0x00000010, 353 .mask = GENMASK(16, 16), 354 }; 355 356 static struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = { 357 .msb = 0x00000011, 358 .lsb = 0x00000011, 359 .mask = GENMASK(17, 17), 360 }; 361 362 static struct ath10k_hw_ce_regs_addr_map qcax_dmax = { 363 .msb = 0x0000000f, 364 .lsb = 0x00000000, 365 .mask = GENMASK(15, 0), 366 }; 367 368 static struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = { 369 .addr = 0x00000010, 370 .hw_mask = 0x0007ffff, 371 .sw_mask = 0x0007ffff, 372 .hw_wr_mask = 0x00000000, 373 .sw_wr_mask = 0x0007ffff, 374 .reset_mask = 0xffffffff, 375 .reset = 0x00000080, 376 .src_ring = &qcax_src_ring, 377 .dst_ring = &qcax_dst_ring, 378 .dmax = &qcax_dmax, 379 }; 380 381 static struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = { 382 .msb = 0x00000003, 383 .lsb = 0x00000003, 384 .mask = GENMASK(3, 3), 385 }; 386 387 static struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = { 388 .msb = 0x00000000, 389 .mask = GENMASK(0, 0), 390 .status_reset = 0x00000000, 391 .status = &qcax_cmd_halt_status, 392 }; 393 394 static struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = { 395 .msb = 0x00000000, 396 .lsb = 0x00000000, 397 .mask = GENMASK(0, 0), 398 }; 399 400 static struct ath10k_hw_ce_host_ie qcax_host_ie = { 401 .copy_complete_reset = 0x00000000, 402 .copy_complete = &qcax_host_ie_cc, 403 }; 404 405 static struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = { 406 .dstr_lmask = 0x00000010, 407 .dstr_hmask = 0x00000008, 408 .srcr_lmask = 0x00000004, 409 .srcr_hmask = 0x00000002, 410 .cc_mask = 0x00000001, 411 .wm_mask = 0x0000001E, 412 .addr = 0x00000030, 413 }; 414 415 static struct ath10k_hw_ce_misc_regs qcax_misc_reg = { 416 .axi_err = 0x00000400, 417 .dstr_add_err = 0x00000200, 418 .srcr_len_err = 0x00000100, 419 .dstr_mlen_vio = 0x00000080, 420 .dstr_overflow = 0x00000040, 421 .srcr_overflow = 0x00000020, 422 .err_mask = 0x000007E0, 423 .addr = 0x00000038, 424 }; 425 426 static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = { 427 .msb = 0x0000001f, 428 .lsb = 0x00000010, 429 .mask = GENMASK(31, 16), 430 }; 431 432 static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = { 433 .msb = 0x0000000f, 434 .lsb = 0x00000000, 435 .mask = GENMASK(15, 0), 436 }; 437 438 static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = { 439 .addr = 0x0000004c, 440 .low_rst = 0x00000000, 441 .high_rst = 0x00000000, 442 .wm_low = &qcax_src_wm_low, 443 .wm_high = &qcax_src_wm_high, 444 }; 445 446 static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = { 447 .lsb = 0x00000010, 448 .mask = GENMASK(31, 16), 449 }; 450 451 static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = { 452 .msb = 0x0000000f, 453 .lsb = 0x00000000, 454 .mask = GENMASK(15, 0), 455 }; 456 457 static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = { 458 .addr = 0x00000050, 459 .low_rst = 0x00000000, 460 .high_rst = 0x00000000, 461 .wm_low = &qcax_dst_wm_low, 462 .wm_high = &qcax_dst_wm_high, 463 }; 464 465 const struct ath10k_hw_ce_regs qcax_ce_regs = { 466 .sr_base_addr = 0x00000000, 467 .sr_size_addr = 0x00000004, 468 .dr_base_addr = 0x00000008, 469 .dr_size_addr = 0x0000000c, 470 .ce_cmd_addr = 0x00000018, 471 .misc_ie_addr = 0x00000034, 472 .sr_wr_index_addr = 0x0000003c, 473 .dst_wr_index_addr = 0x00000040, 474 .current_srri_addr = 0x00000044, 475 .current_drri_addr = 0x00000048, 476 .host_ie_addr = 0x0000002c, 477 .ctrl1_regs = &qcax_ctrl1, 478 .cmd_halt = &qcax_cmd_halt, 479 .host_ie = &qcax_host_ie, 480 .wm_regs = &qcax_wm_reg, 481 .misc_regs = &qcax_misc_reg, 482 .wm_srcr = &qcax_wm_src_ring, 483 .wm_dstr = &qcax_wm_dst_ring, 484 }; 485 486 const struct ath10k_hw_clk_params qca6174_clk[ATH10K_HW_REFCLK_COUNT] = { 487 { 488 .refclk = 48000000, 489 .div = 0xe, 490 .rnfrac = 0x2aaa8, 491 .settle_time = 2400, 492 .refdiv = 0, 493 .outdiv = 1, 494 }, 495 { 496 .refclk = 19200000, 497 .div = 0x24, 498 .rnfrac = 0x2aaa8, 499 .settle_time = 960, 500 .refdiv = 0, 501 .outdiv = 1, 502 }, 503 { 504 .refclk = 24000000, 505 .div = 0x1d, 506 .rnfrac = 0x15551, 507 .settle_time = 1200, 508 .refdiv = 0, 509 .outdiv = 1, 510 }, 511 { 512 .refclk = 26000000, 513 .div = 0x1b, 514 .rnfrac = 0x4ec4, 515 .settle_time = 1300, 516 .refdiv = 0, 517 .outdiv = 1, 518 }, 519 { 520 .refclk = 37400000, 521 .div = 0x12, 522 .rnfrac = 0x34b49, 523 .settle_time = 1870, 524 .refdiv = 0, 525 .outdiv = 1, 526 }, 527 { 528 .refclk = 38400000, 529 .div = 0x12, 530 .rnfrac = 0x15551, 531 .settle_time = 1920, 532 .refdiv = 0, 533 .outdiv = 1, 534 }, 535 { 536 .refclk = 40000000, 537 .div = 0x12, 538 .rnfrac = 0x26665, 539 .settle_time = 2000, 540 .refdiv = 0, 541 .outdiv = 1, 542 }, 543 { 544 .refclk = 52000000, 545 .div = 0x1b, 546 .rnfrac = 0x4ec4, 547 .settle_time = 2600, 548 .refdiv = 0, 549 .outdiv = 1, 550 }, 551 }; 552 553 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 554 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev) 555 { 556 u32 cc_fix = 0; 557 u32 rcc_fix = 0; 558 enum ath10k_hw_cc_wraparound_type wraparound_type; 559 560 survey->filled |= SURVEY_INFO_TIME | 561 SURVEY_INFO_TIME_BUSY; 562 563 wraparound_type = ar->hw_params.cc_wraparound_type; 564 565 if (cc < cc_prev || rcc < rcc_prev) { 566 switch (wraparound_type) { 567 case ATH10K_HW_CC_WRAP_SHIFTED_ALL: 568 if (cc < cc_prev) { 569 cc_fix = 0x7fffffff; 570 survey->filled &= ~SURVEY_INFO_TIME_BUSY; 571 } 572 break; 573 case ATH10K_HW_CC_WRAP_SHIFTED_EACH: 574 if (cc < cc_prev) 575 cc_fix = 0x7fffffff; 576 577 if (rcc < rcc_prev) 578 rcc_fix = 0x7fffffff; 579 break; 580 case ATH10K_HW_CC_WRAP_DISABLED: 581 break; 582 } 583 } 584 585 cc -= cc_prev - cc_fix; 586 rcc -= rcc_prev - rcc_fix; 587 588 survey->time = CCNT_TO_MSEC(ar, cc); 589 survey->time_busy = CCNT_TO_MSEC(ar, rcc); 590 } 591 592 /* The firmware does not support setting the coverage class. Instead this 593 * function monitors and modifies the corresponding MAC registers. 594 */ 595 static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar, 596 s16 value) 597 { 598 u32 slottime_reg; 599 u32 slottime; 600 u32 timeout_reg; 601 u32 ack_timeout; 602 u32 cts_timeout; 603 u32 phyclk_reg; 604 u32 phyclk; 605 u64 fw_dbglog_mask; 606 u32 fw_dbglog_level; 607 608 mutex_lock(&ar->conf_mutex); 609 610 /* Only modify registers if the core is started. */ 611 if ((ar->state != ATH10K_STATE_ON) && 612 (ar->state != ATH10K_STATE_RESTARTED)) { 613 spin_lock_bh(&ar->data_lock); 614 /* Store config value for when radio boots up */ 615 ar->fw_coverage.coverage_class = value; 616 spin_unlock_bh(&ar->data_lock); 617 goto unlock; 618 } 619 620 /* Retrieve the current values of the two registers that need to be 621 * adjusted. 622 */ 623 slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS + 624 WAVE1_PCU_GBL_IFS_SLOT); 625 timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS + 626 WAVE1_PCU_ACK_CTS_TIMEOUT); 627 phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS + 628 WAVE1_PHYCLK); 629 phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1; 630 631 if (value < 0) 632 value = ar->fw_coverage.coverage_class; 633 634 /* Break out if the coverage class and registers have the expected 635 * value. 636 */ 637 if (value == ar->fw_coverage.coverage_class && 638 slottime_reg == ar->fw_coverage.reg_slottime_conf && 639 timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf && 640 phyclk_reg == ar->fw_coverage.reg_phyclk) 641 goto unlock; 642 643 /* Store new initial register values from the firmware. */ 644 if (slottime_reg != ar->fw_coverage.reg_slottime_conf) 645 ar->fw_coverage.reg_slottime_orig = slottime_reg; 646 if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf) 647 ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg; 648 ar->fw_coverage.reg_phyclk = phyclk_reg; 649 650 /* Calculate new value based on the (original) firmware calculation. */ 651 slottime_reg = ar->fw_coverage.reg_slottime_orig; 652 timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig; 653 654 /* Do some sanity checks on the slottime register. */ 655 if (slottime_reg % phyclk) { 656 ath10k_warn(ar, 657 "failed to set coverage class: expected integer microsecond value in register\n"); 658 659 goto store_regs; 660 } 661 662 slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT); 663 slottime = slottime / phyclk; 664 if (slottime != 9 && slottime != 20) { 665 ath10k_warn(ar, 666 "failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n", 667 slottime); 668 669 goto store_regs; 670 } 671 672 /* Recalculate the register values by adding the additional propagation 673 * delay (3us per coverage class). 674 */ 675 676 slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT); 677 slottime += value * 3 * phyclk; 678 slottime = min_t(u32, slottime, WAVE1_PCU_GBL_IFS_SLOT_MAX); 679 slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT); 680 slottime_reg = (slottime_reg & ~WAVE1_PCU_GBL_IFS_SLOT_MASK) | slottime; 681 682 /* Update ack timeout (lower halfword). */ 683 ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK); 684 ack_timeout += 3 * value * phyclk; 685 ack_timeout = min_t(u32, ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX); 686 ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK); 687 688 /* Update cts timeout (upper halfword). */ 689 cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS); 690 cts_timeout += 3 * value * phyclk; 691 cts_timeout = min_t(u32, cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX); 692 cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS); 693 694 timeout_reg = ack_timeout | cts_timeout; 695 696 ath10k_hif_write32(ar, 697 WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_GBL_IFS_SLOT, 698 slottime_reg); 699 ath10k_hif_write32(ar, 700 WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_ACK_CTS_TIMEOUT, 701 timeout_reg); 702 703 /* Ensure we have a debug level of WARN set for the case that the 704 * coverage class is larger than 0. This is important as we need to 705 * set the registers again if the firmware does an internal reset and 706 * this way we will be notified of the event. 707 */ 708 fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar); 709 fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar); 710 711 if (value > 0) { 712 if (fw_dbglog_level > ATH10K_DBGLOG_LEVEL_WARN) 713 fw_dbglog_level = ATH10K_DBGLOG_LEVEL_WARN; 714 fw_dbglog_mask = ~0; 715 } 716 717 ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level); 718 719 store_regs: 720 /* After an error we will not retry setting the coverage class. */ 721 spin_lock_bh(&ar->data_lock); 722 ar->fw_coverage.coverage_class = value; 723 spin_unlock_bh(&ar->data_lock); 724 725 ar->fw_coverage.reg_slottime_conf = slottime_reg; 726 ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg; 727 728 unlock: 729 mutex_unlock(&ar->conf_mutex); 730 } 731 732 /** 733 * ath10k_hw_qca6174_enable_pll_clock() - enable the qca6174 hw pll clock 734 * @ar: the ath10k blob 735 * 736 * This function is very hardware specific, the clock initialization 737 * steps is very sensitive and could lead to unknown crash, so they 738 * should be done in sequence. 739 * 740 * *** Be aware if you planned to refactor them. *** 741 * 742 * Return: 0 if successfully enable the pll, otherwise EINVAL 743 */ 744 static int ath10k_hw_qca6174_enable_pll_clock(struct ath10k *ar) 745 { 746 int ret, wait_limit; 747 u32 clk_div_addr, pll_init_addr, speed_addr; 748 u32 addr, reg_val, mem_val; 749 struct ath10k_hw_params *hw; 750 const struct ath10k_hw_clk_params *hw_clk; 751 752 hw = &ar->hw_params; 753 754 if (ar->regs->core_clk_div_address == 0 || 755 ar->regs->cpu_pll_init_address == 0 || 756 ar->regs->cpu_speed_address == 0) 757 return -EINVAL; 758 759 clk_div_addr = ar->regs->core_clk_div_address; 760 pll_init_addr = ar->regs->cpu_pll_init_address; 761 speed_addr = ar->regs->cpu_speed_address; 762 763 /* Read efuse register to find out the right hw clock configuration */ 764 addr = (RTC_SOC_BASE_ADDRESS | EFUSE_OFFSET); 765 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 766 if (ret) 767 return -EINVAL; 768 769 /* sanitize if the hw refclk index is out of the boundary */ 770 if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT) 771 return -EINVAL; 772 773 hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)]; 774 775 /* Set the rnfrac and outdiv params to bb_pll register */ 776 addr = (RTC_SOC_BASE_ADDRESS | BB_PLL_CONFIG_OFFSET); 777 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 778 if (ret) 779 return -EINVAL; 780 781 reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK); 782 reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) | 783 SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV)); 784 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 785 if (ret) 786 return -EINVAL; 787 788 /* Set the correct settle time value to pll_settle register */ 789 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_SETTLE_OFFSET); 790 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 791 if (ret) 792 return -EINVAL; 793 794 reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK; 795 reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME); 796 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 797 if (ret) 798 return -EINVAL; 799 800 /* Set the clock_ctrl div to core_clk_ctrl register */ 801 addr = (RTC_SOC_BASE_ADDRESS | SOC_CORE_CLK_CTRL_OFFSET); 802 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 803 if (ret) 804 return -EINVAL; 805 806 reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK; 807 reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV); 808 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 809 if (ret) 810 return -EINVAL; 811 812 /* Set the clock_div register */ 813 mem_val = 1; 814 ret = ath10k_bmi_write_memory(ar, clk_div_addr, &mem_val, 815 sizeof(mem_val)); 816 if (ret) 817 return -EINVAL; 818 819 /* Configure the pll_control register */ 820 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET); 821 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 822 if (ret) 823 return -EINVAL; 824 825 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | 826 SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) | 827 SM(1, WLAN_PLL_CONTROL_NOPWD)); 828 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 829 if (ret) 830 return -EINVAL; 831 832 /* busy wait (max 1s) the rtc_sync status register indicate ready */ 833 wait_limit = 100000; 834 addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET); 835 do { 836 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 837 if (ret) 838 return -EINVAL; 839 840 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) 841 break; 842 843 wait_limit--; 844 udelay(10); 845 846 } while (wait_limit > 0); 847 848 if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) 849 return -EINVAL; 850 851 /* Unset the pll_bypass in pll_control register */ 852 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET); 853 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 854 if (ret) 855 return -EINVAL; 856 857 reg_val &= ~WLAN_PLL_CONTROL_BYPASS_MASK; 858 reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS); 859 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 860 if (ret) 861 return -EINVAL; 862 863 /* busy wait (max 1s) the rtc_sync status register indicate ready */ 864 wait_limit = 100000; 865 addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET); 866 do { 867 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 868 if (ret) 869 return -EINVAL; 870 871 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) 872 break; 873 874 wait_limit--; 875 udelay(10); 876 877 } while (wait_limit > 0); 878 879 if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) 880 return -EINVAL; 881 882 /* Enable the hardware cpu clock register */ 883 addr = (RTC_SOC_BASE_ADDRESS | SOC_CPU_CLOCK_OFFSET); 884 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 885 if (ret) 886 return -EINVAL; 887 888 reg_val &= ~SOC_CPU_CLOCK_STANDARD_MASK; 889 reg_val |= SM(1, SOC_CPU_CLOCK_STANDARD); 890 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 891 if (ret) 892 return -EINVAL; 893 894 /* unset the nopwd from pll_control register */ 895 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET); 896 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); 897 if (ret) 898 return -EINVAL; 899 900 reg_val &= ~WLAN_PLL_CONTROL_NOPWD_MASK; 901 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); 902 if (ret) 903 return -EINVAL; 904 905 /* enable the pll_init register */ 906 mem_val = 1; 907 ret = ath10k_bmi_write_memory(ar, pll_init_addr, &mem_val, 908 sizeof(mem_val)); 909 if (ret) 910 return -EINVAL; 911 912 /* set the target clock frequency to speed register */ 913 ret = ath10k_bmi_write_memory(ar, speed_addr, &hw->target_cpu_freq, 914 sizeof(hw->target_cpu_freq)); 915 if (ret) 916 return -EINVAL; 917 918 return 0; 919 } 920 921 const struct ath10k_hw_ops qca988x_ops = { 922 .set_coverage_class = ath10k_hw_qca988x_set_coverage_class, 923 }; 924 925 static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd) 926 { 927 return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1), 928 RX_MSDU_END_INFO1_L3_HDR_PAD); 929 } 930 931 const struct ath10k_hw_ops qca99x0_ops = { 932 .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes, 933 }; 934 935 const struct ath10k_hw_ops qca6174_ops = { 936 .set_coverage_class = ath10k_hw_qca988x_set_coverage_class, 937 .enable_pll_clk = ath10k_hw_qca6174_enable_pll_clock, 938 }; 939 940 const struct ath10k_hw_ops wcn3990_ops = {}; 941