1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 */ 6 7 #include <linux/etherdevice.h> 8 #include "htt.h" 9 #include "mac.h" 10 #include "hif.h" 11 #include "txrx.h" 12 #include "debug.h" 13 14 static u8 ath10k_htt_tx_txq_calc_size(size_t count) 15 { 16 int exp; 17 int factor; 18 19 exp = 0; 20 factor = count >> 7; 21 22 while (factor >= 64 && exp < 4) { 23 factor >>= 3; 24 exp++; 25 } 26 27 if (exp == 4) 28 return 0xff; 29 30 if (count > 0) 31 factor = max(1, factor); 32 33 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | 34 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); 35 } 36 37 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 38 struct ieee80211_txq *txq) 39 { 40 struct ath10k *ar = hw->priv; 41 struct ath10k_sta *arsta; 42 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv; 43 unsigned long frame_cnt; 44 unsigned long byte_cnt; 45 int idx; 46 u32 bit; 47 u16 peer_id; 48 u8 tid; 49 u8 count; 50 51 lockdep_assert_held(&ar->htt.tx_lock); 52 53 if (!ar->htt.tx_q_state.enabled) 54 return; 55 56 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 57 return; 58 59 if (txq->sta) { 60 arsta = (void *)txq->sta->drv_priv; 61 peer_id = arsta->peer_id; 62 } else { 63 peer_id = arvif->peer_id; 64 } 65 66 tid = txq->tid; 67 bit = BIT(peer_id % 32); 68 idx = peer_id / 32; 69 70 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 71 count = ath10k_htt_tx_txq_calc_size(byte_cnt); 72 73 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || 74 unlikely(tid >= ar->htt.tx_q_state.num_tids)) { 75 ath10k_warn(ar, "refusing to update txq for peer_id %u tid %u due to out of bounds\n", 76 peer_id, tid); 77 return; 78 } 79 80 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count; 81 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit; 82 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0; 83 84 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %u tid %u count %u\n", 85 peer_id, tid, count); 86 } 87 88 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar) 89 { 90 u32 seq; 91 size_t size; 92 93 lockdep_assert_held(&ar->htt.tx_lock); 94 95 if (!ar->htt.tx_q_state.enabled) 96 return; 97 98 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 99 return; 100 101 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq); 102 seq++; 103 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq); 104 105 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n", 106 seq); 107 108 size = sizeof(*ar->htt.tx_q_state.vaddr); 109 dma_sync_single_for_device(ar->dev, 110 ar->htt.tx_q_state.paddr, 111 size, 112 DMA_TO_DEVICE); 113 } 114 115 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 116 struct ieee80211_txq *txq) 117 { 118 struct ath10k *ar = hw->priv; 119 120 spin_lock_bh(&ar->htt.tx_lock); 121 __ath10k_htt_tx_txq_recalc(hw, txq); 122 spin_unlock_bh(&ar->htt.tx_lock); 123 } 124 125 void ath10k_htt_tx_txq_sync(struct ath10k *ar) 126 { 127 spin_lock_bh(&ar->htt.tx_lock); 128 __ath10k_htt_tx_txq_sync(ar); 129 spin_unlock_bh(&ar->htt.tx_lock); 130 } 131 132 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 133 struct ieee80211_txq *txq) 134 { 135 struct ath10k *ar = hw->priv; 136 137 spin_lock_bh(&ar->htt.tx_lock); 138 __ath10k_htt_tx_txq_recalc(hw, txq); 139 __ath10k_htt_tx_txq_sync(ar); 140 spin_unlock_bh(&ar->htt.tx_lock); 141 } 142 143 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt) 144 { 145 lockdep_assert_held(&htt->tx_lock); 146 147 htt->num_pending_tx--; 148 if (htt->num_pending_tx == htt->max_num_pending_tx - 1) 149 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 150 151 if (htt->num_pending_tx == 0) 152 wake_up(&htt->empty_tx_wq); 153 } 154 155 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt) 156 { 157 lockdep_assert_held(&htt->tx_lock); 158 159 if (htt->num_pending_tx >= htt->max_num_pending_tx) 160 return -EBUSY; 161 162 htt->num_pending_tx++; 163 if (htt->num_pending_tx == htt->max_num_pending_tx) 164 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 165 166 return 0; 167 } 168 169 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 170 bool is_presp) 171 { 172 struct ath10k *ar = htt->ar; 173 174 lockdep_assert_held(&htt->tx_lock); 175 176 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres) 177 return 0; 178 179 if (is_presp && 180 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx) 181 return -EBUSY; 182 183 htt->num_pending_mgmt_tx++; 184 185 return 0; 186 } 187 188 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt) 189 { 190 lockdep_assert_held(&htt->tx_lock); 191 192 if (!htt->ar->hw_params.max_probe_resp_desc_thres) 193 return; 194 195 htt->num_pending_mgmt_tx--; 196 } 197 198 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb) 199 { 200 struct ath10k *ar = htt->ar; 201 int ret; 202 203 spin_lock_bh(&htt->tx_lock); 204 ret = idr_alloc(&htt->pending_tx, skb, 0, 205 htt->max_num_pending_tx, GFP_ATOMIC); 206 spin_unlock_bh(&htt->tx_lock); 207 208 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret); 209 210 return ret; 211 } 212 213 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id) 214 { 215 struct ath10k *ar = htt->ar; 216 217 lockdep_assert_held(&htt->tx_lock); 218 219 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %u\n", msdu_id); 220 221 idr_remove(&htt->pending_tx, msdu_id); 222 } 223 224 static void ath10k_htt_tx_free_cont_txbuf_32(struct ath10k_htt *htt) 225 { 226 struct ath10k *ar = htt->ar; 227 size_t size; 228 229 if (!htt->txbuf.vaddr_txbuff_32) 230 return; 231 232 size = htt->txbuf.size; 233 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_32, 234 htt->txbuf.paddr); 235 htt->txbuf.vaddr_txbuff_32 = NULL; 236 } 237 238 static int ath10k_htt_tx_alloc_cont_txbuf_32(struct ath10k_htt *htt) 239 { 240 struct ath10k *ar = htt->ar; 241 size_t size; 242 243 size = htt->max_num_pending_tx * 244 sizeof(struct ath10k_htt_txbuf_32); 245 246 htt->txbuf.vaddr_txbuff_32 = dma_alloc_coherent(ar->dev, size, 247 &htt->txbuf.paddr, 248 GFP_KERNEL); 249 if (!htt->txbuf.vaddr_txbuff_32) 250 return -ENOMEM; 251 252 htt->txbuf.size = size; 253 254 return 0; 255 } 256 257 static void ath10k_htt_tx_free_cont_txbuf_64(struct ath10k_htt *htt) 258 { 259 struct ath10k *ar = htt->ar; 260 size_t size; 261 262 if (!htt->txbuf.vaddr_txbuff_64) 263 return; 264 265 size = htt->txbuf.size; 266 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_64, 267 htt->txbuf.paddr); 268 htt->txbuf.vaddr_txbuff_64 = NULL; 269 } 270 271 static int ath10k_htt_tx_alloc_cont_txbuf_64(struct ath10k_htt *htt) 272 { 273 struct ath10k *ar = htt->ar; 274 size_t size; 275 276 size = htt->max_num_pending_tx * 277 sizeof(struct ath10k_htt_txbuf_64); 278 279 htt->txbuf.vaddr_txbuff_64 = dma_alloc_coherent(ar->dev, size, 280 &htt->txbuf.paddr, 281 GFP_KERNEL); 282 if (!htt->txbuf.vaddr_txbuff_64) 283 return -ENOMEM; 284 285 htt->txbuf.size = size; 286 287 return 0; 288 } 289 290 static void ath10k_htt_tx_free_cont_frag_desc_32(struct ath10k_htt *htt) 291 { 292 size_t size; 293 294 if (!htt->frag_desc.vaddr_desc_32) 295 return; 296 297 size = htt->max_num_pending_tx * 298 sizeof(struct htt_msdu_ext_desc); 299 300 dma_free_coherent(htt->ar->dev, 301 size, 302 htt->frag_desc.vaddr_desc_32, 303 htt->frag_desc.paddr); 304 305 htt->frag_desc.vaddr_desc_32 = NULL; 306 } 307 308 static int ath10k_htt_tx_alloc_cont_frag_desc_32(struct ath10k_htt *htt) 309 { 310 struct ath10k *ar = htt->ar; 311 size_t size; 312 313 if (!ar->hw_params.continuous_frag_desc) 314 return 0; 315 316 size = htt->max_num_pending_tx * 317 sizeof(struct htt_msdu_ext_desc); 318 htt->frag_desc.vaddr_desc_32 = dma_alloc_coherent(ar->dev, size, 319 &htt->frag_desc.paddr, 320 GFP_KERNEL); 321 if (!htt->frag_desc.vaddr_desc_32) { 322 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 323 return -ENOMEM; 324 } 325 htt->frag_desc.size = size; 326 327 return 0; 328 } 329 330 static void ath10k_htt_tx_free_cont_frag_desc_64(struct ath10k_htt *htt) 331 { 332 size_t size; 333 334 if (!htt->frag_desc.vaddr_desc_64) 335 return; 336 337 size = htt->max_num_pending_tx * 338 sizeof(struct htt_msdu_ext_desc_64); 339 340 dma_free_coherent(htt->ar->dev, 341 size, 342 htt->frag_desc.vaddr_desc_64, 343 htt->frag_desc.paddr); 344 345 htt->frag_desc.vaddr_desc_64 = NULL; 346 } 347 348 static int ath10k_htt_tx_alloc_cont_frag_desc_64(struct ath10k_htt *htt) 349 { 350 struct ath10k *ar = htt->ar; 351 size_t size; 352 353 if (!ar->hw_params.continuous_frag_desc) 354 return 0; 355 356 size = htt->max_num_pending_tx * 357 sizeof(struct htt_msdu_ext_desc_64); 358 359 htt->frag_desc.vaddr_desc_64 = dma_alloc_coherent(ar->dev, size, 360 &htt->frag_desc.paddr, 361 GFP_KERNEL); 362 if (!htt->frag_desc.vaddr_desc_64) { 363 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 364 return -ENOMEM; 365 } 366 htt->frag_desc.size = size; 367 368 return 0; 369 } 370 371 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt) 372 { 373 struct ath10k *ar = htt->ar; 374 size_t size; 375 376 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 377 ar->running_fw->fw_file.fw_features)) 378 return; 379 380 size = sizeof(*htt->tx_q_state.vaddr); 381 382 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE); 383 kfree(htt->tx_q_state.vaddr); 384 } 385 386 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt) 387 { 388 struct ath10k *ar = htt->ar; 389 size_t size; 390 int ret; 391 392 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 393 ar->running_fw->fw_file.fw_features)) 394 return 0; 395 396 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS; 397 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS; 398 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES; 399 400 size = sizeof(*htt->tx_q_state.vaddr); 401 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL); 402 if (!htt->tx_q_state.vaddr) 403 return -ENOMEM; 404 405 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr, 406 size, DMA_TO_DEVICE); 407 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr); 408 if (ret) { 409 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret); 410 kfree(htt->tx_q_state.vaddr); 411 return -EIO; 412 } 413 414 return 0; 415 } 416 417 static void ath10k_htt_tx_free_txdone_fifo(struct ath10k_htt *htt) 418 { 419 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo)); 420 kfifo_free(&htt->txdone_fifo); 421 } 422 423 static int ath10k_htt_tx_alloc_txdone_fifo(struct ath10k_htt *htt) 424 { 425 int ret; 426 size_t size; 427 428 size = roundup_pow_of_two(htt->max_num_pending_tx); 429 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL); 430 return ret; 431 } 432 433 static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt) 434 { 435 struct ath10k *ar = htt->ar; 436 int ret; 437 438 ret = ath10k_htt_alloc_txbuff(htt); 439 if (ret) { 440 ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret); 441 return ret; 442 } 443 444 ret = ath10k_htt_alloc_frag_desc(htt); 445 if (ret) { 446 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret); 447 goto free_txbuf; 448 } 449 450 ret = ath10k_htt_tx_alloc_txq(htt); 451 if (ret) { 452 ath10k_err(ar, "failed to alloc txq: %d\n", ret); 453 goto free_frag_desc; 454 } 455 456 ret = ath10k_htt_tx_alloc_txdone_fifo(htt); 457 if (ret) { 458 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret); 459 goto free_txq; 460 } 461 462 return 0; 463 464 free_txq: 465 ath10k_htt_tx_free_txq(htt); 466 467 free_frag_desc: 468 ath10k_htt_free_frag_desc(htt); 469 470 free_txbuf: 471 ath10k_htt_free_txbuff(htt); 472 473 return ret; 474 } 475 476 int ath10k_htt_tx_start(struct ath10k_htt *htt) 477 { 478 struct ath10k *ar = htt->ar; 479 int ret; 480 481 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n", 482 htt->max_num_pending_tx); 483 484 spin_lock_init(&htt->tx_lock); 485 idr_init(&htt->pending_tx); 486 487 if (htt->tx_mem_allocated) 488 return 0; 489 490 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 491 return 0; 492 493 ret = ath10k_htt_tx_alloc_buf(htt); 494 if (ret) 495 goto free_idr_pending_tx; 496 497 htt->tx_mem_allocated = true; 498 499 return 0; 500 501 free_idr_pending_tx: 502 idr_destroy(&htt->pending_tx); 503 504 return ret; 505 } 506 507 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx) 508 { 509 struct ath10k *ar = ctx; 510 struct ath10k_htt *htt = &ar->htt; 511 struct htt_tx_done tx_done = {0}; 512 513 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %u\n", msdu_id); 514 515 tx_done.msdu_id = msdu_id; 516 tx_done.status = HTT_TX_COMPL_STATE_DISCARD; 517 518 ath10k_txrx_tx_unref(htt, &tx_done); 519 520 return 0; 521 } 522 523 void ath10k_htt_tx_destroy(struct ath10k_htt *htt) 524 { 525 if (!htt->tx_mem_allocated) 526 return; 527 528 ath10k_htt_free_txbuff(htt); 529 ath10k_htt_tx_free_txq(htt); 530 ath10k_htt_free_frag_desc(htt); 531 ath10k_htt_tx_free_txdone_fifo(htt); 532 htt->tx_mem_allocated = false; 533 } 534 535 static void ath10k_htt_flush_tx_queue(struct ath10k_htt *htt) 536 { 537 ath10k_htc_stop_hl(htt->ar); 538 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar); 539 } 540 541 void ath10k_htt_tx_stop(struct ath10k_htt *htt) 542 { 543 ath10k_htt_flush_tx_queue(htt); 544 idr_destroy(&htt->pending_tx); 545 } 546 547 void ath10k_htt_tx_free(struct ath10k_htt *htt) 548 { 549 ath10k_htt_tx_stop(htt); 550 ath10k_htt_tx_destroy(htt); 551 } 552 553 void ath10k_htt_op_ep_tx_credits(struct ath10k *ar) 554 { 555 queue_work(ar->workqueue, &ar->bundle_tx_work); 556 } 557 558 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb) 559 { 560 struct ath10k_htt *htt = &ar->htt; 561 struct htt_tx_done tx_done = {0}; 562 struct htt_cmd_hdr *htt_hdr; 563 struct htt_data_tx_desc *desc_hdr = NULL; 564 u16 flags1 = 0; 565 u8 msg_type = 0; 566 567 if (htt->disable_tx_comp) { 568 htt_hdr = (struct htt_cmd_hdr *)skb->data; 569 msg_type = htt_hdr->msg_type; 570 571 if (msg_type == HTT_H2T_MSG_TYPE_TX_FRM) { 572 desc_hdr = (struct htt_data_tx_desc *) 573 (skb->data + sizeof(*htt_hdr)); 574 flags1 = __le16_to_cpu(desc_hdr->flags1); 575 skb_pull(skb, sizeof(struct htt_cmd_hdr)); 576 skb_pull(skb, sizeof(struct htt_data_tx_desc)); 577 } 578 } 579 580 dev_kfree_skb_any(skb); 581 582 if ((!htt->disable_tx_comp) || (msg_type != HTT_H2T_MSG_TYPE_TX_FRM)) 583 return; 584 585 ath10k_dbg(ar, ATH10K_DBG_HTT, 586 "htt tx complete msdu id:%u ,flags1:%x\n", 587 __le16_to_cpu(desc_hdr->id), flags1); 588 589 if (flags1 & HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE) 590 return; 591 592 tx_done.status = HTT_TX_COMPL_STATE_ACK; 593 tx_done.msdu_id = __le16_to_cpu(desc_hdr->id); 594 ath10k_txrx_tx_unref(&ar->htt, &tx_done); 595 } 596 597 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb) 598 { 599 dev_kfree_skb_any(skb); 600 } 601 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete); 602 603 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt) 604 { 605 struct ath10k *ar = htt->ar; 606 struct sk_buff *skb; 607 struct htt_cmd *cmd; 608 int len = 0; 609 int ret; 610 611 len += sizeof(cmd->hdr); 612 len += sizeof(cmd->ver_req); 613 614 skb = ath10k_htc_alloc_skb(ar, len); 615 if (!skb) 616 return -ENOMEM; 617 618 skb_put(skb, len); 619 cmd = (struct htt_cmd *)skb->data; 620 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ; 621 622 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 623 if (ret) { 624 dev_kfree_skb_any(skb); 625 return ret; 626 } 627 628 return 0; 629 } 630 631 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, 632 u64 cookie) 633 { 634 struct ath10k *ar = htt->ar; 635 struct htt_stats_req *req; 636 struct sk_buff *skb; 637 struct htt_cmd *cmd; 638 int len = 0, ret; 639 640 len += sizeof(cmd->hdr); 641 len += sizeof(cmd->stats_req); 642 643 skb = ath10k_htc_alloc_skb(ar, len); 644 if (!skb) 645 return -ENOMEM; 646 647 skb_put(skb, len); 648 cmd = (struct htt_cmd *)skb->data; 649 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ; 650 651 req = &cmd->stats_req; 652 653 memset(req, 0, sizeof(*req)); 654 655 /* currently we support only max 24 bit masks so no need to worry 656 * about endian support 657 */ 658 memcpy(req->upload_types, &mask, 3); 659 memcpy(req->reset_types, &reset_mask, 3); 660 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID; 661 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff); 662 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32); 663 664 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 665 if (ret) { 666 ath10k_warn(ar, "failed to send htt type stats request: %d", 667 ret); 668 dev_kfree_skb_any(skb); 669 return ret; 670 } 671 672 return 0; 673 } 674 675 static int ath10k_htt_send_frag_desc_bank_cfg_32(struct ath10k_htt *htt) 676 { 677 struct ath10k *ar = htt->ar; 678 struct sk_buff *skb; 679 struct htt_cmd *cmd; 680 struct htt_frag_desc_bank_cfg32 *cfg; 681 int ret, size; 682 u8 info; 683 684 if (!ar->hw_params.continuous_frag_desc) 685 return 0; 686 687 if (!htt->frag_desc.paddr) { 688 ath10k_warn(ar, "invalid frag desc memory\n"); 689 return -EINVAL; 690 } 691 692 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg32); 693 skb = ath10k_htc_alloc_skb(ar, size); 694 if (!skb) 695 return -ENOMEM; 696 697 skb_put(skb, size); 698 cmd = (struct htt_cmd *)skb->data; 699 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 700 701 info = 0; 702 info |= SM(htt->tx_q_state.type, 703 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 704 705 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 706 ar->running_fw->fw_file.fw_features)) 707 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 708 709 cfg = &cmd->frag_desc_bank_cfg32; 710 cfg->info = info; 711 cfg->num_banks = 1; 712 cfg->desc_size = sizeof(struct htt_msdu_ext_desc); 713 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr); 714 cfg->bank_id[0].bank_min_id = 0; 715 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 716 1); 717 718 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 719 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 720 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 721 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 722 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 723 724 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 725 726 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 727 if (ret) { 728 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 729 ret); 730 dev_kfree_skb_any(skb); 731 return ret; 732 } 733 734 return 0; 735 } 736 737 static int ath10k_htt_send_frag_desc_bank_cfg_64(struct ath10k_htt *htt) 738 { 739 struct ath10k *ar = htt->ar; 740 struct sk_buff *skb; 741 struct htt_cmd *cmd; 742 struct htt_frag_desc_bank_cfg64 *cfg; 743 int ret, size; 744 u8 info; 745 746 if (!ar->hw_params.continuous_frag_desc) 747 return 0; 748 749 if (!htt->frag_desc.paddr) { 750 ath10k_warn(ar, "invalid frag desc memory\n"); 751 return -EINVAL; 752 } 753 754 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg64); 755 skb = ath10k_htc_alloc_skb(ar, size); 756 if (!skb) 757 return -ENOMEM; 758 759 skb_put(skb, size); 760 cmd = (struct htt_cmd *)skb->data; 761 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 762 763 info = 0; 764 info |= SM(htt->tx_q_state.type, 765 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 766 767 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 768 ar->running_fw->fw_file.fw_features)) 769 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 770 771 cfg = &cmd->frag_desc_bank_cfg64; 772 cfg->info = info; 773 cfg->num_banks = 1; 774 cfg->desc_size = sizeof(struct htt_msdu_ext_desc_64); 775 cfg->bank_base_addrs[0] = __cpu_to_le64(htt->frag_desc.paddr); 776 cfg->bank_id[0].bank_min_id = 0; 777 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 778 1); 779 780 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 781 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 782 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 783 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 784 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 785 786 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 787 788 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 789 if (ret) { 790 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 791 ret); 792 dev_kfree_skb_any(skb); 793 return ret; 794 } 795 796 return 0; 797 } 798 799 static void ath10k_htt_fill_rx_desc_offset_32(void *rx_ring) 800 { 801 struct htt_rx_ring_setup_ring32 *ring = 802 (struct htt_rx_ring_setup_ring32 *)rx_ring; 803 804 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4) 805 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); 806 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); 807 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); 808 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); 809 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); 810 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); 811 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); 812 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); 813 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); 814 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); 815 #undef desc_offset 816 } 817 818 static void ath10k_htt_fill_rx_desc_offset_64(void *rx_ring) 819 { 820 struct htt_rx_ring_setup_ring64 *ring = 821 (struct htt_rx_ring_setup_ring64 *)rx_ring; 822 823 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4) 824 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); 825 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); 826 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); 827 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); 828 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); 829 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); 830 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); 831 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); 832 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); 833 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); 834 #undef desc_offset 835 } 836 837 static int ath10k_htt_send_rx_ring_cfg_32(struct ath10k_htt *htt) 838 { 839 struct ath10k *ar = htt->ar; 840 struct sk_buff *skb; 841 struct htt_cmd *cmd; 842 struct htt_rx_ring_setup_ring32 *ring; 843 const int num_rx_ring = 1; 844 u16 flags; 845 u32 fw_idx; 846 int len; 847 int ret; 848 849 /* 850 * the HW expects the buffer to be an integral number of 4-byte 851 * "words" 852 */ 853 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 854 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 855 856 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 857 + (sizeof(*ring) * num_rx_ring); 858 skb = ath10k_htc_alloc_skb(ar, len); 859 if (!skb) 860 return -ENOMEM; 861 862 skb_put(skb, len); 863 864 cmd = (struct htt_cmd *)skb->data; 865 ring = &cmd->rx_setup_32.rings[0]; 866 867 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 868 cmd->rx_setup_32.hdr.num_rings = 1; 869 870 /* FIXME: do we need all of this? */ 871 flags = 0; 872 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 873 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 874 flags |= HTT_RX_RING_FLAGS_PPDU_START; 875 flags |= HTT_RX_RING_FLAGS_PPDU_END; 876 flags |= HTT_RX_RING_FLAGS_MPDU_START; 877 flags |= HTT_RX_RING_FLAGS_MPDU_END; 878 flags |= HTT_RX_RING_FLAGS_MSDU_START; 879 flags |= HTT_RX_RING_FLAGS_MSDU_END; 880 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 881 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 882 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 883 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 884 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 885 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 886 flags |= HTT_RX_RING_FLAGS_NULL_RX; 887 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 888 889 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 890 891 ring->fw_idx_shadow_reg_paddr = 892 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); 893 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); 894 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 895 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 896 ring->flags = __cpu_to_le16(flags); 897 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 898 899 ath10k_htt_fill_rx_desc_offset_32(ring); 900 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 901 if (ret) { 902 dev_kfree_skb_any(skb); 903 return ret; 904 } 905 906 return 0; 907 } 908 909 static int ath10k_htt_send_rx_ring_cfg_64(struct ath10k_htt *htt) 910 { 911 struct ath10k *ar = htt->ar; 912 struct sk_buff *skb; 913 struct htt_cmd *cmd; 914 struct htt_rx_ring_setup_ring64 *ring; 915 const int num_rx_ring = 1; 916 u16 flags; 917 u32 fw_idx; 918 int len; 919 int ret; 920 921 /* HW expects the buffer to be an integral number of 4-byte 922 * "words" 923 */ 924 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 925 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 926 927 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_64.hdr) 928 + (sizeof(*ring) * num_rx_ring); 929 skb = ath10k_htc_alloc_skb(ar, len); 930 if (!skb) 931 return -ENOMEM; 932 933 skb_put(skb, len); 934 935 cmd = (struct htt_cmd *)skb->data; 936 ring = &cmd->rx_setup_64.rings[0]; 937 938 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 939 cmd->rx_setup_64.hdr.num_rings = 1; 940 941 flags = 0; 942 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 943 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 944 flags |= HTT_RX_RING_FLAGS_PPDU_START; 945 flags |= HTT_RX_RING_FLAGS_PPDU_END; 946 flags |= HTT_RX_RING_FLAGS_MPDU_START; 947 flags |= HTT_RX_RING_FLAGS_MPDU_END; 948 flags |= HTT_RX_RING_FLAGS_MSDU_START; 949 flags |= HTT_RX_RING_FLAGS_MSDU_END; 950 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 951 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 952 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 953 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 954 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 955 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 956 flags |= HTT_RX_RING_FLAGS_NULL_RX; 957 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 958 959 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 960 961 ring->fw_idx_shadow_reg_paddr = __cpu_to_le64(htt->rx_ring.alloc_idx.paddr); 962 ring->rx_ring_base_paddr = __cpu_to_le64(htt->rx_ring.base_paddr); 963 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 964 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 965 ring->flags = __cpu_to_le16(flags); 966 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 967 968 ath10k_htt_fill_rx_desc_offset_64(ring); 969 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 970 if (ret) { 971 dev_kfree_skb_any(skb); 972 return ret; 973 } 974 975 return 0; 976 } 977 978 static int ath10k_htt_send_rx_ring_cfg_hl(struct ath10k_htt *htt) 979 { 980 struct ath10k *ar = htt->ar; 981 struct sk_buff *skb; 982 struct htt_cmd *cmd; 983 struct htt_rx_ring_setup_ring32 *ring; 984 const int num_rx_ring = 1; 985 u16 flags; 986 int len; 987 int ret; 988 989 /* 990 * the HW expects the buffer to be an integral number of 4-byte 991 * "words" 992 */ 993 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 994 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 995 996 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 997 + (sizeof(*ring) * num_rx_ring); 998 skb = ath10k_htc_alloc_skb(ar, len); 999 if (!skb) 1000 return -ENOMEM; 1001 1002 skb_put(skb, len); 1003 1004 cmd = (struct htt_cmd *)skb->data; 1005 ring = &cmd->rx_setup_32.rings[0]; 1006 1007 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 1008 cmd->rx_setup_32.hdr.num_rings = 1; 1009 1010 flags = 0; 1011 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 1012 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 1013 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 1014 1015 memset(ring, 0, sizeof(*ring)); 1016 ring->rx_ring_len = __cpu_to_le16(HTT_RX_RING_SIZE_MIN); 1017 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 1018 ring->flags = __cpu_to_le16(flags); 1019 1020 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1021 if (ret) { 1022 dev_kfree_skb_any(skb); 1023 return ret; 1024 } 1025 1026 return 0; 1027 } 1028 1029 static int ath10k_htt_h2t_aggr_cfg_msg_32(struct ath10k_htt *htt, 1030 u8 max_subfrms_ampdu, 1031 u8 max_subfrms_amsdu) 1032 { 1033 struct ath10k *ar = htt->ar; 1034 struct htt_aggr_conf *aggr_conf; 1035 struct sk_buff *skb; 1036 struct htt_cmd *cmd; 1037 int len; 1038 int ret; 1039 1040 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 1041 1042 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 1043 return -EINVAL; 1044 1045 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 1046 return -EINVAL; 1047 1048 len = sizeof(cmd->hdr); 1049 len += sizeof(cmd->aggr_conf); 1050 1051 skb = ath10k_htc_alloc_skb(ar, len); 1052 if (!skb) 1053 return -ENOMEM; 1054 1055 skb_put(skb, len); 1056 cmd = (struct htt_cmd *)skb->data; 1057 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1058 1059 aggr_conf = &cmd->aggr_conf; 1060 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1061 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1062 1063 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1064 aggr_conf->max_num_amsdu_subframes, 1065 aggr_conf->max_num_ampdu_subframes); 1066 1067 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1068 if (ret) { 1069 dev_kfree_skb_any(skb); 1070 return ret; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int ath10k_htt_h2t_aggr_cfg_msg_v2(struct ath10k_htt *htt, 1077 u8 max_subfrms_ampdu, 1078 u8 max_subfrms_amsdu) 1079 { 1080 struct ath10k *ar = htt->ar; 1081 struct htt_aggr_conf_v2 *aggr_conf; 1082 struct sk_buff *skb; 1083 struct htt_cmd *cmd; 1084 int len; 1085 int ret; 1086 1087 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 1088 1089 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 1090 return -EINVAL; 1091 1092 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 1093 return -EINVAL; 1094 1095 len = sizeof(cmd->hdr); 1096 len += sizeof(cmd->aggr_conf_v2); 1097 1098 skb = ath10k_htc_alloc_skb(ar, len); 1099 if (!skb) 1100 return -ENOMEM; 1101 1102 skb_put(skb, len); 1103 cmd = (struct htt_cmd *)skb->data; 1104 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1105 1106 aggr_conf = &cmd->aggr_conf_v2; 1107 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1108 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1109 1110 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1111 aggr_conf->max_num_amsdu_subframes, 1112 aggr_conf->max_num_ampdu_subframes); 1113 1114 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1115 if (ret) { 1116 dev_kfree_skb_any(skb); 1117 return ret; 1118 } 1119 1120 return 0; 1121 } 1122 1123 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 1124 __le32 token, 1125 __le16 fetch_seq_num, 1126 struct htt_tx_fetch_record *records, 1127 size_t num_records) 1128 { 1129 struct sk_buff *skb; 1130 struct htt_cmd *cmd; 1131 const u16 resp_id = 0; 1132 int len = 0; 1133 int ret; 1134 1135 /* Response IDs are echo-ed back only for host driver convienence 1136 * purposes. They aren't used for anything in the driver yet so use 0. 1137 */ 1138 1139 len += sizeof(cmd->hdr); 1140 len += sizeof(cmd->tx_fetch_resp); 1141 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records; 1142 1143 skb = ath10k_htc_alloc_skb(ar, len); 1144 if (!skb) 1145 return -ENOMEM; 1146 1147 skb_put(skb, len); 1148 cmd = (struct htt_cmd *)skb->data; 1149 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP; 1150 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id); 1151 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num; 1152 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records); 1153 cmd->tx_fetch_resp.token = token; 1154 1155 memcpy(cmd->tx_fetch_resp.records, records, 1156 sizeof(records[0]) * num_records); 1157 1158 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb); 1159 if (ret) { 1160 ath10k_warn(ar, "failed to submit htc command: %d\n", ret); 1161 goto err_free_skb; 1162 } 1163 1164 return 0; 1165 1166 err_free_skb: 1167 dev_kfree_skb_any(skb); 1168 1169 return ret; 1170 } 1171 1172 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb) 1173 { 1174 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1175 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1176 struct ath10k_vif *arvif; 1177 1178 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { 1179 return ar->scan.vdev_id; 1180 } else if (cb->vif) { 1181 arvif = (void *)cb->vif->drv_priv; 1182 return arvif->vdev_id; 1183 } else if (ar->monitor_started) { 1184 return ar->monitor_vdev_id; 1185 } else { 1186 return 0; 1187 } 1188 } 1189 1190 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth) 1191 { 1192 struct ieee80211_hdr *hdr = (void *)skb->data; 1193 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1194 1195 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control)) 1196 return HTT_DATA_TX_EXT_TID_MGMT; 1197 else if (cb->flags & ATH10K_SKB_F_QOS) 1198 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1199 else 1200 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; 1201 } 1202 1203 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) 1204 { 1205 struct ath10k *ar = htt->ar; 1206 struct device *dev = ar->dev; 1207 struct sk_buff *txdesc = NULL; 1208 struct htt_cmd *cmd; 1209 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1210 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1211 int len = 0; 1212 int msdu_id = -1; 1213 int res; 1214 const u8 *peer_addr; 1215 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1216 1217 len += sizeof(cmd->hdr); 1218 len += sizeof(cmd->mgmt_tx); 1219 1220 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1221 if (res < 0) 1222 goto err; 1223 1224 msdu_id = res; 1225 1226 if ((ieee80211_is_action(hdr->frame_control) || 1227 ieee80211_is_deauth(hdr->frame_control) || 1228 ieee80211_is_disassoc(hdr->frame_control)) && 1229 ieee80211_has_protected(hdr->frame_control)) { 1230 peer_addr = hdr->addr1; 1231 if (is_multicast_ether_addr(peer_addr)) { 1232 skb_put(msdu, sizeof(struct ieee80211_mmie_16)); 1233 } else { 1234 if (skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP || 1235 skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP_256) 1236 skb_put(msdu, IEEE80211_GCMP_MIC_LEN); 1237 else 1238 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1239 } 1240 } 1241 1242 txdesc = ath10k_htc_alloc_skb(ar, len); 1243 if (!txdesc) { 1244 res = -ENOMEM; 1245 goto err_free_msdu_id; 1246 } 1247 1248 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1249 DMA_TO_DEVICE); 1250 res = dma_mapping_error(dev, skb_cb->paddr); 1251 if (res) { 1252 res = -EIO; 1253 goto err_free_txdesc; 1254 } 1255 1256 skb_put(txdesc, len); 1257 cmd = (struct htt_cmd *)txdesc->data; 1258 memset(cmd, 0, len); 1259 1260 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX; 1261 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr); 1262 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len); 1263 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id); 1264 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id); 1265 memcpy(cmd->mgmt_tx.hdr, msdu->data, 1266 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN)); 1267 1268 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc); 1269 if (res) 1270 goto err_unmap_msdu; 1271 1272 return 0; 1273 1274 err_unmap_msdu: 1275 if (ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL) 1276 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1277 err_free_txdesc: 1278 dev_kfree_skb_any(txdesc); 1279 err_free_msdu_id: 1280 spin_lock_bh(&htt->tx_lock); 1281 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1282 spin_unlock_bh(&htt->tx_lock); 1283 err: 1284 return res; 1285 } 1286 1287 #define HTT_TX_HL_NEEDED_HEADROOM \ 1288 (unsigned int)(sizeof(struct htt_cmd_hdr) + \ 1289 sizeof(struct htt_data_tx_desc) + \ 1290 sizeof(struct ath10k_htc_hdr)) 1291 1292 static int ath10k_htt_tx_hl(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 1293 struct sk_buff *msdu) 1294 { 1295 struct ath10k *ar = htt->ar; 1296 int res, data_len; 1297 struct htt_cmd_hdr *cmd_hdr; 1298 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1299 struct htt_data_tx_desc *tx_desc; 1300 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1301 struct sk_buff *tmp_skb; 1302 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1303 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1304 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1305 u8 flags0 = 0; 1306 u16 flags1 = 0; 1307 u16 msdu_id = 0; 1308 1309 if ((ieee80211_is_action(hdr->frame_control) || 1310 ieee80211_is_deauth(hdr->frame_control) || 1311 ieee80211_is_disassoc(hdr->frame_control)) && 1312 ieee80211_has_protected(hdr->frame_control)) { 1313 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1314 } 1315 1316 data_len = msdu->len; 1317 1318 switch (txmode) { 1319 case ATH10K_HW_TXRX_RAW: 1320 case ATH10K_HW_TXRX_NATIVE_WIFI: 1321 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1322 fallthrough; 1323 case ATH10K_HW_TXRX_ETHERNET: 1324 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1325 break; 1326 case ATH10K_HW_TXRX_MGMT: 1327 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1328 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1329 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1330 1331 if (htt->disable_tx_comp) 1332 flags1 |= HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE; 1333 break; 1334 } 1335 1336 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1337 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1338 1339 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1340 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1341 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1342 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1343 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1344 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1345 } 1346 1347 /* Prepend the HTT header and TX desc struct to the data message 1348 * and realloc the skb if it does not have enough headroom. 1349 */ 1350 if (skb_headroom(msdu) < HTT_TX_HL_NEEDED_HEADROOM) { 1351 tmp_skb = msdu; 1352 1353 ath10k_dbg(htt->ar, ATH10K_DBG_HTT, 1354 "Not enough headroom in skb. Current headroom: %u, needed: %u. Reallocating...\n", 1355 skb_headroom(msdu), HTT_TX_HL_NEEDED_HEADROOM); 1356 msdu = skb_realloc_headroom(msdu, HTT_TX_HL_NEEDED_HEADROOM); 1357 kfree_skb(tmp_skb); 1358 if (!msdu) { 1359 ath10k_warn(htt->ar, "htt hl tx: Unable to realloc skb!\n"); 1360 res = -ENOMEM; 1361 goto out; 1362 } 1363 } 1364 1365 if (ar->bus_param.hl_msdu_ids) { 1366 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1367 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1368 if (res < 0) { 1369 ath10k_err(ar, "msdu_id allocation failed %d\n", res); 1370 goto out; 1371 } 1372 msdu_id = res; 1373 } 1374 1375 /* As msdu is freed by mac80211 (in ieee80211_tx_status()) and by 1376 * ath10k (in ath10k_htt_htc_tx_complete()) we have to increase 1377 * reference by one to avoid a use-after-free case and a double 1378 * free. 1379 */ 1380 skb_get(msdu); 1381 1382 skb_push(msdu, sizeof(*cmd_hdr)); 1383 skb_push(msdu, sizeof(*tx_desc)); 1384 cmd_hdr = (struct htt_cmd_hdr *)msdu->data; 1385 tx_desc = (struct htt_data_tx_desc *)(msdu->data + sizeof(*cmd_hdr)); 1386 1387 cmd_hdr->msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1388 tx_desc->flags0 = flags0; 1389 tx_desc->flags1 = __cpu_to_le16(flags1); 1390 tx_desc->len = __cpu_to_le16(data_len); 1391 tx_desc->id = __cpu_to_le16(msdu_id); 1392 tx_desc->frags_paddr = 0; /* always zero */ 1393 /* Initialize peer_id to INVALID_PEER because this is NOT 1394 * Reinjection path 1395 */ 1396 tx_desc->peerid = __cpu_to_le32(HTT_INVALID_PEERID); 1397 1398 res = ath10k_htc_send_hl(&htt->ar->htc, htt->eid, msdu); 1399 1400 out: 1401 return res; 1402 } 1403 1404 static int ath10k_htt_tx_32(struct ath10k_htt *htt, 1405 enum ath10k_hw_txrx_mode txmode, 1406 struct sk_buff *msdu) 1407 { 1408 struct ath10k *ar = htt->ar; 1409 struct device *dev = ar->dev; 1410 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1411 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1412 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1413 struct ath10k_hif_sg_item sg_items[2]; 1414 struct ath10k_htt_txbuf_32 *txbuf; 1415 struct htt_data_tx_desc_frag *frags; 1416 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1417 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1418 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1419 int prefetch_len; 1420 int res; 1421 u8 flags0 = 0; 1422 u16 msdu_id, flags1 = 0; 1423 u16 freq = 0; 1424 u32 frags_paddr = 0; 1425 u32 txbuf_paddr; 1426 struct htt_msdu_ext_desc *ext_desc = NULL; 1427 struct htt_msdu_ext_desc *ext_desc_t = NULL; 1428 1429 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1430 if (res < 0) 1431 goto err; 1432 1433 msdu_id = res; 1434 1435 prefetch_len = min(htt->prefetch_len, msdu->len); 1436 prefetch_len = roundup(prefetch_len, 4); 1437 1438 txbuf = htt->txbuf.vaddr_txbuff_32 + msdu_id; 1439 txbuf_paddr = htt->txbuf.paddr + 1440 (sizeof(struct ath10k_htt_txbuf_32) * msdu_id); 1441 1442 if ((ieee80211_is_action(hdr->frame_control) || 1443 ieee80211_is_deauth(hdr->frame_control) || 1444 ieee80211_is_disassoc(hdr->frame_control)) && 1445 ieee80211_has_protected(hdr->frame_control)) { 1446 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1447 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1448 txmode == ATH10K_HW_TXRX_RAW && 1449 ieee80211_has_protected(hdr->frame_control)) { 1450 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1451 } 1452 1453 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1454 DMA_TO_DEVICE); 1455 res = dma_mapping_error(dev, skb_cb->paddr); 1456 if (res) { 1457 res = -EIO; 1458 goto err_free_msdu_id; 1459 } 1460 1461 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1462 freq = ar->scan.roc_freq; 1463 1464 switch (txmode) { 1465 case ATH10K_HW_TXRX_RAW: 1466 case ATH10K_HW_TXRX_NATIVE_WIFI: 1467 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1468 fallthrough; 1469 case ATH10K_HW_TXRX_ETHERNET: 1470 if (ar->hw_params.continuous_frag_desc) { 1471 ext_desc_t = htt->frag_desc.vaddr_desc_32; 1472 memset(&ext_desc_t[msdu_id], 0, 1473 sizeof(struct htt_msdu_ext_desc)); 1474 frags = (struct htt_data_tx_desc_frag *) 1475 &ext_desc_t[msdu_id].frags; 1476 ext_desc = &ext_desc_t[msdu_id]; 1477 frags[0].tword_addr.paddr_lo = 1478 __cpu_to_le32(skb_cb->paddr); 1479 frags[0].tword_addr.paddr_hi = 0; 1480 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1481 1482 frags_paddr = htt->frag_desc.paddr + 1483 (sizeof(struct htt_msdu_ext_desc) * msdu_id); 1484 } else { 1485 frags = txbuf->frags; 1486 frags[0].dword_addr.paddr = 1487 __cpu_to_le32(skb_cb->paddr); 1488 frags[0].dword_addr.len = __cpu_to_le32(msdu->len); 1489 frags[1].dword_addr.paddr = 0; 1490 frags[1].dword_addr.len = 0; 1491 1492 frags_paddr = txbuf_paddr; 1493 } 1494 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1495 break; 1496 case ATH10K_HW_TXRX_MGMT: 1497 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1498 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1499 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1500 1501 frags_paddr = skb_cb->paddr; 1502 break; 1503 } 1504 1505 /* Normally all commands go through HTC which manages tx credits for 1506 * each endpoint and notifies when tx is completed. 1507 * 1508 * HTT endpoint is creditless so there's no need to care about HTC 1509 * flags. In that case it is trivial to fill the HTC header here. 1510 * 1511 * MSDU transmission is considered completed upon HTT event. This 1512 * implies no relevant resources can be freed until after the event is 1513 * received. That's why HTC tx completion handler itself is ignored by 1514 * setting NULL to transfer_context for all sg items. 1515 * 1516 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1517 * as it's a waste of resources. By bypassing HTC it is possible to 1518 * avoid extra memory allocations, compress data structures and thus 1519 * improve performance. 1520 */ 1521 1522 txbuf->htc_hdr.eid = htt->eid; 1523 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1524 sizeof(txbuf->cmd_tx) + 1525 prefetch_len); 1526 txbuf->htc_hdr.flags = 0; 1527 1528 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1529 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1530 1531 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1532 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1533 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1534 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1535 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1536 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1537 if (ar->hw_params.continuous_frag_desc) 1538 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE; 1539 } 1540 1541 /* Prevent firmware from sending up tx inspection requests. There's 1542 * nothing ath10k can do with frames requested for inspection so force 1543 * it to simply rely a regular tx completion with discard status. 1544 */ 1545 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1546 1547 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1548 txbuf->cmd_tx.flags0 = flags0; 1549 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1550 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1551 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1552 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr); 1553 if (ath10k_mac_tx_frm_has_freq(ar)) { 1554 txbuf->cmd_tx.offchan_tx.peerid = 1555 __cpu_to_le16(HTT_INVALID_PEERID); 1556 txbuf->cmd_tx.offchan_tx.freq = 1557 __cpu_to_le16(freq); 1558 } else { 1559 txbuf->cmd_tx.peerid = 1560 __cpu_to_le32(HTT_INVALID_PEERID); 1561 } 1562 1563 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1564 ath10k_dbg(ar, ATH10K_DBG_HTT, 1565 "htt tx flags0 %u flags1 %u len %d id %u frags_paddr %pad, msdu_paddr %pad vdev %u tid %u freq %u\n", 1566 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1567 &skb_cb->paddr, vdev_id, tid, freq); 1568 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1569 msdu->data, msdu->len); 1570 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1571 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1572 1573 sg_items[0].transfer_id = 0; 1574 sg_items[0].transfer_context = NULL; 1575 sg_items[0].vaddr = &txbuf->htc_hdr; 1576 sg_items[0].paddr = txbuf_paddr + 1577 sizeof(txbuf->frags); 1578 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1579 sizeof(txbuf->cmd_hdr) + 1580 sizeof(txbuf->cmd_tx); 1581 1582 sg_items[1].transfer_id = 0; 1583 sg_items[1].transfer_context = NULL; 1584 sg_items[1].vaddr = msdu->data; 1585 sg_items[1].paddr = skb_cb->paddr; 1586 sg_items[1].len = prefetch_len; 1587 1588 res = ath10k_hif_tx_sg(htt->ar, 1589 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1590 sg_items, ARRAY_SIZE(sg_items)); 1591 if (res) 1592 goto err_unmap_msdu; 1593 1594 return 0; 1595 1596 err_unmap_msdu: 1597 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1598 err_free_msdu_id: 1599 spin_lock_bh(&htt->tx_lock); 1600 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1601 spin_unlock_bh(&htt->tx_lock); 1602 err: 1603 return res; 1604 } 1605 1606 static int ath10k_htt_tx_64(struct ath10k_htt *htt, 1607 enum ath10k_hw_txrx_mode txmode, 1608 struct sk_buff *msdu) 1609 { 1610 struct ath10k *ar = htt->ar; 1611 struct device *dev = ar->dev; 1612 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1613 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1614 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1615 struct ath10k_hif_sg_item sg_items[2]; 1616 struct ath10k_htt_txbuf_64 *txbuf; 1617 struct htt_data_tx_desc_frag *frags; 1618 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1619 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1620 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1621 int prefetch_len; 1622 int res; 1623 u8 flags0 = 0; 1624 u16 msdu_id, flags1 = 0; 1625 u16 freq = 0; 1626 dma_addr_t frags_paddr = 0; 1627 dma_addr_t txbuf_paddr; 1628 struct htt_msdu_ext_desc_64 *ext_desc = NULL; 1629 struct htt_msdu_ext_desc_64 *ext_desc_t = NULL; 1630 1631 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1632 if (res < 0) 1633 goto err; 1634 1635 msdu_id = res; 1636 1637 prefetch_len = min(htt->prefetch_len, msdu->len); 1638 prefetch_len = roundup(prefetch_len, 4); 1639 1640 txbuf = htt->txbuf.vaddr_txbuff_64 + msdu_id; 1641 txbuf_paddr = htt->txbuf.paddr + 1642 (sizeof(struct ath10k_htt_txbuf_64) * msdu_id); 1643 1644 if ((ieee80211_is_action(hdr->frame_control) || 1645 ieee80211_is_deauth(hdr->frame_control) || 1646 ieee80211_is_disassoc(hdr->frame_control)) && 1647 ieee80211_has_protected(hdr->frame_control)) { 1648 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1649 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1650 txmode == ATH10K_HW_TXRX_RAW && 1651 ieee80211_has_protected(hdr->frame_control)) { 1652 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1653 } 1654 1655 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1656 DMA_TO_DEVICE); 1657 res = dma_mapping_error(dev, skb_cb->paddr); 1658 if (res) { 1659 res = -EIO; 1660 goto err_free_msdu_id; 1661 } 1662 1663 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1664 freq = ar->scan.roc_freq; 1665 1666 switch (txmode) { 1667 case ATH10K_HW_TXRX_RAW: 1668 case ATH10K_HW_TXRX_NATIVE_WIFI: 1669 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1670 fallthrough; 1671 case ATH10K_HW_TXRX_ETHERNET: 1672 if (ar->hw_params.continuous_frag_desc) { 1673 ext_desc_t = htt->frag_desc.vaddr_desc_64; 1674 memset(&ext_desc_t[msdu_id], 0, 1675 sizeof(struct htt_msdu_ext_desc_64)); 1676 frags = (struct htt_data_tx_desc_frag *) 1677 &ext_desc_t[msdu_id].frags; 1678 ext_desc = &ext_desc_t[msdu_id]; 1679 frags[0].tword_addr.paddr_lo = 1680 __cpu_to_le32(skb_cb->paddr); 1681 frags[0].tword_addr.paddr_hi = 1682 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1683 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1684 1685 frags_paddr = htt->frag_desc.paddr + 1686 (sizeof(struct htt_msdu_ext_desc_64) * msdu_id); 1687 } else { 1688 frags = txbuf->frags; 1689 frags[0].tword_addr.paddr_lo = 1690 __cpu_to_le32(skb_cb->paddr); 1691 frags[0].tword_addr.paddr_hi = 1692 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1693 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1694 frags[1].tword_addr.paddr_lo = 0; 1695 frags[1].tword_addr.paddr_hi = 0; 1696 frags[1].tword_addr.len_16 = 0; 1697 } 1698 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1699 break; 1700 case ATH10K_HW_TXRX_MGMT: 1701 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1702 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1703 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1704 1705 frags_paddr = skb_cb->paddr; 1706 break; 1707 } 1708 1709 /* Normally all commands go through HTC which manages tx credits for 1710 * each endpoint and notifies when tx is completed. 1711 * 1712 * HTT endpoint is creditless so there's no need to care about HTC 1713 * flags. In that case it is trivial to fill the HTC header here. 1714 * 1715 * MSDU transmission is considered completed upon HTT event. This 1716 * implies no relevant resources can be freed until after the event is 1717 * received. That's why HTC tx completion handler itself is ignored by 1718 * setting NULL to transfer_context for all sg items. 1719 * 1720 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1721 * as it's a waste of resources. By bypassing HTC it is possible to 1722 * avoid extra memory allocations, compress data structures and thus 1723 * improve performance. 1724 */ 1725 1726 txbuf->htc_hdr.eid = htt->eid; 1727 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1728 sizeof(txbuf->cmd_tx) + 1729 prefetch_len); 1730 txbuf->htc_hdr.flags = 0; 1731 1732 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1733 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1734 1735 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1736 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1737 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1738 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1739 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1740 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1741 if (ar->hw_params.continuous_frag_desc) { 1742 memset(ext_desc->tso_flag, 0, sizeof(ext_desc->tso_flag)); 1743 ext_desc->tso_flag[3] |= 1744 __cpu_to_le32(HTT_MSDU_CHECKSUM_ENABLE_64); 1745 } 1746 } 1747 1748 /* Prevent firmware from sending up tx inspection requests. There's 1749 * nothing ath10k can do with frames requested for inspection so force 1750 * it to simply rely a regular tx completion with discard status. 1751 */ 1752 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1753 1754 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1755 txbuf->cmd_tx.flags0 = flags0; 1756 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1757 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1758 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1759 1760 /* fill fragment descriptor */ 1761 txbuf->cmd_tx.frags_paddr = __cpu_to_le64(frags_paddr); 1762 if (ath10k_mac_tx_frm_has_freq(ar)) { 1763 txbuf->cmd_tx.offchan_tx.peerid = 1764 __cpu_to_le16(HTT_INVALID_PEERID); 1765 txbuf->cmd_tx.offchan_tx.freq = 1766 __cpu_to_le16(freq); 1767 } else { 1768 txbuf->cmd_tx.peerid = 1769 __cpu_to_le32(HTT_INVALID_PEERID); 1770 } 1771 1772 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1773 ath10k_dbg(ar, ATH10K_DBG_HTT, 1774 "htt tx flags0 %u flags1 %u len %d id %u frags_paddr %pad, msdu_paddr %pad vdev %u tid %u freq %u\n", 1775 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1776 &skb_cb->paddr, vdev_id, tid, freq); 1777 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1778 msdu->data, msdu->len); 1779 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1780 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1781 1782 sg_items[0].transfer_id = 0; 1783 sg_items[0].transfer_context = NULL; 1784 sg_items[0].vaddr = &txbuf->htc_hdr; 1785 sg_items[0].paddr = txbuf_paddr + 1786 sizeof(txbuf->frags); 1787 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1788 sizeof(txbuf->cmd_hdr) + 1789 sizeof(txbuf->cmd_tx); 1790 1791 sg_items[1].transfer_id = 0; 1792 sg_items[1].transfer_context = NULL; 1793 sg_items[1].vaddr = msdu->data; 1794 sg_items[1].paddr = skb_cb->paddr; 1795 sg_items[1].len = prefetch_len; 1796 1797 res = ath10k_hif_tx_sg(htt->ar, 1798 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1799 sg_items, ARRAY_SIZE(sg_items)); 1800 if (res) 1801 goto err_unmap_msdu; 1802 1803 return 0; 1804 1805 err_unmap_msdu: 1806 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1807 err_free_msdu_id: 1808 spin_lock_bh(&htt->tx_lock); 1809 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1810 spin_unlock_bh(&htt->tx_lock); 1811 err: 1812 return res; 1813 } 1814 1815 static const struct ath10k_htt_tx_ops htt_tx_ops_32 = { 1816 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_32, 1817 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1818 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_32, 1819 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_32, 1820 .htt_tx = ath10k_htt_tx_32, 1821 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_32, 1822 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_32, 1823 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32, 1824 }; 1825 1826 static const struct ath10k_htt_tx_ops htt_tx_ops_64 = { 1827 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_64, 1828 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_64, 1829 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_64, 1830 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_64, 1831 .htt_tx = ath10k_htt_tx_64, 1832 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_64, 1833 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_64, 1834 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_v2, 1835 }; 1836 1837 static const struct ath10k_htt_tx_ops htt_tx_ops_hl = { 1838 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_hl, 1839 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1840 .htt_tx = ath10k_htt_tx_hl, 1841 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32, 1842 .htt_flush_tx = ath10k_htt_flush_tx_queue, 1843 }; 1844 1845 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt) 1846 { 1847 struct ath10k *ar = htt->ar; 1848 1849 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 1850 htt->tx_ops = &htt_tx_ops_hl; 1851 else if (ar->hw_params.target_64bit) 1852 htt->tx_ops = &htt_tx_ops_64; 1853 else 1854 htt->tx_ops = &htt_tx_ops_32; 1855 } 1856