1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8 #include <linux/etherdevice.h> 9 #include "htt.h" 10 #include "mac.h" 11 #include "hif.h" 12 #include "txrx.h" 13 #include "debug.h" 14 15 static u8 ath10k_htt_tx_txq_calc_size(size_t count) 16 { 17 int exp; 18 int factor; 19 20 exp = 0; 21 factor = count >> 7; 22 23 while (factor >= 64 && exp < 4) { 24 factor >>= 3; 25 exp++; 26 } 27 28 if (exp == 4) 29 return 0xff; 30 31 if (count > 0) 32 factor = max(1, factor); 33 34 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | 35 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); 36 } 37 38 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 39 struct ieee80211_txq *txq) 40 { 41 struct ath10k *ar = hw->priv; 42 struct ath10k_sta *arsta; 43 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv; 44 unsigned long frame_cnt; 45 unsigned long byte_cnt; 46 int idx; 47 u32 bit; 48 u16 peer_id; 49 u8 tid; 50 u8 count; 51 52 lockdep_assert_held(&ar->htt.tx_lock); 53 54 if (!ar->htt.tx_q_state.enabled) 55 return; 56 57 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 58 return; 59 60 if (txq->sta) { 61 arsta = (void *)txq->sta->drv_priv; 62 peer_id = arsta->peer_id; 63 } else { 64 peer_id = arvif->peer_id; 65 } 66 67 tid = txq->tid; 68 bit = BIT(peer_id % 32); 69 idx = peer_id / 32; 70 71 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 72 count = ath10k_htt_tx_txq_calc_size(byte_cnt); 73 74 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || 75 unlikely(tid >= ar->htt.tx_q_state.num_tids)) { 76 ath10k_warn(ar, "refusing to update txq for peer_id %u tid %u due to out of bounds\n", 77 peer_id, tid); 78 return; 79 } 80 81 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count; 82 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit; 83 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0; 84 85 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %u tid %u count %u\n", 86 peer_id, tid, count); 87 } 88 89 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar) 90 { 91 u32 seq; 92 size_t size; 93 94 lockdep_assert_held(&ar->htt.tx_lock); 95 96 if (!ar->htt.tx_q_state.enabled) 97 return; 98 99 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 100 return; 101 102 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq); 103 seq++; 104 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq); 105 106 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n", 107 seq); 108 109 size = sizeof(*ar->htt.tx_q_state.vaddr); 110 dma_sync_single_for_device(ar->dev, 111 ar->htt.tx_q_state.paddr, 112 size, 113 DMA_TO_DEVICE); 114 } 115 116 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 117 struct ieee80211_txq *txq) 118 { 119 struct ath10k *ar = hw->priv; 120 121 spin_lock_bh(&ar->htt.tx_lock); 122 __ath10k_htt_tx_txq_recalc(hw, txq); 123 spin_unlock_bh(&ar->htt.tx_lock); 124 } 125 126 void ath10k_htt_tx_txq_sync(struct ath10k *ar) 127 { 128 spin_lock_bh(&ar->htt.tx_lock); 129 __ath10k_htt_tx_txq_sync(ar); 130 spin_unlock_bh(&ar->htt.tx_lock); 131 } 132 133 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 134 struct ieee80211_txq *txq) 135 { 136 struct ath10k *ar = hw->priv; 137 138 spin_lock_bh(&ar->htt.tx_lock); 139 __ath10k_htt_tx_txq_recalc(hw, txq); 140 __ath10k_htt_tx_txq_sync(ar); 141 spin_unlock_bh(&ar->htt.tx_lock); 142 } 143 144 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt) 145 { 146 lockdep_assert_held(&htt->tx_lock); 147 148 htt->num_pending_tx--; 149 if (htt->num_pending_tx == htt->max_num_pending_tx - 1) 150 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 151 152 if (htt->num_pending_tx == 0) 153 wake_up(&htt->empty_tx_wq); 154 } 155 156 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt) 157 { 158 lockdep_assert_held(&htt->tx_lock); 159 160 if (htt->num_pending_tx >= htt->max_num_pending_tx) 161 return -EBUSY; 162 163 htt->num_pending_tx++; 164 if (htt->num_pending_tx == htt->max_num_pending_tx) 165 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 166 167 return 0; 168 } 169 170 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 171 bool is_presp) 172 { 173 struct ath10k *ar = htt->ar; 174 175 lockdep_assert_held(&htt->tx_lock); 176 177 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres) 178 return 0; 179 180 if (is_presp && 181 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx) 182 return -EBUSY; 183 184 htt->num_pending_mgmt_tx++; 185 186 return 0; 187 } 188 189 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt) 190 { 191 lockdep_assert_held(&htt->tx_lock); 192 193 if (!htt->ar->hw_params.max_probe_resp_desc_thres) 194 return; 195 196 htt->num_pending_mgmt_tx--; 197 } 198 199 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb) 200 { 201 struct ath10k *ar = htt->ar; 202 int ret; 203 204 spin_lock_bh(&htt->tx_lock); 205 ret = idr_alloc(&htt->pending_tx, skb, 0, 206 htt->max_num_pending_tx, GFP_ATOMIC); 207 spin_unlock_bh(&htt->tx_lock); 208 209 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret); 210 211 return ret; 212 } 213 214 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id) 215 { 216 struct ath10k *ar = htt->ar; 217 218 lockdep_assert_held(&htt->tx_lock); 219 220 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %u\n", msdu_id); 221 222 idr_remove(&htt->pending_tx, msdu_id); 223 } 224 225 static void ath10k_htt_tx_free_cont_txbuf_32(struct ath10k_htt *htt) 226 { 227 struct ath10k *ar = htt->ar; 228 size_t size; 229 230 if (!htt->txbuf.vaddr_txbuff_32) 231 return; 232 233 size = htt->txbuf.size; 234 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_32, 235 htt->txbuf.paddr); 236 htt->txbuf.vaddr_txbuff_32 = NULL; 237 } 238 239 static int ath10k_htt_tx_alloc_cont_txbuf_32(struct ath10k_htt *htt) 240 { 241 struct ath10k *ar = htt->ar; 242 size_t size; 243 244 size = htt->max_num_pending_tx * 245 sizeof(struct ath10k_htt_txbuf_32); 246 247 htt->txbuf.vaddr_txbuff_32 = dma_alloc_coherent(ar->dev, size, 248 &htt->txbuf.paddr, 249 GFP_KERNEL); 250 if (!htt->txbuf.vaddr_txbuff_32) 251 return -ENOMEM; 252 253 htt->txbuf.size = size; 254 255 return 0; 256 } 257 258 static void ath10k_htt_tx_free_cont_txbuf_64(struct ath10k_htt *htt) 259 { 260 struct ath10k *ar = htt->ar; 261 size_t size; 262 263 if (!htt->txbuf.vaddr_txbuff_64) 264 return; 265 266 size = htt->txbuf.size; 267 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_64, 268 htt->txbuf.paddr); 269 htt->txbuf.vaddr_txbuff_64 = NULL; 270 } 271 272 static int ath10k_htt_tx_alloc_cont_txbuf_64(struct ath10k_htt *htt) 273 { 274 struct ath10k *ar = htt->ar; 275 size_t size; 276 277 size = htt->max_num_pending_tx * 278 sizeof(struct ath10k_htt_txbuf_64); 279 280 htt->txbuf.vaddr_txbuff_64 = dma_alloc_coherent(ar->dev, size, 281 &htt->txbuf.paddr, 282 GFP_KERNEL); 283 if (!htt->txbuf.vaddr_txbuff_64) 284 return -ENOMEM; 285 286 htt->txbuf.size = size; 287 288 return 0; 289 } 290 291 static void ath10k_htt_tx_free_cont_frag_desc_32(struct ath10k_htt *htt) 292 { 293 size_t size; 294 295 if (!htt->frag_desc.vaddr_desc_32) 296 return; 297 298 size = htt->max_num_pending_tx * 299 sizeof(struct htt_msdu_ext_desc); 300 301 dma_free_coherent(htt->ar->dev, 302 size, 303 htt->frag_desc.vaddr_desc_32, 304 htt->frag_desc.paddr); 305 306 htt->frag_desc.vaddr_desc_32 = NULL; 307 } 308 309 static int ath10k_htt_tx_alloc_cont_frag_desc_32(struct ath10k_htt *htt) 310 { 311 struct ath10k *ar = htt->ar; 312 size_t size; 313 314 if (!ar->hw_params.continuous_frag_desc) 315 return 0; 316 317 size = htt->max_num_pending_tx * 318 sizeof(struct htt_msdu_ext_desc); 319 htt->frag_desc.vaddr_desc_32 = dma_alloc_coherent(ar->dev, size, 320 &htt->frag_desc.paddr, 321 GFP_KERNEL); 322 if (!htt->frag_desc.vaddr_desc_32) { 323 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 324 return -ENOMEM; 325 } 326 htt->frag_desc.size = size; 327 328 return 0; 329 } 330 331 static void ath10k_htt_tx_free_cont_frag_desc_64(struct ath10k_htt *htt) 332 { 333 size_t size; 334 335 if (!htt->frag_desc.vaddr_desc_64) 336 return; 337 338 size = htt->max_num_pending_tx * 339 sizeof(struct htt_msdu_ext_desc_64); 340 341 dma_free_coherent(htt->ar->dev, 342 size, 343 htt->frag_desc.vaddr_desc_64, 344 htt->frag_desc.paddr); 345 346 htt->frag_desc.vaddr_desc_64 = NULL; 347 } 348 349 static int ath10k_htt_tx_alloc_cont_frag_desc_64(struct ath10k_htt *htt) 350 { 351 struct ath10k *ar = htt->ar; 352 size_t size; 353 354 if (!ar->hw_params.continuous_frag_desc) 355 return 0; 356 357 size = htt->max_num_pending_tx * 358 sizeof(struct htt_msdu_ext_desc_64); 359 360 htt->frag_desc.vaddr_desc_64 = dma_alloc_coherent(ar->dev, size, 361 &htt->frag_desc.paddr, 362 GFP_KERNEL); 363 if (!htt->frag_desc.vaddr_desc_64) { 364 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 365 return -ENOMEM; 366 } 367 htt->frag_desc.size = size; 368 369 return 0; 370 } 371 372 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt) 373 { 374 struct ath10k *ar = htt->ar; 375 size_t size; 376 377 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 378 ar->running_fw->fw_file.fw_features)) 379 return; 380 381 size = sizeof(*htt->tx_q_state.vaddr); 382 383 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE); 384 kfree(htt->tx_q_state.vaddr); 385 } 386 387 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt) 388 { 389 struct ath10k *ar = htt->ar; 390 size_t size; 391 int ret; 392 393 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 394 ar->running_fw->fw_file.fw_features)) 395 return 0; 396 397 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS; 398 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS; 399 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES; 400 401 size = sizeof(*htt->tx_q_state.vaddr); 402 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL); 403 if (!htt->tx_q_state.vaddr) 404 return -ENOMEM; 405 406 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr, 407 size, DMA_TO_DEVICE); 408 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr); 409 if (ret) { 410 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret); 411 kfree(htt->tx_q_state.vaddr); 412 return -EIO; 413 } 414 415 return 0; 416 } 417 418 static void ath10k_htt_tx_free_txdone_fifo(struct ath10k_htt *htt) 419 { 420 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo)); 421 kfifo_free(&htt->txdone_fifo); 422 } 423 424 static int ath10k_htt_tx_alloc_txdone_fifo(struct ath10k_htt *htt) 425 { 426 int ret; 427 size_t size; 428 429 size = roundup_pow_of_two(htt->max_num_pending_tx); 430 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL); 431 return ret; 432 } 433 434 static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt) 435 { 436 struct ath10k *ar = htt->ar; 437 int ret; 438 439 ret = ath10k_htt_alloc_txbuff(htt); 440 if (ret) { 441 ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret); 442 return ret; 443 } 444 445 ret = ath10k_htt_alloc_frag_desc(htt); 446 if (ret) { 447 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret); 448 goto free_txbuf; 449 } 450 451 ret = ath10k_htt_tx_alloc_txq(htt); 452 if (ret) { 453 ath10k_err(ar, "failed to alloc txq: %d\n", ret); 454 goto free_frag_desc; 455 } 456 457 ret = ath10k_htt_tx_alloc_txdone_fifo(htt); 458 if (ret) { 459 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret); 460 goto free_txq; 461 } 462 463 return 0; 464 465 free_txq: 466 ath10k_htt_tx_free_txq(htt); 467 468 free_frag_desc: 469 ath10k_htt_free_frag_desc(htt); 470 471 free_txbuf: 472 ath10k_htt_free_txbuff(htt); 473 474 return ret; 475 } 476 477 int ath10k_htt_tx_start(struct ath10k_htt *htt) 478 { 479 struct ath10k *ar = htt->ar; 480 int ret; 481 482 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n", 483 htt->max_num_pending_tx); 484 485 spin_lock_init(&htt->tx_lock); 486 idr_init(&htt->pending_tx); 487 488 if (htt->tx_mem_allocated) 489 return 0; 490 491 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 492 return 0; 493 494 ret = ath10k_htt_tx_alloc_buf(htt); 495 if (ret) 496 goto free_idr_pending_tx; 497 498 htt->tx_mem_allocated = true; 499 500 return 0; 501 502 free_idr_pending_tx: 503 idr_destroy(&htt->pending_tx); 504 505 return ret; 506 } 507 508 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx) 509 { 510 struct ath10k *ar = ctx; 511 struct ath10k_htt *htt = &ar->htt; 512 struct htt_tx_done tx_done = {0}; 513 514 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %u\n", msdu_id); 515 516 tx_done.msdu_id = msdu_id; 517 tx_done.status = HTT_TX_COMPL_STATE_DISCARD; 518 519 ath10k_txrx_tx_unref(htt, &tx_done); 520 521 return 0; 522 } 523 524 void ath10k_htt_tx_destroy(struct ath10k_htt *htt) 525 { 526 if (!htt->tx_mem_allocated) 527 return; 528 529 ath10k_htt_free_txbuff(htt); 530 ath10k_htt_tx_free_txq(htt); 531 ath10k_htt_free_frag_desc(htt); 532 ath10k_htt_tx_free_txdone_fifo(htt); 533 htt->tx_mem_allocated = false; 534 } 535 536 static void ath10k_htt_flush_tx_queue(struct ath10k_htt *htt) 537 { 538 ath10k_htc_stop_hl(htt->ar); 539 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar); 540 } 541 542 void ath10k_htt_tx_stop(struct ath10k_htt *htt) 543 { 544 ath10k_htt_flush_tx_queue(htt); 545 idr_destroy(&htt->pending_tx); 546 } 547 548 void ath10k_htt_tx_free(struct ath10k_htt *htt) 549 { 550 ath10k_htt_tx_stop(htt); 551 ath10k_htt_tx_destroy(htt); 552 } 553 554 void ath10k_htt_op_ep_tx_credits(struct ath10k *ar) 555 { 556 queue_work(ar->workqueue, &ar->bundle_tx_work); 557 } 558 559 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb) 560 { 561 struct ath10k_htt *htt = &ar->htt; 562 struct htt_tx_done tx_done = {0}; 563 struct htt_cmd_hdr *htt_hdr; 564 struct htt_data_tx_desc *desc_hdr = NULL; 565 u16 flags1 = 0; 566 u8 msg_type = 0; 567 568 if (htt->disable_tx_comp) { 569 htt_hdr = (struct htt_cmd_hdr *)skb->data; 570 msg_type = htt_hdr->msg_type; 571 572 if (msg_type == HTT_H2T_MSG_TYPE_TX_FRM) { 573 desc_hdr = (struct htt_data_tx_desc *) 574 (skb->data + sizeof(*htt_hdr)); 575 flags1 = __le16_to_cpu(desc_hdr->flags1); 576 skb_pull(skb, sizeof(struct htt_cmd_hdr)); 577 skb_pull(skb, sizeof(struct htt_data_tx_desc)); 578 } 579 } 580 581 dev_kfree_skb_any(skb); 582 583 if ((!htt->disable_tx_comp) || (msg_type != HTT_H2T_MSG_TYPE_TX_FRM)) 584 return; 585 586 ath10k_dbg(ar, ATH10K_DBG_HTT, 587 "htt tx complete msdu id:%u ,flags1:%x\n", 588 __le16_to_cpu(desc_hdr->id), flags1); 589 590 if (flags1 & HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE) 591 return; 592 593 tx_done.status = HTT_TX_COMPL_STATE_ACK; 594 tx_done.msdu_id = __le16_to_cpu(desc_hdr->id); 595 ath10k_txrx_tx_unref(&ar->htt, &tx_done); 596 } 597 598 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb) 599 { 600 dev_kfree_skb_any(skb); 601 } 602 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete); 603 604 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt) 605 { 606 struct ath10k *ar = htt->ar; 607 struct sk_buff *skb; 608 struct htt_cmd *cmd; 609 int len = 0; 610 int ret; 611 612 len += sizeof(cmd->hdr); 613 len += sizeof(cmd->ver_req); 614 615 skb = ath10k_htc_alloc_skb(ar, len); 616 if (!skb) 617 return -ENOMEM; 618 619 skb_put(skb, len); 620 cmd = (struct htt_cmd *)skb->data; 621 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ; 622 623 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 624 if (ret) { 625 dev_kfree_skb_any(skb); 626 return ret; 627 } 628 629 return 0; 630 } 631 632 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, 633 u64 cookie) 634 { 635 struct ath10k *ar = htt->ar; 636 struct htt_stats_req *req; 637 struct sk_buff *skb; 638 struct htt_cmd *cmd; 639 int len = 0, ret; 640 641 len += sizeof(cmd->hdr); 642 len += sizeof(cmd->stats_req); 643 644 skb = ath10k_htc_alloc_skb(ar, len); 645 if (!skb) 646 return -ENOMEM; 647 648 skb_put(skb, len); 649 cmd = (struct htt_cmd *)skb->data; 650 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ; 651 652 req = &cmd->stats_req; 653 654 memset(req, 0, sizeof(*req)); 655 656 /* currently we support only max 24 bit masks so no need to worry 657 * about endian support 658 */ 659 memcpy(req->upload_types, &mask, 3); 660 memcpy(req->reset_types, &reset_mask, 3); 661 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID; 662 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff); 663 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32); 664 665 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 666 if (ret) { 667 ath10k_warn(ar, "failed to send htt type stats request: %d", 668 ret); 669 dev_kfree_skb_any(skb); 670 return ret; 671 } 672 673 return 0; 674 } 675 676 static int ath10k_htt_send_frag_desc_bank_cfg_32(struct ath10k_htt *htt) 677 { 678 struct ath10k *ar = htt->ar; 679 struct sk_buff *skb; 680 struct htt_cmd *cmd; 681 struct htt_frag_desc_bank_cfg32 *cfg; 682 int ret, size; 683 u8 info; 684 685 if (!ar->hw_params.continuous_frag_desc) 686 return 0; 687 688 if (!htt->frag_desc.paddr) { 689 ath10k_warn(ar, "invalid frag desc memory\n"); 690 return -EINVAL; 691 } 692 693 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg32); 694 skb = ath10k_htc_alloc_skb(ar, size); 695 if (!skb) 696 return -ENOMEM; 697 698 skb_put(skb, size); 699 cmd = (struct htt_cmd *)skb->data; 700 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 701 702 info = 0; 703 info |= SM(htt->tx_q_state.type, 704 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 705 706 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 707 ar->running_fw->fw_file.fw_features)) 708 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 709 710 cfg = &cmd->frag_desc_bank_cfg32; 711 cfg->info = info; 712 cfg->num_banks = 1; 713 cfg->desc_size = sizeof(struct htt_msdu_ext_desc); 714 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr); 715 cfg->bank_id[0].bank_min_id = 0; 716 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 717 1); 718 719 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 720 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 721 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 722 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 723 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 724 725 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 726 727 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 728 if (ret) { 729 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 730 ret); 731 dev_kfree_skb_any(skb); 732 return ret; 733 } 734 735 return 0; 736 } 737 738 static int ath10k_htt_send_frag_desc_bank_cfg_64(struct ath10k_htt *htt) 739 { 740 struct ath10k *ar = htt->ar; 741 struct sk_buff *skb; 742 struct htt_cmd *cmd; 743 struct htt_frag_desc_bank_cfg64 *cfg; 744 int ret, size; 745 u8 info; 746 747 if (!ar->hw_params.continuous_frag_desc) 748 return 0; 749 750 if (!htt->frag_desc.paddr) { 751 ath10k_warn(ar, "invalid frag desc memory\n"); 752 return -EINVAL; 753 } 754 755 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg64); 756 skb = ath10k_htc_alloc_skb(ar, size); 757 if (!skb) 758 return -ENOMEM; 759 760 skb_put(skb, size); 761 cmd = (struct htt_cmd *)skb->data; 762 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 763 764 info = 0; 765 info |= SM(htt->tx_q_state.type, 766 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 767 768 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 769 ar->running_fw->fw_file.fw_features)) 770 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 771 772 cfg = &cmd->frag_desc_bank_cfg64; 773 cfg->info = info; 774 cfg->num_banks = 1; 775 cfg->desc_size = sizeof(struct htt_msdu_ext_desc_64); 776 cfg->bank_base_addrs[0] = __cpu_to_le64(htt->frag_desc.paddr); 777 cfg->bank_id[0].bank_min_id = 0; 778 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 779 1); 780 781 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 782 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 783 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 784 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 785 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 786 787 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 788 789 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 790 if (ret) { 791 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 792 ret); 793 dev_kfree_skb_any(skb); 794 return ret; 795 } 796 797 return 0; 798 } 799 800 static void ath10k_htt_fill_rx_desc_offset_32(struct ath10k_hw_params *hw, void *rx_ring) 801 { 802 struct htt_rx_ring_setup_ring32 *ring = 803 (struct htt_rx_ring_setup_ring32 *)rx_ring; 804 805 ath10k_htt_rx_desc_get_offsets(hw, &ring->offsets); 806 } 807 808 static void ath10k_htt_fill_rx_desc_offset_64(struct ath10k_hw_params *hw, void *rx_ring) 809 { 810 struct htt_rx_ring_setup_ring64 *ring = 811 (struct htt_rx_ring_setup_ring64 *)rx_ring; 812 813 ath10k_htt_rx_desc_get_offsets(hw, &ring->offsets); 814 } 815 816 static int ath10k_htt_send_rx_ring_cfg_32(struct ath10k_htt *htt) 817 { 818 struct ath10k *ar = htt->ar; 819 struct ath10k_hw_params *hw = &ar->hw_params; 820 struct sk_buff *skb; 821 struct htt_cmd *cmd; 822 struct htt_rx_ring_setup_ring32 *ring; 823 const int num_rx_ring = 1; 824 u16 flags; 825 u32 fw_idx; 826 int len; 827 int ret; 828 829 /* 830 * the HW expects the buffer to be an integral number of 4-byte 831 * "words" 832 */ 833 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 834 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 835 836 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 837 + (sizeof(*ring) * num_rx_ring); 838 skb = ath10k_htc_alloc_skb(ar, len); 839 if (!skb) 840 return -ENOMEM; 841 842 skb_put(skb, len); 843 844 cmd = (struct htt_cmd *)skb->data; 845 ring = &cmd->rx_setup_32.rings[0]; 846 847 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 848 cmd->rx_setup_32.hdr.num_rings = 1; 849 850 /* FIXME: do we need all of this? */ 851 flags = 0; 852 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 853 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 854 flags |= HTT_RX_RING_FLAGS_PPDU_START; 855 flags |= HTT_RX_RING_FLAGS_PPDU_END; 856 flags |= HTT_RX_RING_FLAGS_MPDU_START; 857 flags |= HTT_RX_RING_FLAGS_MPDU_END; 858 flags |= HTT_RX_RING_FLAGS_MSDU_START; 859 flags |= HTT_RX_RING_FLAGS_MSDU_END; 860 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 861 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 862 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 863 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 864 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 865 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 866 flags |= HTT_RX_RING_FLAGS_NULL_RX; 867 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 868 869 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 870 871 ring->fw_idx_shadow_reg_paddr = 872 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); 873 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); 874 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 875 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 876 ring->flags = __cpu_to_le16(flags); 877 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 878 879 ath10k_htt_fill_rx_desc_offset_32(hw, ring); 880 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 881 if (ret) { 882 dev_kfree_skb_any(skb); 883 return ret; 884 } 885 886 return 0; 887 } 888 889 static int ath10k_htt_send_rx_ring_cfg_64(struct ath10k_htt *htt) 890 { 891 struct ath10k *ar = htt->ar; 892 struct ath10k_hw_params *hw = &ar->hw_params; 893 struct sk_buff *skb; 894 struct htt_cmd *cmd; 895 struct htt_rx_ring_setup_ring64 *ring; 896 const int num_rx_ring = 1; 897 u16 flags; 898 u32 fw_idx; 899 int len; 900 int ret; 901 902 /* HW expects the buffer to be an integral number of 4-byte 903 * "words" 904 */ 905 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 906 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 907 908 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_64.hdr) 909 + (sizeof(*ring) * num_rx_ring); 910 skb = ath10k_htc_alloc_skb(ar, len); 911 if (!skb) 912 return -ENOMEM; 913 914 skb_put(skb, len); 915 916 cmd = (struct htt_cmd *)skb->data; 917 ring = &cmd->rx_setup_64.rings[0]; 918 919 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 920 cmd->rx_setup_64.hdr.num_rings = 1; 921 922 flags = 0; 923 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 924 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 925 flags |= HTT_RX_RING_FLAGS_PPDU_START; 926 flags |= HTT_RX_RING_FLAGS_PPDU_END; 927 flags |= HTT_RX_RING_FLAGS_MPDU_START; 928 flags |= HTT_RX_RING_FLAGS_MPDU_END; 929 flags |= HTT_RX_RING_FLAGS_MSDU_START; 930 flags |= HTT_RX_RING_FLAGS_MSDU_END; 931 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 932 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 933 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 934 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 935 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 936 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 937 flags |= HTT_RX_RING_FLAGS_NULL_RX; 938 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 939 940 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 941 942 ring->fw_idx_shadow_reg_paddr = __cpu_to_le64(htt->rx_ring.alloc_idx.paddr); 943 ring->rx_ring_base_paddr = __cpu_to_le64(htt->rx_ring.base_paddr); 944 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 945 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 946 ring->flags = __cpu_to_le16(flags); 947 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 948 949 ath10k_htt_fill_rx_desc_offset_64(hw, ring); 950 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 951 if (ret) { 952 dev_kfree_skb_any(skb); 953 return ret; 954 } 955 956 return 0; 957 } 958 959 static int ath10k_htt_send_rx_ring_cfg_hl(struct ath10k_htt *htt) 960 { 961 struct ath10k *ar = htt->ar; 962 struct sk_buff *skb; 963 struct htt_cmd *cmd; 964 struct htt_rx_ring_setup_ring32 *ring; 965 const int num_rx_ring = 1; 966 u16 flags; 967 int len; 968 int ret; 969 970 /* 971 * the HW expects the buffer to be an integral number of 4-byte 972 * "words" 973 */ 974 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 975 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 976 977 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 978 + (sizeof(*ring) * num_rx_ring); 979 skb = ath10k_htc_alloc_skb(ar, len); 980 if (!skb) 981 return -ENOMEM; 982 983 skb_put(skb, len); 984 985 cmd = (struct htt_cmd *)skb->data; 986 ring = &cmd->rx_setup_32.rings[0]; 987 988 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 989 cmd->rx_setup_32.hdr.num_rings = 1; 990 991 flags = 0; 992 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 993 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 994 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 995 996 memset(ring, 0, sizeof(*ring)); 997 ring->rx_ring_len = __cpu_to_le16(HTT_RX_RING_SIZE_MIN); 998 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 999 ring->flags = __cpu_to_le16(flags); 1000 1001 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1002 if (ret) { 1003 dev_kfree_skb_any(skb); 1004 return ret; 1005 } 1006 1007 return 0; 1008 } 1009 1010 static int ath10k_htt_h2t_aggr_cfg_msg_32(struct ath10k_htt *htt, 1011 u8 max_subfrms_ampdu, 1012 u8 max_subfrms_amsdu) 1013 { 1014 struct ath10k *ar = htt->ar; 1015 struct htt_aggr_conf *aggr_conf; 1016 struct sk_buff *skb; 1017 struct htt_cmd *cmd; 1018 int len; 1019 int ret; 1020 1021 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 1022 1023 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 1024 return -EINVAL; 1025 1026 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 1027 return -EINVAL; 1028 1029 len = sizeof(cmd->hdr); 1030 len += sizeof(cmd->aggr_conf); 1031 1032 skb = ath10k_htc_alloc_skb(ar, len); 1033 if (!skb) 1034 return -ENOMEM; 1035 1036 skb_put(skb, len); 1037 cmd = (struct htt_cmd *)skb->data; 1038 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1039 1040 aggr_conf = &cmd->aggr_conf; 1041 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1042 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1043 1044 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1045 aggr_conf->max_num_amsdu_subframes, 1046 aggr_conf->max_num_ampdu_subframes); 1047 1048 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1049 if (ret) { 1050 dev_kfree_skb_any(skb); 1051 return ret; 1052 } 1053 1054 return 0; 1055 } 1056 1057 static int ath10k_htt_h2t_aggr_cfg_msg_v2(struct ath10k_htt *htt, 1058 u8 max_subfrms_ampdu, 1059 u8 max_subfrms_amsdu) 1060 { 1061 struct ath10k *ar = htt->ar; 1062 struct htt_aggr_conf_v2 *aggr_conf; 1063 struct sk_buff *skb; 1064 struct htt_cmd *cmd; 1065 int len; 1066 int ret; 1067 1068 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 1069 1070 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 1071 return -EINVAL; 1072 1073 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 1074 return -EINVAL; 1075 1076 len = sizeof(cmd->hdr); 1077 len += sizeof(cmd->aggr_conf_v2); 1078 1079 skb = ath10k_htc_alloc_skb(ar, len); 1080 if (!skb) 1081 return -ENOMEM; 1082 1083 skb_put(skb, len); 1084 cmd = (struct htt_cmd *)skb->data; 1085 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1086 1087 aggr_conf = &cmd->aggr_conf_v2; 1088 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1089 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1090 1091 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1092 aggr_conf->max_num_amsdu_subframes, 1093 aggr_conf->max_num_ampdu_subframes); 1094 1095 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1096 if (ret) { 1097 dev_kfree_skb_any(skb); 1098 return ret; 1099 } 1100 1101 return 0; 1102 } 1103 1104 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 1105 __le32 token, 1106 __le16 fetch_seq_num, 1107 struct htt_tx_fetch_record *records, 1108 size_t num_records) 1109 { 1110 struct sk_buff *skb; 1111 struct htt_cmd *cmd; 1112 const u16 resp_id = 0; 1113 int len = 0; 1114 int ret; 1115 1116 /* Response IDs are echo-ed back only for host driver convenience 1117 * purposes. They aren't used for anything in the driver yet so use 0. 1118 */ 1119 1120 len += sizeof(cmd->hdr); 1121 len += sizeof(cmd->tx_fetch_resp); 1122 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records; 1123 1124 skb = ath10k_htc_alloc_skb(ar, len); 1125 if (!skb) 1126 return -ENOMEM; 1127 1128 skb_put(skb, len); 1129 cmd = (struct htt_cmd *)skb->data; 1130 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP; 1131 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id); 1132 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num; 1133 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records); 1134 cmd->tx_fetch_resp.token = token; 1135 1136 memcpy(cmd->tx_fetch_resp.records, records, 1137 sizeof(records[0]) * num_records); 1138 1139 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb); 1140 if (ret) { 1141 ath10k_warn(ar, "failed to submit htc command: %d\n", ret); 1142 goto err_free_skb; 1143 } 1144 1145 return 0; 1146 1147 err_free_skb: 1148 dev_kfree_skb_any(skb); 1149 1150 return ret; 1151 } 1152 1153 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb) 1154 { 1155 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1156 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1157 struct ath10k_vif *arvif; 1158 1159 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { 1160 return ar->scan.vdev_id; 1161 } else if (cb->vif) { 1162 arvif = (void *)cb->vif->drv_priv; 1163 return arvif->vdev_id; 1164 } else if (ar->monitor_started) { 1165 return ar->monitor_vdev_id; 1166 } else { 1167 return 0; 1168 } 1169 } 1170 1171 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth) 1172 { 1173 struct ieee80211_hdr *hdr = (void *)skb->data; 1174 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1175 1176 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control)) 1177 return HTT_DATA_TX_EXT_TID_MGMT; 1178 else if (cb->flags & ATH10K_SKB_F_QOS) 1179 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1180 else 1181 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; 1182 } 1183 1184 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) 1185 { 1186 struct ath10k *ar = htt->ar; 1187 struct device *dev = ar->dev; 1188 struct sk_buff *txdesc = NULL; 1189 struct htt_cmd *cmd; 1190 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1191 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1192 int len = 0; 1193 int msdu_id = -1; 1194 int res; 1195 const u8 *peer_addr; 1196 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1197 1198 len += sizeof(cmd->hdr); 1199 len += sizeof(cmd->mgmt_tx); 1200 1201 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1202 if (res < 0) 1203 goto err; 1204 1205 msdu_id = res; 1206 1207 if ((ieee80211_is_action(hdr->frame_control) || 1208 ieee80211_is_deauth(hdr->frame_control) || 1209 ieee80211_is_disassoc(hdr->frame_control)) && 1210 ieee80211_has_protected(hdr->frame_control)) { 1211 peer_addr = hdr->addr1; 1212 if (is_multicast_ether_addr(peer_addr)) { 1213 skb_put(msdu, sizeof(struct ieee80211_mmie_16)); 1214 } else { 1215 if (skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP || 1216 skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP_256) 1217 skb_put(msdu, IEEE80211_GCMP_MIC_LEN); 1218 else 1219 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1220 } 1221 } 1222 1223 txdesc = ath10k_htc_alloc_skb(ar, len); 1224 if (!txdesc) { 1225 res = -ENOMEM; 1226 goto err_free_msdu_id; 1227 } 1228 1229 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1230 DMA_TO_DEVICE); 1231 res = dma_mapping_error(dev, skb_cb->paddr); 1232 if (res) { 1233 res = -EIO; 1234 goto err_free_txdesc; 1235 } 1236 1237 skb_put(txdesc, len); 1238 cmd = (struct htt_cmd *)txdesc->data; 1239 memset(cmd, 0, len); 1240 1241 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX; 1242 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr); 1243 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len); 1244 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id); 1245 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id); 1246 memcpy(cmd->mgmt_tx.hdr, msdu->data, 1247 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN)); 1248 1249 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc); 1250 if (res) 1251 goto err_unmap_msdu; 1252 1253 return 0; 1254 1255 err_unmap_msdu: 1256 if (ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL) 1257 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1258 err_free_txdesc: 1259 dev_kfree_skb_any(txdesc); 1260 err_free_msdu_id: 1261 spin_lock_bh(&htt->tx_lock); 1262 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1263 spin_unlock_bh(&htt->tx_lock); 1264 err: 1265 return res; 1266 } 1267 1268 #define HTT_TX_HL_NEEDED_HEADROOM \ 1269 (unsigned int)(sizeof(struct htt_cmd_hdr) + \ 1270 sizeof(struct htt_data_tx_desc) + \ 1271 sizeof(struct ath10k_htc_hdr)) 1272 1273 static int ath10k_htt_tx_hl(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 1274 struct sk_buff *msdu) 1275 { 1276 struct ath10k *ar = htt->ar; 1277 int res, data_len; 1278 struct htt_cmd_hdr *cmd_hdr; 1279 struct htt_data_tx_desc *tx_desc; 1280 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1281 struct sk_buff *tmp_skb; 1282 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1283 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1284 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1285 u8 flags0 = 0; 1286 u16 flags1 = 0; 1287 u16 msdu_id = 0; 1288 1289 if (!is_eth) { 1290 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1291 1292 if ((ieee80211_is_action(hdr->frame_control) || 1293 ieee80211_is_deauth(hdr->frame_control) || 1294 ieee80211_is_disassoc(hdr->frame_control)) && 1295 ieee80211_has_protected(hdr->frame_control)) { 1296 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1297 } 1298 } 1299 1300 data_len = msdu->len; 1301 1302 switch (txmode) { 1303 case ATH10K_HW_TXRX_RAW: 1304 case ATH10K_HW_TXRX_NATIVE_WIFI: 1305 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1306 fallthrough; 1307 case ATH10K_HW_TXRX_ETHERNET: 1308 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1309 break; 1310 case ATH10K_HW_TXRX_MGMT: 1311 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1312 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1313 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1314 1315 if (htt->disable_tx_comp) 1316 flags1 |= HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE; 1317 break; 1318 } 1319 1320 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1321 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1322 1323 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1324 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1325 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1326 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1327 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1328 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1329 } 1330 1331 /* Prepend the HTT header and TX desc struct to the data message 1332 * and realloc the skb if it does not have enough headroom. 1333 */ 1334 if (skb_headroom(msdu) < HTT_TX_HL_NEEDED_HEADROOM) { 1335 tmp_skb = msdu; 1336 1337 ath10k_dbg(htt->ar, ATH10K_DBG_HTT, 1338 "Not enough headroom in skb. Current headroom: %u, needed: %u. Reallocating...\n", 1339 skb_headroom(msdu), HTT_TX_HL_NEEDED_HEADROOM); 1340 msdu = skb_realloc_headroom(msdu, HTT_TX_HL_NEEDED_HEADROOM); 1341 kfree_skb(tmp_skb); 1342 if (!msdu) { 1343 ath10k_warn(htt->ar, "htt hl tx: Unable to realloc skb!\n"); 1344 res = -ENOMEM; 1345 goto out; 1346 } 1347 } 1348 1349 if (ar->bus_param.hl_msdu_ids) { 1350 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1351 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1352 if (res < 0) { 1353 ath10k_err(ar, "msdu_id allocation failed %d\n", res); 1354 goto out; 1355 } 1356 msdu_id = res; 1357 } 1358 1359 /* As msdu is freed by mac80211 (in ieee80211_tx_status()) and by 1360 * ath10k (in ath10k_htt_htc_tx_complete()) we have to increase 1361 * reference by one to avoid a use-after-free case and a double 1362 * free. 1363 */ 1364 skb_get(msdu); 1365 1366 skb_push(msdu, sizeof(*cmd_hdr)); 1367 skb_push(msdu, sizeof(*tx_desc)); 1368 cmd_hdr = (struct htt_cmd_hdr *)msdu->data; 1369 tx_desc = (struct htt_data_tx_desc *)(msdu->data + sizeof(*cmd_hdr)); 1370 1371 cmd_hdr->msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1372 tx_desc->flags0 = flags0; 1373 tx_desc->flags1 = __cpu_to_le16(flags1); 1374 tx_desc->len = __cpu_to_le16(data_len); 1375 tx_desc->id = __cpu_to_le16(msdu_id); 1376 tx_desc->frags_paddr = 0; /* always zero */ 1377 /* Initialize peer_id to INVALID_PEER because this is NOT 1378 * Reinjection path 1379 */ 1380 tx_desc->peerid = __cpu_to_le32(HTT_INVALID_PEERID); 1381 1382 res = ath10k_htc_send_hl(&htt->ar->htc, htt->eid, msdu); 1383 1384 out: 1385 return res; 1386 } 1387 1388 static int ath10k_htt_tx_32(struct ath10k_htt *htt, 1389 enum ath10k_hw_txrx_mode txmode, 1390 struct sk_buff *msdu) 1391 { 1392 struct ath10k *ar = htt->ar; 1393 struct device *dev = ar->dev; 1394 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1395 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1396 struct ath10k_hif_sg_item sg_items[2]; 1397 struct ath10k_htt_txbuf_32 *txbuf; 1398 struct htt_data_tx_desc_frag *frags; 1399 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1400 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1401 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1402 int prefetch_len; 1403 int res; 1404 u8 flags0 = 0; 1405 u16 msdu_id, flags1 = 0; 1406 u16 freq = 0; 1407 u32 frags_paddr = 0; 1408 u32 txbuf_paddr; 1409 struct htt_msdu_ext_desc *ext_desc = NULL; 1410 struct htt_msdu_ext_desc *ext_desc_t = NULL; 1411 1412 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1413 if (res < 0) 1414 goto err; 1415 1416 msdu_id = res; 1417 1418 prefetch_len = min(htt->prefetch_len, msdu->len); 1419 prefetch_len = roundup(prefetch_len, 4); 1420 1421 txbuf = htt->txbuf.vaddr_txbuff_32 + msdu_id; 1422 txbuf_paddr = htt->txbuf.paddr + 1423 (sizeof(struct ath10k_htt_txbuf_32) * msdu_id); 1424 1425 if (!is_eth) { 1426 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1427 1428 if ((ieee80211_is_action(hdr->frame_control) || 1429 ieee80211_is_deauth(hdr->frame_control) || 1430 ieee80211_is_disassoc(hdr->frame_control)) && 1431 ieee80211_has_protected(hdr->frame_control)) { 1432 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1433 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1434 txmode == ATH10K_HW_TXRX_RAW && 1435 ieee80211_has_protected(hdr->frame_control)) { 1436 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1437 } 1438 } 1439 1440 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1441 DMA_TO_DEVICE); 1442 res = dma_mapping_error(dev, skb_cb->paddr); 1443 if (res) { 1444 res = -EIO; 1445 goto err_free_msdu_id; 1446 } 1447 1448 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1449 freq = ar->scan.roc_freq; 1450 1451 switch (txmode) { 1452 case ATH10K_HW_TXRX_RAW: 1453 case ATH10K_HW_TXRX_NATIVE_WIFI: 1454 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1455 fallthrough; 1456 case ATH10K_HW_TXRX_ETHERNET: 1457 if (ar->hw_params.continuous_frag_desc) { 1458 ext_desc_t = htt->frag_desc.vaddr_desc_32; 1459 memset(&ext_desc_t[msdu_id], 0, 1460 sizeof(struct htt_msdu_ext_desc)); 1461 frags = (struct htt_data_tx_desc_frag *) 1462 &ext_desc_t[msdu_id].frags; 1463 ext_desc = &ext_desc_t[msdu_id]; 1464 frags[0].tword_addr.paddr_lo = 1465 __cpu_to_le32(skb_cb->paddr); 1466 frags[0].tword_addr.paddr_hi = 0; 1467 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1468 1469 frags_paddr = htt->frag_desc.paddr + 1470 (sizeof(struct htt_msdu_ext_desc) * msdu_id); 1471 } else { 1472 frags = txbuf->frags; 1473 frags[0].dword_addr.paddr = 1474 __cpu_to_le32(skb_cb->paddr); 1475 frags[0].dword_addr.len = __cpu_to_le32(msdu->len); 1476 frags[1].dword_addr.paddr = 0; 1477 frags[1].dword_addr.len = 0; 1478 1479 frags_paddr = txbuf_paddr; 1480 } 1481 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1482 break; 1483 case ATH10K_HW_TXRX_MGMT: 1484 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1485 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1486 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1487 1488 frags_paddr = skb_cb->paddr; 1489 break; 1490 } 1491 1492 /* Normally all commands go through HTC which manages tx credits for 1493 * each endpoint and notifies when tx is completed. 1494 * 1495 * HTT endpoint is creditless so there's no need to care about HTC 1496 * flags. In that case it is trivial to fill the HTC header here. 1497 * 1498 * MSDU transmission is considered completed upon HTT event. This 1499 * implies no relevant resources can be freed until after the event is 1500 * received. That's why HTC tx completion handler itself is ignored by 1501 * setting NULL to transfer_context for all sg items. 1502 * 1503 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1504 * as it's a waste of resources. By bypassing HTC it is possible to 1505 * avoid extra memory allocations, compress data structures and thus 1506 * improve performance. 1507 */ 1508 1509 txbuf->htc_hdr.eid = htt->eid; 1510 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1511 sizeof(txbuf->cmd_tx) + 1512 prefetch_len); 1513 txbuf->htc_hdr.flags = 0; 1514 1515 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1516 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1517 1518 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1519 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1520 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1521 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1522 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1523 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1524 if (ar->hw_params.continuous_frag_desc) 1525 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE; 1526 } 1527 1528 /* Prevent firmware from sending up tx inspection requests. There's 1529 * nothing ath10k can do with frames requested for inspection so force 1530 * it to simply rely a regular tx completion with discard status. 1531 */ 1532 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1533 1534 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1535 txbuf->cmd_tx.flags0 = flags0; 1536 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1537 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1538 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1539 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr); 1540 if (ath10k_mac_tx_frm_has_freq(ar)) { 1541 txbuf->cmd_tx.offchan_tx.peerid = 1542 __cpu_to_le16(HTT_INVALID_PEERID); 1543 txbuf->cmd_tx.offchan_tx.freq = 1544 __cpu_to_le16(freq); 1545 } else { 1546 txbuf->cmd_tx.peerid = 1547 __cpu_to_le32(HTT_INVALID_PEERID); 1548 } 1549 1550 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1551 ath10k_dbg(ar, ATH10K_DBG_HTT, 1552 "htt tx flags0 %u flags1 %u len %d id %u frags_paddr %pad, msdu_paddr %pad vdev %u tid %u freq %u\n", 1553 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1554 &skb_cb->paddr, vdev_id, tid, freq); 1555 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1556 msdu->data, msdu->len); 1557 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1558 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1559 1560 sg_items[0].transfer_id = 0; 1561 sg_items[0].transfer_context = NULL; 1562 sg_items[0].vaddr = &txbuf->htc_hdr; 1563 sg_items[0].paddr = txbuf_paddr + 1564 sizeof(txbuf->frags); 1565 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1566 sizeof(txbuf->cmd_hdr) + 1567 sizeof(txbuf->cmd_tx); 1568 1569 sg_items[1].transfer_id = 0; 1570 sg_items[1].transfer_context = NULL; 1571 sg_items[1].vaddr = msdu->data; 1572 sg_items[1].paddr = skb_cb->paddr; 1573 sg_items[1].len = prefetch_len; 1574 1575 res = ath10k_hif_tx_sg(htt->ar, 1576 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1577 sg_items, ARRAY_SIZE(sg_items)); 1578 if (res) 1579 goto err_unmap_msdu; 1580 1581 return 0; 1582 1583 err_unmap_msdu: 1584 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1585 err_free_msdu_id: 1586 spin_lock_bh(&htt->tx_lock); 1587 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1588 spin_unlock_bh(&htt->tx_lock); 1589 err: 1590 return res; 1591 } 1592 1593 static int ath10k_htt_tx_64(struct ath10k_htt *htt, 1594 enum ath10k_hw_txrx_mode txmode, 1595 struct sk_buff *msdu) 1596 { 1597 struct ath10k *ar = htt->ar; 1598 struct device *dev = ar->dev; 1599 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1600 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1601 struct ath10k_hif_sg_item sg_items[2]; 1602 struct ath10k_htt_txbuf_64 *txbuf; 1603 struct htt_data_tx_desc_frag *frags; 1604 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1605 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1606 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1607 int prefetch_len; 1608 int res; 1609 u8 flags0 = 0; 1610 u16 msdu_id, flags1 = 0; 1611 u16 freq = 0; 1612 dma_addr_t frags_paddr = 0; 1613 dma_addr_t txbuf_paddr; 1614 struct htt_msdu_ext_desc_64 *ext_desc = NULL; 1615 struct htt_msdu_ext_desc_64 *ext_desc_t = NULL; 1616 1617 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1618 if (res < 0) 1619 goto err; 1620 1621 msdu_id = res; 1622 1623 prefetch_len = min(htt->prefetch_len, msdu->len); 1624 prefetch_len = roundup(prefetch_len, 4); 1625 1626 txbuf = htt->txbuf.vaddr_txbuff_64 + msdu_id; 1627 txbuf_paddr = htt->txbuf.paddr + 1628 (sizeof(struct ath10k_htt_txbuf_64) * msdu_id); 1629 1630 if (!is_eth) { 1631 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1632 1633 if ((ieee80211_is_action(hdr->frame_control) || 1634 ieee80211_is_deauth(hdr->frame_control) || 1635 ieee80211_is_disassoc(hdr->frame_control)) && 1636 ieee80211_has_protected(hdr->frame_control)) { 1637 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1638 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1639 txmode == ATH10K_HW_TXRX_RAW && 1640 ieee80211_has_protected(hdr->frame_control)) { 1641 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1642 } 1643 } 1644 1645 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1646 DMA_TO_DEVICE); 1647 res = dma_mapping_error(dev, skb_cb->paddr); 1648 if (res) { 1649 res = -EIO; 1650 goto err_free_msdu_id; 1651 } 1652 1653 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1654 freq = ar->scan.roc_freq; 1655 1656 switch (txmode) { 1657 case ATH10K_HW_TXRX_RAW: 1658 case ATH10K_HW_TXRX_NATIVE_WIFI: 1659 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1660 fallthrough; 1661 case ATH10K_HW_TXRX_ETHERNET: 1662 if (ar->hw_params.continuous_frag_desc) { 1663 ext_desc_t = htt->frag_desc.vaddr_desc_64; 1664 memset(&ext_desc_t[msdu_id], 0, 1665 sizeof(struct htt_msdu_ext_desc_64)); 1666 frags = (struct htt_data_tx_desc_frag *) 1667 &ext_desc_t[msdu_id].frags; 1668 ext_desc = &ext_desc_t[msdu_id]; 1669 frags[0].tword_addr.paddr_lo = 1670 __cpu_to_le32(skb_cb->paddr); 1671 frags[0].tword_addr.paddr_hi = 1672 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1673 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1674 1675 frags_paddr = htt->frag_desc.paddr + 1676 (sizeof(struct htt_msdu_ext_desc_64) * msdu_id); 1677 } else { 1678 frags = txbuf->frags; 1679 frags[0].tword_addr.paddr_lo = 1680 __cpu_to_le32(skb_cb->paddr); 1681 frags[0].tword_addr.paddr_hi = 1682 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1683 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1684 frags[1].tword_addr.paddr_lo = 0; 1685 frags[1].tword_addr.paddr_hi = 0; 1686 frags[1].tword_addr.len_16 = 0; 1687 } 1688 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1689 break; 1690 case ATH10K_HW_TXRX_MGMT: 1691 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1692 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1693 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1694 1695 frags_paddr = skb_cb->paddr; 1696 break; 1697 } 1698 1699 /* Normally all commands go through HTC which manages tx credits for 1700 * each endpoint and notifies when tx is completed. 1701 * 1702 * HTT endpoint is creditless so there's no need to care about HTC 1703 * flags. In that case it is trivial to fill the HTC header here. 1704 * 1705 * MSDU transmission is considered completed upon HTT event. This 1706 * implies no relevant resources can be freed until after the event is 1707 * received. That's why HTC tx completion handler itself is ignored by 1708 * setting NULL to transfer_context for all sg items. 1709 * 1710 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1711 * as it's a waste of resources. By bypassing HTC it is possible to 1712 * avoid extra memory allocations, compress data structures and thus 1713 * improve performance. 1714 */ 1715 1716 txbuf->htc_hdr.eid = htt->eid; 1717 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1718 sizeof(txbuf->cmd_tx) + 1719 prefetch_len); 1720 txbuf->htc_hdr.flags = 0; 1721 1722 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1723 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1724 1725 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1726 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1727 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1728 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1729 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1730 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1731 if (ar->hw_params.continuous_frag_desc) { 1732 memset(ext_desc->tso_flag, 0, sizeof(ext_desc->tso_flag)); 1733 ext_desc->tso_flag[3] |= 1734 __cpu_to_le32(HTT_MSDU_CHECKSUM_ENABLE_64); 1735 } 1736 } 1737 1738 /* Prevent firmware from sending up tx inspection requests. There's 1739 * nothing ath10k can do with frames requested for inspection so force 1740 * it to simply rely a regular tx completion with discard status. 1741 */ 1742 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1743 1744 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1745 txbuf->cmd_tx.flags0 = flags0; 1746 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1747 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1748 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1749 1750 /* fill fragment descriptor */ 1751 txbuf->cmd_tx.frags_paddr = __cpu_to_le64(frags_paddr); 1752 if (ath10k_mac_tx_frm_has_freq(ar)) { 1753 txbuf->cmd_tx.offchan_tx.peerid = 1754 __cpu_to_le16(HTT_INVALID_PEERID); 1755 txbuf->cmd_tx.offchan_tx.freq = 1756 __cpu_to_le16(freq); 1757 } else { 1758 txbuf->cmd_tx.peerid = 1759 __cpu_to_le32(HTT_INVALID_PEERID); 1760 } 1761 1762 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1763 ath10k_dbg(ar, ATH10K_DBG_HTT, 1764 "htt tx flags0 %u flags1 %u len %d id %u frags_paddr %pad, msdu_paddr %pad vdev %u tid %u freq %u\n", 1765 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1766 &skb_cb->paddr, vdev_id, tid, freq); 1767 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1768 msdu->data, msdu->len); 1769 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1770 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1771 1772 sg_items[0].transfer_id = 0; 1773 sg_items[0].transfer_context = NULL; 1774 sg_items[0].vaddr = &txbuf->htc_hdr; 1775 sg_items[0].paddr = txbuf_paddr + 1776 sizeof(txbuf->frags); 1777 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1778 sizeof(txbuf->cmd_hdr) + 1779 sizeof(txbuf->cmd_tx); 1780 1781 sg_items[1].transfer_id = 0; 1782 sg_items[1].transfer_context = NULL; 1783 sg_items[1].vaddr = msdu->data; 1784 sg_items[1].paddr = skb_cb->paddr; 1785 sg_items[1].len = prefetch_len; 1786 1787 res = ath10k_hif_tx_sg(htt->ar, 1788 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1789 sg_items, ARRAY_SIZE(sg_items)); 1790 if (res) 1791 goto err_unmap_msdu; 1792 1793 return 0; 1794 1795 err_unmap_msdu: 1796 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1797 err_free_msdu_id: 1798 spin_lock_bh(&htt->tx_lock); 1799 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1800 spin_unlock_bh(&htt->tx_lock); 1801 err: 1802 return res; 1803 } 1804 1805 static const struct ath10k_htt_tx_ops htt_tx_ops_32 = { 1806 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_32, 1807 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1808 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_32, 1809 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_32, 1810 .htt_tx = ath10k_htt_tx_32, 1811 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_32, 1812 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_32, 1813 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32, 1814 }; 1815 1816 static const struct ath10k_htt_tx_ops htt_tx_ops_64 = { 1817 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_64, 1818 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_64, 1819 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_64, 1820 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_64, 1821 .htt_tx = ath10k_htt_tx_64, 1822 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_64, 1823 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_64, 1824 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_v2, 1825 }; 1826 1827 static const struct ath10k_htt_tx_ops htt_tx_ops_hl = { 1828 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_hl, 1829 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1830 .htt_tx = ath10k_htt_tx_hl, 1831 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32, 1832 .htt_flush_tx = ath10k_htt_flush_tx_queue, 1833 }; 1834 1835 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt) 1836 { 1837 struct ath10k *ar = htt->ar; 1838 1839 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 1840 htt->tx_ops = &htt_tx_ops_hl; 1841 else if (ar->hw_params.target_64bit) 1842 htt->tx_ops = &htt_tx_ops_64; 1843 else 1844 htt->tx_ops = &htt_tx_ops_32; 1845 } 1846