1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/etherdevice.h> 19 #include "htt.h" 20 #include "mac.h" 21 #include "hif.h" 22 #include "txrx.h" 23 #include "debug.h" 24 25 static u8 ath10k_htt_tx_txq_calc_size(size_t count) 26 { 27 int exp; 28 int factor; 29 30 exp = 0; 31 factor = count >> 7; 32 33 while (factor >= 64 && exp < 4) { 34 factor >>= 3; 35 exp++; 36 } 37 38 if (exp == 4) 39 return 0xff; 40 41 if (count > 0) 42 factor = max(1, factor); 43 44 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | 45 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); 46 } 47 48 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 49 struct ieee80211_txq *txq) 50 { 51 struct ath10k *ar = hw->priv; 52 struct ath10k_sta *arsta; 53 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv; 54 unsigned long frame_cnt; 55 unsigned long byte_cnt; 56 int idx; 57 u32 bit; 58 u16 peer_id; 59 u8 tid; 60 u8 count; 61 62 lockdep_assert_held(&ar->htt.tx_lock); 63 64 if (!ar->htt.tx_q_state.enabled) 65 return; 66 67 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 68 return; 69 70 if (txq->sta) { 71 arsta = (void *)txq->sta->drv_priv; 72 peer_id = arsta->peer_id; 73 } else { 74 peer_id = arvif->peer_id; 75 } 76 77 tid = txq->tid; 78 bit = BIT(peer_id % 32); 79 idx = peer_id / 32; 80 81 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 82 count = ath10k_htt_tx_txq_calc_size(byte_cnt); 83 84 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || 85 unlikely(tid >= ar->htt.tx_q_state.num_tids)) { 86 ath10k_warn(ar, "refusing to update txq for peer_id %hu tid %hhu due to out of bounds\n", 87 peer_id, tid); 88 return; 89 } 90 91 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count; 92 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit; 93 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0; 94 95 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %hu tid %hhu count %hhu\n", 96 peer_id, tid, count); 97 } 98 99 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar) 100 { 101 u32 seq; 102 size_t size; 103 104 lockdep_assert_held(&ar->htt.tx_lock); 105 106 if (!ar->htt.tx_q_state.enabled) 107 return; 108 109 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 110 return; 111 112 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq); 113 seq++; 114 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq); 115 116 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n", 117 seq); 118 119 size = sizeof(*ar->htt.tx_q_state.vaddr); 120 dma_sync_single_for_device(ar->dev, 121 ar->htt.tx_q_state.paddr, 122 size, 123 DMA_TO_DEVICE); 124 } 125 126 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 127 struct ieee80211_txq *txq) 128 { 129 struct ath10k *ar = hw->priv; 130 131 spin_lock_bh(&ar->htt.tx_lock); 132 __ath10k_htt_tx_txq_recalc(hw, txq); 133 spin_unlock_bh(&ar->htt.tx_lock); 134 } 135 136 void ath10k_htt_tx_txq_sync(struct ath10k *ar) 137 { 138 spin_lock_bh(&ar->htt.tx_lock); 139 __ath10k_htt_tx_txq_sync(ar); 140 spin_unlock_bh(&ar->htt.tx_lock); 141 } 142 143 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 144 struct ieee80211_txq *txq) 145 { 146 struct ath10k *ar = hw->priv; 147 148 spin_lock_bh(&ar->htt.tx_lock); 149 __ath10k_htt_tx_txq_recalc(hw, txq); 150 __ath10k_htt_tx_txq_sync(ar); 151 spin_unlock_bh(&ar->htt.tx_lock); 152 } 153 154 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt) 155 { 156 lockdep_assert_held(&htt->tx_lock); 157 158 htt->num_pending_tx--; 159 if (htt->num_pending_tx == htt->max_num_pending_tx - 1) 160 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 161 } 162 163 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt) 164 { 165 lockdep_assert_held(&htt->tx_lock); 166 167 if (htt->num_pending_tx >= htt->max_num_pending_tx) 168 return -EBUSY; 169 170 htt->num_pending_tx++; 171 if (htt->num_pending_tx == htt->max_num_pending_tx) 172 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 173 174 return 0; 175 } 176 177 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 178 bool is_presp) 179 { 180 struct ath10k *ar = htt->ar; 181 182 lockdep_assert_held(&htt->tx_lock); 183 184 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres) 185 return 0; 186 187 if (is_presp && 188 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx) 189 return -EBUSY; 190 191 htt->num_pending_mgmt_tx++; 192 193 return 0; 194 } 195 196 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt) 197 { 198 lockdep_assert_held(&htt->tx_lock); 199 200 if (!htt->ar->hw_params.max_probe_resp_desc_thres) 201 return; 202 203 htt->num_pending_mgmt_tx--; 204 } 205 206 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb) 207 { 208 struct ath10k *ar = htt->ar; 209 int ret; 210 211 lockdep_assert_held(&htt->tx_lock); 212 213 ret = idr_alloc(&htt->pending_tx, skb, 0, 214 htt->max_num_pending_tx, GFP_ATOMIC); 215 216 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret); 217 218 return ret; 219 } 220 221 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id) 222 { 223 struct ath10k *ar = htt->ar; 224 225 lockdep_assert_held(&htt->tx_lock); 226 227 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id); 228 229 idr_remove(&htt->pending_tx, msdu_id); 230 } 231 232 static void ath10k_htt_tx_free_cont_frag_desc(struct ath10k_htt *htt) 233 { 234 size_t size; 235 236 if (!htt->frag_desc.vaddr) 237 return; 238 239 size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc); 240 241 dma_free_coherent(htt->ar->dev, 242 size, 243 htt->frag_desc.vaddr, 244 htt->frag_desc.paddr); 245 } 246 247 static int ath10k_htt_tx_alloc_cont_frag_desc(struct ath10k_htt *htt) 248 { 249 struct ath10k *ar = htt->ar; 250 size_t size; 251 252 if (!ar->hw_params.continuous_frag_desc) 253 return 0; 254 255 size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc); 256 htt->frag_desc.vaddr = dma_alloc_coherent(ar->dev, size, 257 &htt->frag_desc.paddr, 258 GFP_KERNEL); 259 if (!htt->frag_desc.vaddr) { 260 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 261 return -ENOMEM; 262 } 263 264 return 0; 265 } 266 267 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt) 268 { 269 struct ath10k *ar = htt->ar; 270 size_t size; 271 272 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 273 ar->running_fw->fw_file.fw_features)) 274 return; 275 276 size = sizeof(*htt->tx_q_state.vaddr); 277 278 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE); 279 kfree(htt->tx_q_state.vaddr); 280 } 281 282 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt) 283 { 284 struct ath10k *ar = htt->ar; 285 size_t size; 286 int ret; 287 288 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 289 ar->running_fw->fw_file.fw_features)) 290 return 0; 291 292 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS; 293 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS; 294 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES; 295 296 size = sizeof(*htt->tx_q_state.vaddr); 297 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL); 298 if (!htt->tx_q_state.vaddr) 299 return -ENOMEM; 300 301 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr, 302 size, DMA_TO_DEVICE); 303 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr); 304 if (ret) { 305 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret); 306 kfree(htt->tx_q_state.vaddr); 307 return -EIO; 308 } 309 310 return 0; 311 } 312 313 int ath10k_htt_tx_alloc(struct ath10k_htt *htt) 314 { 315 struct ath10k *ar = htt->ar; 316 int ret, size; 317 318 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n", 319 htt->max_num_pending_tx); 320 321 spin_lock_init(&htt->tx_lock); 322 idr_init(&htt->pending_tx); 323 324 size = htt->max_num_pending_tx * sizeof(struct ath10k_htt_txbuf); 325 htt->txbuf.vaddr = dma_alloc_coherent(ar->dev, size, 326 &htt->txbuf.paddr, 327 GFP_KERNEL); 328 if (!htt->txbuf.vaddr) { 329 ath10k_err(ar, "failed to alloc tx buffer\n"); 330 ret = -ENOMEM; 331 goto free_idr_pending_tx; 332 } 333 334 ret = ath10k_htt_tx_alloc_cont_frag_desc(htt); 335 if (ret) { 336 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret); 337 goto free_txbuf; 338 } 339 340 ret = ath10k_htt_tx_alloc_txq(htt); 341 if (ret) { 342 ath10k_err(ar, "failed to alloc txq: %d\n", ret); 343 goto free_frag_desc; 344 } 345 346 size = roundup_pow_of_two(htt->max_num_pending_tx); 347 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL); 348 if (ret) { 349 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret); 350 goto free_txq; 351 } 352 353 return 0; 354 355 free_txq: 356 ath10k_htt_tx_free_txq(htt); 357 358 free_frag_desc: 359 ath10k_htt_tx_free_cont_frag_desc(htt); 360 361 free_txbuf: 362 size = htt->max_num_pending_tx * 363 sizeof(struct ath10k_htt_txbuf); 364 dma_free_coherent(htt->ar->dev, size, htt->txbuf.vaddr, 365 htt->txbuf.paddr); 366 367 free_idr_pending_tx: 368 idr_destroy(&htt->pending_tx); 369 370 return ret; 371 } 372 373 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx) 374 { 375 struct ath10k *ar = ctx; 376 struct ath10k_htt *htt = &ar->htt; 377 struct htt_tx_done tx_done = {0}; 378 379 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id); 380 381 tx_done.msdu_id = msdu_id; 382 tx_done.status = HTT_TX_COMPL_STATE_DISCARD; 383 384 ath10k_txrx_tx_unref(htt, &tx_done); 385 386 return 0; 387 } 388 389 void ath10k_htt_tx_free(struct ath10k_htt *htt) 390 { 391 int size; 392 393 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar); 394 idr_destroy(&htt->pending_tx); 395 396 if (htt->txbuf.vaddr) { 397 size = htt->max_num_pending_tx * 398 sizeof(struct ath10k_htt_txbuf); 399 dma_free_coherent(htt->ar->dev, size, htt->txbuf.vaddr, 400 htt->txbuf.paddr); 401 } 402 403 ath10k_htt_tx_free_txq(htt); 404 ath10k_htt_tx_free_cont_frag_desc(htt); 405 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo)); 406 kfifo_free(&htt->txdone_fifo); 407 } 408 409 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb) 410 { 411 dev_kfree_skb_any(skb); 412 } 413 414 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb) 415 { 416 dev_kfree_skb_any(skb); 417 } 418 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete); 419 420 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt) 421 { 422 struct ath10k *ar = htt->ar; 423 struct sk_buff *skb; 424 struct htt_cmd *cmd; 425 int len = 0; 426 int ret; 427 428 len += sizeof(cmd->hdr); 429 len += sizeof(cmd->ver_req); 430 431 skb = ath10k_htc_alloc_skb(ar, len); 432 if (!skb) 433 return -ENOMEM; 434 435 skb_put(skb, len); 436 cmd = (struct htt_cmd *)skb->data; 437 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ; 438 439 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 440 if (ret) { 441 dev_kfree_skb_any(skb); 442 return ret; 443 } 444 445 return 0; 446 } 447 448 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie) 449 { 450 struct ath10k *ar = htt->ar; 451 struct htt_stats_req *req; 452 struct sk_buff *skb; 453 struct htt_cmd *cmd; 454 int len = 0, ret; 455 456 len += sizeof(cmd->hdr); 457 len += sizeof(cmd->stats_req); 458 459 skb = ath10k_htc_alloc_skb(ar, len); 460 if (!skb) 461 return -ENOMEM; 462 463 skb_put(skb, len); 464 cmd = (struct htt_cmd *)skb->data; 465 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ; 466 467 req = &cmd->stats_req; 468 469 memset(req, 0, sizeof(*req)); 470 471 /* currently we support only max 8 bit masks so no need to worry 472 * about endian support */ 473 req->upload_types[0] = mask; 474 req->reset_types[0] = mask; 475 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID; 476 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff); 477 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32); 478 479 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 480 if (ret) { 481 ath10k_warn(ar, "failed to send htt type stats request: %d", 482 ret); 483 dev_kfree_skb_any(skb); 484 return ret; 485 } 486 487 return 0; 488 } 489 490 int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) 491 { 492 struct ath10k *ar = htt->ar; 493 struct sk_buff *skb; 494 struct htt_cmd *cmd; 495 struct htt_frag_desc_bank_cfg *cfg; 496 int ret, size; 497 u8 info; 498 499 if (!ar->hw_params.continuous_frag_desc) 500 return 0; 501 502 if (!htt->frag_desc.paddr) { 503 ath10k_warn(ar, "invalid frag desc memory\n"); 504 return -EINVAL; 505 } 506 507 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg); 508 skb = ath10k_htc_alloc_skb(ar, size); 509 if (!skb) 510 return -ENOMEM; 511 512 skb_put(skb, size); 513 cmd = (struct htt_cmd *)skb->data; 514 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 515 516 info = 0; 517 info |= SM(htt->tx_q_state.type, 518 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 519 520 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 521 ar->running_fw->fw_file.fw_features)) 522 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 523 524 cfg = &cmd->frag_desc_bank_cfg; 525 cfg->info = info; 526 cfg->num_banks = 1; 527 cfg->desc_size = sizeof(struct htt_msdu_ext_desc); 528 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr); 529 cfg->bank_id[0].bank_min_id = 0; 530 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 531 1); 532 533 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 534 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 535 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 536 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 537 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 538 539 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 540 541 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 542 if (ret) { 543 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 544 ret); 545 dev_kfree_skb_any(skb); 546 return ret; 547 } 548 549 return 0; 550 } 551 552 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt) 553 { 554 struct ath10k *ar = htt->ar; 555 struct sk_buff *skb; 556 struct htt_cmd *cmd; 557 struct htt_rx_ring_setup_ring *ring; 558 const int num_rx_ring = 1; 559 u16 flags; 560 u32 fw_idx; 561 int len; 562 int ret; 563 564 /* 565 * the HW expects the buffer to be an integral number of 4-byte 566 * "words" 567 */ 568 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 569 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 570 571 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr) 572 + (sizeof(*ring) * num_rx_ring); 573 skb = ath10k_htc_alloc_skb(ar, len); 574 if (!skb) 575 return -ENOMEM; 576 577 skb_put(skb, len); 578 579 cmd = (struct htt_cmd *)skb->data; 580 ring = &cmd->rx_setup.rings[0]; 581 582 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 583 cmd->rx_setup.hdr.num_rings = 1; 584 585 /* FIXME: do we need all of this? */ 586 flags = 0; 587 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 588 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 589 flags |= HTT_RX_RING_FLAGS_PPDU_START; 590 flags |= HTT_RX_RING_FLAGS_PPDU_END; 591 flags |= HTT_RX_RING_FLAGS_MPDU_START; 592 flags |= HTT_RX_RING_FLAGS_MPDU_END; 593 flags |= HTT_RX_RING_FLAGS_MSDU_START; 594 flags |= HTT_RX_RING_FLAGS_MSDU_END; 595 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 596 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 597 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 598 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 599 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 600 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 601 flags |= HTT_RX_RING_FLAGS_NULL_RX; 602 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 603 604 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 605 606 ring->fw_idx_shadow_reg_paddr = 607 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); 608 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); 609 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 610 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 611 ring->flags = __cpu_to_le16(flags); 612 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 613 614 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4) 615 616 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); 617 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); 618 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); 619 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); 620 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); 621 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); 622 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); 623 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); 624 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); 625 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); 626 627 #undef desc_offset 628 629 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 630 if (ret) { 631 dev_kfree_skb_any(skb); 632 return ret; 633 } 634 635 return 0; 636 } 637 638 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 639 u8 max_subfrms_ampdu, 640 u8 max_subfrms_amsdu) 641 { 642 struct ath10k *ar = htt->ar; 643 struct htt_aggr_conf *aggr_conf; 644 struct sk_buff *skb; 645 struct htt_cmd *cmd; 646 int len; 647 int ret; 648 649 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 650 651 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 652 return -EINVAL; 653 654 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 655 return -EINVAL; 656 657 len = sizeof(cmd->hdr); 658 len += sizeof(cmd->aggr_conf); 659 660 skb = ath10k_htc_alloc_skb(ar, len); 661 if (!skb) 662 return -ENOMEM; 663 664 skb_put(skb, len); 665 cmd = (struct htt_cmd *)skb->data; 666 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 667 668 aggr_conf = &cmd->aggr_conf; 669 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 670 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 671 672 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 673 aggr_conf->max_num_amsdu_subframes, 674 aggr_conf->max_num_ampdu_subframes); 675 676 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 677 if (ret) { 678 dev_kfree_skb_any(skb); 679 return ret; 680 } 681 682 return 0; 683 } 684 685 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 686 __le32 token, 687 __le16 fetch_seq_num, 688 struct htt_tx_fetch_record *records, 689 size_t num_records) 690 { 691 struct sk_buff *skb; 692 struct htt_cmd *cmd; 693 const u16 resp_id = 0; 694 int len = 0; 695 int ret; 696 697 /* Response IDs are echo-ed back only for host driver convienence 698 * purposes. They aren't used for anything in the driver yet so use 0. 699 */ 700 701 len += sizeof(cmd->hdr); 702 len += sizeof(cmd->tx_fetch_resp); 703 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records; 704 705 skb = ath10k_htc_alloc_skb(ar, len); 706 if (!skb) 707 return -ENOMEM; 708 709 skb_put(skb, len); 710 cmd = (struct htt_cmd *)skb->data; 711 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP; 712 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id); 713 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num; 714 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records); 715 cmd->tx_fetch_resp.token = token; 716 717 memcpy(cmd->tx_fetch_resp.records, records, 718 sizeof(records[0]) * num_records); 719 720 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb); 721 if (ret) { 722 ath10k_warn(ar, "failed to submit htc command: %d\n", ret); 723 goto err_free_skb; 724 } 725 726 return 0; 727 728 err_free_skb: 729 dev_kfree_skb_any(skb); 730 731 return ret; 732 } 733 734 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb) 735 { 736 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 737 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 738 struct ath10k_vif *arvif; 739 740 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { 741 return ar->scan.vdev_id; 742 } else if (cb->vif) { 743 arvif = (void *)cb->vif->drv_priv; 744 return arvif->vdev_id; 745 } else if (ar->monitor_started) { 746 return ar->monitor_vdev_id; 747 } else { 748 return 0; 749 } 750 } 751 752 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth) 753 { 754 struct ieee80211_hdr *hdr = (void *)skb->data; 755 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 756 757 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control)) 758 return HTT_DATA_TX_EXT_TID_MGMT; 759 else if (cb->flags & ATH10K_SKB_F_QOS) 760 return skb->priority % IEEE80211_QOS_CTL_TID_MASK; 761 else 762 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; 763 } 764 765 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) 766 { 767 struct ath10k *ar = htt->ar; 768 struct device *dev = ar->dev; 769 struct sk_buff *txdesc = NULL; 770 struct htt_cmd *cmd; 771 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 772 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 773 int len = 0; 774 int msdu_id = -1; 775 int res; 776 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 777 778 len += sizeof(cmd->hdr); 779 len += sizeof(cmd->mgmt_tx); 780 781 spin_lock_bh(&htt->tx_lock); 782 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 783 spin_unlock_bh(&htt->tx_lock); 784 if (res < 0) 785 goto err; 786 787 msdu_id = res; 788 789 if ((ieee80211_is_action(hdr->frame_control) || 790 ieee80211_is_deauth(hdr->frame_control) || 791 ieee80211_is_disassoc(hdr->frame_control)) && 792 ieee80211_has_protected(hdr->frame_control)) { 793 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 794 } 795 796 txdesc = ath10k_htc_alloc_skb(ar, len); 797 if (!txdesc) { 798 res = -ENOMEM; 799 goto err_free_msdu_id; 800 } 801 802 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 803 DMA_TO_DEVICE); 804 res = dma_mapping_error(dev, skb_cb->paddr); 805 if (res) { 806 res = -EIO; 807 goto err_free_txdesc; 808 } 809 810 skb_put(txdesc, len); 811 cmd = (struct htt_cmd *)txdesc->data; 812 memset(cmd, 0, len); 813 814 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX; 815 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr); 816 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len); 817 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id); 818 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id); 819 memcpy(cmd->mgmt_tx.hdr, msdu->data, 820 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN)); 821 822 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc); 823 if (res) 824 goto err_unmap_msdu; 825 826 return 0; 827 828 err_unmap_msdu: 829 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 830 err_free_txdesc: 831 dev_kfree_skb_any(txdesc); 832 err_free_msdu_id: 833 spin_lock_bh(&htt->tx_lock); 834 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 835 spin_unlock_bh(&htt->tx_lock); 836 err: 837 return res; 838 } 839 840 int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 841 struct sk_buff *msdu) 842 { 843 struct ath10k *ar = htt->ar; 844 struct device *dev = ar->dev; 845 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 846 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 847 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 848 struct ath10k_hif_sg_item sg_items[2]; 849 struct ath10k_htt_txbuf *txbuf; 850 struct htt_data_tx_desc_frag *frags; 851 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 852 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 853 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 854 int prefetch_len; 855 int res; 856 u8 flags0 = 0; 857 u16 msdu_id, flags1 = 0; 858 u16 freq = 0; 859 u32 frags_paddr = 0; 860 u32 txbuf_paddr; 861 struct htt_msdu_ext_desc *ext_desc = NULL; 862 863 spin_lock_bh(&htt->tx_lock); 864 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 865 spin_unlock_bh(&htt->tx_lock); 866 if (res < 0) 867 goto err; 868 869 msdu_id = res; 870 871 prefetch_len = min(htt->prefetch_len, msdu->len); 872 prefetch_len = roundup(prefetch_len, 4); 873 874 txbuf = &htt->txbuf.vaddr[msdu_id]; 875 txbuf_paddr = htt->txbuf.paddr + 876 (sizeof(struct ath10k_htt_txbuf) * msdu_id); 877 878 if ((ieee80211_is_action(hdr->frame_control) || 879 ieee80211_is_deauth(hdr->frame_control) || 880 ieee80211_is_disassoc(hdr->frame_control)) && 881 ieee80211_has_protected(hdr->frame_control)) { 882 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 883 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 884 txmode == ATH10K_HW_TXRX_RAW && 885 ieee80211_has_protected(hdr->frame_control)) { 886 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 887 } 888 889 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 890 DMA_TO_DEVICE); 891 res = dma_mapping_error(dev, skb_cb->paddr); 892 if (res) { 893 res = -EIO; 894 goto err_free_msdu_id; 895 } 896 897 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 898 freq = ar->scan.roc_freq; 899 900 switch (txmode) { 901 case ATH10K_HW_TXRX_RAW: 902 case ATH10K_HW_TXRX_NATIVE_WIFI: 903 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 904 /* pass through */ 905 case ATH10K_HW_TXRX_ETHERNET: 906 if (ar->hw_params.continuous_frag_desc) { 907 memset(&htt->frag_desc.vaddr[msdu_id], 0, 908 sizeof(struct htt_msdu_ext_desc)); 909 frags = (struct htt_data_tx_desc_frag *) 910 &htt->frag_desc.vaddr[msdu_id].frags; 911 ext_desc = &htt->frag_desc.vaddr[msdu_id]; 912 frags[0].tword_addr.paddr_lo = 913 __cpu_to_le32(skb_cb->paddr); 914 frags[0].tword_addr.paddr_hi = 0; 915 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 916 917 frags_paddr = htt->frag_desc.paddr + 918 (sizeof(struct htt_msdu_ext_desc) * msdu_id); 919 } else { 920 frags = txbuf->frags; 921 frags[0].dword_addr.paddr = 922 __cpu_to_le32(skb_cb->paddr); 923 frags[0].dword_addr.len = __cpu_to_le32(msdu->len); 924 frags[1].dword_addr.paddr = 0; 925 frags[1].dword_addr.len = 0; 926 927 frags_paddr = txbuf_paddr; 928 } 929 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 930 break; 931 case ATH10K_HW_TXRX_MGMT: 932 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 933 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 934 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 935 936 frags_paddr = skb_cb->paddr; 937 break; 938 } 939 940 /* Normally all commands go through HTC which manages tx credits for 941 * each endpoint and notifies when tx is completed. 942 * 943 * HTT endpoint is creditless so there's no need to care about HTC 944 * flags. In that case it is trivial to fill the HTC header here. 945 * 946 * MSDU transmission is considered completed upon HTT event. This 947 * implies no relevant resources can be freed until after the event is 948 * received. That's why HTC tx completion handler itself is ignored by 949 * setting NULL to transfer_context for all sg items. 950 * 951 * There is simply no point in pushing HTT TX_FRM through HTC tx path 952 * as it's a waste of resources. By bypassing HTC it is possible to 953 * avoid extra memory allocations, compress data structures and thus 954 * improve performance. */ 955 956 txbuf->htc_hdr.eid = htt->eid; 957 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 958 sizeof(txbuf->cmd_tx) + 959 prefetch_len); 960 txbuf->htc_hdr.flags = 0; 961 962 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 963 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 964 965 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 966 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 967 if (msdu->ip_summed == CHECKSUM_PARTIAL && 968 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 969 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 970 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 971 if (ar->hw_params.continuous_frag_desc) 972 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE; 973 } 974 975 /* Prevent firmware from sending up tx inspection requests. There's 976 * nothing ath10k can do with frames requested for inspection so force 977 * it to simply rely a regular tx completion with discard status. 978 */ 979 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 980 981 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 982 txbuf->cmd_tx.flags0 = flags0; 983 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 984 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 985 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 986 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr); 987 if (ath10k_mac_tx_frm_has_freq(ar)) { 988 txbuf->cmd_tx.offchan_tx.peerid = 989 __cpu_to_le16(HTT_INVALID_PEERID); 990 txbuf->cmd_tx.offchan_tx.freq = 991 __cpu_to_le16(freq); 992 } else { 993 txbuf->cmd_tx.peerid = 994 __cpu_to_le32(HTT_INVALID_PEERID); 995 } 996 997 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 998 ath10k_dbg(ar, ATH10K_DBG_HTT, 999 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu freq %hu\n", 1000 flags0, flags1, msdu->len, msdu_id, frags_paddr, 1001 (u32)skb_cb->paddr, vdev_id, tid, freq); 1002 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1003 msdu->data, msdu->len); 1004 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1005 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1006 1007 sg_items[0].transfer_id = 0; 1008 sg_items[0].transfer_context = NULL; 1009 sg_items[0].vaddr = &txbuf->htc_hdr; 1010 sg_items[0].paddr = txbuf_paddr + 1011 sizeof(txbuf->frags); 1012 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1013 sizeof(txbuf->cmd_hdr) + 1014 sizeof(txbuf->cmd_tx); 1015 1016 sg_items[1].transfer_id = 0; 1017 sg_items[1].transfer_context = NULL; 1018 sg_items[1].vaddr = msdu->data; 1019 sg_items[1].paddr = skb_cb->paddr; 1020 sg_items[1].len = prefetch_len; 1021 1022 res = ath10k_hif_tx_sg(htt->ar, 1023 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1024 sg_items, ARRAY_SIZE(sg_items)); 1025 if (res) 1026 goto err_unmap_msdu; 1027 1028 return 0; 1029 1030 err_unmap_msdu: 1031 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1032 err_free_msdu_id: 1033 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1034 err: 1035 return res; 1036 } 1037