1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/etherdevice.h> 19 #include "htt.h" 20 #include "mac.h" 21 #include "hif.h" 22 #include "txrx.h" 23 #include "debug.h" 24 25 static u8 ath10k_htt_tx_txq_calc_size(size_t count) 26 { 27 int exp; 28 int factor; 29 30 exp = 0; 31 factor = count >> 7; 32 33 while (factor >= 64 && exp < 4) { 34 factor >>= 3; 35 exp++; 36 } 37 38 if (exp == 4) 39 return 0xff; 40 41 if (count > 0) 42 factor = max(1, factor); 43 44 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | 45 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); 46 } 47 48 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 49 struct ieee80211_txq *txq) 50 { 51 struct ath10k *ar = hw->priv; 52 struct ath10k_sta *arsta; 53 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv; 54 unsigned long frame_cnt; 55 unsigned long byte_cnt; 56 int idx; 57 u32 bit; 58 u16 peer_id; 59 u8 tid; 60 u8 count; 61 62 lockdep_assert_held(&ar->htt.tx_lock); 63 64 if (!ar->htt.tx_q_state.enabled) 65 return; 66 67 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 68 return; 69 70 if (txq->sta) { 71 arsta = (void *)txq->sta->drv_priv; 72 peer_id = arsta->peer_id; 73 } else { 74 peer_id = arvif->peer_id; 75 } 76 77 tid = txq->tid; 78 bit = BIT(peer_id % 32); 79 idx = peer_id / 32; 80 81 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 82 count = ath10k_htt_tx_txq_calc_size(byte_cnt); 83 84 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || 85 unlikely(tid >= ar->htt.tx_q_state.num_tids)) { 86 ath10k_warn(ar, "refusing to update txq for peer_id %hu tid %hhu due to out of bounds\n", 87 peer_id, tid); 88 return; 89 } 90 91 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count; 92 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit; 93 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0; 94 95 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %hu tid %hhu count %hhu\n", 96 peer_id, tid, count); 97 } 98 99 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar) 100 { 101 u32 seq; 102 size_t size; 103 104 lockdep_assert_held(&ar->htt.tx_lock); 105 106 if (!ar->htt.tx_q_state.enabled) 107 return; 108 109 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 110 return; 111 112 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq); 113 seq++; 114 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq); 115 116 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n", 117 seq); 118 119 size = sizeof(*ar->htt.tx_q_state.vaddr); 120 dma_sync_single_for_device(ar->dev, 121 ar->htt.tx_q_state.paddr, 122 size, 123 DMA_TO_DEVICE); 124 } 125 126 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 127 struct ieee80211_txq *txq) 128 { 129 struct ath10k *ar = hw->priv; 130 131 spin_lock_bh(&ar->htt.tx_lock); 132 __ath10k_htt_tx_txq_recalc(hw, txq); 133 spin_unlock_bh(&ar->htt.tx_lock); 134 } 135 136 void ath10k_htt_tx_txq_sync(struct ath10k *ar) 137 { 138 spin_lock_bh(&ar->htt.tx_lock); 139 __ath10k_htt_tx_txq_sync(ar); 140 spin_unlock_bh(&ar->htt.tx_lock); 141 } 142 143 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 144 struct ieee80211_txq *txq) 145 { 146 struct ath10k *ar = hw->priv; 147 148 spin_lock_bh(&ar->htt.tx_lock); 149 __ath10k_htt_tx_txq_recalc(hw, txq); 150 __ath10k_htt_tx_txq_sync(ar); 151 spin_unlock_bh(&ar->htt.tx_lock); 152 } 153 154 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt) 155 { 156 lockdep_assert_held(&htt->tx_lock); 157 158 htt->num_pending_tx--; 159 if (htt->num_pending_tx == htt->max_num_pending_tx - 1) 160 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 161 } 162 163 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt) 164 { 165 lockdep_assert_held(&htt->tx_lock); 166 167 if (htt->num_pending_tx >= htt->max_num_pending_tx) 168 return -EBUSY; 169 170 htt->num_pending_tx++; 171 if (htt->num_pending_tx == htt->max_num_pending_tx) 172 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 173 174 return 0; 175 } 176 177 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 178 bool is_presp) 179 { 180 struct ath10k *ar = htt->ar; 181 182 lockdep_assert_held(&htt->tx_lock); 183 184 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres) 185 return 0; 186 187 if (is_presp && 188 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx) 189 return -EBUSY; 190 191 htt->num_pending_mgmt_tx++; 192 193 return 0; 194 } 195 196 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt) 197 { 198 lockdep_assert_held(&htt->tx_lock); 199 200 if (!htt->ar->hw_params.max_probe_resp_desc_thres) 201 return; 202 203 htt->num_pending_mgmt_tx--; 204 } 205 206 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb) 207 { 208 struct ath10k *ar = htt->ar; 209 int ret; 210 211 lockdep_assert_held(&htt->tx_lock); 212 213 ret = idr_alloc(&htt->pending_tx, skb, 0, 214 htt->max_num_pending_tx, GFP_ATOMIC); 215 216 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret); 217 218 return ret; 219 } 220 221 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id) 222 { 223 struct ath10k *ar = htt->ar; 224 225 lockdep_assert_held(&htt->tx_lock); 226 227 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id); 228 229 idr_remove(&htt->pending_tx, msdu_id); 230 } 231 232 static void ath10k_htt_tx_free_cont_txbuf(struct ath10k_htt *htt) 233 { 234 struct ath10k *ar = htt->ar; 235 size_t size; 236 237 if (!htt->txbuf.vaddr) 238 return; 239 240 size = htt->max_num_pending_tx * sizeof(struct ath10k_htt_txbuf); 241 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr, htt->txbuf.paddr); 242 htt->txbuf.vaddr = NULL; 243 } 244 245 static int ath10k_htt_tx_alloc_cont_txbuf(struct ath10k_htt *htt) 246 { 247 struct ath10k *ar = htt->ar; 248 size_t size; 249 250 size = htt->max_num_pending_tx * sizeof(struct ath10k_htt_txbuf); 251 htt->txbuf.vaddr = dma_alloc_coherent(ar->dev, size, &htt->txbuf.paddr, 252 GFP_KERNEL); 253 if (!htt->txbuf.vaddr) 254 return -ENOMEM; 255 256 return 0; 257 } 258 259 static void ath10k_htt_tx_free_cont_frag_desc(struct ath10k_htt *htt) 260 { 261 size_t size; 262 263 if (!htt->frag_desc.vaddr) 264 return; 265 266 size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc); 267 268 dma_free_coherent(htt->ar->dev, 269 size, 270 htt->frag_desc.vaddr, 271 htt->frag_desc.paddr); 272 htt->frag_desc.vaddr = NULL; 273 } 274 275 static int ath10k_htt_tx_alloc_cont_frag_desc(struct ath10k_htt *htt) 276 { 277 struct ath10k *ar = htt->ar; 278 size_t size; 279 280 if (!ar->hw_params.continuous_frag_desc) 281 return 0; 282 283 size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc); 284 htt->frag_desc.vaddr = dma_alloc_coherent(ar->dev, size, 285 &htt->frag_desc.paddr, 286 GFP_KERNEL); 287 if (!htt->frag_desc.vaddr) 288 return -ENOMEM; 289 290 return 0; 291 } 292 293 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt) 294 { 295 struct ath10k *ar = htt->ar; 296 size_t size; 297 298 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 299 ar->running_fw->fw_file.fw_features)) 300 return; 301 302 size = sizeof(*htt->tx_q_state.vaddr); 303 304 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE); 305 kfree(htt->tx_q_state.vaddr); 306 } 307 308 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt) 309 { 310 struct ath10k *ar = htt->ar; 311 size_t size; 312 int ret; 313 314 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 315 ar->running_fw->fw_file.fw_features)) 316 return 0; 317 318 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS; 319 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS; 320 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES; 321 322 size = sizeof(*htt->tx_q_state.vaddr); 323 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL); 324 if (!htt->tx_q_state.vaddr) 325 return -ENOMEM; 326 327 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr, 328 size, DMA_TO_DEVICE); 329 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr); 330 if (ret) { 331 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret); 332 kfree(htt->tx_q_state.vaddr); 333 return -EIO; 334 } 335 336 return 0; 337 } 338 339 static void ath10k_htt_tx_free_txdone_fifo(struct ath10k_htt *htt) 340 { 341 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo)); 342 kfifo_free(&htt->txdone_fifo); 343 } 344 345 static int ath10k_htt_tx_alloc_txdone_fifo(struct ath10k_htt *htt) 346 { 347 int ret; 348 size_t size; 349 350 size = roundup_pow_of_two(htt->max_num_pending_tx); 351 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL); 352 return ret; 353 } 354 355 static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt) 356 { 357 struct ath10k *ar = htt->ar; 358 int ret; 359 360 ret = ath10k_htt_tx_alloc_cont_txbuf(htt); 361 if (ret) { 362 ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret); 363 return ret; 364 } 365 366 ret = ath10k_htt_tx_alloc_cont_frag_desc(htt); 367 if (ret) { 368 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret); 369 goto free_txbuf; 370 } 371 372 ret = ath10k_htt_tx_alloc_txq(htt); 373 if (ret) { 374 ath10k_err(ar, "failed to alloc txq: %d\n", ret); 375 goto free_frag_desc; 376 } 377 378 ret = ath10k_htt_tx_alloc_txdone_fifo(htt); 379 if (ret) { 380 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret); 381 goto free_txq; 382 } 383 384 return 0; 385 386 free_txq: 387 ath10k_htt_tx_free_txq(htt); 388 389 free_frag_desc: 390 ath10k_htt_tx_free_cont_frag_desc(htt); 391 392 free_txbuf: 393 ath10k_htt_tx_free_cont_txbuf(htt); 394 395 return ret; 396 } 397 398 int ath10k_htt_tx_start(struct ath10k_htt *htt) 399 { 400 struct ath10k *ar = htt->ar; 401 int ret; 402 403 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n", 404 htt->max_num_pending_tx); 405 406 spin_lock_init(&htt->tx_lock); 407 idr_init(&htt->pending_tx); 408 409 if (htt->tx_mem_allocated) 410 return 0; 411 412 ret = ath10k_htt_tx_alloc_buf(htt); 413 if (ret) 414 goto free_idr_pending_tx; 415 416 htt->tx_mem_allocated = true; 417 418 return 0; 419 420 free_idr_pending_tx: 421 idr_destroy(&htt->pending_tx); 422 423 return ret; 424 } 425 426 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx) 427 { 428 struct ath10k *ar = ctx; 429 struct ath10k_htt *htt = &ar->htt; 430 struct htt_tx_done tx_done = {0}; 431 432 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id); 433 434 tx_done.msdu_id = msdu_id; 435 tx_done.status = HTT_TX_COMPL_STATE_DISCARD; 436 437 ath10k_txrx_tx_unref(htt, &tx_done); 438 439 return 0; 440 } 441 442 void ath10k_htt_tx_destroy(struct ath10k_htt *htt) 443 { 444 if (!htt->tx_mem_allocated) 445 return; 446 447 ath10k_htt_tx_free_cont_txbuf(htt); 448 ath10k_htt_tx_free_txq(htt); 449 ath10k_htt_tx_free_cont_frag_desc(htt); 450 ath10k_htt_tx_free_txdone_fifo(htt); 451 htt->tx_mem_allocated = false; 452 } 453 454 void ath10k_htt_tx_stop(struct ath10k_htt *htt) 455 { 456 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar); 457 idr_destroy(&htt->pending_tx); 458 } 459 460 void ath10k_htt_tx_free(struct ath10k_htt *htt) 461 { 462 ath10k_htt_tx_stop(htt); 463 ath10k_htt_tx_destroy(htt); 464 } 465 466 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb) 467 { 468 dev_kfree_skb_any(skb); 469 } 470 471 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb) 472 { 473 dev_kfree_skb_any(skb); 474 } 475 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete); 476 477 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt) 478 { 479 struct ath10k *ar = htt->ar; 480 struct sk_buff *skb; 481 struct htt_cmd *cmd; 482 int len = 0; 483 int ret; 484 485 len += sizeof(cmd->hdr); 486 len += sizeof(cmd->ver_req); 487 488 skb = ath10k_htc_alloc_skb(ar, len); 489 if (!skb) 490 return -ENOMEM; 491 492 skb_put(skb, len); 493 cmd = (struct htt_cmd *)skb->data; 494 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ; 495 496 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 497 if (ret) { 498 dev_kfree_skb_any(skb); 499 return ret; 500 } 501 502 return 0; 503 } 504 505 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie) 506 { 507 struct ath10k *ar = htt->ar; 508 struct htt_stats_req *req; 509 struct sk_buff *skb; 510 struct htt_cmd *cmd; 511 int len = 0, ret; 512 513 len += sizeof(cmd->hdr); 514 len += sizeof(cmd->stats_req); 515 516 skb = ath10k_htc_alloc_skb(ar, len); 517 if (!skb) 518 return -ENOMEM; 519 520 skb_put(skb, len); 521 cmd = (struct htt_cmd *)skb->data; 522 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ; 523 524 req = &cmd->stats_req; 525 526 memset(req, 0, sizeof(*req)); 527 528 /* currently we support only max 8 bit masks so no need to worry 529 * about endian support 530 */ 531 req->upload_types[0] = mask; 532 req->reset_types[0] = mask; 533 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID; 534 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff); 535 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32); 536 537 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 538 if (ret) { 539 ath10k_warn(ar, "failed to send htt type stats request: %d", 540 ret); 541 dev_kfree_skb_any(skb); 542 return ret; 543 } 544 545 return 0; 546 } 547 548 int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) 549 { 550 struct ath10k *ar = htt->ar; 551 struct sk_buff *skb; 552 struct htt_cmd *cmd; 553 struct htt_frag_desc_bank_cfg *cfg; 554 int ret, size; 555 u8 info; 556 557 if (!ar->hw_params.continuous_frag_desc) 558 return 0; 559 560 if (!htt->frag_desc.paddr) { 561 ath10k_warn(ar, "invalid frag desc memory\n"); 562 return -EINVAL; 563 } 564 565 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg); 566 skb = ath10k_htc_alloc_skb(ar, size); 567 if (!skb) 568 return -ENOMEM; 569 570 skb_put(skb, size); 571 cmd = (struct htt_cmd *)skb->data; 572 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 573 574 info = 0; 575 info |= SM(htt->tx_q_state.type, 576 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 577 578 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 579 ar->running_fw->fw_file.fw_features)) 580 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 581 582 cfg = &cmd->frag_desc_bank_cfg; 583 cfg->info = info; 584 cfg->num_banks = 1; 585 cfg->desc_size = sizeof(struct htt_msdu_ext_desc); 586 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr); 587 cfg->bank_id[0].bank_min_id = 0; 588 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 589 1); 590 591 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 592 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 593 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 594 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 595 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 596 597 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 598 599 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 600 if (ret) { 601 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 602 ret); 603 dev_kfree_skb_any(skb); 604 return ret; 605 } 606 607 return 0; 608 } 609 610 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt) 611 { 612 struct ath10k *ar = htt->ar; 613 struct sk_buff *skb; 614 struct htt_cmd *cmd; 615 struct htt_rx_ring_setup_ring *ring; 616 const int num_rx_ring = 1; 617 u16 flags; 618 u32 fw_idx; 619 int len; 620 int ret; 621 622 /* 623 * the HW expects the buffer to be an integral number of 4-byte 624 * "words" 625 */ 626 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 627 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 628 629 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr) 630 + (sizeof(*ring) * num_rx_ring); 631 skb = ath10k_htc_alloc_skb(ar, len); 632 if (!skb) 633 return -ENOMEM; 634 635 skb_put(skb, len); 636 637 cmd = (struct htt_cmd *)skb->data; 638 ring = &cmd->rx_setup.rings[0]; 639 640 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 641 cmd->rx_setup.hdr.num_rings = 1; 642 643 /* FIXME: do we need all of this? */ 644 flags = 0; 645 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 646 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 647 flags |= HTT_RX_RING_FLAGS_PPDU_START; 648 flags |= HTT_RX_RING_FLAGS_PPDU_END; 649 flags |= HTT_RX_RING_FLAGS_MPDU_START; 650 flags |= HTT_RX_RING_FLAGS_MPDU_END; 651 flags |= HTT_RX_RING_FLAGS_MSDU_START; 652 flags |= HTT_RX_RING_FLAGS_MSDU_END; 653 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 654 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 655 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 656 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 657 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 658 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 659 flags |= HTT_RX_RING_FLAGS_NULL_RX; 660 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 661 662 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 663 664 ring->fw_idx_shadow_reg_paddr = 665 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); 666 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); 667 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 668 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 669 ring->flags = __cpu_to_le16(flags); 670 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 671 672 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4) 673 674 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); 675 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); 676 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); 677 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); 678 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); 679 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); 680 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); 681 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); 682 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); 683 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); 684 685 #undef desc_offset 686 687 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 688 if (ret) { 689 dev_kfree_skb_any(skb); 690 return ret; 691 } 692 693 return 0; 694 } 695 696 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 697 u8 max_subfrms_ampdu, 698 u8 max_subfrms_amsdu) 699 { 700 struct ath10k *ar = htt->ar; 701 struct htt_aggr_conf *aggr_conf; 702 struct sk_buff *skb; 703 struct htt_cmd *cmd; 704 int len; 705 int ret; 706 707 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 708 709 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 710 return -EINVAL; 711 712 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 713 return -EINVAL; 714 715 len = sizeof(cmd->hdr); 716 len += sizeof(cmd->aggr_conf); 717 718 skb = ath10k_htc_alloc_skb(ar, len); 719 if (!skb) 720 return -ENOMEM; 721 722 skb_put(skb, len); 723 cmd = (struct htt_cmd *)skb->data; 724 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 725 726 aggr_conf = &cmd->aggr_conf; 727 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 728 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 729 730 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 731 aggr_conf->max_num_amsdu_subframes, 732 aggr_conf->max_num_ampdu_subframes); 733 734 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 735 if (ret) { 736 dev_kfree_skb_any(skb); 737 return ret; 738 } 739 740 return 0; 741 } 742 743 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 744 __le32 token, 745 __le16 fetch_seq_num, 746 struct htt_tx_fetch_record *records, 747 size_t num_records) 748 { 749 struct sk_buff *skb; 750 struct htt_cmd *cmd; 751 const u16 resp_id = 0; 752 int len = 0; 753 int ret; 754 755 /* Response IDs are echo-ed back only for host driver convienence 756 * purposes. They aren't used for anything in the driver yet so use 0. 757 */ 758 759 len += sizeof(cmd->hdr); 760 len += sizeof(cmd->tx_fetch_resp); 761 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records; 762 763 skb = ath10k_htc_alloc_skb(ar, len); 764 if (!skb) 765 return -ENOMEM; 766 767 skb_put(skb, len); 768 cmd = (struct htt_cmd *)skb->data; 769 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP; 770 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id); 771 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num; 772 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records); 773 cmd->tx_fetch_resp.token = token; 774 775 memcpy(cmd->tx_fetch_resp.records, records, 776 sizeof(records[0]) * num_records); 777 778 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb); 779 if (ret) { 780 ath10k_warn(ar, "failed to submit htc command: %d\n", ret); 781 goto err_free_skb; 782 } 783 784 return 0; 785 786 err_free_skb: 787 dev_kfree_skb_any(skb); 788 789 return ret; 790 } 791 792 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb) 793 { 794 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 795 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 796 struct ath10k_vif *arvif; 797 798 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { 799 return ar->scan.vdev_id; 800 } else if (cb->vif) { 801 arvif = (void *)cb->vif->drv_priv; 802 return arvif->vdev_id; 803 } else if (ar->monitor_started) { 804 return ar->monitor_vdev_id; 805 } else { 806 return 0; 807 } 808 } 809 810 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth) 811 { 812 struct ieee80211_hdr *hdr = (void *)skb->data; 813 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 814 815 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control)) 816 return HTT_DATA_TX_EXT_TID_MGMT; 817 else if (cb->flags & ATH10K_SKB_F_QOS) 818 return skb->priority % IEEE80211_QOS_CTL_TID_MASK; 819 else 820 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; 821 } 822 823 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) 824 { 825 struct ath10k *ar = htt->ar; 826 struct device *dev = ar->dev; 827 struct sk_buff *txdesc = NULL; 828 struct htt_cmd *cmd; 829 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 830 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 831 int len = 0; 832 int msdu_id = -1; 833 int res; 834 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 835 836 len += sizeof(cmd->hdr); 837 len += sizeof(cmd->mgmt_tx); 838 839 spin_lock_bh(&htt->tx_lock); 840 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 841 spin_unlock_bh(&htt->tx_lock); 842 if (res < 0) 843 goto err; 844 845 msdu_id = res; 846 847 if ((ieee80211_is_action(hdr->frame_control) || 848 ieee80211_is_deauth(hdr->frame_control) || 849 ieee80211_is_disassoc(hdr->frame_control)) && 850 ieee80211_has_protected(hdr->frame_control)) { 851 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 852 } 853 854 txdesc = ath10k_htc_alloc_skb(ar, len); 855 if (!txdesc) { 856 res = -ENOMEM; 857 goto err_free_msdu_id; 858 } 859 860 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 861 DMA_TO_DEVICE); 862 res = dma_mapping_error(dev, skb_cb->paddr); 863 if (res) { 864 res = -EIO; 865 goto err_free_txdesc; 866 } 867 868 skb_put(txdesc, len); 869 cmd = (struct htt_cmd *)txdesc->data; 870 memset(cmd, 0, len); 871 872 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX; 873 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr); 874 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len); 875 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id); 876 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id); 877 memcpy(cmd->mgmt_tx.hdr, msdu->data, 878 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN)); 879 880 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc); 881 if (res) 882 goto err_unmap_msdu; 883 884 return 0; 885 886 err_unmap_msdu: 887 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 888 err_free_txdesc: 889 dev_kfree_skb_any(txdesc); 890 err_free_msdu_id: 891 spin_lock_bh(&htt->tx_lock); 892 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 893 spin_unlock_bh(&htt->tx_lock); 894 err: 895 return res; 896 } 897 898 int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 899 struct sk_buff *msdu) 900 { 901 struct ath10k *ar = htt->ar; 902 struct device *dev = ar->dev; 903 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 904 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 905 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 906 struct ath10k_hif_sg_item sg_items[2]; 907 struct ath10k_htt_txbuf *txbuf; 908 struct htt_data_tx_desc_frag *frags; 909 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 910 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 911 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 912 int prefetch_len; 913 int res; 914 u8 flags0 = 0; 915 u16 msdu_id, flags1 = 0; 916 u16 freq = 0; 917 u32 frags_paddr = 0; 918 u32 txbuf_paddr; 919 struct htt_msdu_ext_desc *ext_desc = NULL; 920 921 spin_lock_bh(&htt->tx_lock); 922 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 923 spin_unlock_bh(&htt->tx_lock); 924 if (res < 0) 925 goto err; 926 927 msdu_id = res; 928 929 prefetch_len = min(htt->prefetch_len, msdu->len); 930 prefetch_len = roundup(prefetch_len, 4); 931 932 txbuf = &htt->txbuf.vaddr[msdu_id]; 933 txbuf_paddr = htt->txbuf.paddr + 934 (sizeof(struct ath10k_htt_txbuf) * msdu_id); 935 936 if ((ieee80211_is_action(hdr->frame_control) || 937 ieee80211_is_deauth(hdr->frame_control) || 938 ieee80211_is_disassoc(hdr->frame_control)) && 939 ieee80211_has_protected(hdr->frame_control)) { 940 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 941 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 942 txmode == ATH10K_HW_TXRX_RAW && 943 ieee80211_has_protected(hdr->frame_control)) { 944 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 945 } 946 947 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 948 DMA_TO_DEVICE); 949 res = dma_mapping_error(dev, skb_cb->paddr); 950 if (res) { 951 res = -EIO; 952 goto err_free_msdu_id; 953 } 954 955 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 956 freq = ar->scan.roc_freq; 957 958 switch (txmode) { 959 case ATH10K_HW_TXRX_RAW: 960 case ATH10K_HW_TXRX_NATIVE_WIFI: 961 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 962 /* pass through */ 963 case ATH10K_HW_TXRX_ETHERNET: 964 if (ar->hw_params.continuous_frag_desc) { 965 memset(&htt->frag_desc.vaddr[msdu_id], 0, 966 sizeof(struct htt_msdu_ext_desc)); 967 frags = (struct htt_data_tx_desc_frag *) 968 &htt->frag_desc.vaddr[msdu_id].frags; 969 ext_desc = &htt->frag_desc.vaddr[msdu_id]; 970 frags[0].tword_addr.paddr_lo = 971 __cpu_to_le32(skb_cb->paddr); 972 frags[0].tword_addr.paddr_hi = 0; 973 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 974 975 frags_paddr = htt->frag_desc.paddr + 976 (sizeof(struct htt_msdu_ext_desc) * msdu_id); 977 } else { 978 frags = txbuf->frags; 979 frags[0].dword_addr.paddr = 980 __cpu_to_le32(skb_cb->paddr); 981 frags[0].dword_addr.len = __cpu_to_le32(msdu->len); 982 frags[1].dword_addr.paddr = 0; 983 frags[1].dword_addr.len = 0; 984 985 frags_paddr = txbuf_paddr; 986 } 987 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 988 break; 989 case ATH10K_HW_TXRX_MGMT: 990 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 991 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 992 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 993 994 frags_paddr = skb_cb->paddr; 995 break; 996 } 997 998 /* Normally all commands go through HTC which manages tx credits for 999 * each endpoint and notifies when tx is completed. 1000 * 1001 * HTT endpoint is creditless so there's no need to care about HTC 1002 * flags. In that case it is trivial to fill the HTC header here. 1003 * 1004 * MSDU transmission is considered completed upon HTT event. This 1005 * implies no relevant resources can be freed until after the event is 1006 * received. That's why HTC tx completion handler itself is ignored by 1007 * setting NULL to transfer_context for all sg items. 1008 * 1009 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1010 * as it's a waste of resources. By bypassing HTC it is possible to 1011 * avoid extra memory allocations, compress data structures and thus 1012 * improve performance. 1013 */ 1014 1015 txbuf->htc_hdr.eid = htt->eid; 1016 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1017 sizeof(txbuf->cmd_tx) + 1018 prefetch_len); 1019 txbuf->htc_hdr.flags = 0; 1020 1021 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1022 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1023 1024 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1025 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1026 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1027 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1028 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1029 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1030 if (ar->hw_params.continuous_frag_desc) 1031 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE; 1032 } 1033 1034 /* Prevent firmware from sending up tx inspection requests. There's 1035 * nothing ath10k can do with frames requested for inspection so force 1036 * it to simply rely a regular tx completion with discard status. 1037 */ 1038 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1039 1040 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1041 txbuf->cmd_tx.flags0 = flags0; 1042 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1043 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1044 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1045 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr); 1046 if (ath10k_mac_tx_frm_has_freq(ar)) { 1047 txbuf->cmd_tx.offchan_tx.peerid = 1048 __cpu_to_le16(HTT_INVALID_PEERID); 1049 txbuf->cmd_tx.offchan_tx.freq = 1050 __cpu_to_le16(freq); 1051 } else { 1052 txbuf->cmd_tx.peerid = 1053 __cpu_to_le32(HTT_INVALID_PEERID); 1054 } 1055 1056 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1057 ath10k_dbg(ar, ATH10K_DBG_HTT, 1058 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu freq %hu\n", 1059 flags0, flags1, msdu->len, msdu_id, frags_paddr, 1060 (u32)skb_cb->paddr, vdev_id, tid, freq); 1061 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1062 msdu->data, msdu->len); 1063 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1064 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1065 1066 sg_items[0].transfer_id = 0; 1067 sg_items[0].transfer_context = NULL; 1068 sg_items[0].vaddr = &txbuf->htc_hdr; 1069 sg_items[0].paddr = txbuf_paddr + 1070 sizeof(txbuf->frags); 1071 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1072 sizeof(txbuf->cmd_hdr) + 1073 sizeof(txbuf->cmd_tx); 1074 1075 sg_items[1].transfer_id = 0; 1076 sg_items[1].transfer_context = NULL; 1077 sg_items[1].vaddr = msdu->data; 1078 sg_items[1].paddr = skb_cb->paddr; 1079 sg_items[1].len = prefetch_len; 1080 1081 res = ath10k_hif_tx_sg(htt->ar, 1082 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1083 sg_items, ARRAY_SIZE(sg_items)); 1084 if (res) 1085 goto err_unmap_msdu; 1086 1087 return 0; 1088 1089 err_unmap_msdu: 1090 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1091 err_free_msdu_id: 1092 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1093 err: 1094 return res; 1095 } 1096