15e3dd157SKalle Valo /*
25e3dd157SKalle Valo  * Copyright (c) 2005-2011 Atheros Communications Inc.
35e3dd157SKalle Valo  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
45e3dd157SKalle Valo  *
55e3dd157SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
65e3dd157SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
75e3dd157SKalle Valo  * copyright notice and this permission notice appear in all copies.
85e3dd157SKalle Valo  *
95e3dd157SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
105e3dd157SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
115e3dd157SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
125e3dd157SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
135e3dd157SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
145e3dd157SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
155e3dd157SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
165e3dd157SKalle Valo  */
175e3dd157SKalle Valo 
18edb8236dSMichal Kazior #include "core.h"
195e3dd157SKalle Valo #include "htc.h"
205e3dd157SKalle Valo #include "htt.h"
215e3dd157SKalle Valo #include "txrx.h"
225e3dd157SKalle Valo #include "debug.h"
23a9bf0506SKalle Valo #include "trace.h"
245e3dd157SKalle Valo 
255e3dd157SKalle Valo #include <linux/log2.h>
265e3dd157SKalle Valo 
275e3dd157SKalle Valo /* slightly larger than one large A-MPDU */
285e3dd157SKalle Valo #define HTT_RX_RING_SIZE_MIN 128
295e3dd157SKalle Valo 
305e3dd157SKalle Valo /* roughly 20 ms @ 1 Gbps of 1500B MSDUs */
315e3dd157SKalle Valo #define HTT_RX_RING_SIZE_MAX 2048
325e3dd157SKalle Valo 
335e3dd157SKalle Valo #define HTT_RX_AVG_FRM_BYTES 1000
345e3dd157SKalle Valo 
355e3dd157SKalle Valo /* ms, very conservative */
365e3dd157SKalle Valo #define HTT_RX_HOST_LATENCY_MAX_MS 20
375e3dd157SKalle Valo 
385e3dd157SKalle Valo /* ms, conservative */
395e3dd157SKalle Valo #define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10
405e3dd157SKalle Valo 
415e3dd157SKalle Valo /* when under memory pressure rx ring refill may fail and needs a retry */
425e3dd157SKalle Valo #define HTT_RX_RING_REFILL_RETRY_MS 50
435e3dd157SKalle Valo 
44f6dc2095SMichal Kazior 
45f6dc2095SMichal Kazior static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb);
46f6dc2095SMichal Kazior 
47f6dc2095SMichal Kazior 
485e3dd157SKalle Valo static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt)
495e3dd157SKalle Valo {
505e3dd157SKalle Valo 	int size;
515e3dd157SKalle Valo 
525e3dd157SKalle Valo 	/*
535e3dd157SKalle Valo 	 * It is expected that the host CPU will typically be able to
545e3dd157SKalle Valo 	 * service the rx indication from one A-MPDU before the rx
555e3dd157SKalle Valo 	 * indication from the subsequent A-MPDU happens, roughly 1-2 ms
565e3dd157SKalle Valo 	 * later. However, the rx ring should be sized very conservatively,
575e3dd157SKalle Valo 	 * to accomodate the worst reasonable delay before the host CPU
585e3dd157SKalle Valo 	 * services a rx indication interrupt.
595e3dd157SKalle Valo 	 *
605e3dd157SKalle Valo 	 * The rx ring need not be kept full of empty buffers. In theory,
615e3dd157SKalle Valo 	 * the htt host SW can dynamically track the low-water mark in the
625e3dd157SKalle Valo 	 * rx ring, and dynamically adjust the level to which the rx ring
635e3dd157SKalle Valo 	 * is filled with empty buffers, to dynamically meet the desired
645e3dd157SKalle Valo 	 * low-water mark.
655e3dd157SKalle Valo 	 *
665e3dd157SKalle Valo 	 * In contrast, it's difficult to resize the rx ring itself, once
675e3dd157SKalle Valo 	 * it's in use. Thus, the ring itself should be sized very
685e3dd157SKalle Valo 	 * conservatively, while the degree to which the ring is filled
695e3dd157SKalle Valo 	 * with empty buffers should be sized moderately conservatively.
705e3dd157SKalle Valo 	 */
715e3dd157SKalle Valo 
725e3dd157SKalle Valo 	/* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
735e3dd157SKalle Valo 	size =
745e3dd157SKalle Valo 	    htt->max_throughput_mbps +
755e3dd157SKalle Valo 	    1000  /
765e3dd157SKalle Valo 	    (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS;
775e3dd157SKalle Valo 
785e3dd157SKalle Valo 	if (size < HTT_RX_RING_SIZE_MIN)
795e3dd157SKalle Valo 		size = HTT_RX_RING_SIZE_MIN;
805e3dd157SKalle Valo 
815e3dd157SKalle Valo 	if (size > HTT_RX_RING_SIZE_MAX)
825e3dd157SKalle Valo 		size = HTT_RX_RING_SIZE_MAX;
835e3dd157SKalle Valo 
845e3dd157SKalle Valo 	size = roundup_pow_of_two(size);
855e3dd157SKalle Valo 
865e3dd157SKalle Valo 	return size;
875e3dd157SKalle Valo }
885e3dd157SKalle Valo 
895e3dd157SKalle Valo static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt)
905e3dd157SKalle Valo {
915e3dd157SKalle Valo 	int size;
925e3dd157SKalle Valo 
935e3dd157SKalle Valo 	/* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
945e3dd157SKalle Valo 	size =
955e3dd157SKalle Valo 	    htt->max_throughput_mbps *
965e3dd157SKalle Valo 	    1000  /
975e3dd157SKalle Valo 	    (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS;
985e3dd157SKalle Valo 
995e3dd157SKalle Valo 	/*
1005e3dd157SKalle Valo 	 * Make sure the fill level is at least 1 less than the ring size.
1015e3dd157SKalle Valo 	 * Leaving 1 element empty allows the SW to easily distinguish
1025e3dd157SKalle Valo 	 * between a full ring vs. an empty ring.
1035e3dd157SKalle Valo 	 */
1045e3dd157SKalle Valo 	if (size >= htt->rx_ring.size)
1055e3dd157SKalle Valo 		size = htt->rx_ring.size - 1;
1065e3dd157SKalle Valo 
1075e3dd157SKalle Valo 	return size;
1085e3dd157SKalle Valo }
1095e3dd157SKalle Valo 
1105e3dd157SKalle Valo static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt)
1115e3dd157SKalle Valo {
1125e3dd157SKalle Valo 	struct sk_buff *skb;
1135e3dd157SKalle Valo 	struct ath10k_skb_cb *cb;
1145e3dd157SKalle Valo 	int i;
1155e3dd157SKalle Valo 
1165e3dd157SKalle Valo 	for (i = 0; i < htt->rx_ring.fill_cnt; i++) {
1175e3dd157SKalle Valo 		skb = htt->rx_ring.netbufs_ring[i];
1185e3dd157SKalle Valo 		cb = ATH10K_SKB_CB(skb);
1195e3dd157SKalle Valo 		dma_unmap_single(htt->ar->dev, cb->paddr,
1205e3dd157SKalle Valo 				 skb->len + skb_tailroom(skb),
1215e3dd157SKalle Valo 				 DMA_FROM_DEVICE);
1225e3dd157SKalle Valo 		dev_kfree_skb_any(skb);
1235e3dd157SKalle Valo 	}
1245e3dd157SKalle Valo 
1255e3dd157SKalle Valo 	htt->rx_ring.fill_cnt = 0;
1265e3dd157SKalle Valo }
1275e3dd157SKalle Valo 
1285e3dd157SKalle Valo static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
1295e3dd157SKalle Valo {
1305e3dd157SKalle Valo 	struct htt_rx_desc *rx_desc;
1315e3dd157SKalle Valo 	struct sk_buff *skb;
1325e3dd157SKalle Valo 	dma_addr_t paddr;
1335e3dd157SKalle Valo 	int ret = 0, idx;
1345e3dd157SKalle Valo 
1355e3dd157SKalle Valo 	idx = __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr));
1365e3dd157SKalle Valo 	while (num > 0) {
1375e3dd157SKalle Valo 		skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN);
1385e3dd157SKalle Valo 		if (!skb) {
1395e3dd157SKalle Valo 			ret = -ENOMEM;
1405e3dd157SKalle Valo 			goto fail;
1415e3dd157SKalle Valo 		}
1425e3dd157SKalle Valo 
1435e3dd157SKalle Valo 		if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN))
1445e3dd157SKalle Valo 			skb_pull(skb,
1455e3dd157SKalle Valo 				 PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) -
1465e3dd157SKalle Valo 				 skb->data);
1475e3dd157SKalle Valo 
1485e3dd157SKalle Valo 		/* Clear rx_desc attention word before posting to Rx ring */
1495e3dd157SKalle Valo 		rx_desc = (struct htt_rx_desc *)skb->data;
1505e3dd157SKalle Valo 		rx_desc->attention.flags = __cpu_to_le32(0);
1515e3dd157SKalle Valo 
1525e3dd157SKalle Valo 		paddr = dma_map_single(htt->ar->dev, skb->data,
1535e3dd157SKalle Valo 				       skb->len + skb_tailroom(skb),
1545e3dd157SKalle Valo 				       DMA_FROM_DEVICE);
1555e3dd157SKalle Valo 
1565e3dd157SKalle Valo 		if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) {
1575e3dd157SKalle Valo 			dev_kfree_skb_any(skb);
1585e3dd157SKalle Valo 			ret = -ENOMEM;
1595e3dd157SKalle Valo 			goto fail;
1605e3dd157SKalle Valo 		}
1615e3dd157SKalle Valo 
1625e3dd157SKalle Valo 		ATH10K_SKB_CB(skb)->paddr = paddr;
1635e3dd157SKalle Valo 		htt->rx_ring.netbufs_ring[idx] = skb;
1645e3dd157SKalle Valo 		htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr);
1655e3dd157SKalle Valo 		htt->rx_ring.fill_cnt++;
1665e3dd157SKalle Valo 
1675e3dd157SKalle Valo 		num--;
1685e3dd157SKalle Valo 		idx++;
1695e3dd157SKalle Valo 		idx &= htt->rx_ring.size_mask;
1705e3dd157SKalle Valo 	}
1715e3dd157SKalle Valo 
1725e3dd157SKalle Valo fail:
1735e3dd157SKalle Valo 	*(htt->rx_ring.alloc_idx.vaddr) = __cpu_to_le32(idx);
1745e3dd157SKalle Valo 	return ret;
1755e3dd157SKalle Valo }
1765e3dd157SKalle Valo 
1775e3dd157SKalle Valo static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
1785e3dd157SKalle Valo {
1795e3dd157SKalle Valo 	lockdep_assert_held(&htt->rx_ring.lock);
1805e3dd157SKalle Valo 	return __ath10k_htt_rx_ring_fill_n(htt, num);
1815e3dd157SKalle Valo }
1825e3dd157SKalle Valo 
1835e3dd157SKalle Valo static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt)
1845e3dd157SKalle Valo {
1856e712d42SMichal Kazior 	int ret, num_deficit, num_to_fill;
1865e3dd157SKalle Valo 
1876e712d42SMichal Kazior 	/* Refilling the whole RX ring buffer proves to be a bad idea. The
1886e712d42SMichal Kazior 	 * reason is RX may take up significant amount of CPU cycles and starve
1896e712d42SMichal Kazior 	 * other tasks, e.g. TX on an ethernet device while acting as a bridge
1906e712d42SMichal Kazior 	 * with ath10k wlan interface. This ended up with very poor performance
1916e712d42SMichal Kazior 	 * once CPU the host system was overwhelmed with RX on ath10k.
1926e712d42SMichal Kazior 	 *
1936e712d42SMichal Kazior 	 * By limiting the number of refills the replenishing occurs
1946e712d42SMichal Kazior 	 * progressively. This in turns makes use of the fact tasklets are
1956e712d42SMichal Kazior 	 * processed in FIFO order. This means actual RX processing can starve
1966e712d42SMichal Kazior 	 * out refilling. If there's not enough buffers on RX ring FW will not
1976e712d42SMichal Kazior 	 * report RX until it is refilled with enough buffers. This
1986e712d42SMichal Kazior 	 * automatically balances load wrt to CPU power.
1996e712d42SMichal Kazior 	 *
2006e712d42SMichal Kazior 	 * This probably comes at a cost of lower maximum throughput but
2016e712d42SMichal Kazior 	 * improves the avarage and stability. */
2025e3dd157SKalle Valo 	spin_lock_bh(&htt->rx_ring.lock);
2036e712d42SMichal Kazior 	num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt;
2046e712d42SMichal Kazior 	num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit);
2056e712d42SMichal Kazior 	num_deficit -= num_to_fill;
2065e3dd157SKalle Valo 	ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill);
2075e3dd157SKalle Valo 	if (ret == -ENOMEM) {
2085e3dd157SKalle Valo 		/*
2095e3dd157SKalle Valo 		 * Failed to fill it to the desired level -
2105e3dd157SKalle Valo 		 * we'll start a timer and try again next time.
2115e3dd157SKalle Valo 		 * As long as enough buffers are left in the ring for
2125e3dd157SKalle Valo 		 * another A-MPDU rx, no special recovery is needed.
2135e3dd157SKalle Valo 		 */
2145e3dd157SKalle Valo 		mod_timer(&htt->rx_ring.refill_retry_timer, jiffies +
2155e3dd157SKalle Valo 			  msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS));
2166e712d42SMichal Kazior 	} else if (num_deficit > 0) {
2176e712d42SMichal Kazior 		tasklet_schedule(&htt->rx_replenish_task);
2185e3dd157SKalle Valo 	}
2195e3dd157SKalle Valo 	spin_unlock_bh(&htt->rx_ring.lock);
2205e3dd157SKalle Valo }
2215e3dd157SKalle Valo 
2225e3dd157SKalle Valo static void ath10k_htt_rx_ring_refill_retry(unsigned long arg)
2235e3dd157SKalle Valo {
2245e3dd157SKalle Valo 	struct ath10k_htt *htt = (struct ath10k_htt *)arg;
2255e3dd157SKalle Valo 	ath10k_htt_rx_msdu_buff_replenish(htt);
2265e3dd157SKalle Valo }
2275e3dd157SKalle Valo 
2285e3dd157SKalle Valo static unsigned ath10k_htt_rx_ring_elems(struct ath10k_htt *htt)
2295e3dd157SKalle Valo {
2305e3dd157SKalle Valo 	return (__le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr) -
2315e3dd157SKalle Valo 		htt->rx_ring.sw_rd_idx.msdu_payld) & htt->rx_ring.size_mask;
2325e3dd157SKalle Valo }
2335e3dd157SKalle Valo 
2345e3dd157SKalle Valo void ath10k_htt_rx_detach(struct ath10k_htt *htt)
2355e3dd157SKalle Valo {
2365e3dd157SKalle Valo 	int sw_rd_idx = htt->rx_ring.sw_rd_idx.msdu_payld;
2375e3dd157SKalle Valo 
2385e3dd157SKalle Valo 	del_timer_sync(&htt->rx_ring.refill_retry_timer);
2396e712d42SMichal Kazior 	tasklet_kill(&htt->rx_replenish_task);
2405e3dd157SKalle Valo 
2415e3dd157SKalle Valo 	while (sw_rd_idx != __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr))) {
2425e3dd157SKalle Valo 		struct sk_buff *skb =
2435e3dd157SKalle Valo 				htt->rx_ring.netbufs_ring[sw_rd_idx];
2445e3dd157SKalle Valo 		struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb);
2455e3dd157SKalle Valo 
2465e3dd157SKalle Valo 		dma_unmap_single(htt->ar->dev, cb->paddr,
2475e3dd157SKalle Valo 				 skb->len + skb_tailroom(skb),
2485e3dd157SKalle Valo 				 DMA_FROM_DEVICE);
2495e3dd157SKalle Valo 		dev_kfree_skb_any(htt->rx_ring.netbufs_ring[sw_rd_idx]);
2505e3dd157SKalle Valo 		sw_rd_idx++;
2515e3dd157SKalle Valo 		sw_rd_idx &= htt->rx_ring.size_mask;
2525e3dd157SKalle Valo 	}
2535e3dd157SKalle Valo 
2545e3dd157SKalle Valo 	dma_free_coherent(htt->ar->dev,
2555e3dd157SKalle Valo 			  (htt->rx_ring.size *
2565e3dd157SKalle Valo 			   sizeof(htt->rx_ring.paddrs_ring)),
2575e3dd157SKalle Valo 			  htt->rx_ring.paddrs_ring,
2585e3dd157SKalle Valo 			  htt->rx_ring.base_paddr);
2595e3dd157SKalle Valo 
2605e3dd157SKalle Valo 	dma_free_coherent(htt->ar->dev,
2615e3dd157SKalle Valo 			  sizeof(*htt->rx_ring.alloc_idx.vaddr),
2625e3dd157SKalle Valo 			  htt->rx_ring.alloc_idx.vaddr,
2635e3dd157SKalle Valo 			  htt->rx_ring.alloc_idx.paddr);
2645e3dd157SKalle Valo 
2655e3dd157SKalle Valo 	kfree(htt->rx_ring.netbufs_ring);
2665e3dd157SKalle Valo }
2675e3dd157SKalle Valo 
2685e3dd157SKalle Valo static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
2695e3dd157SKalle Valo {
2705e3dd157SKalle Valo 	int idx;
2715e3dd157SKalle Valo 	struct sk_buff *msdu;
2725e3dd157SKalle Valo 
2735e3dd157SKalle Valo 	spin_lock_bh(&htt->rx_ring.lock);
2745e3dd157SKalle Valo 
2755e3dd157SKalle Valo 	if (ath10k_htt_rx_ring_elems(htt) == 0)
2765e3dd157SKalle Valo 		ath10k_warn("htt rx ring is empty!\n");
2775e3dd157SKalle Valo 
2785e3dd157SKalle Valo 	idx = htt->rx_ring.sw_rd_idx.msdu_payld;
2795e3dd157SKalle Valo 	msdu = htt->rx_ring.netbufs_ring[idx];
2805e3dd157SKalle Valo 
2815e3dd157SKalle Valo 	idx++;
2825e3dd157SKalle Valo 	idx &= htt->rx_ring.size_mask;
2835e3dd157SKalle Valo 	htt->rx_ring.sw_rd_idx.msdu_payld = idx;
2845e3dd157SKalle Valo 	htt->rx_ring.fill_cnt--;
2855e3dd157SKalle Valo 
2865e3dd157SKalle Valo 	spin_unlock_bh(&htt->rx_ring.lock);
2875e3dd157SKalle Valo 	return msdu;
2885e3dd157SKalle Valo }
2895e3dd157SKalle Valo 
2905e3dd157SKalle Valo static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb)
2915e3dd157SKalle Valo {
2925e3dd157SKalle Valo 	struct sk_buff *next;
2935e3dd157SKalle Valo 
2945e3dd157SKalle Valo 	while (skb) {
2955e3dd157SKalle Valo 		next = skb->next;
2965e3dd157SKalle Valo 		dev_kfree_skb_any(skb);
2975e3dd157SKalle Valo 		skb = next;
2985e3dd157SKalle Valo 	}
2995e3dd157SKalle Valo }
3005e3dd157SKalle Valo 
3015e3dd157SKalle Valo static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
3025e3dd157SKalle Valo 				   u8 **fw_desc, int *fw_desc_len,
3035e3dd157SKalle Valo 				   struct sk_buff **head_msdu,
3045e3dd157SKalle Valo 				   struct sk_buff **tail_msdu)
3055e3dd157SKalle Valo {
3065e3dd157SKalle Valo 	int msdu_len, msdu_chaining = 0;
3075e3dd157SKalle Valo 	struct sk_buff *msdu;
3085e3dd157SKalle Valo 	struct htt_rx_desc *rx_desc;
3095e3dd157SKalle Valo 
3105e3dd157SKalle Valo 	if (ath10k_htt_rx_ring_elems(htt) == 0)
3115e3dd157SKalle Valo 		ath10k_warn("htt rx ring is empty!\n");
3125e3dd157SKalle Valo 
3135e3dd157SKalle Valo 	if (htt->rx_confused) {
3145e3dd157SKalle Valo 		ath10k_warn("htt is confused. refusing rx\n");
3155e3dd157SKalle Valo 		return 0;
3165e3dd157SKalle Valo 	}
3175e3dd157SKalle Valo 
3185e3dd157SKalle Valo 	msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt);
3195e3dd157SKalle Valo 	while (msdu) {
3205e3dd157SKalle Valo 		int last_msdu, msdu_len_invalid, msdu_chained;
3215e3dd157SKalle Valo 
3225e3dd157SKalle Valo 		dma_unmap_single(htt->ar->dev,
3235e3dd157SKalle Valo 				 ATH10K_SKB_CB(msdu)->paddr,
3245e3dd157SKalle Valo 				 msdu->len + skb_tailroom(msdu),
3255e3dd157SKalle Valo 				 DMA_FROM_DEVICE);
3265e3dd157SKalle Valo 
3275e3dd157SKalle Valo 		ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx: ",
3285e3dd157SKalle Valo 				msdu->data, msdu->len + skb_tailroom(msdu));
3295e3dd157SKalle Valo 
3305e3dd157SKalle Valo 		rx_desc = (struct htt_rx_desc *)msdu->data;
3315e3dd157SKalle Valo 
3325e3dd157SKalle Valo 		/* FIXME: we must report msdu payload since this is what caller
3335e3dd157SKalle Valo 		 *        expects now */
3345e3dd157SKalle Valo 		skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload));
3355e3dd157SKalle Valo 		skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload));
3365e3dd157SKalle Valo 
3375e3dd157SKalle Valo 		/*
3385e3dd157SKalle Valo 		 * Sanity check - confirm the HW is finished filling in the
3395e3dd157SKalle Valo 		 * rx data.
3405e3dd157SKalle Valo 		 * If the HW and SW are working correctly, then it's guaranteed
3415e3dd157SKalle Valo 		 * that the HW's MAC DMA is done before this point in the SW.
3425e3dd157SKalle Valo 		 * To prevent the case that we handle a stale Rx descriptor,
3435e3dd157SKalle Valo 		 * just assert for now until we have a way to recover.
3445e3dd157SKalle Valo 		 */
3455e3dd157SKalle Valo 		if (!(__le32_to_cpu(rx_desc->attention.flags)
3465e3dd157SKalle Valo 				& RX_ATTENTION_FLAGS_MSDU_DONE)) {
3475e3dd157SKalle Valo 			ath10k_htt_rx_free_msdu_chain(*head_msdu);
3485e3dd157SKalle Valo 			*head_msdu = NULL;
3495e3dd157SKalle Valo 			msdu = NULL;
3505e3dd157SKalle Valo 			ath10k_err("htt rx stopped. cannot recover\n");
3515e3dd157SKalle Valo 			htt->rx_confused = true;
3525e3dd157SKalle Valo 			break;
3535e3dd157SKalle Valo 		}
3545e3dd157SKalle Valo 
3555e3dd157SKalle Valo 		/*
3565e3dd157SKalle Valo 		 * Copy the FW rx descriptor for this MSDU from the rx
3575e3dd157SKalle Valo 		 * indication message into the MSDU's netbuf. HL uses the
3585e3dd157SKalle Valo 		 * same rx indication message definition as LL, and simply
3595e3dd157SKalle Valo 		 * appends new info (fields from the HW rx desc, and the
3605e3dd157SKalle Valo 		 * MSDU payload itself). So, the offset into the rx
3615e3dd157SKalle Valo 		 * indication message only has to account for the standard
3625e3dd157SKalle Valo 		 * offset of the per-MSDU FW rx desc info within the
3635e3dd157SKalle Valo 		 * message, and how many bytes of the per-MSDU FW rx desc
3645e3dd157SKalle Valo 		 * info have already been consumed. (And the endianness of
3655e3dd157SKalle Valo 		 * the host, since for a big-endian host, the rx ind
3665e3dd157SKalle Valo 		 * message contents, including the per-MSDU rx desc bytes,
3675e3dd157SKalle Valo 		 * were byteswapped during upload.)
3685e3dd157SKalle Valo 		 */
3695e3dd157SKalle Valo 		if (*fw_desc_len > 0) {
3705e3dd157SKalle Valo 			rx_desc->fw_desc.info0 = **fw_desc;
3715e3dd157SKalle Valo 			/*
3725e3dd157SKalle Valo 			 * The target is expected to only provide the basic
3735e3dd157SKalle Valo 			 * per-MSDU rx descriptors. Just to be sure, verify
3745e3dd157SKalle Valo 			 * that the target has not attached extension data
3755e3dd157SKalle Valo 			 * (e.g. LRO flow ID).
3765e3dd157SKalle Valo 			 */
3775e3dd157SKalle Valo 
3785e3dd157SKalle Valo 			/* or more, if there's extension data */
3795e3dd157SKalle Valo 			(*fw_desc)++;
3805e3dd157SKalle Valo 			(*fw_desc_len)--;
3815e3dd157SKalle Valo 		} else {
3825e3dd157SKalle Valo 			/*
3835e3dd157SKalle Valo 			 * When an oversized AMSDU happened, FW will lost
3845e3dd157SKalle Valo 			 * some of MSDU status - in this case, the FW
3855e3dd157SKalle Valo 			 * descriptors provided will be less than the
3865e3dd157SKalle Valo 			 * actual MSDUs inside this MPDU. Mark the FW
3875e3dd157SKalle Valo 			 * descriptors so that it will still deliver to
3885e3dd157SKalle Valo 			 * upper stack, if no CRC error for this MPDU.
3895e3dd157SKalle Valo 			 *
3905e3dd157SKalle Valo 			 * FIX THIS - the FW descriptors are actually for
3915e3dd157SKalle Valo 			 * MSDUs in the end of this A-MSDU instead of the
3925e3dd157SKalle Valo 			 * beginning.
3935e3dd157SKalle Valo 			 */
3945e3dd157SKalle Valo 			rx_desc->fw_desc.info0 = 0;
3955e3dd157SKalle Valo 		}
3965e3dd157SKalle Valo 
3975e3dd157SKalle Valo 		msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags)
3985e3dd157SKalle Valo 					& (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR |
3995e3dd157SKalle Valo 					   RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR));
4005e3dd157SKalle Valo 		msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0),
4015e3dd157SKalle Valo 			      RX_MSDU_START_INFO0_MSDU_LENGTH);
4025e3dd157SKalle Valo 		msdu_chained = rx_desc->frag_info.ring2_more_count;
4035e3dd157SKalle Valo 
4045e3dd157SKalle Valo 		if (msdu_len_invalid)
4055e3dd157SKalle Valo 			msdu_len = 0;
4065e3dd157SKalle Valo 
4075e3dd157SKalle Valo 		skb_trim(msdu, 0);
4085e3dd157SKalle Valo 		skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE));
4095e3dd157SKalle Valo 		msdu_len -= msdu->len;
4105e3dd157SKalle Valo 
4115e3dd157SKalle Valo 		/* FIXME: Do chained buffers include htt_rx_desc or not? */
4125e3dd157SKalle Valo 		while (msdu_chained--) {
4135e3dd157SKalle Valo 			struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt);
4145e3dd157SKalle Valo 
4155e3dd157SKalle Valo 			dma_unmap_single(htt->ar->dev,
4165e3dd157SKalle Valo 					 ATH10K_SKB_CB(next)->paddr,
4175e3dd157SKalle Valo 					 next->len + skb_tailroom(next),
4185e3dd157SKalle Valo 					 DMA_FROM_DEVICE);
4195e3dd157SKalle Valo 
4205e3dd157SKalle Valo 			ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx: ",
4215e3dd157SKalle Valo 					next->data,
4225e3dd157SKalle Valo 					next->len + skb_tailroom(next));
4235e3dd157SKalle Valo 
4245e3dd157SKalle Valo 			skb_trim(next, 0);
4255e3dd157SKalle Valo 			skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE));
4265e3dd157SKalle Valo 			msdu_len -= next->len;
4275e3dd157SKalle Valo 
4285e3dd157SKalle Valo 			msdu->next = next;
4295e3dd157SKalle Valo 			msdu = next;
4305e3dd157SKalle Valo 			msdu_chaining = 1;
4315e3dd157SKalle Valo 		}
4325e3dd157SKalle Valo 
4335e3dd157SKalle Valo 		if (msdu_len > 0) {
4345e3dd157SKalle Valo 			/* This may suggest FW bug? */
4355e3dd157SKalle Valo 			ath10k_warn("htt rx msdu len not consumed (%d)\n",
4365e3dd157SKalle Valo 				    msdu_len);
4375e3dd157SKalle Valo 		}
4385e3dd157SKalle Valo 
4395e3dd157SKalle Valo 		last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) &
4405e3dd157SKalle Valo 				RX_MSDU_END_INFO0_LAST_MSDU;
4415e3dd157SKalle Valo 
4425e3dd157SKalle Valo 		if (last_msdu) {
4435e3dd157SKalle Valo 			msdu->next = NULL;
4445e3dd157SKalle Valo 			break;
4455e3dd157SKalle Valo 		} else {
4465e3dd157SKalle Valo 			struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt);
4475e3dd157SKalle Valo 			msdu->next = next;
4485e3dd157SKalle Valo 			msdu = next;
4495e3dd157SKalle Valo 		}
4505e3dd157SKalle Valo 	}
4515e3dd157SKalle Valo 	*tail_msdu = msdu;
4525e3dd157SKalle Valo 
4535e3dd157SKalle Valo 	/*
4545e3dd157SKalle Valo 	 * Don't refill the ring yet.
4555e3dd157SKalle Valo 	 *
4565e3dd157SKalle Valo 	 * First, the elements popped here are still in use - it is not
4575e3dd157SKalle Valo 	 * safe to overwrite them until the matching call to
4585e3dd157SKalle Valo 	 * mpdu_desc_list_next. Second, for efficiency it is preferable to
4595e3dd157SKalle Valo 	 * refill the rx ring with 1 PPDU's worth of rx buffers (something
4605e3dd157SKalle Valo 	 * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers
4615e3dd157SKalle Valo 	 * (something like 3 buffers). Consequently, we'll rely on the txrx
4625e3dd157SKalle Valo 	 * SW to tell us when it is done pulling all the PPDU's rx buffers
4635e3dd157SKalle Valo 	 * out of the rx ring, and then refill it just once.
4645e3dd157SKalle Valo 	 */
4655e3dd157SKalle Valo 
4665e3dd157SKalle Valo 	return msdu_chaining;
4675e3dd157SKalle Valo }
4685e3dd157SKalle Valo 
4696e712d42SMichal Kazior static void ath10k_htt_rx_replenish_task(unsigned long ptr)
4706e712d42SMichal Kazior {
4716e712d42SMichal Kazior 	struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
4726e712d42SMichal Kazior 	ath10k_htt_rx_msdu_buff_replenish(htt);
4736e712d42SMichal Kazior }
4746e712d42SMichal Kazior 
4755e3dd157SKalle Valo int ath10k_htt_rx_attach(struct ath10k_htt *htt)
4765e3dd157SKalle Valo {
4775e3dd157SKalle Valo 	dma_addr_t paddr;
4785e3dd157SKalle Valo 	void *vaddr;
4795e3dd157SKalle Valo 	struct timer_list *timer = &htt->rx_ring.refill_retry_timer;
4805e3dd157SKalle Valo 
4815e3dd157SKalle Valo 	htt->rx_ring.size = ath10k_htt_rx_ring_size(htt);
4825e3dd157SKalle Valo 	if (!is_power_of_2(htt->rx_ring.size)) {
4835e3dd157SKalle Valo 		ath10k_warn("htt rx ring size is not power of 2\n");
4845e3dd157SKalle Valo 		return -EINVAL;
4855e3dd157SKalle Valo 	}
4865e3dd157SKalle Valo 
4875e3dd157SKalle Valo 	htt->rx_ring.size_mask = htt->rx_ring.size - 1;
4885e3dd157SKalle Valo 
4895e3dd157SKalle Valo 	/*
4905e3dd157SKalle Valo 	 * Set the initial value for the level to which the rx ring
4915e3dd157SKalle Valo 	 * should be filled, based on the max throughput and the
4925e3dd157SKalle Valo 	 * worst likely latency for the host to fill the rx ring
4935e3dd157SKalle Valo 	 * with new buffers. In theory, this fill level can be
4945e3dd157SKalle Valo 	 * dynamically adjusted from the initial value set here, to
4955e3dd157SKalle Valo 	 * reflect the actual host latency rather than a
4965e3dd157SKalle Valo 	 * conservative assumption about the host latency.
4975e3dd157SKalle Valo 	 */
4985e3dd157SKalle Valo 	htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt);
4995e3dd157SKalle Valo 
5005e3dd157SKalle Valo 	htt->rx_ring.netbufs_ring =
5015e3dd157SKalle Valo 		kmalloc(htt->rx_ring.size * sizeof(struct sk_buff *),
5025e3dd157SKalle Valo 			GFP_KERNEL);
5035e3dd157SKalle Valo 	if (!htt->rx_ring.netbufs_ring)
5045e3dd157SKalle Valo 		goto err_netbuf;
5055e3dd157SKalle Valo 
5065e3dd157SKalle Valo 	vaddr = dma_alloc_coherent(htt->ar->dev,
5075e3dd157SKalle Valo 		   (htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring)),
5085e3dd157SKalle Valo 		   &paddr, GFP_DMA);
5095e3dd157SKalle Valo 	if (!vaddr)
5105e3dd157SKalle Valo 		goto err_dma_ring;
5115e3dd157SKalle Valo 
5125e3dd157SKalle Valo 	htt->rx_ring.paddrs_ring = vaddr;
5135e3dd157SKalle Valo 	htt->rx_ring.base_paddr = paddr;
5145e3dd157SKalle Valo 
5155e3dd157SKalle Valo 	vaddr = dma_alloc_coherent(htt->ar->dev,
5165e3dd157SKalle Valo 				   sizeof(*htt->rx_ring.alloc_idx.vaddr),
5175e3dd157SKalle Valo 				   &paddr, GFP_DMA);
5185e3dd157SKalle Valo 	if (!vaddr)
5195e3dd157SKalle Valo 		goto err_dma_idx;
5205e3dd157SKalle Valo 
5215e3dd157SKalle Valo 	htt->rx_ring.alloc_idx.vaddr = vaddr;
5225e3dd157SKalle Valo 	htt->rx_ring.alloc_idx.paddr = paddr;
5235e3dd157SKalle Valo 	htt->rx_ring.sw_rd_idx.msdu_payld = 0;
5245e3dd157SKalle Valo 	*htt->rx_ring.alloc_idx.vaddr = 0;
5255e3dd157SKalle Valo 
5265e3dd157SKalle Valo 	/* Initialize the Rx refill retry timer */
5275e3dd157SKalle Valo 	setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt);
5285e3dd157SKalle Valo 
5295e3dd157SKalle Valo 	spin_lock_init(&htt->rx_ring.lock);
5305e3dd157SKalle Valo 
5315e3dd157SKalle Valo 	htt->rx_ring.fill_cnt = 0;
5325e3dd157SKalle Valo 	if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level))
5335e3dd157SKalle Valo 		goto err_fill_ring;
5345e3dd157SKalle Valo 
5356e712d42SMichal Kazior 	tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task,
5366e712d42SMichal Kazior 		     (unsigned long)htt);
5376e712d42SMichal Kazior 
538aad0b65fSKalle Valo 	ath10k_dbg(ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n",
5395e3dd157SKalle Valo 		   htt->rx_ring.size, htt->rx_ring.fill_level);
5405e3dd157SKalle Valo 	return 0;
5415e3dd157SKalle Valo 
5425e3dd157SKalle Valo err_fill_ring:
5435e3dd157SKalle Valo 	ath10k_htt_rx_ring_free(htt);
5445e3dd157SKalle Valo 	dma_free_coherent(htt->ar->dev,
5455e3dd157SKalle Valo 			  sizeof(*htt->rx_ring.alloc_idx.vaddr),
5465e3dd157SKalle Valo 			  htt->rx_ring.alloc_idx.vaddr,
5475e3dd157SKalle Valo 			  htt->rx_ring.alloc_idx.paddr);
5485e3dd157SKalle Valo err_dma_idx:
5495e3dd157SKalle Valo 	dma_free_coherent(htt->ar->dev,
5505e3dd157SKalle Valo 			  (htt->rx_ring.size *
5515e3dd157SKalle Valo 			   sizeof(htt->rx_ring.paddrs_ring)),
5525e3dd157SKalle Valo 			  htt->rx_ring.paddrs_ring,
5535e3dd157SKalle Valo 			  htt->rx_ring.base_paddr);
5545e3dd157SKalle Valo err_dma_ring:
5555e3dd157SKalle Valo 	kfree(htt->rx_ring.netbufs_ring);
5565e3dd157SKalle Valo err_netbuf:
5575e3dd157SKalle Valo 	return -ENOMEM;
5585e3dd157SKalle Valo }
5595e3dd157SKalle Valo 
5605e3dd157SKalle Valo static int ath10k_htt_rx_crypto_param_len(enum htt_rx_mpdu_encrypt_type type)
5615e3dd157SKalle Valo {
5625e3dd157SKalle Valo 	switch (type) {
5635e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_WEP40:
5645e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_WEP104:
5655e3dd157SKalle Valo 		return 4;
5665e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
5675e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_WEP128: /* not tested */
5685e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
5695e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_WAPI: /* not tested */
5705e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
5715e3dd157SKalle Valo 		return 8;
5725e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_NONE:
5735e3dd157SKalle Valo 		return 0;
5745e3dd157SKalle Valo 	}
5755e3dd157SKalle Valo 
5765e3dd157SKalle Valo 	ath10k_warn("unknown encryption type %d\n", type);
5775e3dd157SKalle Valo 	return 0;
5785e3dd157SKalle Valo }
5795e3dd157SKalle Valo 
5805e3dd157SKalle Valo static int ath10k_htt_rx_crypto_tail_len(enum htt_rx_mpdu_encrypt_type type)
5815e3dd157SKalle Valo {
5825e3dd157SKalle Valo 	switch (type) {
5835e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_NONE:
5845e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_WEP40:
5855e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_WEP104:
5865e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_WEP128:
5875e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_WAPI:
5885e3dd157SKalle Valo 		return 0;
5895e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
5905e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
5915e3dd157SKalle Valo 		return 4;
5925e3dd157SKalle Valo 	case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
5935e3dd157SKalle Valo 		return 8;
5945e3dd157SKalle Valo 	}
5955e3dd157SKalle Valo 
5965e3dd157SKalle Valo 	ath10k_warn("unknown encryption type %d\n", type);
5975e3dd157SKalle Valo 	return 0;
5985e3dd157SKalle Valo }
5995e3dd157SKalle Valo 
6005e3dd157SKalle Valo /* Applies for first msdu in chain, before altering it. */
6015e3dd157SKalle Valo static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb)
6025e3dd157SKalle Valo {
6035e3dd157SKalle Valo 	struct htt_rx_desc *rxd;
6045e3dd157SKalle Valo 	enum rx_msdu_decap_format fmt;
6055e3dd157SKalle Valo 
6065e3dd157SKalle Valo 	rxd = (void *)skb->data - sizeof(*rxd);
6075e3dd157SKalle Valo 	fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
6085e3dd157SKalle Valo 			RX_MSDU_START_INFO1_DECAP_FORMAT);
6095e3dd157SKalle Valo 
6105e3dd157SKalle Valo 	if (fmt == RX_MSDU_DECAP_RAW)
6115e3dd157SKalle Valo 		return (void *)skb->data;
6125e3dd157SKalle Valo 	else
6135e3dd157SKalle Valo 		return (void *)skb->data - RX_HTT_HDR_STATUS_LEN;
6145e3dd157SKalle Valo }
6155e3dd157SKalle Valo 
6165e3dd157SKalle Valo /* This function only applies for first msdu in an msdu chain */
6175e3dd157SKalle Valo static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr)
6185e3dd157SKalle Valo {
6195e3dd157SKalle Valo 	if (ieee80211_is_data_qos(hdr->frame_control)) {
6205e3dd157SKalle Valo 		u8 *qc = ieee80211_get_qos_ctl(hdr);
6215e3dd157SKalle Valo 		if (qc[0] & 0x80)
6225e3dd157SKalle Valo 			return true;
6235e3dd157SKalle Valo 	}
6245e3dd157SKalle Valo 	return false;
6255e3dd157SKalle Valo }
6265e3dd157SKalle Valo 
627f6dc2095SMichal Kazior struct rfc1042_hdr {
628f6dc2095SMichal Kazior 	u8 llc_dsap;
629f6dc2095SMichal Kazior 	u8 llc_ssap;
630f6dc2095SMichal Kazior 	u8 llc_ctrl;
631f6dc2095SMichal Kazior 	u8 snap_oui[3];
632f6dc2095SMichal Kazior 	__be16 snap_type;
633f6dc2095SMichal Kazior } __packed;
634f6dc2095SMichal Kazior 
635f6dc2095SMichal Kazior struct amsdu_subframe_hdr {
636f6dc2095SMichal Kazior 	u8 dst[ETH_ALEN];
637f6dc2095SMichal Kazior 	u8 src[ETH_ALEN];
638f6dc2095SMichal Kazior 	__be16 len;
639f6dc2095SMichal Kazior } __packed;
640f6dc2095SMichal Kazior 
641f6dc2095SMichal Kazior static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
6425e3dd157SKalle Valo 				struct htt_rx_info *info)
6435e3dd157SKalle Valo {
6445e3dd157SKalle Valo 	struct htt_rx_desc *rxd;
6455e3dd157SKalle Valo 	struct sk_buff *first;
6465e3dd157SKalle Valo 	struct sk_buff *skb = info->skb;
6475e3dd157SKalle Valo 	enum rx_msdu_decap_format fmt;
6485e3dd157SKalle Valo 	enum htt_rx_mpdu_encrypt_type enctype;
649f6dc2095SMichal Kazior 	struct ieee80211_hdr *hdr;
650784f69d3SMichal Kazior 	u8 hdr_buf[64], addr[ETH_ALEN], *qos;
6515e3dd157SKalle Valo 	unsigned int hdr_len;
6525e3dd157SKalle Valo 
6535e3dd157SKalle Valo 	rxd = (void *)skb->data - sizeof(*rxd);
6545e3dd157SKalle Valo 	enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
6555e3dd157SKalle Valo 			RX_MPDU_START_INFO0_ENCRYPT_TYPE);
6565e3dd157SKalle Valo 
657f6dc2095SMichal Kazior 	hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
658f6dc2095SMichal Kazior 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
659f6dc2095SMichal Kazior 	memcpy(hdr_buf, hdr, hdr_len);
660f6dc2095SMichal Kazior 	hdr = (struct ieee80211_hdr *)hdr_buf;
6615e3dd157SKalle Valo 
6625e3dd157SKalle Valo 	first = skb;
6635e3dd157SKalle Valo 	while (skb) {
6645e3dd157SKalle Valo 		void *decap_hdr;
665f6dc2095SMichal Kazior 		int len;
6665e3dd157SKalle Valo 
6675e3dd157SKalle Valo 		rxd = (void *)skb->data - sizeof(*rxd);
6685e3dd157SKalle Valo 		fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
6695e3dd157SKalle Valo 			 RX_MSDU_START_INFO1_DECAP_FORMAT);
6705e3dd157SKalle Valo 		decap_hdr = (void *)rxd->rx_hdr_status;
6715e3dd157SKalle Valo 
672f6dc2095SMichal Kazior 		skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
673f6dc2095SMichal Kazior 
674f6dc2095SMichal Kazior 		/* First frame in an A-MSDU chain has more decapped data. */
6755e3dd157SKalle Valo 		if (skb == first) {
676f6dc2095SMichal Kazior 			len = round_up(ieee80211_hdrlen(hdr->frame_control), 4);
677f6dc2095SMichal Kazior 			len += round_up(ath10k_htt_rx_crypto_param_len(enctype),
678f6dc2095SMichal Kazior 					4);
679f6dc2095SMichal Kazior 			decap_hdr += len;
6805e3dd157SKalle Valo 		}
6815e3dd157SKalle Valo 
682f6dc2095SMichal Kazior 		switch (fmt) {
683f6dc2095SMichal Kazior 		case RX_MSDU_DECAP_RAW:
684e3fbf8d2SMichal Kazior 			/* remove trailing FCS */
685f6dc2095SMichal Kazior 			skb_trim(skb, skb->len - FCS_LEN);
686f6dc2095SMichal Kazior 			break;
687f6dc2095SMichal Kazior 		case RX_MSDU_DECAP_NATIVE_WIFI:
688784f69d3SMichal Kazior 			/* pull decapped header and copy DA */
689784f69d3SMichal Kazior 			hdr = (struct ieee80211_hdr *)skb->data;
690784f69d3SMichal Kazior 			hdr_len = ieee80211_hdrlen(hdr->frame_control);
691784f69d3SMichal Kazior 			memcpy(addr, ieee80211_get_DA(hdr), ETH_ALEN);
692784f69d3SMichal Kazior 			skb_pull(skb, hdr_len);
693784f69d3SMichal Kazior 
694784f69d3SMichal Kazior 			/* push original 802.11 header */
695784f69d3SMichal Kazior 			hdr = (struct ieee80211_hdr *)hdr_buf;
696784f69d3SMichal Kazior 			hdr_len = ieee80211_hdrlen(hdr->frame_control);
697784f69d3SMichal Kazior 			memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
698784f69d3SMichal Kazior 
699784f69d3SMichal Kazior 			/* original A-MSDU header has the bit set but we're
700784f69d3SMichal Kazior 			 * not including A-MSDU subframe header */
701784f69d3SMichal Kazior 			hdr = (struct ieee80211_hdr *)skb->data;
702784f69d3SMichal Kazior 			qos = ieee80211_get_qos_ctl(hdr);
703784f69d3SMichal Kazior 			qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
704784f69d3SMichal Kazior 
705784f69d3SMichal Kazior 			/* original 802.11 header has a different DA */
706784f69d3SMichal Kazior 			memcpy(ieee80211_get_DA(hdr), addr, ETH_ALEN);
707f6dc2095SMichal Kazior 			break;
708f6dc2095SMichal Kazior 		case RX_MSDU_DECAP_ETHERNET2_DIX:
709e3fbf8d2SMichal Kazior 			/* strip ethernet header and insert decapped 802.11
710e3fbf8d2SMichal Kazior 			 * header, amsdu subframe header and rfc1042 header */
711e3fbf8d2SMichal Kazior 
712f6dc2095SMichal Kazior 			len = 0;
713f6dc2095SMichal Kazior 			len += sizeof(struct rfc1042_hdr);
714f6dc2095SMichal Kazior 			len += sizeof(struct amsdu_subframe_hdr);
715dfa95b50SMichal Kazior 
716f6dc2095SMichal Kazior 			skb_pull(skb, sizeof(struct ethhdr));
717f6dc2095SMichal Kazior 			memcpy(skb_push(skb, len), decap_hdr, len);
718f6dc2095SMichal Kazior 			memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
719f6dc2095SMichal Kazior 			break;
720f6dc2095SMichal Kazior 		case RX_MSDU_DECAP_8023_SNAP_LLC:
721e3fbf8d2SMichal Kazior 			/* insert decapped 802.11 header making a singly
722e3fbf8d2SMichal Kazior 			 * A-MSDU */
723f6dc2095SMichal Kazior 			memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
724f6dc2095SMichal Kazior 			break;
7255e3dd157SKalle Valo 		}
7265e3dd157SKalle Valo 
727f6dc2095SMichal Kazior 		info->skb = skb;
7285e3dd157SKalle Valo 		info->encrypt_type = enctype;
729f6dc2095SMichal Kazior 		skb = skb->next;
730f6dc2095SMichal Kazior 		info->skb->next = NULL;
7315e3dd157SKalle Valo 
732652de35eSKalle Valo 		if (skb)
733652de35eSKalle Valo 			info->amsdu_more = true;
734652de35eSKalle Valo 
735f6dc2095SMichal Kazior 		ath10k_process_rx(htt->ar, info);
7365e3dd157SKalle Valo 	}
7375e3dd157SKalle Valo 
738f6dc2095SMichal Kazior 	/* FIXME: It might be nice to re-assemble the A-MSDU when there's a
739f6dc2095SMichal Kazior 	 * monitor interface active for sniffing purposes. */
740f6dc2095SMichal Kazior }
741f6dc2095SMichal Kazior 
742f6dc2095SMichal Kazior static void ath10k_htt_rx_msdu(struct ath10k_htt *htt, struct htt_rx_info *info)
7435e3dd157SKalle Valo {
7445e3dd157SKalle Valo 	struct sk_buff *skb = info->skb;
7455e3dd157SKalle Valo 	struct htt_rx_desc *rxd;
7465e3dd157SKalle Valo 	struct ieee80211_hdr *hdr;
7475e3dd157SKalle Valo 	enum rx_msdu_decap_format fmt;
7485e3dd157SKalle Valo 	enum htt_rx_mpdu_encrypt_type enctype;
749e3fbf8d2SMichal Kazior 	int hdr_len;
750e3fbf8d2SMichal Kazior 	void *rfc1042;
7515e3dd157SKalle Valo 
7525e3dd157SKalle Valo 	/* This shouldn't happen. If it does than it may be a FW bug. */
7535e3dd157SKalle Valo 	if (skb->next) {
7545e3dd157SKalle Valo 		ath10k_warn("received chained non A-MSDU frame\n");
7555e3dd157SKalle Valo 		ath10k_htt_rx_free_msdu_chain(skb->next);
7565e3dd157SKalle Valo 		skb->next = NULL;
7575e3dd157SKalle Valo 	}
7585e3dd157SKalle Valo 
7595e3dd157SKalle Valo 	rxd = (void *)skb->data - sizeof(*rxd);
7605e3dd157SKalle Valo 	fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
7615e3dd157SKalle Valo 			RX_MSDU_START_INFO1_DECAP_FORMAT);
7625e3dd157SKalle Valo 	enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
7635e3dd157SKalle Valo 			RX_MPDU_START_INFO0_ENCRYPT_TYPE);
764e3fbf8d2SMichal Kazior 	hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
765e3fbf8d2SMichal Kazior 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
7665e3dd157SKalle Valo 
767f6dc2095SMichal Kazior 	skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
768f6dc2095SMichal Kazior 
7695e3dd157SKalle Valo 	switch (fmt) {
7705e3dd157SKalle Valo 	case RX_MSDU_DECAP_RAW:
7715e3dd157SKalle Valo 		/* remove trailing FCS */
772e3fbf8d2SMichal Kazior 		skb_trim(skb, skb->len - FCS_LEN);
7735e3dd157SKalle Valo 		break;
7745e3dd157SKalle Valo 	case RX_MSDU_DECAP_NATIVE_WIFI:
775784f69d3SMichal Kazior 		/* Pull decapped header */
776784f69d3SMichal Kazior 		hdr = (struct ieee80211_hdr *)skb->data;
777784f69d3SMichal Kazior 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
778784f69d3SMichal Kazior 		skb_pull(skb, hdr_len);
779784f69d3SMichal Kazior 
780784f69d3SMichal Kazior 		/* Push original header */
781784f69d3SMichal Kazior 		hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
782784f69d3SMichal Kazior 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
783784f69d3SMichal Kazior 		memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
7845e3dd157SKalle Valo 		break;
7855e3dd157SKalle Valo 	case RX_MSDU_DECAP_ETHERNET2_DIX:
786e3fbf8d2SMichal Kazior 		/* strip ethernet header and insert decapped 802.11 header and
787e3fbf8d2SMichal Kazior 		 * rfc1042 header */
788e3fbf8d2SMichal Kazior 
789e3fbf8d2SMichal Kazior 		rfc1042 = hdr;
790e3fbf8d2SMichal Kazior 		rfc1042 += roundup(hdr_len, 4);
791e3fbf8d2SMichal Kazior 		rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(enctype), 4);
792e3fbf8d2SMichal Kazior 
793e3fbf8d2SMichal Kazior 		skb_pull(skb, sizeof(struct ethhdr));
794e3fbf8d2SMichal Kazior 		memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)),
795e3fbf8d2SMichal Kazior 		       rfc1042, sizeof(struct rfc1042_hdr));
796e3fbf8d2SMichal Kazior 		memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
7975e3dd157SKalle Valo 		break;
7985e3dd157SKalle Valo 	case RX_MSDU_DECAP_8023_SNAP_LLC:
799e3fbf8d2SMichal Kazior 		/* remove A-MSDU subframe header and insert
800e3fbf8d2SMichal Kazior 		 * decapped 802.11 header. rfc1042 header is already there */
801e3fbf8d2SMichal Kazior 
802e3fbf8d2SMichal Kazior 		skb_pull(skb, sizeof(struct amsdu_subframe_hdr));
803e3fbf8d2SMichal Kazior 		memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
8045e3dd157SKalle Valo 		break;
8055e3dd157SKalle Valo 	}
8065e3dd157SKalle Valo 
8075e3dd157SKalle Valo 	info->skb = skb;
8085e3dd157SKalle Valo 	info->encrypt_type = enctype;
809f6dc2095SMichal Kazior 
810f6dc2095SMichal Kazior 	ath10k_process_rx(htt->ar, info);
8115e3dd157SKalle Valo }
8125e3dd157SKalle Valo 
8135e3dd157SKalle Valo static bool ath10k_htt_rx_has_decrypt_err(struct sk_buff *skb)
8145e3dd157SKalle Valo {
8155e3dd157SKalle Valo 	struct htt_rx_desc *rxd;
8165e3dd157SKalle Valo 	u32 flags;
8175e3dd157SKalle Valo 
8185e3dd157SKalle Valo 	rxd = (void *)skb->data - sizeof(*rxd);
8195e3dd157SKalle Valo 	flags = __le32_to_cpu(rxd->attention.flags);
8205e3dd157SKalle Valo 
8215e3dd157SKalle Valo 	if (flags & RX_ATTENTION_FLAGS_DECRYPT_ERR)
8225e3dd157SKalle Valo 		return true;
8235e3dd157SKalle Valo 
8245e3dd157SKalle Valo 	return false;
8255e3dd157SKalle Valo }
8265e3dd157SKalle Valo 
8275e3dd157SKalle Valo static bool ath10k_htt_rx_has_fcs_err(struct sk_buff *skb)
8285e3dd157SKalle Valo {
8295e3dd157SKalle Valo 	struct htt_rx_desc *rxd;
8305e3dd157SKalle Valo 	u32 flags;
8315e3dd157SKalle Valo 
8325e3dd157SKalle Valo 	rxd = (void *)skb->data - sizeof(*rxd);
8335e3dd157SKalle Valo 	flags = __le32_to_cpu(rxd->attention.flags);
8345e3dd157SKalle Valo 
8355e3dd157SKalle Valo 	if (flags & RX_ATTENTION_FLAGS_FCS_ERR)
8365e3dd157SKalle Valo 		return true;
8375e3dd157SKalle Valo 
8385e3dd157SKalle Valo 	return false;
8395e3dd157SKalle Valo }
8405e3dd157SKalle Valo 
841605f81aaSMichal Kazior static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb)
842605f81aaSMichal Kazior {
843605f81aaSMichal Kazior 	struct htt_rx_desc *rxd;
844605f81aaSMichal Kazior 	u32 flags, info;
845605f81aaSMichal Kazior 	bool is_ip4, is_ip6;
846605f81aaSMichal Kazior 	bool is_tcp, is_udp;
847605f81aaSMichal Kazior 	bool ip_csum_ok, tcpudp_csum_ok;
848605f81aaSMichal Kazior 
849605f81aaSMichal Kazior 	rxd = (void *)skb->data - sizeof(*rxd);
850605f81aaSMichal Kazior 	flags = __le32_to_cpu(rxd->attention.flags);
851605f81aaSMichal Kazior 	info = __le32_to_cpu(rxd->msdu_start.info1);
852605f81aaSMichal Kazior 
853605f81aaSMichal Kazior 	is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO);
854605f81aaSMichal Kazior 	is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO);
855605f81aaSMichal Kazior 	is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO);
856605f81aaSMichal Kazior 	is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO);
857605f81aaSMichal Kazior 	ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL);
858605f81aaSMichal Kazior 	tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL);
859605f81aaSMichal Kazior 
860605f81aaSMichal Kazior 	if (!is_ip4 && !is_ip6)
861605f81aaSMichal Kazior 		return CHECKSUM_NONE;
862605f81aaSMichal Kazior 	if (!is_tcp && !is_udp)
863605f81aaSMichal Kazior 		return CHECKSUM_NONE;
864605f81aaSMichal Kazior 	if (!ip_csum_ok)
865605f81aaSMichal Kazior 		return CHECKSUM_NONE;
866605f81aaSMichal Kazior 	if (!tcpudp_csum_ok)
867605f81aaSMichal Kazior 		return CHECKSUM_NONE;
868605f81aaSMichal Kazior 
869605f81aaSMichal Kazior 	return CHECKSUM_UNNECESSARY;
870605f81aaSMichal Kazior }
871605f81aaSMichal Kazior 
8725e3dd157SKalle Valo static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
8735e3dd157SKalle Valo 				  struct htt_rx_indication *rx)
8745e3dd157SKalle Valo {
8755e3dd157SKalle Valo 	struct htt_rx_info info;
8765e3dd157SKalle Valo 	struct htt_rx_indication_mpdu_range *mpdu_ranges;
8775e3dd157SKalle Valo 	struct ieee80211_hdr *hdr;
8785e3dd157SKalle Valo 	int num_mpdu_ranges;
8795e3dd157SKalle Valo 	int fw_desc_len;
8805e3dd157SKalle Valo 	u8 *fw_desc;
8815e3dd157SKalle Valo 	int i, j;
8825e3dd157SKalle Valo 
8835e3dd157SKalle Valo 	memset(&info, 0, sizeof(info));
8845e3dd157SKalle Valo 
8855e3dd157SKalle Valo 	fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes);
8865e3dd157SKalle Valo 	fw_desc = (u8 *)&rx->fw_desc;
8875e3dd157SKalle Valo 
8885e3dd157SKalle Valo 	num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1),
8895e3dd157SKalle Valo 			     HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES);
8905e3dd157SKalle Valo 	mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx);
8915e3dd157SKalle Valo 
8925e3dd157SKalle Valo 	ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ",
8935e3dd157SKalle Valo 			rx, sizeof(*rx) +
8945e3dd157SKalle Valo 			(sizeof(struct htt_rx_indication_mpdu_range) *
8955e3dd157SKalle Valo 				num_mpdu_ranges));
8965e3dd157SKalle Valo 
8975e3dd157SKalle Valo 	for (i = 0; i < num_mpdu_ranges; i++) {
8985e3dd157SKalle Valo 		info.status = mpdu_ranges[i].mpdu_range_status;
8995e3dd157SKalle Valo 
9005e3dd157SKalle Valo 		for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) {
9015e3dd157SKalle Valo 			struct sk_buff *msdu_head, *msdu_tail;
9025e3dd157SKalle Valo 			enum htt_rx_mpdu_status status;
9035e3dd157SKalle Valo 			int msdu_chaining;
9045e3dd157SKalle Valo 
9055e3dd157SKalle Valo 			msdu_head = NULL;
9065e3dd157SKalle Valo 			msdu_tail = NULL;
9075e3dd157SKalle Valo 			msdu_chaining = ath10k_htt_rx_amsdu_pop(htt,
9085e3dd157SKalle Valo 							 &fw_desc,
9095e3dd157SKalle Valo 							 &fw_desc_len,
9105e3dd157SKalle Valo 							 &msdu_head,
9115e3dd157SKalle Valo 							 &msdu_tail);
9125e3dd157SKalle Valo 
9135e3dd157SKalle Valo 			if (!msdu_head) {
9145e3dd157SKalle Valo 				ath10k_warn("htt rx no data!\n");
9155e3dd157SKalle Valo 				continue;
9165e3dd157SKalle Valo 			}
9175e3dd157SKalle Valo 
9185e3dd157SKalle Valo 			if (msdu_head->len == 0) {
9195e3dd157SKalle Valo 				ath10k_dbg(ATH10K_DBG_HTT,
9205e3dd157SKalle Valo 					   "htt rx dropping due to zero-len\n");
9215e3dd157SKalle Valo 				ath10k_htt_rx_free_msdu_chain(msdu_head);
9225e3dd157SKalle Valo 				continue;
9235e3dd157SKalle Valo 			}
9245e3dd157SKalle Valo 
9255e3dd157SKalle Valo 			if (ath10k_htt_rx_has_decrypt_err(msdu_head)) {
9265e3dd157SKalle Valo 				ath10k_htt_rx_free_msdu_chain(msdu_head);
9275e3dd157SKalle Valo 				continue;
9285e3dd157SKalle Valo 			}
9295e3dd157SKalle Valo 
9305e3dd157SKalle Valo 			status = info.status;
9315e3dd157SKalle Valo 
9325e3dd157SKalle Valo 			/* Skip mgmt frames while we handle this in WMI */
9335e3dd157SKalle Valo 			if (status == HTT_RX_IND_MPDU_STATUS_MGMT_CTRL) {
9345e3dd157SKalle Valo 				ath10k_htt_rx_free_msdu_chain(msdu_head);
9355e3dd157SKalle Valo 				continue;
9365e3dd157SKalle Valo 			}
9375e3dd157SKalle Valo 
9385e3dd157SKalle Valo 			if (status != HTT_RX_IND_MPDU_STATUS_OK &&
9395e3dd157SKalle Valo 			    status != HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR &&
9405e3dd157SKalle Valo 			    !htt->ar->monitor_enabled) {
9415e3dd157SKalle Valo 				ath10k_dbg(ATH10K_DBG_HTT,
9425e3dd157SKalle Valo 					   "htt rx ignoring frame w/ status %d\n",
9435e3dd157SKalle Valo 					   status);
9445e3dd157SKalle Valo 				ath10k_htt_rx_free_msdu_chain(msdu_head);
9455e3dd157SKalle Valo 				continue;
9465e3dd157SKalle Valo 			}
9475e3dd157SKalle Valo 
948e8a50f8bSMarek Puzyniak 			if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) {
949e8a50f8bSMarek Puzyniak 				ath10k_htt_rx_free_msdu_chain(msdu_head);
950e8a50f8bSMarek Puzyniak 				continue;
951e8a50f8bSMarek Puzyniak 			}
952e8a50f8bSMarek Puzyniak 
9535e3dd157SKalle Valo 			/* FIXME: we do not support chaining yet.
9545e3dd157SKalle Valo 			 * this needs investigation */
9555e3dd157SKalle Valo 			if (msdu_chaining) {
9565e3dd157SKalle Valo 				ath10k_warn("msdu_chaining is true\n");
9575e3dd157SKalle Valo 				ath10k_htt_rx_free_msdu_chain(msdu_head);
9585e3dd157SKalle Valo 				continue;
9595e3dd157SKalle Valo 			}
9605e3dd157SKalle Valo 
9615e3dd157SKalle Valo 			info.skb     = msdu_head;
9625e3dd157SKalle Valo 			info.fcs_err = ath10k_htt_rx_has_fcs_err(msdu_head);
9635e3dd157SKalle Valo 			info.signal  = ATH10K_DEFAULT_NOISE_FLOOR;
9645e3dd157SKalle Valo 			info.signal += rx->ppdu.combined_rssi;
9655e3dd157SKalle Valo 
9665e3dd157SKalle Valo 			info.rate.info0 = rx->ppdu.info0;
9675e3dd157SKalle Valo 			info.rate.info1 = __le32_to_cpu(rx->ppdu.info1);
9685e3dd157SKalle Valo 			info.rate.info2 = __le32_to_cpu(rx->ppdu.info2);
9695e3dd157SKalle Valo 
9705e3dd157SKalle Valo 			hdr = ath10k_htt_rx_skb_get_hdr(msdu_head);
9715e3dd157SKalle Valo 
9725e3dd157SKalle Valo 			if (ath10k_htt_rx_hdr_is_amsdu(hdr))
973f6dc2095SMichal Kazior 				ath10k_htt_rx_amsdu(htt, &info);
9745e3dd157SKalle Valo 			else
975f6dc2095SMichal Kazior 				ath10k_htt_rx_msdu(htt, &info);
9765e3dd157SKalle Valo 		}
9775e3dd157SKalle Valo 	}
9785e3dd157SKalle Valo 
9796e712d42SMichal Kazior 	tasklet_schedule(&htt->rx_replenish_task);
9805e3dd157SKalle Valo }
9815e3dd157SKalle Valo 
9825e3dd157SKalle Valo static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
9835e3dd157SKalle Valo 				struct htt_rx_fragment_indication *frag)
9845e3dd157SKalle Valo {
9855e3dd157SKalle Valo 	struct sk_buff *msdu_head, *msdu_tail;
9865e3dd157SKalle Valo 	struct htt_rx_desc *rxd;
9875e3dd157SKalle Valo 	enum rx_msdu_decap_format fmt;
9885e3dd157SKalle Valo 	struct htt_rx_info info = {};
9895e3dd157SKalle Valo 	struct ieee80211_hdr *hdr;
9905e3dd157SKalle Valo 	int msdu_chaining;
9915e3dd157SKalle Valo 	bool tkip_mic_err;
9925e3dd157SKalle Valo 	bool decrypt_err;
9935e3dd157SKalle Valo 	u8 *fw_desc;
9945e3dd157SKalle Valo 	int fw_desc_len, hdrlen, paramlen;
9955e3dd157SKalle Valo 	int trim;
9965e3dd157SKalle Valo 
9975e3dd157SKalle Valo 	fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes);
9985e3dd157SKalle Valo 	fw_desc = (u8 *)frag->fw_msdu_rx_desc;
9995e3dd157SKalle Valo 
10005e3dd157SKalle Valo 	msdu_head = NULL;
10015e3dd157SKalle Valo 	msdu_tail = NULL;
10025e3dd157SKalle Valo 	msdu_chaining = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len,
10035e3dd157SKalle Valo 						&msdu_head, &msdu_tail);
10045e3dd157SKalle Valo 
10055e3dd157SKalle Valo 	ath10k_dbg(ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n");
10065e3dd157SKalle Valo 
10075e3dd157SKalle Valo 	if (!msdu_head) {
10085e3dd157SKalle Valo 		ath10k_warn("htt rx frag no data\n");
10095e3dd157SKalle Valo 		return;
10105e3dd157SKalle Valo 	}
10115e3dd157SKalle Valo 
10125e3dd157SKalle Valo 	if (msdu_chaining || msdu_head != msdu_tail) {
10135e3dd157SKalle Valo 		ath10k_warn("aggregation with fragmentation?!\n");
10145e3dd157SKalle Valo 		ath10k_htt_rx_free_msdu_chain(msdu_head);
10155e3dd157SKalle Valo 		return;
10165e3dd157SKalle Valo 	}
10175e3dd157SKalle Valo 
10185e3dd157SKalle Valo 	/* FIXME: implement signal strength */
10195e3dd157SKalle Valo 
10205e3dd157SKalle Valo 	hdr = (struct ieee80211_hdr *)msdu_head->data;
10215e3dd157SKalle Valo 	rxd = (void *)msdu_head->data - sizeof(*rxd);
10225e3dd157SKalle Valo 	tkip_mic_err = !!(__le32_to_cpu(rxd->attention.flags) &
10235e3dd157SKalle Valo 				RX_ATTENTION_FLAGS_TKIP_MIC_ERR);
10245e3dd157SKalle Valo 	decrypt_err = !!(__le32_to_cpu(rxd->attention.flags) &
10255e3dd157SKalle Valo 				RX_ATTENTION_FLAGS_DECRYPT_ERR);
10265e3dd157SKalle Valo 	fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
10275e3dd157SKalle Valo 			RX_MSDU_START_INFO1_DECAP_FORMAT);
10285e3dd157SKalle Valo 
10295e3dd157SKalle Valo 	if (fmt != RX_MSDU_DECAP_RAW) {
10305e3dd157SKalle Valo 		ath10k_warn("we dont support non-raw fragmented rx yet\n");
10315e3dd157SKalle Valo 		dev_kfree_skb_any(msdu_head);
10325e3dd157SKalle Valo 		goto end;
10335e3dd157SKalle Valo 	}
10345e3dd157SKalle Valo 
10355e3dd157SKalle Valo 	info.skb = msdu_head;
10365e3dd157SKalle Valo 	info.status = HTT_RX_IND_MPDU_STATUS_OK;
10375e3dd157SKalle Valo 	info.encrypt_type = MS(__le32_to_cpu(rxd->mpdu_start.info0),
10385e3dd157SKalle Valo 				RX_MPDU_START_INFO0_ENCRYPT_TYPE);
1039605f81aaSMichal Kazior 	info.skb->ip_summed = ath10k_htt_rx_get_csum_state(info.skb);
10405e3dd157SKalle Valo 
10415e3dd157SKalle Valo 	if (tkip_mic_err) {
10425e3dd157SKalle Valo 		ath10k_warn("tkip mic error\n");
10435e3dd157SKalle Valo 		info.status = HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR;
10445e3dd157SKalle Valo 	}
10455e3dd157SKalle Valo 
10465e3dd157SKalle Valo 	if (decrypt_err) {
10475e3dd157SKalle Valo 		ath10k_warn("decryption err in fragmented rx\n");
10485e3dd157SKalle Valo 		dev_kfree_skb_any(info.skb);
10495e3dd157SKalle Valo 		goto end;
10505e3dd157SKalle Valo 	}
10515e3dd157SKalle Valo 
10525e3dd157SKalle Valo 	if (info.encrypt_type != HTT_RX_MPDU_ENCRYPT_NONE) {
10535e3dd157SKalle Valo 		hdrlen = ieee80211_hdrlen(hdr->frame_control);
10545e3dd157SKalle Valo 		paramlen = ath10k_htt_rx_crypto_param_len(info.encrypt_type);
10555e3dd157SKalle Valo 
10565e3dd157SKalle Valo 		/* It is more efficient to move the header than the payload */
10575e3dd157SKalle Valo 		memmove((void *)info.skb->data + paramlen,
10585e3dd157SKalle Valo 			(void *)info.skb->data,
10595e3dd157SKalle Valo 			hdrlen);
10605e3dd157SKalle Valo 		skb_pull(info.skb, paramlen);
10615e3dd157SKalle Valo 		hdr = (struct ieee80211_hdr *)info.skb->data;
10625e3dd157SKalle Valo 	}
10635e3dd157SKalle Valo 
10645e3dd157SKalle Valo 	/* remove trailing FCS */
10655e3dd157SKalle Valo 	trim  = 4;
10665e3dd157SKalle Valo 
10675e3dd157SKalle Valo 	/* remove crypto trailer */
10685e3dd157SKalle Valo 	trim += ath10k_htt_rx_crypto_tail_len(info.encrypt_type);
10695e3dd157SKalle Valo 
10705e3dd157SKalle Valo 	/* last fragment of TKIP frags has MIC */
10715e3dd157SKalle Valo 	if (!ieee80211_has_morefrags(hdr->frame_control) &&
10725e3dd157SKalle Valo 	    info.encrypt_type == HTT_RX_MPDU_ENCRYPT_TKIP_WPA)
10735e3dd157SKalle Valo 		trim += 8;
10745e3dd157SKalle Valo 
10755e3dd157SKalle Valo 	if (trim > info.skb->len) {
10765e3dd157SKalle Valo 		ath10k_warn("htt rx fragment: trailer longer than the frame itself? drop\n");
10775e3dd157SKalle Valo 		dev_kfree_skb_any(info.skb);
10785e3dd157SKalle Valo 		goto end;
10795e3dd157SKalle Valo 	}
10805e3dd157SKalle Valo 
10815e3dd157SKalle Valo 	skb_trim(info.skb, info.skb->len - trim);
10825e3dd157SKalle Valo 
10835e3dd157SKalle Valo 	ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt frag mpdu: ",
10845e3dd157SKalle Valo 			info.skb->data, info.skb->len);
10855e3dd157SKalle Valo 	ath10k_process_rx(htt->ar, &info);
10865e3dd157SKalle Valo 
10875e3dd157SKalle Valo end:
10885e3dd157SKalle Valo 	if (fw_desc_len > 0) {
10895e3dd157SKalle Valo 		ath10k_dbg(ATH10K_DBG_HTT,
10905e3dd157SKalle Valo 			   "expecting more fragmented rx in one indication %d\n",
10915e3dd157SKalle Valo 			   fw_desc_len);
10925e3dd157SKalle Valo 	}
10935e3dd157SKalle Valo }
10945e3dd157SKalle Valo 
10955e3dd157SKalle Valo void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
10965e3dd157SKalle Valo {
1097edb8236dSMichal Kazior 	struct ath10k_htt *htt = &ar->htt;
10985e3dd157SKalle Valo 	struct htt_resp *resp = (struct htt_resp *)skb->data;
10995e3dd157SKalle Valo 
11005e3dd157SKalle Valo 	/* confirm alignment */
11015e3dd157SKalle Valo 	if (!IS_ALIGNED((unsigned long)skb->data, 4))
11025e3dd157SKalle Valo 		ath10k_warn("unaligned htt message, expect trouble\n");
11035e3dd157SKalle Valo 
11045e3dd157SKalle Valo 	ath10k_dbg(ATH10K_DBG_HTT, "HTT RX, msg_type: 0x%0X\n",
11055e3dd157SKalle Valo 		   resp->hdr.msg_type);
11065e3dd157SKalle Valo 	switch (resp->hdr.msg_type) {
11075e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_VERSION_CONF: {
11085e3dd157SKalle Valo 		htt->target_version_major = resp->ver_resp.major;
11095e3dd157SKalle Valo 		htt->target_version_minor = resp->ver_resp.minor;
11105e3dd157SKalle Valo 		complete(&htt->target_version_received);
11115e3dd157SKalle Valo 		break;
11125e3dd157SKalle Valo 	}
11135e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_RX_IND: {
11145e3dd157SKalle Valo 		ath10k_htt_rx_handler(htt, &resp->rx_ind);
11155e3dd157SKalle Valo 		break;
11165e3dd157SKalle Valo 	}
11175e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_PEER_MAP: {
11185e3dd157SKalle Valo 		struct htt_peer_map_event ev = {
11195e3dd157SKalle Valo 			.vdev_id = resp->peer_map.vdev_id,
11205e3dd157SKalle Valo 			.peer_id = __le16_to_cpu(resp->peer_map.peer_id),
11215e3dd157SKalle Valo 		};
11225e3dd157SKalle Valo 		memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr));
11235e3dd157SKalle Valo 		ath10k_peer_map_event(htt, &ev);
11245e3dd157SKalle Valo 		break;
11255e3dd157SKalle Valo 	}
11265e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_PEER_UNMAP: {
11275e3dd157SKalle Valo 		struct htt_peer_unmap_event ev = {
11285e3dd157SKalle Valo 			.peer_id = __le16_to_cpu(resp->peer_unmap.peer_id),
11295e3dd157SKalle Valo 		};
11305e3dd157SKalle Valo 		ath10k_peer_unmap_event(htt, &ev);
11315e3dd157SKalle Valo 		break;
11325e3dd157SKalle Valo 	}
11335e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: {
11345e3dd157SKalle Valo 		struct htt_tx_done tx_done = {};
11355e3dd157SKalle Valo 		int status = __le32_to_cpu(resp->mgmt_tx_completion.status);
11365e3dd157SKalle Valo 
11375e3dd157SKalle Valo 		tx_done.msdu_id =
11385e3dd157SKalle Valo 			__le32_to_cpu(resp->mgmt_tx_completion.desc_id);
11395e3dd157SKalle Valo 
11405e3dd157SKalle Valo 		switch (status) {
11415e3dd157SKalle Valo 		case HTT_MGMT_TX_STATUS_OK:
11425e3dd157SKalle Valo 			break;
11435e3dd157SKalle Valo 		case HTT_MGMT_TX_STATUS_RETRY:
11445e3dd157SKalle Valo 			tx_done.no_ack = true;
11455e3dd157SKalle Valo 			break;
11465e3dd157SKalle Valo 		case HTT_MGMT_TX_STATUS_DROP:
11475e3dd157SKalle Valo 			tx_done.discard = true;
11485e3dd157SKalle Valo 			break;
11495e3dd157SKalle Valo 		}
11505e3dd157SKalle Valo 
11510a89f8a0SMichal Kazior 		ath10k_txrx_tx_unref(htt, &tx_done);
11525e3dd157SKalle Valo 		break;
11535e3dd157SKalle Valo 	}
11545e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_TX_COMPL_IND: {
11555e3dd157SKalle Valo 		struct htt_tx_done tx_done = {};
11565e3dd157SKalle Valo 		int status = MS(resp->data_tx_completion.flags,
11575e3dd157SKalle Valo 				HTT_DATA_TX_STATUS);
11585e3dd157SKalle Valo 		__le16 msdu_id;
11595e3dd157SKalle Valo 		int i;
11605e3dd157SKalle Valo 
11615e3dd157SKalle Valo 		switch (status) {
11625e3dd157SKalle Valo 		case HTT_DATA_TX_STATUS_NO_ACK:
11635e3dd157SKalle Valo 			tx_done.no_ack = true;
11645e3dd157SKalle Valo 			break;
11655e3dd157SKalle Valo 		case HTT_DATA_TX_STATUS_OK:
11665e3dd157SKalle Valo 			break;
11675e3dd157SKalle Valo 		case HTT_DATA_TX_STATUS_DISCARD:
11685e3dd157SKalle Valo 		case HTT_DATA_TX_STATUS_POSTPONE:
11695e3dd157SKalle Valo 		case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL:
11705e3dd157SKalle Valo 			tx_done.discard = true;
11715e3dd157SKalle Valo 			break;
11725e3dd157SKalle Valo 		default:
11735e3dd157SKalle Valo 			ath10k_warn("unhandled tx completion status %d\n",
11745e3dd157SKalle Valo 				    status);
11755e3dd157SKalle Valo 			tx_done.discard = true;
11765e3dd157SKalle Valo 			break;
11775e3dd157SKalle Valo 		}
11785e3dd157SKalle Valo 
11795e3dd157SKalle Valo 		ath10k_dbg(ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n",
11805e3dd157SKalle Valo 			   resp->data_tx_completion.num_msdus);
11815e3dd157SKalle Valo 
11825e3dd157SKalle Valo 		for (i = 0; i < resp->data_tx_completion.num_msdus; i++) {
11835e3dd157SKalle Valo 			msdu_id = resp->data_tx_completion.msdus[i];
11845e3dd157SKalle Valo 			tx_done.msdu_id = __le16_to_cpu(msdu_id);
11850a89f8a0SMichal Kazior 			ath10k_txrx_tx_unref(htt, &tx_done);
11865e3dd157SKalle Valo 		}
11875e3dd157SKalle Valo 		break;
11885e3dd157SKalle Valo 	}
11895e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_SEC_IND: {
11905e3dd157SKalle Valo 		struct ath10k *ar = htt->ar;
11915e3dd157SKalle Valo 		struct htt_security_indication *ev = &resp->security_indication;
11925e3dd157SKalle Valo 
11935e3dd157SKalle Valo 		ath10k_dbg(ATH10K_DBG_HTT,
11945e3dd157SKalle Valo 			   "sec ind peer_id %d unicast %d type %d\n",
11955e3dd157SKalle Valo 			  __le16_to_cpu(ev->peer_id),
11965e3dd157SKalle Valo 			  !!(ev->flags & HTT_SECURITY_IS_UNICAST),
11975e3dd157SKalle Valo 			  MS(ev->flags, HTT_SECURITY_TYPE));
11985e3dd157SKalle Valo 		complete(&ar->install_key_done);
11995e3dd157SKalle Valo 		break;
12005e3dd157SKalle Valo 	}
12015e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_RX_FRAG_IND: {
12025e3dd157SKalle Valo 		ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
12035e3dd157SKalle Valo 				skb->data, skb->len);
12045e3dd157SKalle Valo 		ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind);
12055e3dd157SKalle Valo 		break;
12065e3dd157SKalle Valo 	}
12075e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_TEST:
12085e3dd157SKalle Valo 		/* FIX THIS */
12095e3dd157SKalle Valo 		break;
12105e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_STATS_CONF:
1211a9bf0506SKalle Valo 		trace_ath10k_htt_stats(skb->data, skb->len);
1212a9bf0506SKalle Valo 		break;
1213a9bf0506SKalle Valo 	case HTT_T2H_MSG_TYPE_TX_INSPECT_IND:
12145e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_RX_ADDBA:
12155e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_RX_DELBA:
12165e3dd157SKalle Valo 	case HTT_T2H_MSG_TYPE_RX_FLUSH:
12175e3dd157SKalle Valo 	default:
12185e3dd157SKalle Valo 		ath10k_dbg(ATH10K_DBG_HTT, "htt event (%d) not handled\n",
12195e3dd157SKalle Valo 			   resp->hdr.msg_type);
12205e3dd157SKalle Valo 		ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
12215e3dd157SKalle Valo 				skb->data, skb->len);
12225e3dd157SKalle Valo 		break;
12235e3dd157SKalle Valo 	};
12245e3dd157SKalle Valo 
12255e3dd157SKalle Valo 	/* Free the indication buffer */
12265e3dd157SKalle Valo 	dev_kfree_skb_any(skb);
12275e3dd157SKalle Valo }
1228