15e3dd157SKalle Valo /* 25e3dd157SKalle Valo * Copyright (c) 2005-2011 Atheros Communications Inc. 35e3dd157SKalle Valo * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 45e3dd157SKalle Valo * 55e3dd157SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 65e3dd157SKalle Valo * purpose with or without fee is hereby granted, provided that the above 75e3dd157SKalle Valo * copyright notice and this permission notice appear in all copies. 85e3dd157SKalle Valo * 95e3dd157SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 105e3dd157SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 115e3dd157SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 125e3dd157SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 135e3dd157SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 145e3dd157SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 155e3dd157SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 165e3dd157SKalle Valo */ 175e3dd157SKalle Valo 18edb8236dSMichal Kazior #include "core.h" 195e3dd157SKalle Valo #include "htc.h" 205e3dd157SKalle Valo #include "htt.h" 215e3dd157SKalle Valo #include "txrx.h" 225e3dd157SKalle Valo #include "debug.h" 23a9bf0506SKalle Valo #include "trace.h" 24aa5b4fbcSMichal Kazior #include "mac.h" 255e3dd157SKalle Valo 265e3dd157SKalle Valo #include <linux/log2.h> 275e3dd157SKalle Valo 285e3dd157SKalle Valo /* slightly larger than one large A-MPDU */ 295e3dd157SKalle Valo #define HTT_RX_RING_SIZE_MIN 128 305e3dd157SKalle Valo 315e3dd157SKalle Valo /* roughly 20 ms @ 1 Gbps of 1500B MSDUs */ 325e3dd157SKalle Valo #define HTT_RX_RING_SIZE_MAX 2048 335e3dd157SKalle Valo 345e3dd157SKalle Valo #define HTT_RX_AVG_FRM_BYTES 1000 355e3dd157SKalle Valo 365e3dd157SKalle Valo /* ms, very conservative */ 375e3dd157SKalle Valo #define HTT_RX_HOST_LATENCY_MAX_MS 20 385e3dd157SKalle Valo 395e3dd157SKalle Valo /* ms, conservative */ 405e3dd157SKalle Valo #define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10 415e3dd157SKalle Valo 425e3dd157SKalle Valo /* when under memory pressure rx ring refill may fail and needs a retry */ 435e3dd157SKalle Valo #define HTT_RX_RING_REFILL_RETRY_MS 50 445e3dd157SKalle Valo 45f6dc2095SMichal Kazior static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb); 466c5151a9SMichal Kazior static void ath10k_htt_txrx_compl_task(unsigned long ptr); 47f6dc2095SMichal Kazior 485e3dd157SKalle Valo static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt) 495e3dd157SKalle Valo { 505e3dd157SKalle Valo int size; 515e3dd157SKalle Valo 525e3dd157SKalle Valo /* 535e3dd157SKalle Valo * It is expected that the host CPU will typically be able to 545e3dd157SKalle Valo * service the rx indication from one A-MPDU before the rx 555e3dd157SKalle Valo * indication from the subsequent A-MPDU happens, roughly 1-2 ms 565e3dd157SKalle Valo * later. However, the rx ring should be sized very conservatively, 575e3dd157SKalle Valo * to accomodate the worst reasonable delay before the host CPU 585e3dd157SKalle Valo * services a rx indication interrupt. 595e3dd157SKalle Valo * 605e3dd157SKalle Valo * The rx ring need not be kept full of empty buffers. In theory, 615e3dd157SKalle Valo * the htt host SW can dynamically track the low-water mark in the 625e3dd157SKalle Valo * rx ring, and dynamically adjust the level to which the rx ring 635e3dd157SKalle Valo * is filled with empty buffers, to dynamically meet the desired 645e3dd157SKalle Valo * low-water mark. 655e3dd157SKalle Valo * 665e3dd157SKalle Valo * In contrast, it's difficult to resize the rx ring itself, once 675e3dd157SKalle Valo * it's in use. Thus, the ring itself should be sized very 685e3dd157SKalle Valo * conservatively, while the degree to which the ring is filled 695e3dd157SKalle Valo * with empty buffers should be sized moderately conservatively. 705e3dd157SKalle Valo */ 715e3dd157SKalle Valo 725e3dd157SKalle Valo /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */ 735e3dd157SKalle Valo size = 745e3dd157SKalle Valo htt->max_throughput_mbps + 755e3dd157SKalle Valo 1000 / 765e3dd157SKalle Valo (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS; 775e3dd157SKalle Valo 785e3dd157SKalle Valo if (size < HTT_RX_RING_SIZE_MIN) 795e3dd157SKalle Valo size = HTT_RX_RING_SIZE_MIN; 805e3dd157SKalle Valo 815e3dd157SKalle Valo if (size > HTT_RX_RING_SIZE_MAX) 825e3dd157SKalle Valo size = HTT_RX_RING_SIZE_MAX; 835e3dd157SKalle Valo 845e3dd157SKalle Valo size = roundup_pow_of_two(size); 855e3dd157SKalle Valo 865e3dd157SKalle Valo return size; 875e3dd157SKalle Valo } 885e3dd157SKalle Valo 895e3dd157SKalle Valo static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt) 905e3dd157SKalle Valo { 915e3dd157SKalle Valo int size; 925e3dd157SKalle Valo 935e3dd157SKalle Valo /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */ 945e3dd157SKalle Valo size = 955e3dd157SKalle Valo htt->max_throughput_mbps * 965e3dd157SKalle Valo 1000 / 975e3dd157SKalle Valo (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS; 985e3dd157SKalle Valo 995e3dd157SKalle Valo /* 1005e3dd157SKalle Valo * Make sure the fill level is at least 1 less than the ring size. 1015e3dd157SKalle Valo * Leaving 1 element empty allows the SW to easily distinguish 1025e3dd157SKalle Valo * between a full ring vs. an empty ring. 1035e3dd157SKalle Valo */ 1045e3dd157SKalle Valo if (size >= htt->rx_ring.size) 1055e3dd157SKalle Valo size = htt->rx_ring.size - 1; 1065e3dd157SKalle Valo 1075e3dd157SKalle Valo return size; 1085e3dd157SKalle Valo } 1095e3dd157SKalle Valo 1105e3dd157SKalle Valo static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt) 1115e3dd157SKalle Valo { 1125e3dd157SKalle Valo struct sk_buff *skb; 1135e3dd157SKalle Valo struct ath10k_skb_cb *cb; 1145e3dd157SKalle Valo int i; 1155e3dd157SKalle Valo 1165e3dd157SKalle Valo for (i = 0; i < htt->rx_ring.fill_cnt; i++) { 1175e3dd157SKalle Valo skb = htt->rx_ring.netbufs_ring[i]; 1185e3dd157SKalle Valo cb = ATH10K_SKB_CB(skb); 1195e3dd157SKalle Valo dma_unmap_single(htt->ar->dev, cb->paddr, 1205e3dd157SKalle Valo skb->len + skb_tailroom(skb), 1215e3dd157SKalle Valo DMA_FROM_DEVICE); 1225e3dd157SKalle Valo dev_kfree_skb_any(skb); 1235e3dd157SKalle Valo } 1245e3dd157SKalle Valo 1255e3dd157SKalle Valo htt->rx_ring.fill_cnt = 0; 1265e3dd157SKalle Valo } 1275e3dd157SKalle Valo 1285e3dd157SKalle Valo static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num) 1295e3dd157SKalle Valo { 1305e3dd157SKalle Valo struct htt_rx_desc *rx_desc; 1315e3dd157SKalle Valo struct sk_buff *skb; 1325e3dd157SKalle Valo dma_addr_t paddr; 1335e3dd157SKalle Valo int ret = 0, idx; 1345e3dd157SKalle Valo 1358cc7f26cSKalle Valo idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 1365e3dd157SKalle Valo while (num > 0) { 1375e3dd157SKalle Valo skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN); 1385e3dd157SKalle Valo if (!skb) { 1395e3dd157SKalle Valo ret = -ENOMEM; 1405e3dd157SKalle Valo goto fail; 1415e3dd157SKalle Valo } 1425e3dd157SKalle Valo 1435e3dd157SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN)) 1445e3dd157SKalle Valo skb_pull(skb, 1455e3dd157SKalle Valo PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) - 1465e3dd157SKalle Valo skb->data); 1475e3dd157SKalle Valo 1485e3dd157SKalle Valo /* Clear rx_desc attention word before posting to Rx ring */ 1495e3dd157SKalle Valo rx_desc = (struct htt_rx_desc *)skb->data; 1505e3dd157SKalle Valo rx_desc->attention.flags = __cpu_to_le32(0); 1515e3dd157SKalle Valo 1525e3dd157SKalle Valo paddr = dma_map_single(htt->ar->dev, skb->data, 1535e3dd157SKalle Valo skb->len + skb_tailroom(skb), 1545e3dd157SKalle Valo DMA_FROM_DEVICE); 1555e3dd157SKalle Valo 1565e3dd157SKalle Valo if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) { 1575e3dd157SKalle Valo dev_kfree_skb_any(skb); 1585e3dd157SKalle Valo ret = -ENOMEM; 1595e3dd157SKalle Valo goto fail; 1605e3dd157SKalle Valo } 1615e3dd157SKalle Valo 1625e3dd157SKalle Valo ATH10K_SKB_CB(skb)->paddr = paddr; 1635e3dd157SKalle Valo htt->rx_ring.netbufs_ring[idx] = skb; 1645e3dd157SKalle Valo htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr); 1655e3dd157SKalle Valo htt->rx_ring.fill_cnt++; 1665e3dd157SKalle Valo 1675e3dd157SKalle Valo num--; 1685e3dd157SKalle Valo idx++; 1695e3dd157SKalle Valo idx &= htt->rx_ring.size_mask; 1705e3dd157SKalle Valo } 1715e3dd157SKalle Valo 1725e3dd157SKalle Valo fail: 1738cc7f26cSKalle Valo *htt->rx_ring.alloc_idx.vaddr = __cpu_to_le32(idx); 1745e3dd157SKalle Valo return ret; 1755e3dd157SKalle Valo } 1765e3dd157SKalle Valo 1775e3dd157SKalle Valo static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num) 1785e3dd157SKalle Valo { 1795e3dd157SKalle Valo lockdep_assert_held(&htt->rx_ring.lock); 1805e3dd157SKalle Valo return __ath10k_htt_rx_ring_fill_n(htt, num); 1815e3dd157SKalle Valo } 1825e3dd157SKalle Valo 1835e3dd157SKalle Valo static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt) 1845e3dd157SKalle Valo { 1856e712d42SMichal Kazior int ret, num_deficit, num_to_fill; 1865e3dd157SKalle Valo 1876e712d42SMichal Kazior /* Refilling the whole RX ring buffer proves to be a bad idea. The 1886e712d42SMichal Kazior * reason is RX may take up significant amount of CPU cycles and starve 1896e712d42SMichal Kazior * other tasks, e.g. TX on an ethernet device while acting as a bridge 1906e712d42SMichal Kazior * with ath10k wlan interface. This ended up with very poor performance 1916e712d42SMichal Kazior * once CPU the host system was overwhelmed with RX on ath10k. 1926e712d42SMichal Kazior * 1936e712d42SMichal Kazior * By limiting the number of refills the replenishing occurs 1946e712d42SMichal Kazior * progressively. This in turns makes use of the fact tasklets are 1956e712d42SMichal Kazior * processed in FIFO order. This means actual RX processing can starve 1966e712d42SMichal Kazior * out refilling. If there's not enough buffers on RX ring FW will not 1976e712d42SMichal Kazior * report RX until it is refilled with enough buffers. This 1986e712d42SMichal Kazior * automatically balances load wrt to CPU power. 1996e712d42SMichal Kazior * 2006e712d42SMichal Kazior * This probably comes at a cost of lower maximum throughput but 2016e712d42SMichal Kazior * improves the avarage and stability. */ 2025e3dd157SKalle Valo spin_lock_bh(&htt->rx_ring.lock); 2036e712d42SMichal Kazior num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt; 2046e712d42SMichal Kazior num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit); 2056e712d42SMichal Kazior num_deficit -= num_to_fill; 2065e3dd157SKalle Valo ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill); 2075e3dd157SKalle Valo if (ret == -ENOMEM) { 2085e3dd157SKalle Valo /* 2095e3dd157SKalle Valo * Failed to fill it to the desired level - 2105e3dd157SKalle Valo * we'll start a timer and try again next time. 2115e3dd157SKalle Valo * As long as enough buffers are left in the ring for 2125e3dd157SKalle Valo * another A-MPDU rx, no special recovery is needed. 2135e3dd157SKalle Valo */ 2145e3dd157SKalle Valo mod_timer(&htt->rx_ring.refill_retry_timer, jiffies + 2155e3dd157SKalle Valo msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS)); 2166e712d42SMichal Kazior } else if (num_deficit > 0) { 2176e712d42SMichal Kazior tasklet_schedule(&htt->rx_replenish_task); 2185e3dd157SKalle Valo } 2195e3dd157SKalle Valo spin_unlock_bh(&htt->rx_ring.lock); 2205e3dd157SKalle Valo } 2215e3dd157SKalle Valo 2225e3dd157SKalle Valo static void ath10k_htt_rx_ring_refill_retry(unsigned long arg) 2235e3dd157SKalle Valo { 2245e3dd157SKalle Valo struct ath10k_htt *htt = (struct ath10k_htt *)arg; 225af762c0bSKalle Valo 2265e3dd157SKalle Valo ath10k_htt_rx_msdu_buff_replenish(htt); 2275e3dd157SKalle Valo } 2285e3dd157SKalle Valo 2293e841fd0SMichal Kazior static void ath10k_htt_rx_ring_clean_up(struct ath10k_htt *htt) 2303e841fd0SMichal Kazior { 2313e841fd0SMichal Kazior struct sk_buff *skb; 2323e841fd0SMichal Kazior int i; 2333e841fd0SMichal Kazior 2343e841fd0SMichal Kazior for (i = 0; i < htt->rx_ring.size; i++) { 2353e841fd0SMichal Kazior skb = htt->rx_ring.netbufs_ring[i]; 2363e841fd0SMichal Kazior if (!skb) 2373e841fd0SMichal Kazior continue; 2383e841fd0SMichal Kazior 2393e841fd0SMichal Kazior dma_unmap_single(htt->ar->dev, ATH10K_SKB_CB(skb)->paddr, 2403e841fd0SMichal Kazior skb->len + skb_tailroom(skb), 2413e841fd0SMichal Kazior DMA_FROM_DEVICE); 2423e841fd0SMichal Kazior dev_kfree_skb_any(skb); 2433e841fd0SMichal Kazior htt->rx_ring.netbufs_ring[i] = NULL; 2443e841fd0SMichal Kazior } 2453e841fd0SMichal Kazior } 2463e841fd0SMichal Kazior 24795bf21f9SMichal Kazior void ath10k_htt_rx_free(struct ath10k_htt *htt) 2485e3dd157SKalle Valo { 2495e3dd157SKalle Valo del_timer_sync(&htt->rx_ring.refill_retry_timer); 2506e712d42SMichal Kazior tasklet_kill(&htt->rx_replenish_task); 2516c5151a9SMichal Kazior tasklet_kill(&htt->txrx_compl_task); 2526c5151a9SMichal Kazior 2536c5151a9SMichal Kazior skb_queue_purge(&htt->tx_compl_q); 2546c5151a9SMichal Kazior skb_queue_purge(&htt->rx_compl_q); 2555e3dd157SKalle Valo 2563e841fd0SMichal Kazior ath10k_htt_rx_ring_clean_up(htt); 2575e3dd157SKalle Valo 2585e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 2595e3dd157SKalle Valo (htt->rx_ring.size * 2605e3dd157SKalle Valo sizeof(htt->rx_ring.paddrs_ring)), 2615e3dd157SKalle Valo htt->rx_ring.paddrs_ring, 2625e3dd157SKalle Valo htt->rx_ring.base_paddr); 2635e3dd157SKalle Valo 2645e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 2655e3dd157SKalle Valo sizeof(*htt->rx_ring.alloc_idx.vaddr), 2665e3dd157SKalle Valo htt->rx_ring.alloc_idx.vaddr, 2675e3dd157SKalle Valo htt->rx_ring.alloc_idx.paddr); 2685e3dd157SKalle Valo 2695e3dd157SKalle Valo kfree(htt->rx_ring.netbufs_ring); 2705e3dd157SKalle Valo } 2715e3dd157SKalle Valo 2725e3dd157SKalle Valo static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt) 2735e3dd157SKalle Valo { 2747aa7a72aSMichal Kazior struct ath10k *ar = htt->ar; 2755e3dd157SKalle Valo int idx; 2765e3dd157SKalle Valo struct sk_buff *msdu; 2775e3dd157SKalle Valo 27845967089SMichal Kazior lockdep_assert_held(&htt->rx_ring.lock); 2795e3dd157SKalle Valo 2808d60ee87SMichal Kazior if (htt->rx_ring.fill_cnt == 0) { 2817aa7a72aSMichal Kazior ath10k_warn(ar, "tried to pop sk_buff from an empty rx ring\n"); 2828d60ee87SMichal Kazior return NULL; 2838d60ee87SMichal Kazior } 2845e3dd157SKalle Valo 2855e3dd157SKalle Valo idx = htt->rx_ring.sw_rd_idx.msdu_payld; 2865e3dd157SKalle Valo msdu = htt->rx_ring.netbufs_ring[idx]; 2873e841fd0SMichal Kazior htt->rx_ring.netbufs_ring[idx] = NULL; 2885e3dd157SKalle Valo 2895e3dd157SKalle Valo idx++; 2905e3dd157SKalle Valo idx &= htt->rx_ring.size_mask; 2915e3dd157SKalle Valo htt->rx_ring.sw_rd_idx.msdu_payld = idx; 2925e3dd157SKalle Valo htt->rx_ring.fill_cnt--; 2935e3dd157SKalle Valo 2944de02806SMichal Kazior dma_unmap_single(htt->ar->dev, 2954de02806SMichal Kazior ATH10K_SKB_CB(msdu)->paddr, 2964de02806SMichal Kazior msdu->len + skb_tailroom(msdu), 2974de02806SMichal Kazior DMA_FROM_DEVICE); 2984de02806SMichal Kazior ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx netbuf pop: ", 2994de02806SMichal Kazior msdu->data, msdu->len + skb_tailroom(msdu)); 3004de02806SMichal Kazior trace_ath10k_htt_rx_pop_msdu(ar, msdu->data, msdu->len + 3014de02806SMichal Kazior skb_tailroom(msdu)); 3024de02806SMichal Kazior 3035e3dd157SKalle Valo return msdu; 3045e3dd157SKalle Valo } 3055e3dd157SKalle Valo 3065e3dd157SKalle Valo static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb) 3075e3dd157SKalle Valo { 3085e3dd157SKalle Valo struct sk_buff *next; 3095e3dd157SKalle Valo 3105e3dd157SKalle Valo while (skb) { 3115e3dd157SKalle Valo next = skb->next; 3125e3dd157SKalle Valo dev_kfree_skb_any(skb); 3135e3dd157SKalle Valo skb = next; 3145e3dd157SKalle Valo } 3155e3dd157SKalle Valo } 3165e3dd157SKalle Valo 317d84dd60fSJanusz Dziedzic /* return: < 0 fatal error, 0 - non chained msdu, 1 chained msdu */ 3185e3dd157SKalle Valo static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt, 3195e3dd157SKalle Valo u8 **fw_desc, int *fw_desc_len, 3205e3dd157SKalle Valo struct sk_buff **head_msdu, 3210ccb7a34SJanusz Dziedzic struct sk_buff **tail_msdu, 3220ccb7a34SJanusz Dziedzic u32 *attention) 3235e3dd157SKalle Valo { 3247aa7a72aSMichal Kazior struct ath10k *ar = htt->ar; 3255e3dd157SKalle Valo int msdu_len, msdu_chaining = 0; 326af762c0bSKalle Valo struct sk_buff *msdu, *next; 3275e3dd157SKalle Valo struct htt_rx_desc *rx_desc; 3285e3dd157SKalle Valo 32945967089SMichal Kazior lockdep_assert_held(&htt->rx_ring.lock); 33045967089SMichal Kazior 3315e3dd157SKalle Valo if (htt->rx_confused) { 3327aa7a72aSMichal Kazior ath10k_warn(ar, "htt is confused. refusing rx\n"); 333d84dd60fSJanusz Dziedzic return -1; 3345e3dd157SKalle Valo } 3355e3dd157SKalle Valo 3365e3dd157SKalle Valo msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt); 3375e3dd157SKalle Valo while (msdu) { 3385e3dd157SKalle Valo int last_msdu, msdu_len_invalid, msdu_chained; 3395e3dd157SKalle Valo 3405e3dd157SKalle Valo rx_desc = (struct htt_rx_desc *)msdu->data; 3415e3dd157SKalle Valo 3425e3dd157SKalle Valo /* FIXME: we must report msdu payload since this is what caller 3435e3dd157SKalle Valo * expects now */ 3445e3dd157SKalle Valo skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload)); 3455e3dd157SKalle Valo skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload)); 3465e3dd157SKalle Valo 3475e3dd157SKalle Valo /* 3485e3dd157SKalle Valo * Sanity check - confirm the HW is finished filling in the 3495e3dd157SKalle Valo * rx data. 3505e3dd157SKalle Valo * If the HW and SW are working correctly, then it's guaranteed 3515e3dd157SKalle Valo * that the HW's MAC DMA is done before this point in the SW. 3525e3dd157SKalle Valo * To prevent the case that we handle a stale Rx descriptor, 3535e3dd157SKalle Valo * just assert for now until we have a way to recover. 3545e3dd157SKalle Valo */ 3555e3dd157SKalle Valo if (!(__le32_to_cpu(rx_desc->attention.flags) 3565e3dd157SKalle Valo & RX_ATTENTION_FLAGS_MSDU_DONE)) { 3575e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(*head_msdu); 3585e3dd157SKalle Valo *head_msdu = NULL; 3595e3dd157SKalle Valo msdu = NULL; 3607aa7a72aSMichal Kazior ath10k_err(ar, "htt rx stopped. cannot recover\n"); 3615e3dd157SKalle Valo htt->rx_confused = true; 3625e3dd157SKalle Valo break; 3635e3dd157SKalle Valo } 3645e3dd157SKalle Valo 3650ccb7a34SJanusz Dziedzic *attention |= __le32_to_cpu(rx_desc->attention.flags) & 3660ccb7a34SJanusz Dziedzic (RX_ATTENTION_FLAGS_TKIP_MIC_ERR | 3670ccb7a34SJanusz Dziedzic RX_ATTENTION_FLAGS_DECRYPT_ERR | 3680ccb7a34SJanusz Dziedzic RX_ATTENTION_FLAGS_FCS_ERR | 3690ccb7a34SJanusz Dziedzic RX_ATTENTION_FLAGS_MGMT_TYPE); 3705e3dd157SKalle Valo /* 3715e3dd157SKalle Valo * Copy the FW rx descriptor for this MSDU from the rx 3725e3dd157SKalle Valo * indication message into the MSDU's netbuf. HL uses the 3735e3dd157SKalle Valo * same rx indication message definition as LL, and simply 3745e3dd157SKalle Valo * appends new info (fields from the HW rx desc, and the 3755e3dd157SKalle Valo * MSDU payload itself). So, the offset into the rx 3765e3dd157SKalle Valo * indication message only has to account for the standard 3775e3dd157SKalle Valo * offset of the per-MSDU FW rx desc info within the 3785e3dd157SKalle Valo * message, and how many bytes of the per-MSDU FW rx desc 3795e3dd157SKalle Valo * info have already been consumed. (And the endianness of 3805e3dd157SKalle Valo * the host, since for a big-endian host, the rx ind 3815e3dd157SKalle Valo * message contents, including the per-MSDU rx desc bytes, 3825e3dd157SKalle Valo * were byteswapped during upload.) 3835e3dd157SKalle Valo */ 3845e3dd157SKalle Valo if (*fw_desc_len > 0) { 3855e3dd157SKalle Valo rx_desc->fw_desc.info0 = **fw_desc; 3865e3dd157SKalle Valo /* 3875e3dd157SKalle Valo * The target is expected to only provide the basic 3885e3dd157SKalle Valo * per-MSDU rx descriptors. Just to be sure, verify 3895e3dd157SKalle Valo * that the target has not attached extension data 3905e3dd157SKalle Valo * (e.g. LRO flow ID). 3915e3dd157SKalle Valo */ 3925e3dd157SKalle Valo 3935e3dd157SKalle Valo /* or more, if there's extension data */ 3945e3dd157SKalle Valo (*fw_desc)++; 3955e3dd157SKalle Valo (*fw_desc_len)--; 3965e3dd157SKalle Valo } else { 3975e3dd157SKalle Valo /* 3985e3dd157SKalle Valo * When an oversized AMSDU happened, FW will lost 3995e3dd157SKalle Valo * some of MSDU status - in this case, the FW 4005e3dd157SKalle Valo * descriptors provided will be less than the 4015e3dd157SKalle Valo * actual MSDUs inside this MPDU. Mark the FW 4025e3dd157SKalle Valo * descriptors so that it will still deliver to 4035e3dd157SKalle Valo * upper stack, if no CRC error for this MPDU. 4045e3dd157SKalle Valo * 4055e3dd157SKalle Valo * FIX THIS - the FW descriptors are actually for 4065e3dd157SKalle Valo * MSDUs in the end of this A-MSDU instead of the 4075e3dd157SKalle Valo * beginning. 4085e3dd157SKalle Valo */ 4095e3dd157SKalle Valo rx_desc->fw_desc.info0 = 0; 4105e3dd157SKalle Valo } 4115e3dd157SKalle Valo 4125e3dd157SKalle Valo msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags) 4135e3dd157SKalle Valo & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR | 4145e3dd157SKalle Valo RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR)); 4155e3dd157SKalle Valo msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0), 4165e3dd157SKalle Valo RX_MSDU_START_INFO0_MSDU_LENGTH); 4175e3dd157SKalle Valo msdu_chained = rx_desc->frag_info.ring2_more_count; 4185e3dd157SKalle Valo 4195e3dd157SKalle Valo if (msdu_len_invalid) 4205e3dd157SKalle Valo msdu_len = 0; 4215e3dd157SKalle Valo 4225e3dd157SKalle Valo skb_trim(msdu, 0); 4235e3dd157SKalle Valo skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE)); 4245e3dd157SKalle Valo msdu_len -= msdu->len; 4255e3dd157SKalle Valo 4265e3dd157SKalle Valo /* FIXME: Do chained buffers include htt_rx_desc or not? */ 4275e3dd157SKalle Valo while (msdu_chained--) { 4285e3dd157SKalle Valo struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt); 4295e3dd157SKalle Valo 430b30595aeSMichal Kazior if (!next) { 431b30595aeSMichal Kazior ath10k_warn(ar, "failed to pop chained msdu\n"); 432b30595aeSMichal Kazior ath10k_htt_rx_free_msdu_chain(*head_msdu); 433b30595aeSMichal Kazior *head_msdu = NULL; 434b30595aeSMichal Kazior msdu = NULL; 435b30595aeSMichal Kazior htt->rx_confused = true; 436b30595aeSMichal Kazior break; 437b30595aeSMichal Kazior } 438b30595aeSMichal Kazior 4395e3dd157SKalle Valo skb_trim(next, 0); 4405e3dd157SKalle Valo skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE)); 4415e3dd157SKalle Valo msdu_len -= next->len; 4425e3dd157SKalle Valo 4435e3dd157SKalle Valo msdu->next = next; 4445e3dd157SKalle Valo msdu = next; 445ede9c8e0SMichal Kazior msdu_chaining = 1; 4465e3dd157SKalle Valo } 4475e3dd157SKalle Valo 4485e3dd157SKalle Valo last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) & 4495e3dd157SKalle Valo RX_MSDU_END_INFO0_LAST_MSDU; 4505e3dd157SKalle Valo 451b04e204fSMichal Kazior trace_ath10k_htt_rx_desc(ar, &rx_desc->attention, 452a0883cf7SRajkumar Manoharan sizeof(*rx_desc) - sizeof(u32)); 4535e3dd157SKalle Valo if (last_msdu) { 4545e3dd157SKalle Valo msdu->next = NULL; 4555e3dd157SKalle Valo break; 456d8bb26b9SKalle Valo } 457d8bb26b9SKalle Valo 458af762c0bSKalle Valo next = ath10k_htt_rx_netbuf_pop(htt); 4595e3dd157SKalle Valo msdu->next = next; 4605e3dd157SKalle Valo msdu = next; 4615e3dd157SKalle Valo } 4625e3dd157SKalle Valo *tail_msdu = msdu; 4635e3dd157SKalle Valo 464d84dd60fSJanusz Dziedzic if (*head_msdu == NULL) 465d84dd60fSJanusz Dziedzic msdu_chaining = -1; 466d84dd60fSJanusz Dziedzic 4675e3dd157SKalle Valo /* 4685e3dd157SKalle Valo * Don't refill the ring yet. 4695e3dd157SKalle Valo * 4705e3dd157SKalle Valo * First, the elements popped here are still in use - it is not 4715e3dd157SKalle Valo * safe to overwrite them until the matching call to 4725e3dd157SKalle Valo * mpdu_desc_list_next. Second, for efficiency it is preferable to 4735e3dd157SKalle Valo * refill the rx ring with 1 PPDU's worth of rx buffers (something 4745e3dd157SKalle Valo * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers 4755e3dd157SKalle Valo * (something like 3 buffers). Consequently, we'll rely on the txrx 4765e3dd157SKalle Valo * SW to tell us when it is done pulling all the PPDU's rx buffers 4775e3dd157SKalle Valo * out of the rx ring, and then refill it just once. 4785e3dd157SKalle Valo */ 4795e3dd157SKalle Valo 4805e3dd157SKalle Valo return msdu_chaining; 4815e3dd157SKalle Valo } 4825e3dd157SKalle Valo 4836e712d42SMichal Kazior static void ath10k_htt_rx_replenish_task(unsigned long ptr) 4846e712d42SMichal Kazior { 4856e712d42SMichal Kazior struct ath10k_htt *htt = (struct ath10k_htt *)ptr; 486af762c0bSKalle Valo 4876e712d42SMichal Kazior ath10k_htt_rx_msdu_buff_replenish(htt); 4886e712d42SMichal Kazior } 4896e712d42SMichal Kazior 49095bf21f9SMichal Kazior int ath10k_htt_rx_alloc(struct ath10k_htt *htt) 4915e3dd157SKalle Valo { 4927aa7a72aSMichal Kazior struct ath10k *ar = htt->ar; 4935e3dd157SKalle Valo dma_addr_t paddr; 4945e3dd157SKalle Valo void *vaddr; 495bd8bdbb6SKalle Valo size_t size; 4965e3dd157SKalle Valo struct timer_list *timer = &htt->rx_ring.refill_retry_timer; 4975e3dd157SKalle Valo 49851fc7d74SMichal Kazior htt->rx_confused = false; 49951fc7d74SMichal Kazior 5005e3dd157SKalle Valo htt->rx_ring.size = ath10k_htt_rx_ring_size(htt); 5015e3dd157SKalle Valo if (!is_power_of_2(htt->rx_ring.size)) { 5027aa7a72aSMichal Kazior ath10k_warn(ar, "htt rx ring size is not power of 2\n"); 5035e3dd157SKalle Valo return -EINVAL; 5045e3dd157SKalle Valo } 5055e3dd157SKalle Valo 5065e3dd157SKalle Valo htt->rx_ring.size_mask = htt->rx_ring.size - 1; 5075e3dd157SKalle Valo 5085e3dd157SKalle Valo /* 5095e3dd157SKalle Valo * Set the initial value for the level to which the rx ring 5105e3dd157SKalle Valo * should be filled, based on the max throughput and the 5115e3dd157SKalle Valo * worst likely latency for the host to fill the rx ring 5125e3dd157SKalle Valo * with new buffers. In theory, this fill level can be 5135e3dd157SKalle Valo * dynamically adjusted from the initial value set here, to 5145e3dd157SKalle Valo * reflect the actual host latency rather than a 5155e3dd157SKalle Valo * conservative assumption about the host latency. 5165e3dd157SKalle Valo */ 5175e3dd157SKalle Valo htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt); 5185e3dd157SKalle Valo 5195e3dd157SKalle Valo htt->rx_ring.netbufs_ring = 5203e841fd0SMichal Kazior kzalloc(htt->rx_ring.size * sizeof(struct sk_buff *), 5215e3dd157SKalle Valo GFP_KERNEL); 5225e3dd157SKalle Valo if (!htt->rx_ring.netbufs_ring) 5235e3dd157SKalle Valo goto err_netbuf; 5245e3dd157SKalle Valo 525bd8bdbb6SKalle Valo size = htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring); 526bd8bdbb6SKalle Valo 527bd8bdbb6SKalle Valo vaddr = dma_alloc_coherent(htt->ar->dev, size, &paddr, GFP_DMA); 5285e3dd157SKalle Valo if (!vaddr) 5295e3dd157SKalle Valo goto err_dma_ring; 5305e3dd157SKalle Valo 5315e3dd157SKalle Valo htt->rx_ring.paddrs_ring = vaddr; 5325e3dd157SKalle Valo htt->rx_ring.base_paddr = paddr; 5335e3dd157SKalle Valo 5345e3dd157SKalle Valo vaddr = dma_alloc_coherent(htt->ar->dev, 5355e3dd157SKalle Valo sizeof(*htt->rx_ring.alloc_idx.vaddr), 5365e3dd157SKalle Valo &paddr, GFP_DMA); 5375e3dd157SKalle Valo if (!vaddr) 5385e3dd157SKalle Valo goto err_dma_idx; 5395e3dd157SKalle Valo 5405e3dd157SKalle Valo htt->rx_ring.alloc_idx.vaddr = vaddr; 5415e3dd157SKalle Valo htt->rx_ring.alloc_idx.paddr = paddr; 5425e3dd157SKalle Valo htt->rx_ring.sw_rd_idx.msdu_payld = 0; 5435e3dd157SKalle Valo *htt->rx_ring.alloc_idx.vaddr = 0; 5445e3dd157SKalle Valo 5455e3dd157SKalle Valo /* Initialize the Rx refill retry timer */ 5465e3dd157SKalle Valo setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt); 5475e3dd157SKalle Valo 5485e3dd157SKalle Valo spin_lock_init(&htt->rx_ring.lock); 5495e3dd157SKalle Valo 5505e3dd157SKalle Valo htt->rx_ring.fill_cnt = 0; 5515e3dd157SKalle Valo if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level)) 5525e3dd157SKalle Valo goto err_fill_ring; 5535e3dd157SKalle Valo 5546e712d42SMichal Kazior tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task, 5556e712d42SMichal Kazior (unsigned long)htt); 5566e712d42SMichal Kazior 5576c5151a9SMichal Kazior skb_queue_head_init(&htt->tx_compl_q); 5586c5151a9SMichal Kazior skb_queue_head_init(&htt->rx_compl_q); 5596c5151a9SMichal Kazior 5606c5151a9SMichal Kazior tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task, 5616c5151a9SMichal Kazior (unsigned long)htt); 5626c5151a9SMichal Kazior 5637aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n", 5645e3dd157SKalle Valo htt->rx_ring.size, htt->rx_ring.fill_level); 5655e3dd157SKalle Valo return 0; 5665e3dd157SKalle Valo 5675e3dd157SKalle Valo err_fill_ring: 5685e3dd157SKalle Valo ath10k_htt_rx_ring_free(htt); 5695e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 5705e3dd157SKalle Valo sizeof(*htt->rx_ring.alloc_idx.vaddr), 5715e3dd157SKalle Valo htt->rx_ring.alloc_idx.vaddr, 5725e3dd157SKalle Valo htt->rx_ring.alloc_idx.paddr); 5735e3dd157SKalle Valo err_dma_idx: 5745e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 5755e3dd157SKalle Valo (htt->rx_ring.size * 5765e3dd157SKalle Valo sizeof(htt->rx_ring.paddrs_ring)), 5775e3dd157SKalle Valo htt->rx_ring.paddrs_ring, 5785e3dd157SKalle Valo htt->rx_ring.base_paddr); 5795e3dd157SKalle Valo err_dma_ring: 5805e3dd157SKalle Valo kfree(htt->rx_ring.netbufs_ring); 5815e3dd157SKalle Valo err_netbuf: 5825e3dd157SKalle Valo return -ENOMEM; 5835e3dd157SKalle Valo } 5845e3dd157SKalle Valo 5857aa7a72aSMichal Kazior static int ath10k_htt_rx_crypto_param_len(struct ath10k *ar, 5867aa7a72aSMichal Kazior enum htt_rx_mpdu_encrypt_type type) 5875e3dd157SKalle Valo { 5885e3dd157SKalle Valo switch (type) { 589890d3b2aSMichal Kazior case HTT_RX_MPDU_ENCRYPT_NONE: 590890d3b2aSMichal Kazior return 0; 5915e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP40: 5925e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP104: 593890d3b2aSMichal Kazior return IEEE80211_WEP_IV_LEN; 5945e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC: 5955e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WPA: 596890d3b2aSMichal Kazior return IEEE80211_TKIP_IV_LEN; 5975e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2: 598890d3b2aSMichal Kazior return IEEE80211_CCMP_HDR_LEN; 599890d3b2aSMichal Kazior case HTT_RX_MPDU_ENCRYPT_WEP128: 600890d3b2aSMichal Kazior case HTT_RX_MPDU_ENCRYPT_WAPI: 601890d3b2aSMichal Kazior break; 602890d3b2aSMichal Kazior } 603890d3b2aSMichal Kazior 604890d3b2aSMichal Kazior ath10k_warn(ar, "unsupported encryption type %d\n", type); 6055e3dd157SKalle Valo return 0; 6065e3dd157SKalle Valo } 6075e3dd157SKalle Valo 608890d3b2aSMichal Kazior #define MICHAEL_MIC_LEN 8 6095e3dd157SKalle Valo 6107aa7a72aSMichal Kazior static int ath10k_htt_rx_crypto_tail_len(struct ath10k *ar, 6117aa7a72aSMichal Kazior enum htt_rx_mpdu_encrypt_type type) 6125e3dd157SKalle Valo { 6135e3dd157SKalle Valo switch (type) { 6145e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_NONE: 615890d3b2aSMichal Kazior return 0; 6165e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP40: 6175e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP104: 618890d3b2aSMichal Kazior return IEEE80211_WEP_ICV_LEN; 6195e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC: 6205e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WPA: 621890d3b2aSMichal Kazior return IEEE80211_TKIP_ICV_LEN; 6225e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2: 623890d3b2aSMichal Kazior return IEEE80211_CCMP_MIC_LEN; 624890d3b2aSMichal Kazior case HTT_RX_MPDU_ENCRYPT_WEP128: 625890d3b2aSMichal Kazior case HTT_RX_MPDU_ENCRYPT_WAPI: 626890d3b2aSMichal Kazior break; 6275e3dd157SKalle Valo } 6285e3dd157SKalle Valo 629890d3b2aSMichal Kazior ath10k_warn(ar, "unsupported encryption type %d\n", type); 6305e3dd157SKalle Valo return 0; 6315e3dd157SKalle Valo } 6325e3dd157SKalle Valo 6335e3dd157SKalle Valo /* Applies for first msdu in chain, before altering it. */ 6345e3dd157SKalle Valo static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb) 6355e3dd157SKalle Valo { 6365e3dd157SKalle Valo struct htt_rx_desc *rxd; 6375e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 6385e3dd157SKalle Valo 6395e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 6405e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 6415e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 6425e3dd157SKalle Valo 6435e3dd157SKalle Valo if (fmt == RX_MSDU_DECAP_RAW) 6445e3dd157SKalle Valo return (void *)skb->data; 645d8bb26b9SKalle Valo 6465e3dd157SKalle Valo return (void *)skb->data - RX_HTT_HDR_STATUS_LEN; 6475e3dd157SKalle Valo } 6485e3dd157SKalle Valo 6495e3dd157SKalle Valo /* This function only applies for first msdu in an msdu chain */ 6505e3dd157SKalle Valo static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr) 6515e3dd157SKalle Valo { 652af762c0bSKalle Valo u8 *qc; 653af762c0bSKalle Valo 6545e3dd157SKalle Valo if (ieee80211_is_data_qos(hdr->frame_control)) { 655af762c0bSKalle Valo qc = ieee80211_get_qos_ctl(hdr); 6565e3dd157SKalle Valo if (qc[0] & 0x80) 6575e3dd157SKalle Valo return true; 6585e3dd157SKalle Valo } 6595e3dd157SKalle Valo return false; 6605e3dd157SKalle Valo } 6615e3dd157SKalle Valo 662f6dc2095SMichal Kazior struct rfc1042_hdr { 663f6dc2095SMichal Kazior u8 llc_dsap; 664f6dc2095SMichal Kazior u8 llc_ssap; 665f6dc2095SMichal Kazior u8 llc_ctrl; 666f6dc2095SMichal Kazior u8 snap_oui[3]; 667f6dc2095SMichal Kazior __be16 snap_type; 668f6dc2095SMichal Kazior } __packed; 669f6dc2095SMichal Kazior 670f6dc2095SMichal Kazior struct amsdu_subframe_hdr { 671f6dc2095SMichal Kazior u8 dst[ETH_ALEN]; 672f6dc2095SMichal Kazior u8 src[ETH_ALEN]; 673f6dc2095SMichal Kazior __be16 len; 674f6dc2095SMichal Kazior } __packed; 675f6dc2095SMichal Kazior 67673539b40SJanusz Dziedzic static const u8 rx_legacy_rate_idx[] = { 67773539b40SJanusz Dziedzic 3, /* 0x00 - 11Mbps */ 67873539b40SJanusz Dziedzic 2, /* 0x01 - 5.5Mbps */ 67973539b40SJanusz Dziedzic 1, /* 0x02 - 2Mbps */ 68073539b40SJanusz Dziedzic 0, /* 0x03 - 1Mbps */ 68173539b40SJanusz Dziedzic 3, /* 0x04 - 11Mbps */ 68273539b40SJanusz Dziedzic 2, /* 0x05 - 5.5Mbps */ 68373539b40SJanusz Dziedzic 1, /* 0x06 - 2Mbps */ 68473539b40SJanusz Dziedzic 0, /* 0x07 - 1Mbps */ 68573539b40SJanusz Dziedzic 10, /* 0x08 - 48Mbps */ 68673539b40SJanusz Dziedzic 8, /* 0x09 - 24Mbps */ 68773539b40SJanusz Dziedzic 6, /* 0x0A - 12Mbps */ 68873539b40SJanusz Dziedzic 4, /* 0x0B - 6Mbps */ 68973539b40SJanusz Dziedzic 11, /* 0x0C - 54Mbps */ 69073539b40SJanusz Dziedzic 9, /* 0x0D - 36Mbps */ 69173539b40SJanusz Dziedzic 7, /* 0x0E - 18Mbps */ 69273539b40SJanusz Dziedzic 5, /* 0x0F - 9Mbps */ 69373539b40SJanusz Dziedzic }; 69473539b40SJanusz Dziedzic 69587326c97SJanusz Dziedzic static void ath10k_htt_rx_h_rates(struct ath10k *ar, 69673539b40SJanusz Dziedzic enum ieee80211_band band, 69787326c97SJanusz Dziedzic u8 info0, u32 info1, u32 info2, 69873539b40SJanusz Dziedzic struct ieee80211_rx_status *status) 69973539b40SJanusz Dziedzic { 70073539b40SJanusz Dziedzic u8 cck, rate, rate_idx, bw, sgi, mcs, nss; 70173539b40SJanusz Dziedzic u8 preamble = 0; 70273539b40SJanusz Dziedzic 70373539b40SJanusz Dziedzic /* Check if valid fields */ 70473539b40SJanusz Dziedzic if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID)) 70573539b40SJanusz Dziedzic return; 70673539b40SJanusz Dziedzic 70773539b40SJanusz Dziedzic preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE); 70873539b40SJanusz Dziedzic 70973539b40SJanusz Dziedzic switch (preamble) { 71073539b40SJanusz Dziedzic case HTT_RX_LEGACY: 71173539b40SJanusz Dziedzic cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK; 71273539b40SJanusz Dziedzic rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE); 71373539b40SJanusz Dziedzic rate_idx = 0; 71473539b40SJanusz Dziedzic 71573539b40SJanusz Dziedzic if (rate < 0x08 || rate > 0x0F) 71673539b40SJanusz Dziedzic break; 71773539b40SJanusz Dziedzic 71873539b40SJanusz Dziedzic switch (band) { 71973539b40SJanusz Dziedzic case IEEE80211_BAND_2GHZ: 72073539b40SJanusz Dziedzic if (cck) 72173539b40SJanusz Dziedzic rate &= ~BIT(3); 72273539b40SJanusz Dziedzic rate_idx = rx_legacy_rate_idx[rate]; 72373539b40SJanusz Dziedzic break; 72473539b40SJanusz Dziedzic case IEEE80211_BAND_5GHZ: 72573539b40SJanusz Dziedzic rate_idx = rx_legacy_rate_idx[rate]; 72673539b40SJanusz Dziedzic /* We are using same rate table registering 72773539b40SJanusz Dziedzic HW - ath10k_rates[]. In case of 5GHz skip 72873539b40SJanusz Dziedzic CCK rates, so -4 here */ 72973539b40SJanusz Dziedzic rate_idx -= 4; 73073539b40SJanusz Dziedzic break; 73173539b40SJanusz Dziedzic default: 73273539b40SJanusz Dziedzic break; 73373539b40SJanusz Dziedzic } 73473539b40SJanusz Dziedzic 73573539b40SJanusz Dziedzic status->rate_idx = rate_idx; 73673539b40SJanusz Dziedzic break; 73773539b40SJanusz Dziedzic case HTT_RX_HT: 73873539b40SJanusz Dziedzic case HTT_RX_HT_WITH_TXBF: 73973539b40SJanusz Dziedzic /* HT-SIG - Table 20-11 in info1 and info2 */ 74073539b40SJanusz Dziedzic mcs = info1 & 0x1F; 74173539b40SJanusz Dziedzic nss = mcs >> 3; 74273539b40SJanusz Dziedzic bw = (info1 >> 7) & 1; 74373539b40SJanusz Dziedzic sgi = (info2 >> 7) & 1; 74473539b40SJanusz Dziedzic 74573539b40SJanusz Dziedzic status->rate_idx = mcs; 74673539b40SJanusz Dziedzic status->flag |= RX_FLAG_HT; 74773539b40SJanusz Dziedzic if (sgi) 74873539b40SJanusz Dziedzic status->flag |= RX_FLAG_SHORT_GI; 74973539b40SJanusz Dziedzic if (bw) 75073539b40SJanusz Dziedzic status->flag |= RX_FLAG_40MHZ; 75173539b40SJanusz Dziedzic break; 75273539b40SJanusz Dziedzic case HTT_RX_VHT: 75373539b40SJanusz Dziedzic case HTT_RX_VHT_WITH_TXBF: 75473539b40SJanusz Dziedzic /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2 75573539b40SJanusz Dziedzic TODO check this */ 75673539b40SJanusz Dziedzic mcs = (info2 >> 4) & 0x0F; 75773539b40SJanusz Dziedzic nss = ((info1 >> 10) & 0x07) + 1; 75873539b40SJanusz Dziedzic bw = info1 & 3; 75973539b40SJanusz Dziedzic sgi = info2 & 1; 76073539b40SJanusz Dziedzic 76173539b40SJanusz Dziedzic status->rate_idx = mcs; 76273539b40SJanusz Dziedzic status->vht_nss = nss; 76373539b40SJanusz Dziedzic 76473539b40SJanusz Dziedzic if (sgi) 76573539b40SJanusz Dziedzic status->flag |= RX_FLAG_SHORT_GI; 76673539b40SJanusz Dziedzic 76773539b40SJanusz Dziedzic switch (bw) { 76873539b40SJanusz Dziedzic /* 20MHZ */ 76973539b40SJanusz Dziedzic case 0: 77073539b40SJanusz Dziedzic break; 77173539b40SJanusz Dziedzic /* 40MHZ */ 77273539b40SJanusz Dziedzic case 1: 77373539b40SJanusz Dziedzic status->flag |= RX_FLAG_40MHZ; 77473539b40SJanusz Dziedzic break; 77573539b40SJanusz Dziedzic /* 80MHZ */ 77673539b40SJanusz Dziedzic case 2: 77773539b40SJanusz Dziedzic status->vht_flag |= RX_VHT_FLAG_80MHZ; 77873539b40SJanusz Dziedzic } 77973539b40SJanusz Dziedzic 78073539b40SJanusz Dziedzic status->flag |= RX_FLAG_VHT; 78173539b40SJanusz Dziedzic break; 78273539b40SJanusz Dziedzic default: 78373539b40SJanusz Dziedzic break; 78473539b40SJanusz Dziedzic } 78573539b40SJanusz Dziedzic } 78673539b40SJanusz Dziedzic 78787326c97SJanusz Dziedzic static void ath10k_htt_rx_h_protected(struct ath10k_htt *htt, 78885f6d7cfSJanusz Dziedzic struct ieee80211_rx_status *rx_status, 78985f6d7cfSJanusz Dziedzic struct sk_buff *skb, 790c071dcb2SMichal Kazior enum htt_rx_mpdu_encrypt_type enctype, 791c071dcb2SMichal Kazior enum rx_msdu_decap_format fmt, 792c071dcb2SMichal Kazior bool dot11frag) 79387326c97SJanusz Dziedzic { 79485f6d7cfSJanusz Dziedzic struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 79587326c97SJanusz Dziedzic 79685f6d7cfSJanusz Dziedzic rx_status->flag &= ~(RX_FLAG_DECRYPTED | 79787326c97SJanusz Dziedzic RX_FLAG_IV_STRIPPED | 79887326c97SJanusz Dziedzic RX_FLAG_MMIC_STRIPPED); 799c071dcb2SMichal Kazior 800c071dcb2SMichal Kazior if (enctype == HTT_RX_MPDU_ENCRYPT_NONE) 80187326c97SJanusz Dziedzic return; 802c071dcb2SMichal Kazior 803c071dcb2SMichal Kazior /* 804c071dcb2SMichal Kazior * There's no explicit rx descriptor flag to indicate whether a given 805c071dcb2SMichal Kazior * frame has been decrypted or not. We're forced to use the decap 806c071dcb2SMichal Kazior * format as an implicit indication. However fragmentation rx is always 807c071dcb2SMichal Kazior * raw and it probably never reports undecrypted raws. 808c071dcb2SMichal Kazior * 809c071dcb2SMichal Kazior * This makes sure sniffed frames are reported as-is without stripping 810c071dcb2SMichal Kazior * the protected flag. 811c071dcb2SMichal Kazior */ 812c071dcb2SMichal Kazior if (fmt == RX_MSDU_DECAP_RAW && !dot11frag) 813c071dcb2SMichal Kazior return; 81487326c97SJanusz Dziedzic 81585f6d7cfSJanusz Dziedzic rx_status->flag |= RX_FLAG_DECRYPTED | 81687326c97SJanusz Dziedzic RX_FLAG_IV_STRIPPED | 81787326c97SJanusz Dziedzic RX_FLAG_MMIC_STRIPPED; 81887326c97SJanusz Dziedzic hdr->frame_control = __cpu_to_le16(__le16_to_cpu(hdr->frame_control) & 81987326c97SJanusz Dziedzic ~IEEE80211_FCTL_PROTECTED); 82087326c97SJanusz Dziedzic } 82187326c97SJanusz Dziedzic 82236653f05SJanusz Dziedzic static bool ath10k_htt_rx_h_channel(struct ath10k *ar, 82336653f05SJanusz Dziedzic struct ieee80211_rx_status *status) 82436653f05SJanusz Dziedzic { 82536653f05SJanusz Dziedzic struct ieee80211_channel *ch; 82636653f05SJanusz Dziedzic 82736653f05SJanusz Dziedzic spin_lock_bh(&ar->data_lock); 82836653f05SJanusz Dziedzic ch = ar->scan_channel; 82936653f05SJanusz Dziedzic if (!ch) 83036653f05SJanusz Dziedzic ch = ar->rx_channel; 83136653f05SJanusz Dziedzic spin_unlock_bh(&ar->data_lock); 83236653f05SJanusz Dziedzic 83336653f05SJanusz Dziedzic if (!ch) 83436653f05SJanusz Dziedzic return false; 83536653f05SJanusz Dziedzic 83636653f05SJanusz Dziedzic status->band = ch->band; 83736653f05SJanusz Dziedzic status->freq = ch->center_freq; 83836653f05SJanusz Dziedzic 83936653f05SJanusz Dziedzic return true; 84036653f05SJanusz Dziedzic } 84136653f05SJanusz Dziedzic 84276f5329aSJanusz Dziedzic static const char * const tid_to_ac[] = { 84376f5329aSJanusz Dziedzic "BE", 84476f5329aSJanusz Dziedzic "BK", 84576f5329aSJanusz Dziedzic "BK", 84676f5329aSJanusz Dziedzic "BE", 84776f5329aSJanusz Dziedzic "VI", 84876f5329aSJanusz Dziedzic "VI", 84976f5329aSJanusz Dziedzic "VO", 85076f5329aSJanusz Dziedzic "VO", 85176f5329aSJanusz Dziedzic }; 85276f5329aSJanusz Dziedzic 85376f5329aSJanusz Dziedzic static char *ath10k_get_tid(struct ieee80211_hdr *hdr, char *out, size_t size) 85476f5329aSJanusz Dziedzic { 85576f5329aSJanusz Dziedzic u8 *qc; 85676f5329aSJanusz Dziedzic int tid; 85776f5329aSJanusz Dziedzic 85876f5329aSJanusz Dziedzic if (!ieee80211_is_data_qos(hdr->frame_control)) 85976f5329aSJanusz Dziedzic return ""; 86076f5329aSJanusz Dziedzic 86176f5329aSJanusz Dziedzic qc = ieee80211_get_qos_ctl(hdr); 86276f5329aSJanusz Dziedzic tid = *qc & IEEE80211_QOS_CTL_TID_MASK; 86376f5329aSJanusz Dziedzic if (tid < 8) 86476f5329aSJanusz Dziedzic snprintf(out, size, "tid %d (%s)", tid, tid_to_ac[tid]); 86576f5329aSJanusz Dziedzic else 86676f5329aSJanusz Dziedzic snprintf(out, size, "tid %d", tid); 86776f5329aSJanusz Dziedzic 86876f5329aSJanusz Dziedzic return out; 86976f5329aSJanusz Dziedzic } 87076f5329aSJanusz Dziedzic 87185f6d7cfSJanusz Dziedzic static void ath10k_process_rx(struct ath10k *ar, 87285f6d7cfSJanusz Dziedzic struct ieee80211_rx_status *rx_status, 87385f6d7cfSJanusz Dziedzic struct sk_buff *skb) 87473539b40SJanusz Dziedzic { 87573539b40SJanusz Dziedzic struct ieee80211_rx_status *status; 87676f5329aSJanusz Dziedzic struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 87776f5329aSJanusz Dziedzic char tid[32]; 87873539b40SJanusz Dziedzic 87985f6d7cfSJanusz Dziedzic status = IEEE80211_SKB_RXCB(skb); 88085f6d7cfSJanusz Dziedzic *status = *rx_status; 88173539b40SJanusz Dziedzic 8827aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_DATA, 88376f5329aSJanusz Dziedzic "rx skb %p len %u peer %pM %s %s sn %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 88485f6d7cfSJanusz Dziedzic skb, 88585f6d7cfSJanusz Dziedzic skb->len, 88676f5329aSJanusz Dziedzic ieee80211_get_SA(hdr), 88776f5329aSJanusz Dziedzic ath10k_get_tid(hdr, tid, sizeof(tid)), 88876f5329aSJanusz Dziedzic is_multicast_ether_addr(ieee80211_get_DA(hdr)) ? 88976f5329aSJanusz Dziedzic "mcast" : "ucast", 89076f5329aSJanusz Dziedzic (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4, 89173539b40SJanusz Dziedzic status->flag == 0 ? "legacy" : "", 89273539b40SJanusz Dziedzic status->flag & RX_FLAG_HT ? "ht" : "", 89373539b40SJanusz Dziedzic status->flag & RX_FLAG_VHT ? "vht" : "", 89473539b40SJanusz Dziedzic status->flag & RX_FLAG_40MHZ ? "40" : "", 89573539b40SJanusz Dziedzic status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "", 89673539b40SJanusz Dziedzic status->flag & RX_FLAG_SHORT_GI ? "sgi " : "", 89773539b40SJanusz Dziedzic status->rate_idx, 89873539b40SJanusz Dziedzic status->vht_nss, 89973539b40SJanusz Dziedzic status->freq, 90087326c97SJanusz Dziedzic status->band, status->flag, 90178433f96SJanusz Dziedzic !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 90276f5329aSJanusz Dziedzic !!(status->flag & RX_FLAG_MMIC_ERROR), 90376f5329aSJanusz Dziedzic !!(status->flag & RX_FLAG_AMSDU_MORE)); 9047aa7a72aSMichal Kazior ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ", 90585f6d7cfSJanusz Dziedzic skb->data, skb->len); 90673539b40SJanusz Dziedzic 90785f6d7cfSJanusz Dziedzic ieee80211_rx(ar->hw, skb); 90873539b40SJanusz Dziedzic } 90973539b40SJanusz Dziedzic 910d960c369SMichal Kazior static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr) 911d960c369SMichal Kazior { 912d960c369SMichal Kazior /* nwifi header is padded to 4 bytes. this fixes 4addr rx */ 913d960c369SMichal Kazior return round_up(ieee80211_hdrlen(hdr->frame_control), 4); 914d960c369SMichal Kazior } 915d960c369SMichal Kazior 916f6dc2095SMichal Kazior static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt, 91785f6d7cfSJanusz Dziedzic struct ieee80211_rx_status *rx_status, 91885f6d7cfSJanusz Dziedzic struct sk_buff *skb_in) 9195e3dd157SKalle Valo { 9207aa7a72aSMichal Kazior struct ath10k *ar = htt->ar; 9215e3dd157SKalle Valo struct htt_rx_desc *rxd; 92285f6d7cfSJanusz Dziedzic struct sk_buff *skb = skb_in; 9235e3dd157SKalle Valo struct sk_buff *first; 9245e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 9255e3dd157SKalle Valo enum htt_rx_mpdu_encrypt_type enctype; 926f6dc2095SMichal Kazior struct ieee80211_hdr *hdr; 92772bdeb86SMichal Kazior u8 hdr_buf[64], da[ETH_ALEN], sa[ETH_ALEN], *qos; 9285e3dd157SKalle Valo unsigned int hdr_len; 9295e3dd157SKalle Valo 9305e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 9315e3dd157SKalle Valo enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), 9325e3dd157SKalle Valo RX_MPDU_START_INFO0_ENCRYPT_TYPE); 9335e3dd157SKalle Valo 934f6dc2095SMichal Kazior hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; 935f6dc2095SMichal Kazior hdr_len = ieee80211_hdrlen(hdr->frame_control); 936f6dc2095SMichal Kazior memcpy(hdr_buf, hdr, hdr_len); 937f6dc2095SMichal Kazior hdr = (struct ieee80211_hdr *)hdr_buf; 9385e3dd157SKalle Valo 9395e3dd157SKalle Valo first = skb; 9405e3dd157SKalle Valo while (skb) { 9415e3dd157SKalle Valo void *decap_hdr; 942f6dc2095SMichal Kazior int len; 9435e3dd157SKalle Valo 9445e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 9455e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 9465e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 9475e3dd157SKalle Valo decap_hdr = (void *)rxd->rx_hdr_status; 9485e3dd157SKalle Valo 949f6dc2095SMichal Kazior skb->ip_summed = ath10k_htt_rx_get_csum_state(skb); 950f6dc2095SMichal Kazior 951f6dc2095SMichal Kazior /* First frame in an A-MSDU chain has more decapped data. */ 9525e3dd157SKalle Valo if (skb == first) { 953f6dc2095SMichal Kazior len = round_up(ieee80211_hdrlen(hdr->frame_control), 4); 9547aa7a72aSMichal Kazior len += round_up(ath10k_htt_rx_crypto_param_len(ar, 9557aa7a72aSMichal Kazior enctype), 4); 956f6dc2095SMichal Kazior decap_hdr += len; 9575e3dd157SKalle Valo } 9585e3dd157SKalle Valo 959f6dc2095SMichal Kazior switch (fmt) { 960f6dc2095SMichal Kazior case RX_MSDU_DECAP_RAW: 961e3fbf8d2SMichal Kazior /* remove trailing FCS */ 962f6dc2095SMichal Kazior skb_trim(skb, skb->len - FCS_LEN); 963f6dc2095SMichal Kazior break; 964f6dc2095SMichal Kazior case RX_MSDU_DECAP_NATIVE_WIFI: 96572bdeb86SMichal Kazior /* pull decapped header and copy SA & DA */ 966784f69d3SMichal Kazior hdr = (struct ieee80211_hdr *)skb->data; 967d960c369SMichal Kazior hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr); 968b25f32cbSKalle Valo ether_addr_copy(da, ieee80211_get_DA(hdr)); 969b25f32cbSKalle Valo ether_addr_copy(sa, ieee80211_get_SA(hdr)); 970784f69d3SMichal Kazior skb_pull(skb, hdr_len); 971784f69d3SMichal Kazior 972784f69d3SMichal Kazior /* push original 802.11 header */ 973784f69d3SMichal Kazior hdr = (struct ieee80211_hdr *)hdr_buf; 974784f69d3SMichal Kazior hdr_len = ieee80211_hdrlen(hdr->frame_control); 975784f69d3SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 976784f69d3SMichal Kazior 977784f69d3SMichal Kazior /* original A-MSDU header has the bit set but we're 978784f69d3SMichal Kazior * not including A-MSDU subframe header */ 979784f69d3SMichal Kazior hdr = (struct ieee80211_hdr *)skb->data; 980784f69d3SMichal Kazior qos = ieee80211_get_qos_ctl(hdr); 981784f69d3SMichal Kazior qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 982784f69d3SMichal Kazior 98372bdeb86SMichal Kazior /* original 802.11 header has a different DA and in 98472bdeb86SMichal Kazior * case of 4addr it may also have different SA 98572bdeb86SMichal Kazior */ 986b25f32cbSKalle Valo ether_addr_copy(ieee80211_get_DA(hdr), da); 987b25f32cbSKalle Valo ether_addr_copy(ieee80211_get_SA(hdr), sa); 988f6dc2095SMichal Kazior break; 989f6dc2095SMichal Kazior case RX_MSDU_DECAP_ETHERNET2_DIX: 990e3fbf8d2SMichal Kazior /* strip ethernet header and insert decapped 802.11 991e3fbf8d2SMichal Kazior * header, amsdu subframe header and rfc1042 header */ 992e3fbf8d2SMichal Kazior 993f6dc2095SMichal Kazior len = 0; 994f6dc2095SMichal Kazior len += sizeof(struct rfc1042_hdr); 995f6dc2095SMichal Kazior len += sizeof(struct amsdu_subframe_hdr); 996dfa95b50SMichal Kazior 997f6dc2095SMichal Kazior skb_pull(skb, sizeof(struct ethhdr)); 998f6dc2095SMichal Kazior memcpy(skb_push(skb, len), decap_hdr, len); 999f6dc2095SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 1000f6dc2095SMichal Kazior break; 1001f6dc2095SMichal Kazior case RX_MSDU_DECAP_8023_SNAP_LLC: 1002e3fbf8d2SMichal Kazior /* insert decapped 802.11 header making a singly 1003e3fbf8d2SMichal Kazior * A-MSDU */ 1004f6dc2095SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 1005f6dc2095SMichal Kazior break; 10065e3dd157SKalle Valo } 10075e3dd157SKalle Valo 100885f6d7cfSJanusz Dziedzic skb_in = skb; 1009c071dcb2SMichal Kazior ath10k_htt_rx_h_protected(htt, rx_status, skb_in, enctype, fmt, 1010c071dcb2SMichal Kazior false); 1011f6dc2095SMichal Kazior skb = skb->next; 101285f6d7cfSJanusz Dziedzic skb_in->next = NULL; 10135e3dd157SKalle Valo 1014652de35eSKalle Valo if (skb) 101585f6d7cfSJanusz Dziedzic rx_status->flag |= RX_FLAG_AMSDU_MORE; 101687326c97SJanusz Dziedzic else 101785f6d7cfSJanusz Dziedzic rx_status->flag &= ~RX_FLAG_AMSDU_MORE; 1018652de35eSKalle Valo 101985f6d7cfSJanusz Dziedzic ath10k_process_rx(htt->ar, rx_status, skb_in); 10205e3dd157SKalle Valo } 10215e3dd157SKalle Valo 1022f6dc2095SMichal Kazior /* FIXME: It might be nice to re-assemble the A-MSDU when there's a 1023f6dc2095SMichal Kazior * monitor interface active for sniffing purposes. */ 1024f6dc2095SMichal Kazior } 1025f6dc2095SMichal Kazior 102685f6d7cfSJanusz Dziedzic static void ath10k_htt_rx_msdu(struct ath10k_htt *htt, 102785f6d7cfSJanusz Dziedzic struct ieee80211_rx_status *rx_status, 102885f6d7cfSJanusz Dziedzic struct sk_buff *skb) 10295e3dd157SKalle Valo { 10307aa7a72aSMichal Kazior struct ath10k *ar = htt->ar; 10315e3dd157SKalle Valo struct htt_rx_desc *rxd; 10325e3dd157SKalle Valo struct ieee80211_hdr *hdr; 10335e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 10345e3dd157SKalle Valo enum htt_rx_mpdu_encrypt_type enctype; 1035e3fbf8d2SMichal Kazior int hdr_len; 1036e3fbf8d2SMichal Kazior void *rfc1042; 10375e3dd157SKalle Valo 10385e3dd157SKalle Valo /* This shouldn't happen. If it does than it may be a FW bug. */ 10395e3dd157SKalle Valo if (skb->next) { 10407aa7a72aSMichal Kazior ath10k_warn(ar, "htt rx received chained non A-MSDU frame\n"); 10415e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(skb->next); 10425e3dd157SKalle Valo skb->next = NULL; 10435e3dd157SKalle Valo } 10445e3dd157SKalle Valo 10455e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 10465e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 10475e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 10485e3dd157SKalle Valo enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), 10495e3dd157SKalle Valo RX_MPDU_START_INFO0_ENCRYPT_TYPE); 1050e3fbf8d2SMichal Kazior hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; 1051e3fbf8d2SMichal Kazior hdr_len = ieee80211_hdrlen(hdr->frame_control); 10525e3dd157SKalle Valo 1053f6dc2095SMichal Kazior skb->ip_summed = ath10k_htt_rx_get_csum_state(skb); 1054f6dc2095SMichal Kazior 10555e3dd157SKalle Valo switch (fmt) { 10565e3dd157SKalle Valo case RX_MSDU_DECAP_RAW: 10575e3dd157SKalle Valo /* remove trailing FCS */ 1058e3fbf8d2SMichal Kazior skb_trim(skb, skb->len - FCS_LEN); 10595e3dd157SKalle Valo break; 10605e3dd157SKalle Valo case RX_MSDU_DECAP_NATIVE_WIFI: 1061784f69d3SMichal Kazior /* Pull decapped header */ 1062784f69d3SMichal Kazior hdr = (struct ieee80211_hdr *)skb->data; 1063d960c369SMichal Kazior hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr); 1064784f69d3SMichal Kazior skb_pull(skb, hdr_len); 1065784f69d3SMichal Kazior 1066784f69d3SMichal Kazior /* Push original header */ 1067784f69d3SMichal Kazior hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; 1068784f69d3SMichal Kazior hdr_len = ieee80211_hdrlen(hdr->frame_control); 1069784f69d3SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 10705e3dd157SKalle Valo break; 10715e3dd157SKalle Valo case RX_MSDU_DECAP_ETHERNET2_DIX: 1072e3fbf8d2SMichal Kazior /* strip ethernet header and insert decapped 802.11 header and 1073e3fbf8d2SMichal Kazior * rfc1042 header */ 1074e3fbf8d2SMichal Kazior 1075e3fbf8d2SMichal Kazior rfc1042 = hdr; 1076e3fbf8d2SMichal Kazior rfc1042 += roundup(hdr_len, 4); 10777aa7a72aSMichal Kazior rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(ar, 10787aa7a72aSMichal Kazior enctype), 4); 1079e3fbf8d2SMichal Kazior 1080e3fbf8d2SMichal Kazior skb_pull(skb, sizeof(struct ethhdr)); 1081e3fbf8d2SMichal Kazior memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)), 1082e3fbf8d2SMichal Kazior rfc1042, sizeof(struct rfc1042_hdr)); 1083e3fbf8d2SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 10845e3dd157SKalle Valo break; 10855e3dd157SKalle Valo case RX_MSDU_DECAP_8023_SNAP_LLC: 1086e3fbf8d2SMichal Kazior /* remove A-MSDU subframe header and insert 1087e3fbf8d2SMichal Kazior * decapped 802.11 header. rfc1042 header is already there */ 1088e3fbf8d2SMichal Kazior 1089e3fbf8d2SMichal Kazior skb_pull(skb, sizeof(struct amsdu_subframe_hdr)); 1090e3fbf8d2SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 10915e3dd157SKalle Valo break; 10925e3dd157SKalle Valo } 10935e3dd157SKalle Valo 1094c071dcb2SMichal Kazior ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype, fmt, false); 1095f6dc2095SMichal Kazior 109685f6d7cfSJanusz Dziedzic ath10k_process_rx(htt->ar, rx_status, skb); 10975e3dd157SKalle Valo } 10985e3dd157SKalle Valo 1099605f81aaSMichal Kazior static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb) 1100605f81aaSMichal Kazior { 1101605f81aaSMichal Kazior struct htt_rx_desc *rxd; 1102605f81aaSMichal Kazior u32 flags, info; 1103605f81aaSMichal Kazior bool is_ip4, is_ip6; 1104605f81aaSMichal Kazior bool is_tcp, is_udp; 1105605f81aaSMichal Kazior bool ip_csum_ok, tcpudp_csum_ok; 1106605f81aaSMichal Kazior 1107605f81aaSMichal Kazior rxd = (void *)skb->data - sizeof(*rxd); 1108605f81aaSMichal Kazior flags = __le32_to_cpu(rxd->attention.flags); 1109605f81aaSMichal Kazior info = __le32_to_cpu(rxd->msdu_start.info1); 1110605f81aaSMichal Kazior 1111605f81aaSMichal Kazior is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO); 1112605f81aaSMichal Kazior is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO); 1113605f81aaSMichal Kazior is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO); 1114605f81aaSMichal Kazior is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO); 1115605f81aaSMichal Kazior ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL); 1116605f81aaSMichal Kazior tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL); 1117605f81aaSMichal Kazior 1118605f81aaSMichal Kazior if (!is_ip4 && !is_ip6) 1119605f81aaSMichal Kazior return CHECKSUM_NONE; 1120605f81aaSMichal Kazior if (!is_tcp && !is_udp) 1121605f81aaSMichal Kazior return CHECKSUM_NONE; 1122605f81aaSMichal Kazior if (!ip_csum_ok) 1123605f81aaSMichal Kazior return CHECKSUM_NONE; 1124605f81aaSMichal Kazior if (!tcpudp_csum_ok) 1125605f81aaSMichal Kazior return CHECKSUM_NONE; 1126605f81aaSMichal Kazior 1127605f81aaSMichal Kazior return CHECKSUM_UNNECESSARY; 1128605f81aaSMichal Kazior } 1129605f81aaSMichal Kazior 1130bfa35368SBen Greear static int ath10k_unchain_msdu(struct sk_buff *msdu_head) 1131bfa35368SBen Greear { 1132bfa35368SBen Greear struct sk_buff *next = msdu_head->next; 1133bfa35368SBen Greear struct sk_buff *to_free = next; 1134bfa35368SBen Greear int space; 1135bfa35368SBen Greear int total_len = 0; 1136bfa35368SBen Greear 1137bfa35368SBen Greear /* TODO: Might could optimize this by using 1138bfa35368SBen Greear * skb_try_coalesce or similar method to 1139bfa35368SBen Greear * decrease copying, or maybe get mac80211 to 1140bfa35368SBen Greear * provide a way to just receive a list of 1141bfa35368SBen Greear * skb? 1142bfa35368SBen Greear */ 1143bfa35368SBen Greear 1144bfa35368SBen Greear msdu_head->next = NULL; 1145bfa35368SBen Greear 1146bfa35368SBen Greear /* Allocate total length all at once. */ 1147bfa35368SBen Greear while (next) { 1148bfa35368SBen Greear total_len += next->len; 1149bfa35368SBen Greear next = next->next; 1150bfa35368SBen Greear } 1151bfa35368SBen Greear 1152bfa35368SBen Greear space = total_len - skb_tailroom(msdu_head); 1153bfa35368SBen Greear if ((space > 0) && 1154bfa35368SBen Greear (pskb_expand_head(msdu_head, 0, space, GFP_ATOMIC) < 0)) { 1155bfa35368SBen Greear /* TODO: bump some rx-oom error stat */ 1156bfa35368SBen Greear /* put it back together so we can free the 1157bfa35368SBen Greear * whole list at once. 1158bfa35368SBen Greear */ 1159bfa35368SBen Greear msdu_head->next = to_free; 1160bfa35368SBen Greear return -1; 1161bfa35368SBen Greear } 1162bfa35368SBen Greear 1163bfa35368SBen Greear /* Walk list again, copying contents into 1164bfa35368SBen Greear * msdu_head 1165bfa35368SBen Greear */ 1166bfa35368SBen Greear next = to_free; 1167bfa35368SBen Greear while (next) { 1168bfa35368SBen Greear skb_copy_from_linear_data(next, skb_put(msdu_head, next->len), 1169bfa35368SBen Greear next->len); 1170bfa35368SBen Greear next = next->next; 1171bfa35368SBen Greear } 1172bfa35368SBen Greear 1173bfa35368SBen Greear /* If here, we have consolidated skb. Free the 1174bfa35368SBen Greear * fragments and pass the main skb on up the 1175bfa35368SBen Greear * stack. 1176bfa35368SBen Greear */ 1177bfa35368SBen Greear ath10k_htt_rx_free_msdu_chain(to_free); 1178bfa35368SBen Greear return 0; 1179bfa35368SBen Greear } 1180bfa35368SBen Greear 11812acc4eb2SJanusz Dziedzic static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt, 11822acc4eb2SJanusz Dziedzic struct sk_buff *head, 118378433f96SJanusz Dziedzic bool channel_set, 118478433f96SJanusz Dziedzic u32 attention) 11852acc4eb2SJanusz Dziedzic { 11867aa7a72aSMichal Kazior struct ath10k *ar = htt->ar; 11877aa7a72aSMichal Kazior 11882acc4eb2SJanusz Dziedzic if (head->len == 0) { 11897aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, 11902acc4eb2SJanusz Dziedzic "htt rx dropping due to zero-len\n"); 11912acc4eb2SJanusz Dziedzic return false; 11922acc4eb2SJanusz Dziedzic } 11932acc4eb2SJanusz Dziedzic 119478433f96SJanusz Dziedzic if (attention & RX_ATTENTION_FLAGS_DECRYPT_ERR) { 11957aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, 11962acc4eb2SJanusz Dziedzic "htt rx dropping due to decrypt-err\n"); 11972acc4eb2SJanusz Dziedzic return false; 11982acc4eb2SJanusz Dziedzic } 11992acc4eb2SJanusz Dziedzic 120036653f05SJanusz Dziedzic if (!channel_set) { 12017aa7a72aSMichal Kazior ath10k_warn(ar, "no channel configured; ignoring frame!\n"); 120236653f05SJanusz Dziedzic return false; 120336653f05SJanusz Dziedzic } 120436653f05SJanusz Dziedzic 12052acc4eb2SJanusz Dziedzic /* Skip mgmt frames while we handle this in WMI */ 1206f6b946efSMichal Kazior if (attention & RX_ATTENTION_FLAGS_MGMT_TYPE) { 12077aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx mgmt ctrl\n"); 12082acc4eb2SJanusz Dziedzic return false; 12092acc4eb2SJanusz Dziedzic } 12102acc4eb2SJanusz Dziedzic 12112acc4eb2SJanusz Dziedzic if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) { 12127aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, 12132acc4eb2SJanusz Dziedzic "htt rx CAC running\n"); 12142acc4eb2SJanusz Dziedzic return false; 12152acc4eb2SJanusz Dziedzic } 12162acc4eb2SJanusz Dziedzic 12172acc4eb2SJanusz Dziedzic return true; 12182acc4eb2SJanusz Dziedzic } 12192acc4eb2SJanusz Dziedzic 12205e3dd157SKalle Valo static void ath10k_htt_rx_handler(struct ath10k_htt *htt, 12215e3dd157SKalle Valo struct htt_rx_indication *rx) 12225e3dd157SKalle Valo { 12237aa7a72aSMichal Kazior struct ath10k *ar = htt->ar; 12246df92a3dSJanusz Dziedzic struct ieee80211_rx_status *rx_status = &htt->rx_status; 12255e3dd157SKalle Valo struct htt_rx_indication_mpdu_range *mpdu_ranges; 12265e3dd157SKalle Valo struct ieee80211_hdr *hdr; 12275e3dd157SKalle Valo int num_mpdu_ranges; 122878433f96SJanusz Dziedzic u32 attention; 12295e3dd157SKalle Valo int fw_desc_len; 12305e3dd157SKalle Valo u8 *fw_desc; 123178433f96SJanusz Dziedzic bool channel_set; 12325e3dd157SKalle Valo int i, j; 1233d84dd60fSJanusz Dziedzic int ret; 12345e3dd157SKalle Valo 123545967089SMichal Kazior lockdep_assert_held(&htt->rx_ring.lock); 123645967089SMichal Kazior 12375e3dd157SKalle Valo fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes); 12385e3dd157SKalle Valo fw_desc = (u8 *)&rx->fw_desc; 12395e3dd157SKalle Valo 12405e3dd157SKalle Valo num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1), 12415e3dd157SKalle Valo HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES); 12425e3dd157SKalle Valo mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx); 12435e3dd157SKalle Valo 1244e8dc1a96SJanusz Dziedzic /* Fill this once, while this is per-ppdu */ 12452289188cSJanusz Dziedzic if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_START_VALID) { 12462289188cSJanusz Dziedzic memset(rx_status, 0, sizeof(*rx_status)); 12472289188cSJanusz Dziedzic rx_status->signal = ATH10K_DEFAULT_NOISE_FLOOR + 12482289188cSJanusz Dziedzic rx->ppdu.combined_rssi; 12492289188cSJanusz Dziedzic } 125087326c97SJanusz Dziedzic 125187326c97SJanusz Dziedzic if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_END_VALID) { 125287326c97SJanusz Dziedzic /* TSF available only in 32-bit */ 12536df92a3dSJanusz Dziedzic rx_status->mactime = __le32_to_cpu(rx->ppdu.tsf) & 0xffffffff; 12546df92a3dSJanusz Dziedzic rx_status->flag |= RX_FLAG_MACTIME_END; 125587326c97SJanusz Dziedzic } 1256e8dc1a96SJanusz Dziedzic 12576df92a3dSJanusz Dziedzic channel_set = ath10k_htt_rx_h_channel(htt->ar, rx_status); 125836653f05SJanusz Dziedzic 125987326c97SJanusz Dziedzic if (channel_set) { 12606df92a3dSJanusz Dziedzic ath10k_htt_rx_h_rates(htt->ar, rx_status->band, 126187326c97SJanusz Dziedzic rx->ppdu.info0, 126287326c97SJanusz Dziedzic __le32_to_cpu(rx->ppdu.info1), 126387326c97SJanusz Dziedzic __le32_to_cpu(rx->ppdu.info2), 12646df92a3dSJanusz Dziedzic rx_status); 126587326c97SJanusz Dziedzic } 1266e8dc1a96SJanusz Dziedzic 12677aa7a72aSMichal Kazior ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ", 12685e3dd157SKalle Valo rx, sizeof(*rx) + 12695e3dd157SKalle Valo (sizeof(struct htt_rx_indication_mpdu_range) * 12705e3dd157SKalle Valo num_mpdu_ranges)); 12715e3dd157SKalle Valo 12725e3dd157SKalle Valo for (i = 0; i < num_mpdu_ranges; i++) { 12735e3dd157SKalle Valo for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) { 12745e3dd157SKalle Valo struct sk_buff *msdu_head, *msdu_tail; 12755e3dd157SKalle Valo 12760ccb7a34SJanusz Dziedzic attention = 0; 12775e3dd157SKalle Valo msdu_head = NULL; 12785e3dd157SKalle Valo msdu_tail = NULL; 1279d84dd60fSJanusz Dziedzic ret = ath10k_htt_rx_amsdu_pop(htt, 12805e3dd157SKalle Valo &fw_desc, 12815e3dd157SKalle Valo &fw_desc_len, 12825e3dd157SKalle Valo &msdu_head, 12830ccb7a34SJanusz Dziedzic &msdu_tail, 12840ccb7a34SJanusz Dziedzic &attention); 12855e3dd157SKalle Valo 1286d84dd60fSJanusz Dziedzic if (ret < 0) { 12877aa7a72aSMichal Kazior ath10k_warn(ar, "failed to pop amsdu from htt rx ring %d\n", 1288d84dd60fSJanusz Dziedzic ret); 1289d84dd60fSJanusz Dziedzic ath10k_htt_rx_free_msdu_chain(msdu_head); 1290d84dd60fSJanusz Dziedzic continue; 1291d84dd60fSJanusz Dziedzic } 1292d84dd60fSJanusz Dziedzic 12932acc4eb2SJanusz Dziedzic if (!ath10k_htt_rx_amsdu_allowed(htt, msdu_head, 129478433f96SJanusz Dziedzic channel_set, 129578433f96SJanusz Dziedzic attention)) { 1296e8a50f8bSMarek Puzyniak ath10k_htt_rx_free_msdu_chain(msdu_head); 1297e8a50f8bSMarek Puzyniak continue; 1298e8a50f8bSMarek Puzyniak } 1299e8a50f8bSMarek Puzyniak 1300d84dd60fSJanusz Dziedzic if (ret > 0 && 1301d84dd60fSJanusz Dziedzic ath10k_unchain_msdu(msdu_head) < 0) { 13025e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(msdu_head); 13035e3dd157SKalle Valo continue; 13045e3dd157SKalle Valo } 13055e3dd157SKalle Valo 130678433f96SJanusz Dziedzic if (attention & RX_ATTENTION_FLAGS_FCS_ERR) 13076df92a3dSJanusz Dziedzic rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 130887326c97SJanusz Dziedzic else 13096df92a3dSJanusz Dziedzic rx_status->flag &= ~RX_FLAG_FAILED_FCS_CRC; 131087326c97SJanusz Dziedzic 131178433f96SJanusz Dziedzic if (attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR) 13126df92a3dSJanusz Dziedzic rx_status->flag |= RX_FLAG_MMIC_ERROR; 131387326c97SJanusz Dziedzic else 13146df92a3dSJanusz Dziedzic rx_status->flag &= ~RX_FLAG_MMIC_ERROR; 131587326c97SJanusz Dziedzic 13165e3dd157SKalle Valo hdr = ath10k_htt_rx_skb_get_hdr(msdu_head); 13175e3dd157SKalle Valo 13185e3dd157SKalle Valo if (ath10k_htt_rx_hdr_is_amsdu(hdr)) 13196df92a3dSJanusz Dziedzic ath10k_htt_rx_amsdu(htt, rx_status, msdu_head); 13205e3dd157SKalle Valo else 13216df92a3dSJanusz Dziedzic ath10k_htt_rx_msdu(htt, rx_status, msdu_head); 13225e3dd157SKalle Valo } 13235e3dd157SKalle Valo } 13245e3dd157SKalle Valo 13256e712d42SMichal Kazior tasklet_schedule(&htt->rx_replenish_task); 13265e3dd157SKalle Valo } 13275e3dd157SKalle Valo 13285e3dd157SKalle Valo static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt, 13295e3dd157SKalle Valo struct htt_rx_fragment_indication *frag) 13305e3dd157SKalle Valo { 13317aa7a72aSMichal Kazior struct ath10k *ar = htt->ar; 13325e3dd157SKalle Valo struct sk_buff *msdu_head, *msdu_tail; 133387326c97SJanusz Dziedzic enum htt_rx_mpdu_encrypt_type enctype; 13345e3dd157SKalle Valo struct htt_rx_desc *rxd; 13355e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 13366df92a3dSJanusz Dziedzic struct ieee80211_rx_status *rx_status = &htt->rx_status; 13375e3dd157SKalle Valo struct ieee80211_hdr *hdr; 1338d84dd60fSJanusz Dziedzic int ret; 13395e3dd157SKalle Valo bool tkip_mic_err; 13405e3dd157SKalle Valo bool decrypt_err; 13415e3dd157SKalle Valo u8 *fw_desc; 13425e3dd157SKalle Valo int fw_desc_len, hdrlen, paramlen; 13435e3dd157SKalle Valo int trim; 13440ccb7a34SJanusz Dziedzic u32 attention = 0; 13455e3dd157SKalle Valo 13465e3dd157SKalle Valo fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes); 13475e3dd157SKalle Valo fw_desc = (u8 *)frag->fw_msdu_rx_desc; 13485e3dd157SKalle Valo 13495e3dd157SKalle Valo msdu_head = NULL; 13505e3dd157SKalle Valo msdu_tail = NULL; 135145967089SMichal Kazior 135245967089SMichal Kazior spin_lock_bh(&htt->rx_ring.lock); 1353d84dd60fSJanusz Dziedzic ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len, 13540ccb7a34SJanusz Dziedzic &msdu_head, &msdu_tail, 13550ccb7a34SJanusz Dziedzic &attention); 135645967089SMichal Kazior spin_unlock_bh(&htt->rx_ring.lock); 13575e3dd157SKalle Valo 1358686687c9SMichal Kazior tasklet_schedule(&htt->rx_replenish_task); 1359686687c9SMichal Kazior 13607aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n"); 13615e3dd157SKalle Valo 1362d84dd60fSJanusz Dziedzic if (ret) { 13637aa7a72aSMichal Kazior ath10k_warn(ar, "failed to pop amsdu from httr rx ring for fragmented rx %d\n", 1364d84dd60fSJanusz Dziedzic ret); 13655e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(msdu_head); 13665e3dd157SKalle Valo return; 13675e3dd157SKalle Valo } 13685e3dd157SKalle Valo 13695e3dd157SKalle Valo /* FIXME: implement signal strength */ 13704b81d177SBen Greear rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 13715e3dd157SKalle Valo 13725e3dd157SKalle Valo hdr = (struct ieee80211_hdr *)msdu_head->data; 13735e3dd157SKalle Valo rxd = (void *)msdu_head->data - sizeof(*rxd); 13740ccb7a34SJanusz Dziedzic tkip_mic_err = !!(attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR); 13750ccb7a34SJanusz Dziedzic decrypt_err = !!(attention & RX_ATTENTION_FLAGS_DECRYPT_ERR); 13765e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 13775e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 13785e3dd157SKalle Valo 13795e3dd157SKalle Valo if (fmt != RX_MSDU_DECAP_RAW) { 13807aa7a72aSMichal Kazior ath10k_warn(ar, "we dont support non-raw fragmented rx yet\n"); 13815e3dd157SKalle Valo dev_kfree_skb_any(msdu_head); 13825e3dd157SKalle Valo goto end; 13835e3dd157SKalle Valo } 13845e3dd157SKalle Valo 138587326c97SJanusz Dziedzic enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), 13865e3dd157SKalle Valo RX_MPDU_START_INFO0_ENCRYPT_TYPE); 1387c071dcb2SMichal Kazior ath10k_htt_rx_h_protected(htt, rx_status, msdu_head, enctype, fmt, 1388c071dcb2SMichal Kazior true); 138985f6d7cfSJanusz Dziedzic msdu_head->ip_summed = ath10k_htt_rx_get_csum_state(msdu_head); 13905e3dd157SKalle Valo 139187326c97SJanusz Dziedzic if (tkip_mic_err) 13927aa7a72aSMichal Kazior ath10k_warn(ar, "tkip mic error\n"); 13935e3dd157SKalle Valo 13945e3dd157SKalle Valo if (decrypt_err) { 13957aa7a72aSMichal Kazior ath10k_warn(ar, "decryption err in fragmented rx\n"); 139685f6d7cfSJanusz Dziedzic dev_kfree_skb_any(msdu_head); 13975e3dd157SKalle Valo goto end; 13985e3dd157SKalle Valo } 13995e3dd157SKalle Valo 140087326c97SJanusz Dziedzic if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) { 14015e3dd157SKalle Valo hdrlen = ieee80211_hdrlen(hdr->frame_control); 14027aa7a72aSMichal Kazior paramlen = ath10k_htt_rx_crypto_param_len(ar, enctype); 14035e3dd157SKalle Valo 14045e3dd157SKalle Valo /* It is more efficient to move the header than the payload */ 140585f6d7cfSJanusz Dziedzic memmove((void *)msdu_head->data + paramlen, 140685f6d7cfSJanusz Dziedzic (void *)msdu_head->data, 14075e3dd157SKalle Valo hdrlen); 140885f6d7cfSJanusz Dziedzic skb_pull(msdu_head, paramlen); 140985f6d7cfSJanusz Dziedzic hdr = (struct ieee80211_hdr *)msdu_head->data; 14105e3dd157SKalle Valo } 14115e3dd157SKalle Valo 14125e3dd157SKalle Valo /* remove trailing FCS */ 14135e3dd157SKalle Valo trim = 4; 14145e3dd157SKalle Valo 14155e3dd157SKalle Valo /* remove crypto trailer */ 14167aa7a72aSMichal Kazior trim += ath10k_htt_rx_crypto_tail_len(ar, enctype); 14175e3dd157SKalle Valo 14185e3dd157SKalle Valo /* last fragment of TKIP frags has MIC */ 14195e3dd157SKalle Valo if (!ieee80211_has_morefrags(hdr->frame_control) && 142087326c97SJanusz Dziedzic enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA) 1421890d3b2aSMichal Kazior trim += MICHAEL_MIC_LEN; 14225e3dd157SKalle Valo 142385f6d7cfSJanusz Dziedzic if (trim > msdu_head->len) { 14247aa7a72aSMichal Kazior ath10k_warn(ar, "htt rx fragment: trailer longer than the frame itself? drop\n"); 142585f6d7cfSJanusz Dziedzic dev_kfree_skb_any(msdu_head); 14265e3dd157SKalle Valo goto end; 14275e3dd157SKalle Valo } 14285e3dd157SKalle Valo 142985f6d7cfSJanusz Dziedzic skb_trim(msdu_head, msdu_head->len - trim); 14305e3dd157SKalle Valo 14317aa7a72aSMichal Kazior ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ", 143285f6d7cfSJanusz Dziedzic msdu_head->data, msdu_head->len); 14336df92a3dSJanusz Dziedzic ath10k_process_rx(htt->ar, rx_status, msdu_head); 14345e3dd157SKalle Valo 14355e3dd157SKalle Valo end: 14365e3dd157SKalle Valo if (fw_desc_len > 0) { 14377aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, 14385e3dd157SKalle Valo "expecting more fragmented rx in one indication %d\n", 14395e3dd157SKalle Valo fw_desc_len); 14405e3dd157SKalle Valo } 14415e3dd157SKalle Valo } 14425e3dd157SKalle Valo 14436c5151a9SMichal Kazior static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar, 14446c5151a9SMichal Kazior struct sk_buff *skb) 14456c5151a9SMichal Kazior { 14466c5151a9SMichal Kazior struct ath10k_htt *htt = &ar->htt; 14476c5151a9SMichal Kazior struct htt_resp *resp = (struct htt_resp *)skb->data; 14486c5151a9SMichal Kazior struct htt_tx_done tx_done = {}; 14496c5151a9SMichal Kazior int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS); 14506c5151a9SMichal Kazior __le16 msdu_id; 14516c5151a9SMichal Kazior int i; 14526c5151a9SMichal Kazior 145345967089SMichal Kazior lockdep_assert_held(&htt->tx_lock); 145445967089SMichal Kazior 14556c5151a9SMichal Kazior switch (status) { 14566c5151a9SMichal Kazior case HTT_DATA_TX_STATUS_NO_ACK: 14576c5151a9SMichal Kazior tx_done.no_ack = true; 14586c5151a9SMichal Kazior break; 14596c5151a9SMichal Kazior case HTT_DATA_TX_STATUS_OK: 14606c5151a9SMichal Kazior break; 14616c5151a9SMichal Kazior case HTT_DATA_TX_STATUS_DISCARD: 14626c5151a9SMichal Kazior case HTT_DATA_TX_STATUS_POSTPONE: 14636c5151a9SMichal Kazior case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL: 14646c5151a9SMichal Kazior tx_done.discard = true; 14656c5151a9SMichal Kazior break; 14666c5151a9SMichal Kazior default: 14677aa7a72aSMichal Kazior ath10k_warn(ar, "unhandled tx completion status %d\n", status); 14686c5151a9SMichal Kazior tx_done.discard = true; 14696c5151a9SMichal Kazior break; 14706c5151a9SMichal Kazior } 14716c5151a9SMichal Kazior 14727aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n", 14736c5151a9SMichal Kazior resp->data_tx_completion.num_msdus); 14746c5151a9SMichal Kazior 14756c5151a9SMichal Kazior for (i = 0; i < resp->data_tx_completion.num_msdus; i++) { 14766c5151a9SMichal Kazior msdu_id = resp->data_tx_completion.msdus[i]; 14776c5151a9SMichal Kazior tx_done.msdu_id = __le16_to_cpu(msdu_id); 14786c5151a9SMichal Kazior ath10k_txrx_tx_unref(htt, &tx_done); 14796c5151a9SMichal Kazior } 14806c5151a9SMichal Kazior } 14816c5151a9SMichal Kazior 1482aa5b4fbcSMichal Kazior static void ath10k_htt_rx_addba(struct ath10k *ar, struct htt_resp *resp) 1483aa5b4fbcSMichal Kazior { 1484aa5b4fbcSMichal Kazior struct htt_rx_addba *ev = &resp->rx_addba; 1485aa5b4fbcSMichal Kazior struct ath10k_peer *peer; 1486aa5b4fbcSMichal Kazior struct ath10k_vif *arvif; 1487aa5b4fbcSMichal Kazior u16 info0, tid, peer_id; 1488aa5b4fbcSMichal Kazior 1489aa5b4fbcSMichal Kazior info0 = __le16_to_cpu(ev->info0); 1490aa5b4fbcSMichal Kazior tid = MS(info0, HTT_RX_BA_INFO0_TID); 1491aa5b4fbcSMichal Kazior peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID); 1492aa5b4fbcSMichal Kazior 14937aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, 1494aa5b4fbcSMichal Kazior "htt rx addba tid %hu peer_id %hu size %hhu\n", 1495aa5b4fbcSMichal Kazior tid, peer_id, ev->window_size); 1496aa5b4fbcSMichal Kazior 1497aa5b4fbcSMichal Kazior spin_lock_bh(&ar->data_lock); 1498aa5b4fbcSMichal Kazior peer = ath10k_peer_find_by_id(ar, peer_id); 1499aa5b4fbcSMichal Kazior if (!peer) { 15007aa7a72aSMichal Kazior ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n", 1501aa5b4fbcSMichal Kazior peer_id); 1502aa5b4fbcSMichal Kazior spin_unlock_bh(&ar->data_lock); 1503aa5b4fbcSMichal Kazior return; 1504aa5b4fbcSMichal Kazior } 1505aa5b4fbcSMichal Kazior 1506aa5b4fbcSMichal Kazior arvif = ath10k_get_arvif(ar, peer->vdev_id); 1507aa5b4fbcSMichal Kazior if (!arvif) { 15087aa7a72aSMichal Kazior ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n", 1509aa5b4fbcSMichal Kazior peer->vdev_id); 1510aa5b4fbcSMichal Kazior spin_unlock_bh(&ar->data_lock); 1511aa5b4fbcSMichal Kazior return; 1512aa5b4fbcSMichal Kazior } 1513aa5b4fbcSMichal Kazior 15147aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, 1515aa5b4fbcSMichal Kazior "htt rx start rx ba session sta %pM tid %hu size %hhu\n", 1516aa5b4fbcSMichal Kazior peer->addr, tid, ev->window_size); 1517aa5b4fbcSMichal Kazior 1518aa5b4fbcSMichal Kazior ieee80211_start_rx_ba_session_offl(arvif->vif, peer->addr, tid); 1519aa5b4fbcSMichal Kazior spin_unlock_bh(&ar->data_lock); 1520aa5b4fbcSMichal Kazior } 1521aa5b4fbcSMichal Kazior 1522aa5b4fbcSMichal Kazior static void ath10k_htt_rx_delba(struct ath10k *ar, struct htt_resp *resp) 1523aa5b4fbcSMichal Kazior { 1524aa5b4fbcSMichal Kazior struct htt_rx_delba *ev = &resp->rx_delba; 1525aa5b4fbcSMichal Kazior struct ath10k_peer *peer; 1526aa5b4fbcSMichal Kazior struct ath10k_vif *arvif; 1527aa5b4fbcSMichal Kazior u16 info0, tid, peer_id; 1528aa5b4fbcSMichal Kazior 1529aa5b4fbcSMichal Kazior info0 = __le16_to_cpu(ev->info0); 1530aa5b4fbcSMichal Kazior tid = MS(info0, HTT_RX_BA_INFO0_TID); 1531aa5b4fbcSMichal Kazior peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID); 1532aa5b4fbcSMichal Kazior 15337aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, 1534aa5b4fbcSMichal Kazior "htt rx delba tid %hu peer_id %hu\n", 1535aa5b4fbcSMichal Kazior tid, peer_id); 1536aa5b4fbcSMichal Kazior 1537aa5b4fbcSMichal Kazior spin_lock_bh(&ar->data_lock); 1538aa5b4fbcSMichal Kazior peer = ath10k_peer_find_by_id(ar, peer_id); 1539aa5b4fbcSMichal Kazior if (!peer) { 15407aa7a72aSMichal Kazior ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n", 1541aa5b4fbcSMichal Kazior peer_id); 1542aa5b4fbcSMichal Kazior spin_unlock_bh(&ar->data_lock); 1543aa5b4fbcSMichal Kazior return; 1544aa5b4fbcSMichal Kazior } 1545aa5b4fbcSMichal Kazior 1546aa5b4fbcSMichal Kazior arvif = ath10k_get_arvif(ar, peer->vdev_id); 1547aa5b4fbcSMichal Kazior if (!arvif) { 15487aa7a72aSMichal Kazior ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n", 1549aa5b4fbcSMichal Kazior peer->vdev_id); 1550aa5b4fbcSMichal Kazior spin_unlock_bh(&ar->data_lock); 1551aa5b4fbcSMichal Kazior return; 1552aa5b4fbcSMichal Kazior } 1553aa5b4fbcSMichal Kazior 15547aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, 1555aa5b4fbcSMichal Kazior "htt rx stop rx ba session sta %pM tid %hu\n", 1556aa5b4fbcSMichal Kazior peer->addr, tid); 1557aa5b4fbcSMichal Kazior 1558aa5b4fbcSMichal Kazior ieee80211_stop_rx_ba_session_offl(arvif->vif, peer->addr, tid); 1559aa5b4fbcSMichal Kazior spin_unlock_bh(&ar->data_lock); 1560aa5b4fbcSMichal Kazior } 1561aa5b4fbcSMichal Kazior 15625e3dd157SKalle Valo void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb) 15635e3dd157SKalle Valo { 1564edb8236dSMichal Kazior struct ath10k_htt *htt = &ar->htt; 15655e3dd157SKalle Valo struct htt_resp *resp = (struct htt_resp *)skb->data; 15665e3dd157SKalle Valo 15675e3dd157SKalle Valo /* confirm alignment */ 15685e3dd157SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, 4)) 15697aa7a72aSMichal Kazior ath10k_warn(ar, "unaligned htt message, expect trouble\n"); 15705e3dd157SKalle Valo 15717aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n", 15725e3dd157SKalle Valo resp->hdr.msg_type); 15735e3dd157SKalle Valo switch (resp->hdr.msg_type) { 15745e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_VERSION_CONF: { 15755e3dd157SKalle Valo htt->target_version_major = resp->ver_resp.major; 15765e3dd157SKalle Valo htt->target_version_minor = resp->ver_resp.minor; 15775e3dd157SKalle Valo complete(&htt->target_version_received); 15785e3dd157SKalle Valo break; 15795e3dd157SKalle Valo } 15806c5151a9SMichal Kazior case HTT_T2H_MSG_TYPE_RX_IND: 158145967089SMichal Kazior spin_lock_bh(&htt->rx_ring.lock); 158245967089SMichal Kazior __skb_queue_tail(&htt->rx_compl_q, skb); 158345967089SMichal Kazior spin_unlock_bh(&htt->rx_ring.lock); 15846c5151a9SMichal Kazior tasklet_schedule(&htt->txrx_compl_task); 15856c5151a9SMichal Kazior return; 15865e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_PEER_MAP: { 15875e3dd157SKalle Valo struct htt_peer_map_event ev = { 15885e3dd157SKalle Valo .vdev_id = resp->peer_map.vdev_id, 15895e3dd157SKalle Valo .peer_id = __le16_to_cpu(resp->peer_map.peer_id), 15905e3dd157SKalle Valo }; 15915e3dd157SKalle Valo memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr)); 15925e3dd157SKalle Valo ath10k_peer_map_event(htt, &ev); 15935e3dd157SKalle Valo break; 15945e3dd157SKalle Valo } 15955e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_PEER_UNMAP: { 15965e3dd157SKalle Valo struct htt_peer_unmap_event ev = { 15975e3dd157SKalle Valo .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id), 15985e3dd157SKalle Valo }; 15995e3dd157SKalle Valo ath10k_peer_unmap_event(htt, &ev); 16005e3dd157SKalle Valo break; 16015e3dd157SKalle Valo } 16025e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: { 16035e3dd157SKalle Valo struct htt_tx_done tx_done = {}; 16045e3dd157SKalle Valo int status = __le32_to_cpu(resp->mgmt_tx_completion.status); 16055e3dd157SKalle Valo 16065e3dd157SKalle Valo tx_done.msdu_id = 16075e3dd157SKalle Valo __le32_to_cpu(resp->mgmt_tx_completion.desc_id); 16085e3dd157SKalle Valo 16095e3dd157SKalle Valo switch (status) { 16105e3dd157SKalle Valo case HTT_MGMT_TX_STATUS_OK: 16115e3dd157SKalle Valo break; 16125e3dd157SKalle Valo case HTT_MGMT_TX_STATUS_RETRY: 16135e3dd157SKalle Valo tx_done.no_ack = true; 16145e3dd157SKalle Valo break; 16155e3dd157SKalle Valo case HTT_MGMT_TX_STATUS_DROP: 16165e3dd157SKalle Valo tx_done.discard = true; 16175e3dd157SKalle Valo break; 16185e3dd157SKalle Valo } 16195e3dd157SKalle Valo 16206c5151a9SMichal Kazior spin_lock_bh(&htt->tx_lock); 16210a89f8a0SMichal Kazior ath10k_txrx_tx_unref(htt, &tx_done); 16226c5151a9SMichal Kazior spin_unlock_bh(&htt->tx_lock); 16235e3dd157SKalle Valo break; 16245e3dd157SKalle Valo } 16256c5151a9SMichal Kazior case HTT_T2H_MSG_TYPE_TX_COMPL_IND: 16266c5151a9SMichal Kazior spin_lock_bh(&htt->tx_lock); 16276c5151a9SMichal Kazior __skb_queue_tail(&htt->tx_compl_q, skb); 16286c5151a9SMichal Kazior spin_unlock_bh(&htt->tx_lock); 16296c5151a9SMichal Kazior tasklet_schedule(&htt->txrx_compl_task); 16306c5151a9SMichal Kazior return; 16315e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_SEC_IND: { 16325e3dd157SKalle Valo struct ath10k *ar = htt->ar; 16335e3dd157SKalle Valo struct htt_security_indication *ev = &resp->security_indication; 16345e3dd157SKalle Valo 16357aa7a72aSMichal Kazior ath10k_dbg(ar, ATH10K_DBG_HTT, 16365e3dd157SKalle Valo "sec ind peer_id %d unicast %d type %d\n", 16375e3dd157SKalle Valo __le16_to_cpu(ev->peer_id), 16385e3dd157SKalle Valo !!(ev->flags & HTT_SECURITY_IS_UNICAST), 16395e3dd157SKalle Valo MS(ev->flags, HTT_SECURITY_TYPE)); 16405e3dd157SKalle Valo complete(&ar->install_key_done); 16415e3dd157SKalle Valo break; 16425e3dd157SKalle Valo } 16435e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_FRAG_IND: { 16447aa7a72aSMichal Kazior ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ", 16455e3dd157SKalle Valo skb->data, skb->len); 16465e3dd157SKalle Valo ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind); 16475e3dd157SKalle Valo break; 16485e3dd157SKalle Valo } 16495e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_TEST: 16505e3dd157SKalle Valo /* FIX THIS */ 16515e3dd157SKalle Valo break; 16525e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_STATS_CONF: 1653d35a6c18SMichal Kazior trace_ath10k_htt_stats(ar, skb->data, skb->len); 1654a9bf0506SKalle Valo break; 1655a9bf0506SKalle Valo case HTT_T2H_MSG_TYPE_TX_INSPECT_IND: 1656708b9bdeSMichal Kazior /* Firmware can return tx frames if it's unable to fully 1657708b9bdeSMichal Kazior * process them and suspects host may be able to fix it. ath10k 1658708b9bdeSMichal Kazior * sends all tx frames as already inspected so this shouldn't 1659708b9bdeSMichal Kazior * happen unless fw has a bug. 1660708b9bdeSMichal Kazior */ 16617aa7a72aSMichal Kazior ath10k_warn(ar, "received an unexpected htt tx inspect event\n"); 1662708b9bdeSMichal Kazior break; 16635e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_ADDBA: 1664aa5b4fbcSMichal Kazior ath10k_htt_rx_addba(ar, resp); 1665aa5b4fbcSMichal Kazior break; 16665e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_DELBA: 1667aa5b4fbcSMichal Kazior ath10k_htt_rx_delba(ar, resp); 1668aa5b4fbcSMichal Kazior break; 1669bfdd7937SRajkumar Manoharan case HTT_T2H_MSG_TYPE_PKTLOG: { 1670bfdd7937SRajkumar Manoharan struct ath10k_pktlog_hdr *hdr = 1671bfdd7937SRajkumar Manoharan (struct ath10k_pktlog_hdr *)resp->pktlog_msg.payload; 1672bfdd7937SRajkumar Manoharan 1673bfdd7937SRajkumar Manoharan trace_ath10k_htt_pktlog(ar, resp->pktlog_msg.payload, 1674bfdd7937SRajkumar Manoharan sizeof(*hdr) + 1675bfdd7937SRajkumar Manoharan __le16_to_cpu(hdr->size)); 1676bfdd7937SRajkumar Manoharan break; 1677bfdd7937SRajkumar Manoharan } 1678aa5b4fbcSMichal Kazior case HTT_T2H_MSG_TYPE_RX_FLUSH: { 1679aa5b4fbcSMichal Kazior /* Ignore this event because mac80211 takes care of Rx 1680aa5b4fbcSMichal Kazior * aggregation reordering. 1681aa5b4fbcSMichal Kazior */ 1682aa5b4fbcSMichal Kazior break; 1683aa5b4fbcSMichal Kazior } 16845e3dd157SKalle Valo default: 16852358a544SMichal Kazior ath10k_warn(ar, "htt event (%d) not handled\n", 16865e3dd157SKalle Valo resp->hdr.msg_type); 16877aa7a72aSMichal Kazior ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ", 16885e3dd157SKalle Valo skb->data, skb->len); 16895e3dd157SKalle Valo break; 16905e3dd157SKalle Valo }; 16915e3dd157SKalle Valo 16925e3dd157SKalle Valo /* Free the indication buffer */ 16935e3dd157SKalle Valo dev_kfree_skb_any(skb); 16945e3dd157SKalle Valo } 16956c5151a9SMichal Kazior 16966c5151a9SMichal Kazior static void ath10k_htt_txrx_compl_task(unsigned long ptr) 16976c5151a9SMichal Kazior { 16986c5151a9SMichal Kazior struct ath10k_htt *htt = (struct ath10k_htt *)ptr; 16996c5151a9SMichal Kazior struct htt_resp *resp; 17006c5151a9SMichal Kazior struct sk_buff *skb; 17016c5151a9SMichal Kazior 170245967089SMichal Kazior spin_lock_bh(&htt->tx_lock); 170345967089SMichal Kazior while ((skb = __skb_dequeue(&htt->tx_compl_q))) { 17046c5151a9SMichal Kazior ath10k_htt_rx_frm_tx_compl(htt->ar, skb); 17056c5151a9SMichal Kazior dev_kfree_skb_any(skb); 17066c5151a9SMichal Kazior } 170745967089SMichal Kazior spin_unlock_bh(&htt->tx_lock); 17086c5151a9SMichal Kazior 170945967089SMichal Kazior spin_lock_bh(&htt->rx_ring.lock); 171045967089SMichal Kazior while ((skb = __skb_dequeue(&htt->rx_compl_q))) { 17116c5151a9SMichal Kazior resp = (struct htt_resp *)skb->data; 17126c5151a9SMichal Kazior ath10k_htt_rx_handler(htt, &resp->rx_ind); 17136c5151a9SMichal Kazior dev_kfree_skb_any(skb); 17146c5151a9SMichal Kazior } 171545967089SMichal Kazior spin_unlock_bh(&htt->rx_ring.lock); 17166c5151a9SMichal Kazior } 1717