15e3dd157SKalle Valo /* 25e3dd157SKalle Valo * Copyright (c) 2005-2011 Atheros Communications Inc. 35e3dd157SKalle Valo * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 45e3dd157SKalle Valo * 55e3dd157SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 65e3dd157SKalle Valo * purpose with or without fee is hereby granted, provided that the above 75e3dd157SKalle Valo * copyright notice and this permission notice appear in all copies. 85e3dd157SKalle Valo * 95e3dd157SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 105e3dd157SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 115e3dd157SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 125e3dd157SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 135e3dd157SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 145e3dd157SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 155e3dd157SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 165e3dd157SKalle Valo */ 175e3dd157SKalle Valo 18edb8236dSMichal Kazior #include "core.h" 195e3dd157SKalle Valo #include "htc.h" 205e3dd157SKalle Valo #include "htt.h" 215e3dd157SKalle Valo #include "txrx.h" 225e3dd157SKalle Valo #include "debug.h" 23a9bf0506SKalle Valo #include "trace.h" 245e3dd157SKalle Valo 255e3dd157SKalle Valo #include <linux/log2.h> 265e3dd157SKalle Valo 275e3dd157SKalle Valo /* slightly larger than one large A-MPDU */ 285e3dd157SKalle Valo #define HTT_RX_RING_SIZE_MIN 128 295e3dd157SKalle Valo 305e3dd157SKalle Valo /* roughly 20 ms @ 1 Gbps of 1500B MSDUs */ 315e3dd157SKalle Valo #define HTT_RX_RING_SIZE_MAX 2048 325e3dd157SKalle Valo 335e3dd157SKalle Valo #define HTT_RX_AVG_FRM_BYTES 1000 345e3dd157SKalle Valo 355e3dd157SKalle Valo /* ms, very conservative */ 365e3dd157SKalle Valo #define HTT_RX_HOST_LATENCY_MAX_MS 20 375e3dd157SKalle Valo 385e3dd157SKalle Valo /* ms, conservative */ 395e3dd157SKalle Valo #define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10 405e3dd157SKalle Valo 415e3dd157SKalle Valo /* when under memory pressure rx ring refill may fail and needs a retry */ 425e3dd157SKalle Valo #define HTT_RX_RING_REFILL_RETRY_MS 50 435e3dd157SKalle Valo 44f6dc2095SMichal Kazior 45f6dc2095SMichal Kazior static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb); 466c5151a9SMichal Kazior static void ath10k_htt_txrx_compl_task(unsigned long ptr); 47f6dc2095SMichal Kazior 485e3dd157SKalle Valo static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt) 495e3dd157SKalle Valo { 505e3dd157SKalle Valo int size; 515e3dd157SKalle Valo 525e3dd157SKalle Valo /* 535e3dd157SKalle Valo * It is expected that the host CPU will typically be able to 545e3dd157SKalle Valo * service the rx indication from one A-MPDU before the rx 555e3dd157SKalle Valo * indication from the subsequent A-MPDU happens, roughly 1-2 ms 565e3dd157SKalle Valo * later. However, the rx ring should be sized very conservatively, 575e3dd157SKalle Valo * to accomodate the worst reasonable delay before the host CPU 585e3dd157SKalle Valo * services a rx indication interrupt. 595e3dd157SKalle Valo * 605e3dd157SKalle Valo * The rx ring need not be kept full of empty buffers. In theory, 615e3dd157SKalle Valo * the htt host SW can dynamically track the low-water mark in the 625e3dd157SKalle Valo * rx ring, and dynamically adjust the level to which the rx ring 635e3dd157SKalle Valo * is filled with empty buffers, to dynamically meet the desired 645e3dd157SKalle Valo * low-water mark. 655e3dd157SKalle Valo * 665e3dd157SKalle Valo * In contrast, it's difficult to resize the rx ring itself, once 675e3dd157SKalle Valo * it's in use. Thus, the ring itself should be sized very 685e3dd157SKalle Valo * conservatively, while the degree to which the ring is filled 695e3dd157SKalle Valo * with empty buffers should be sized moderately conservatively. 705e3dd157SKalle Valo */ 715e3dd157SKalle Valo 725e3dd157SKalle Valo /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */ 735e3dd157SKalle Valo size = 745e3dd157SKalle Valo htt->max_throughput_mbps + 755e3dd157SKalle Valo 1000 / 765e3dd157SKalle Valo (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS; 775e3dd157SKalle Valo 785e3dd157SKalle Valo if (size < HTT_RX_RING_SIZE_MIN) 795e3dd157SKalle Valo size = HTT_RX_RING_SIZE_MIN; 805e3dd157SKalle Valo 815e3dd157SKalle Valo if (size > HTT_RX_RING_SIZE_MAX) 825e3dd157SKalle Valo size = HTT_RX_RING_SIZE_MAX; 835e3dd157SKalle Valo 845e3dd157SKalle Valo size = roundup_pow_of_two(size); 855e3dd157SKalle Valo 865e3dd157SKalle Valo return size; 875e3dd157SKalle Valo } 885e3dd157SKalle Valo 895e3dd157SKalle Valo static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt) 905e3dd157SKalle Valo { 915e3dd157SKalle Valo int size; 925e3dd157SKalle Valo 935e3dd157SKalle Valo /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */ 945e3dd157SKalle Valo size = 955e3dd157SKalle Valo htt->max_throughput_mbps * 965e3dd157SKalle Valo 1000 / 975e3dd157SKalle Valo (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS; 985e3dd157SKalle Valo 995e3dd157SKalle Valo /* 1005e3dd157SKalle Valo * Make sure the fill level is at least 1 less than the ring size. 1015e3dd157SKalle Valo * Leaving 1 element empty allows the SW to easily distinguish 1025e3dd157SKalle Valo * between a full ring vs. an empty ring. 1035e3dd157SKalle Valo */ 1045e3dd157SKalle Valo if (size >= htt->rx_ring.size) 1055e3dd157SKalle Valo size = htt->rx_ring.size - 1; 1065e3dd157SKalle Valo 1075e3dd157SKalle Valo return size; 1085e3dd157SKalle Valo } 1095e3dd157SKalle Valo 1105e3dd157SKalle Valo static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt) 1115e3dd157SKalle Valo { 1125e3dd157SKalle Valo struct sk_buff *skb; 1135e3dd157SKalle Valo struct ath10k_skb_cb *cb; 1145e3dd157SKalle Valo int i; 1155e3dd157SKalle Valo 1165e3dd157SKalle Valo for (i = 0; i < htt->rx_ring.fill_cnt; i++) { 1175e3dd157SKalle Valo skb = htt->rx_ring.netbufs_ring[i]; 1185e3dd157SKalle Valo cb = ATH10K_SKB_CB(skb); 1195e3dd157SKalle Valo dma_unmap_single(htt->ar->dev, cb->paddr, 1205e3dd157SKalle Valo skb->len + skb_tailroom(skb), 1215e3dd157SKalle Valo DMA_FROM_DEVICE); 1225e3dd157SKalle Valo dev_kfree_skb_any(skb); 1235e3dd157SKalle Valo } 1245e3dd157SKalle Valo 1255e3dd157SKalle Valo htt->rx_ring.fill_cnt = 0; 1265e3dd157SKalle Valo } 1275e3dd157SKalle Valo 1285e3dd157SKalle Valo static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num) 1295e3dd157SKalle Valo { 1305e3dd157SKalle Valo struct htt_rx_desc *rx_desc; 1315e3dd157SKalle Valo struct sk_buff *skb; 1325e3dd157SKalle Valo dma_addr_t paddr; 1335e3dd157SKalle Valo int ret = 0, idx; 1345e3dd157SKalle Valo 1355e3dd157SKalle Valo idx = __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr)); 1365e3dd157SKalle Valo while (num > 0) { 1375e3dd157SKalle Valo skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN); 1385e3dd157SKalle Valo if (!skb) { 1395e3dd157SKalle Valo ret = -ENOMEM; 1405e3dd157SKalle Valo goto fail; 1415e3dd157SKalle Valo } 1425e3dd157SKalle Valo 1435e3dd157SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN)) 1445e3dd157SKalle Valo skb_pull(skb, 1455e3dd157SKalle Valo PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) - 1465e3dd157SKalle Valo skb->data); 1475e3dd157SKalle Valo 1485e3dd157SKalle Valo /* Clear rx_desc attention word before posting to Rx ring */ 1495e3dd157SKalle Valo rx_desc = (struct htt_rx_desc *)skb->data; 1505e3dd157SKalle Valo rx_desc->attention.flags = __cpu_to_le32(0); 1515e3dd157SKalle Valo 1525e3dd157SKalle Valo paddr = dma_map_single(htt->ar->dev, skb->data, 1535e3dd157SKalle Valo skb->len + skb_tailroom(skb), 1545e3dd157SKalle Valo DMA_FROM_DEVICE); 1555e3dd157SKalle Valo 1565e3dd157SKalle Valo if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) { 1575e3dd157SKalle Valo dev_kfree_skb_any(skb); 1585e3dd157SKalle Valo ret = -ENOMEM; 1595e3dd157SKalle Valo goto fail; 1605e3dd157SKalle Valo } 1615e3dd157SKalle Valo 1625e3dd157SKalle Valo ATH10K_SKB_CB(skb)->paddr = paddr; 1635e3dd157SKalle Valo htt->rx_ring.netbufs_ring[idx] = skb; 1645e3dd157SKalle Valo htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr); 1655e3dd157SKalle Valo htt->rx_ring.fill_cnt++; 1665e3dd157SKalle Valo 1675e3dd157SKalle Valo num--; 1685e3dd157SKalle Valo idx++; 1695e3dd157SKalle Valo idx &= htt->rx_ring.size_mask; 1705e3dd157SKalle Valo } 1715e3dd157SKalle Valo 1725e3dd157SKalle Valo fail: 1735e3dd157SKalle Valo *(htt->rx_ring.alloc_idx.vaddr) = __cpu_to_le32(idx); 1745e3dd157SKalle Valo return ret; 1755e3dd157SKalle Valo } 1765e3dd157SKalle Valo 1775e3dd157SKalle Valo static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num) 1785e3dd157SKalle Valo { 1795e3dd157SKalle Valo lockdep_assert_held(&htt->rx_ring.lock); 1805e3dd157SKalle Valo return __ath10k_htt_rx_ring_fill_n(htt, num); 1815e3dd157SKalle Valo } 1825e3dd157SKalle Valo 1835e3dd157SKalle Valo static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt) 1845e3dd157SKalle Valo { 1856e712d42SMichal Kazior int ret, num_deficit, num_to_fill; 1865e3dd157SKalle Valo 1876e712d42SMichal Kazior /* Refilling the whole RX ring buffer proves to be a bad idea. The 1886e712d42SMichal Kazior * reason is RX may take up significant amount of CPU cycles and starve 1896e712d42SMichal Kazior * other tasks, e.g. TX on an ethernet device while acting as a bridge 1906e712d42SMichal Kazior * with ath10k wlan interface. This ended up with very poor performance 1916e712d42SMichal Kazior * once CPU the host system was overwhelmed with RX on ath10k. 1926e712d42SMichal Kazior * 1936e712d42SMichal Kazior * By limiting the number of refills the replenishing occurs 1946e712d42SMichal Kazior * progressively. This in turns makes use of the fact tasklets are 1956e712d42SMichal Kazior * processed in FIFO order. This means actual RX processing can starve 1966e712d42SMichal Kazior * out refilling. If there's not enough buffers on RX ring FW will not 1976e712d42SMichal Kazior * report RX until it is refilled with enough buffers. This 1986e712d42SMichal Kazior * automatically balances load wrt to CPU power. 1996e712d42SMichal Kazior * 2006e712d42SMichal Kazior * This probably comes at a cost of lower maximum throughput but 2016e712d42SMichal Kazior * improves the avarage and stability. */ 2025e3dd157SKalle Valo spin_lock_bh(&htt->rx_ring.lock); 2036e712d42SMichal Kazior num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt; 2046e712d42SMichal Kazior num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit); 2056e712d42SMichal Kazior num_deficit -= num_to_fill; 2065e3dd157SKalle Valo ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill); 2075e3dd157SKalle Valo if (ret == -ENOMEM) { 2085e3dd157SKalle Valo /* 2095e3dd157SKalle Valo * Failed to fill it to the desired level - 2105e3dd157SKalle Valo * we'll start a timer and try again next time. 2115e3dd157SKalle Valo * As long as enough buffers are left in the ring for 2125e3dd157SKalle Valo * another A-MPDU rx, no special recovery is needed. 2135e3dd157SKalle Valo */ 2145e3dd157SKalle Valo mod_timer(&htt->rx_ring.refill_retry_timer, jiffies + 2155e3dd157SKalle Valo msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS)); 2166e712d42SMichal Kazior } else if (num_deficit > 0) { 2176e712d42SMichal Kazior tasklet_schedule(&htt->rx_replenish_task); 2185e3dd157SKalle Valo } 2195e3dd157SKalle Valo spin_unlock_bh(&htt->rx_ring.lock); 2205e3dd157SKalle Valo } 2215e3dd157SKalle Valo 2225e3dd157SKalle Valo static void ath10k_htt_rx_ring_refill_retry(unsigned long arg) 2235e3dd157SKalle Valo { 2245e3dd157SKalle Valo struct ath10k_htt *htt = (struct ath10k_htt *)arg; 2255e3dd157SKalle Valo ath10k_htt_rx_msdu_buff_replenish(htt); 2265e3dd157SKalle Valo } 2275e3dd157SKalle Valo 2285e3dd157SKalle Valo void ath10k_htt_rx_detach(struct ath10k_htt *htt) 2295e3dd157SKalle Valo { 2305e3dd157SKalle Valo int sw_rd_idx = htt->rx_ring.sw_rd_idx.msdu_payld; 2315e3dd157SKalle Valo 2325e3dd157SKalle Valo del_timer_sync(&htt->rx_ring.refill_retry_timer); 2336e712d42SMichal Kazior tasklet_kill(&htt->rx_replenish_task); 2346c5151a9SMichal Kazior tasklet_kill(&htt->txrx_compl_task); 2356c5151a9SMichal Kazior 2366c5151a9SMichal Kazior skb_queue_purge(&htt->tx_compl_q); 2376c5151a9SMichal Kazior skb_queue_purge(&htt->rx_compl_q); 2385e3dd157SKalle Valo 2395e3dd157SKalle Valo while (sw_rd_idx != __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr))) { 2405e3dd157SKalle Valo struct sk_buff *skb = 2415e3dd157SKalle Valo htt->rx_ring.netbufs_ring[sw_rd_idx]; 2425e3dd157SKalle Valo struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 2435e3dd157SKalle Valo 2445e3dd157SKalle Valo dma_unmap_single(htt->ar->dev, cb->paddr, 2455e3dd157SKalle Valo skb->len + skb_tailroom(skb), 2465e3dd157SKalle Valo DMA_FROM_DEVICE); 2475e3dd157SKalle Valo dev_kfree_skb_any(htt->rx_ring.netbufs_ring[sw_rd_idx]); 2485e3dd157SKalle Valo sw_rd_idx++; 2495e3dd157SKalle Valo sw_rd_idx &= htt->rx_ring.size_mask; 2505e3dd157SKalle Valo } 2515e3dd157SKalle Valo 2525e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 2535e3dd157SKalle Valo (htt->rx_ring.size * 2545e3dd157SKalle Valo sizeof(htt->rx_ring.paddrs_ring)), 2555e3dd157SKalle Valo htt->rx_ring.paddrs_ring, 2565e3dd157SKalle Valo htt->rx_ring.base_paddr); 2575e3dd157SKalle Valo 2585e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 2595e3dd157SKalle Valo sizeof(*htt->rx_ring.alloc_idx.vaddr), 2605e3dd157SKalle Valo htt->rx_ring.alloc_idx.vaddr, 2615e3dd157SKalle Valo htt->rx_ring.alloc_idx.paddr); 2625e3dd157SKalle Valo 2635e3dd157SKalle Valo kfree(htt->rx_ring.netbufs_ring); 2645e3dd157SKalle Valo } 2655e3dd157SKalle Valo 2665e3dd157SKalle Valo static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt) 2675e3dd157SKalle Valo { 2685e3dd157SKalle Valo int idx; 2695e3dd157SKalle Valo struct sk_buff *msdu; 2705e3dd157SKalle Valo 27145967089SMichal Kazior lockdep_assert_held(&htt->rx_ring.lock); 2725e3dd157SKalle Valo 2738d60ee87SMichal Kazior if (htt->rx_ring.fill_cnt == 0) { 2748d60ee87SMichal Kazior ath10k_warn("tried to pop sk_buff from an empty rx ring\n"); 2758d60ee87SMichal Kazior return NULL; 2768d60ee87SMichal Kazior } 2775e3dd157SKalle Valo 2785e3dd157SKalle Valo idx = htt->rx_ring.sw_rd_idx.msdu_payld; 2795e3dd157SKalle Valo msdu = htt->rx_ring.netbufs_ring[idx]; 2805e3dd157SKalle Valo 2815e3dd157SKalle Valo idx++; 2825e3dd157SKalle Valo idx &= htt->rx_ring.size_mask; 2835e3dd157SKalle Valo htt->rx_ring.sw_rd_idx.msdu_payld = idx; 2845e3dd157SKalle Valo htt->rx_ring.fill_cnt--; 2855e3dd157SKalle Valo 2865e3dd157SKalle Valo return msdu; 2875e3dd157SKalle Valo } 2885e3dd157SKalle Valo 2895e3dd157SKalle Valo static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb) 2905e3dd157SKalle Valo { 2915e3dd157SKalle Valo struct sk_buff *next; 2925e3dd157SKalle Valo 2935e3dd157SKalle Valo while (skb) { 2945e3dd157SKalle Valo next = skb->next; 2955e3dd157SKalle Valo dev_kfree_skb_any(skb); 2965e3dd157SKalle Valo skb = next; 2975e3dd157SKalle Valo } 2985e3dd157SKalle Valo } 2995e3dd157SKalle Valo 300d84dd60fSJanusz Dziedzic /* return: < 0 fatal error, 0 - non chained msdu, 1 chained msdu */ 3015e3dd157SKalle Valo static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt, 3025e3dd157SKalle Valo u8 **fw_desc, int *fw_desc_len, 3035e3dd157SKalle Valo struct sk_buff **head_msdu, 3045e3dd157SKalle Valo struct sk_buff **tail_msdu) 3055e3dd157SKalle Valo { 3065e3dd157SKalle Valo int msdu_len, msdu_chaining = 0; 3075e3dd157SKalle Valo struct sk_buff *msdu; 3085e3dd157SKalle Valo struct htt_rx_desc *rx_desc; 3095e3dd157SKalle Valo 31045967089SMichal Kazior lockdep_assert_held(&htt->rx_ring.lock); 31145967089SMichal Kazior 3125e3dd157SKalle Valo if (htt->rx_confused) { 3135e3dd157SKalle Valo ath10k_warn("htt is confused. refusing rx\n"); 314d84dd60fSJanusz Dziedzic return -1; 3155e3dd157SKalle Valo } 3165e3dd157SKalle Valo 3175e3dd157SKalle Valo msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt); 3185e3dd157SKalle Valo while (msdu) { 3195e3dd157SKalle Valo int last_msdu, msdu_len_invalid, msdu_chained; 3205e3dd157SKalle Valo 3215e3dd157SKalle Valo dma_unmap_single(htt->ar->dev, 3225e3dd157SKalle Valo ATH10K_SKB_CB(msdu)->paddr, 3235e3dd157SKalle Valo msdu->len + skb_tailroom(msdu), 3245e3dd157SKalle Valo DMA_FROM_DEVICE); 3255e3dd157SKalle Valo 32675fb2f94SBen Greear ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx pop: ", 3275e3dd157SKalle Valo msdu->data, msdu->len + skb_tailroom(msdu)); 3285e3dd157SKalle Valo 3295e3dd157SKalle Valo rx_desc = (struct htt_rx_desc *)msdu->data; 3305e3dd157SKalle Valo 3315e3dd157SKalle Valo /* FIXME: we must report msdu payload since this is what caller 3325e3dd157SKalle Valo * expects now */ 3335e3dd157SKalle Valo skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload)); 3345e3dd157SKalle Valo skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload)); 3355e3dd157SKalle Valo 3365e3dd157SKalle Valo /* 3375e3dd157SKalle Valo * Sanity check - confirm the HW is finished filling in the 3385e3dd157SKalle Valo * rx data. 3395e3dd157SKalle Valo * If the HW and SW are working correctly, then it's guaranteed 3405e3dd157SKalle Valo * that the HW's MAC DMA is done before this point in the SW. 3415e3dd157SKalle Valo * To prevent the case that we handle a stale Rx descriptor, 3425e3dd157SKalle Valo * just assert for now until we have a way to recover. 3435e3dd157SKalle Valo */ 3445e3dd157SKalle Valo if (!(__le32_to_cpu(rx_desc->attention.flags) 3455e3dd157SKalle Valo & RX_ATTENTION_FLAGS_MSDU_DONE)) { 3465e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(*head_msdu); 3475e3dd157SKalle Valo *head_msdu = NULL; 3485e3dd157SKalle Valo msdu = NULL; 3495e3dd157SKalle Valo ath10k_err("htt rx stopped. cannot recover\n"); 3505e3dd157SKalle Valo htt->rx_confused = true; 3515e3dd157SKalle Valo break; 3525e3dd157SKalle Valo } 3535e3dd157SKalle Valo 3545e3dd157SKalle Valo /* 3555e3dd157SKalle Valo * Copy the FW rx descriptor for this MSDU from the rx 3565e3dd157SKalle Valo * indication message into the MSDU's netbuf. HL uses the 3575e3dd157SKalle Valo * same rx indication message definition as LL, and simply 3585e3dd157SKalle Valo * appends new info (fields from the HW rx desc, and the 3595e3dd157SKalle Valo * MSDU payload itself). So, the offset into the rx 3605e3dd157SKalle Valo * indication message only has to account for the standard 3615e3dd157SKalle Valo * offset of the per-MSDU FW rx desc info within the 3625e3dd157SKalle Valo * message, and how many bytes of the per-MSDU FW rx desc 3635e3dd157SKalle Valo * info have already been consumed. (And the endianness of 3645e3dd157SKalle Valo * the host, since for a big-endian host, the rx ind 3655e3dd157SKalle Valo * message contents, including the per-MSDU rx desc bytes, 3665e3dd157SKalle Valo * were byteswapped during upload.) 3675e3dd157SKalle Valo */ 3685e3dd157SKalle Valo if (*fw_desc_len > 0) { 3695e3dd157SKalle Valo rx_desc->fw_desc.info0 = **fw_desc; 3705e3dd157SKalle Valo /* 3715e3dd157SKalle Valo * The target is expected to only provide the basic 3725e3dd157SKalle Valo * per-MSDU rx descriptors. Just to be sure, verify 3735e3dd157SKalle Valo * that the target has not attached extension data 3745e3dd157SKalle Valo * (e.g. LRO flow ID). 3755e3dd157SKalle Valo */ 3765e3dd157SKalle Valo 3775e3dd157SKalle Valo /* or more, if there's extension data */ 3785e3dd157SKalle Valo (*fw_desc)++; 3795e3dd157SKalle Valo (*fw_desc_len)--; 3805e3dd157SKalle Valo } else { 3815e3dd157SKalle Valo /* 3825e3dd157SKalle Valo * When an oversized AMSDU happened, FW will lost 3835e3dd157SKalle Valo * some of MSDU status - in this case, the FW 3845e3dd157SKalle Valo * descriptors provided will be less than the 3855e3dd157SKalle Valo * actual MSDUs inside this MPDU. Mark the FW 3865e3dd157SKalle Valo * descriptors so that it will still deliver to 3875e3dd157SKalle Valo * upper stack, if no CRC error for this MPDU. 3885e3dd157SKalle Valo * 3895e3dd157SKalle Valo * FIX THIS - the FW descriptors are actually for 3905e3dd157SKalle Valo * MSDUs in the end of this A-MSDU instead of the 3915e3dd157SKalle Valo * beginning. 3925e3dd157SKalle Valo */ 3935e3dd157SKalle Valo rx_desc->fw_desc.info0 = 0; 3945e3dd157SKalle Valo } 3955e3dd157SKalle Valo 3965e3dd157SKalle Valo msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags) 3975e3dd157SKalle Valo & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR | 3985e3dd157SKalle Valo RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR)); 3995e3dd157SKalle Valo msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0), 4005e3dd157SKalle Valo RX_MSDU_START_INFO0_MSDU_LENGTH); 4015e3dd157SKalle Valo msdu_chained = rx_desc->frag_info.ring2_more_count; 402bfa35368SBen Greear msdu_chaining = msdu_chained; 4035e3dd157SKalle Valo 4045e3dd157SKalle Valo if (msdu_len_invalid) 4055e3dd157SKalle Valo msdu_len = 0; 4065e3dd157SKalle Valo 4075e3dd157SKalle Valo skb_trim(msdu, 0); 4085e3dd157SKalle Valo skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE)); 4095e3dd157SKalle Valo msdu_len -= msdu->len; 4105e3dd157SKalle Valo 4115e3dd157SKalle Valo /* FIXME: Do chained buffers include htt_rx_desc or not? */ 4125e3dd157SKalle Valo while (msdu_chained--) { 4135e3dd157SKalle Valo struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt); 4145e3dd157SKalle Valo 4155e3dd157SKalle Valo dma_unmap_single(htt->ar->dev, 4165e3dd157SKalle Valo ATH10K_SKB_CB(next)->paddr, 4175e3dd157SKalle Valo next->len + skb_tailroom(next), 4185e3dd157SKalle Valo DMA_FROM_DEVICE); 4195e3dd157SKalle Valo 42075fb2f94SBen Greear ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, 42175fb2f94SBen Greear "htt rx chained: ", next->data, 4225e3dd157SKalle Valo next->len + skb_tailroom(next)); 4235e3dd157SKalle Valo 4245e3dd157SKalle Valo skb_trim(next, 0); 4255e3dd157SKalle Valo skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE)); 4265e3dd157SKalle Valo msdu_len -= next->len; 4275e3dd157SKalle Valo 4285e3dd157SKalle Valo msdu->next = next; 4295e3dd157SKalle Valo msdu = next; 4305e3dd157SKalle Valo } 4315e3dd157SKalle Valo 4325e3dd157SKalle Valo last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) & 4335e3dd157SKalle Valo RX_MSDU_END_INFO0_LAST_MSDU; 4345e3dd157SKalle Valo 4355e3dd157SKalle Valo if (last_msdu) { 4365e3dd157SKalle Valo msdu->next = NULL; 4375e3dd157SKalle Valo break; 4385e3dd157SKalle Valo } else { 4395e3dd157SKalle Valo struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt); 4405e3dd157SKalle Valo msdu->next = next; 4415e3dd157SKalle Valo msdu = next; 4425e3dd157SKalle Valo } 4435e3dd157SKalle Valo } 4445e3dd157SKalle Valo *tail_msdu = msdu; 4455e3dd157SKalle Valo 446d84dd60fSJanusz Dziedzic if (*head_msdu == NULL) 447d84dd60fSJanusz Dziedzic msdu_chaining = -1; 448d84dd60fSJanusz Dziedzic 4495e3dd157SKalle Valo /* 4505e3dd157SKalle Valo * Don't refill the ring yet. 4515e3dd157SKalle Valo * 4525e3dd157SKalle Valo * First, the elements popped here are still in use - it is not 4535e3dd157SKalle Valo * safe to overwrite them until the matching call to 4545e3dd157SKalle Valo * mpdu_desc_list_next. Second, for efficiency it is preferable to 4555e3dd157SKalle Valo * refill the rx ring with 1 PPDU's worth of rx buffers (something 4565e3dd157SKalle Valo * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers 4575e3dd157SKalle Valo * (something like 3 buffers). Consequently, we'll rely on the txrx 4585e3dd157SKalle Valo * SW to tell us when it is done pulling all the PPDU's rx buffers 4595e3dd157SKalle Valo * out of the rx ring, and then refill it just once. 4605e3dd157SKalle Valo */ 4615e3dd157SKalle Valo 4625e3dd157SKalle Valo return msdu_chaining; 4635e3dd157SKalle Valo } 4645e3dd157SKalle Valo 4656e712d42SMichal Kazior static void ath10k_htt_rx_replenish_task(unsigned long ptr) 4666e712d42SMichal Kazior { 4676e712d42SMichal Kazior struct ath10k_htt *htt = (struct ath10k_htt *)ptr; 4686e712d42SMichal Kazior ath10k_htt_rx_msdu_buff_replenish(htt); 4696e712d42SMichal Kazior } 4706e712d42SMichal Kazior 4715e3dd157SKalle Valo int ath10k_htt_rx_attach(struct ath10k_htt *htt) 4725e3dd157SKalle Valo { 4735e3dd157SKalle Valo dma_addr_t paddr; 4745e3dd157SKalle Valo void *vaddr; 4755e3dd157SKalle Valo struct timer_list *timer = &htt->rx_ring.refill_retry_timer; 4765e3dd157SKalle Valo 4775e3dd157SKalle Valo htt->rx_ring.size = ath10k_htt_rx_ring_size(htt); 4785e3dd157SKalle Valo if (!is_power_of_2(htt->rx_ring.size)) { 4795e3dd157SKalle Valo ath10k_warn("htt rx ring size is not power of 2\n"); 4805e3dd157SKalle Valo return -EINVAL; 4815e3dd157SKalle Valo } 4825e3dd157SKalle Valo 4835e3dd157SKalle Valo htt->rx_ring.size_mask = htt->rx_ring.size - 1; 4845e3dd157SKalle Valo 4855e3dd157SKalle Valo /* 4865e3dd157SKalle Valo * Set the initial value for the level to which the rx ring 4875e3dd157SKalle Valo * should be filled, based on the max throughput and the 4885e3dd157SKalle Valo * worst likely latency for the host to fill the rx ring 4895e3dd157SKalle Valo * with new buffers. In theory, this fill level can be 4905e3dd157SKalle Valo * dynamically adjusted from the initial value set here, to 4915e3dd157SKalle Valo * reflect the actual host latency rather than a 4925e3dd157SKalle Valo * conservative assumption about the host latency. 4935e3dd157SKalle Valo */ 4945e3dd157SKalle Valo htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt); 4955e3dd157SKalle Valo 4965e3dd157SKalle Valo htt->rx_ring.netbufs_ring = 4975e3dd157SKalle Valo kmalloc(htt->rx_ring.size * sizeof(struct sk_buff *), 4985e3dd157SKalle Valo GFP_KERNEL); 4995e3dd157SKalle Valo if (!htt->rx_ring.netbufs_ring) 5005e3dd157SKalle Valo goto err_netbuf; 5015e3dd157SKalle Valo 5025e3dd157SKalle Valo vaddr = dma_alloc_coherent(htt->ar->dev, 5035e3dd157SKalle Valo (htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring)), 5045e3dd157SKalle Valo &paddr, GFP_DMA); 5055e3dd157SKalle Valo if (!vaddr) 5065e3dd157SKalle Valo goto err_dma_ring; 5075e3dd157SKalle Valo 5085e3dd157SKalle Valo htt->rx_ring.paddrs_ring = vaddr; 5095e3dd157SKalle Valo htt->rx_ring.base_paddr = paddr; 5105e3dd157SKalle Valo 5115e3dd157SKalle Valo vaddr = dma_alloc_coherent(htt->ar->dev, 5125e3dd157SKalle Valo sizeof(*htt->rx_ring.alloc_idx.vaddr), 5135e3dd157SKalle Valo &paddr, GFP_DMA); 5145e3dd157SKalle Valo if (!vaddr) 5155e3dd157SKalle Valo goto err_dma_idx; 5165e3dd157SKalle Valo 5175e3dd157SKalle Valo htt->rx_ring.alloc_idx.vaddr = vaddr; 5185e3dd157SKalle Valo htt->rx_ring.alloc_idx.paddr = paddr; 5195e3dd157SKalle Valo htt->rx_ring.sw_rd_idx.msdu_payld = 0; 5205e3dd157SKalle Valo *htt->rx_ring.alloc_idx.vaddr = 0; 5215e3dd157SKalle Valo 5225e3dd157SKalle Valo /* Initialize the Rx refill retry timer */ 5235e3dd157SKalle Valo setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt); 5245e3dd157SKalle Valo 5255e3dd157SKalle Valo spin_lock_init(&htt->rx_ring.lock); 5265e3dd157SKalle Valo 5275e3dd157SKalle Valo htt->rx_ring.fill_cnt = 0; 5285e3dd157SKalle Valo if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level)) 5295e3dd157SKalle Valo goto err_fill_ring; 5305e3dd157SKalle Valo 5316e712d42SMichal Kazior tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task, 5326e712d42SMichal Kazior (unsigned long)htt); 5336e712d42SMichal Kazior 5346c5151a9SMichal Kazior skb_queue_head_init(&htt->tx_compl_q); 5356c5151a9SMichal Kazior skb_queue_head_init(&htt->rx_compl_q); 5366c5151a9SMichal Kazior 5376c5151a9SMichal Kazior tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task, 5386c5151a9SMichal Kazior (unsigned long)htt); 5396c5151a9SMichal Kazior 540aad0b65fSKalle Valo ath10k_dbg(ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n", 5415e3dd157SKalle Valo htt->rx_ring.size, htt->rx_ring.fill_level); 5425e3dd157SKalle Valo return 0; 5435e3dd157SKalle Valo 5445e3dd157SKalle Valo err_fill_ring: 5455e3dd157SKalle Valo ath10k_htt_rx_ring_free(htt); 5465e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 5475e3dd157SKalle Valo sizeof(*htt->rx_ring.alloc_idx.vaddr), 5485e3dd157SKalle Valo htt->rx_ring.alloc_idx.vaddr, 5495e3dd157SKalle Valo htt->rx_ring.alloc_idx.paddr); 5505e3dd157SKalle Valo err_dma_idx: 5515e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 5525e3dd157SKalle Valo (htt->rx_ring.size * 5535e3dd157SKalle Valo sizeof(htt->rx_ring.paddrs_ring)), 5545e3dd157SKalle Valo htt->rx_ring.paddrs_ring, 5555e3dd157SKalle Valo htt->rx_ring.base_paddr); 5565e3dd157SKalle Valo err_dma_ring: 5575e3dd157SKalle Valo kfree(htt->rx_ring.netbufs_ring); 5585e3dd157SKalle Valo err_netbuf: 5595e3dd157SKalle Valo return -ENOMEM; 5605e3dd157SKalle Valo } 5615e3dd157SKalle Valo 5625e3dd157SKalle Valo static int ath10k_htt_rx_crypto_param_len(enum htt_rx_mpdu_encrypt_type type) 5635e3dd157SKalle Valo { 5645e3dd157SKalle Valo switch (type) { 5655e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP40: 5665e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP104: 5675e3dd157SKalle Valo return 4; 5685e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC: 5695e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP128: /* not tested */ 5705e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WPA: 5715e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WAPI: /* not tested */ 5725e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2: 5735e3dd157SKalle Valo return 8; 5745e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_NONE: 5755e3dd157SKalle Valo return 0; 5765e3dd157SKalle Valo } 5775e3dd157SKalle Valo 5785e3dd157SKalle Valo ath10k_warn("unknown encryption type %d\n", type); 5795e3dd157SKalle Valo return 0; 5805e3dd157SKalle Valo } 5815e3dd157SKalle Valo 5825e3dd157SKalle Valo static int ath10k_htt_rx_crypto_tail_len(enum htt_rx_mpdu_encrypt_type type) 5835e3dd157SKalle Valo { 5845e3dd157SKalle Valo switch (type) { 5855e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_NONE: 5865e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP40: 5875e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP104: 5885e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP128: 5895e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WAPI: 5905e3dd157SKalle Valo return 0; 5915e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC: 5925e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WPA: 5935e3dd157SKalle Valo return 4; 5945e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2: 5955e3dd157SKalle Valo return 8; 5965e3dd157SKalle Valo } 5975e3dd157SKalle Valo 5985e3dd157SKalle Valo ath10k_warn("unknown encryption type %d\n", type); 5995e3dd157SKalle Valo return 0; 6005e3dd157SKalle Valo } 6015e3dd157SKalle Valo 6025e3dd157SKalle Valo /* Applies for first msdu in chain, before altering it. */ 6035e3dd157SKalle Valo static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb) 6045e3dd157SKalle Valo { 6055e3dd157SKalle Valo struct htt_rx_desc *rxd; 6065e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 6075e3dd157SKalle Valo 6085e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 6095e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 6105e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 6115e3dd157SKalle Valo 6125e3dd157SKalle Valo if (fmt == RX_MSDU_DECAP_RAW) 6135e3dd157SKalle Valo return (void *)skb->data; 6145e3dd157SKalle Valo else 6155e3dd157SKalle Valo return (void *)skb->data - RX_HTT_HDR_STATUS_LEN; 6165e3dd157SKalle Valo } 6175e3dd157SKalle Valo 6185e3dd157SKalle Valo /* This function only applies for first msdu in an msdu chain */ 6195e3dd157SKalle Valo static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr) 6205e3dd157SKalle Valo { 6215e3dd157SKalle Valo if (ieee80211_is_data_qos(hdr->frame_control)) { 6225e3dd157SKalle Valo u8 *qc = ieee80211_get_qos_ctl(hdr); 6235e3dd157SKalle Valo if (qc[0] & 0x80) 6245e3dd157SKalle Valo return true; 6255e3dd157SKalle Valo } 6265e3dd157SKalle Valo return false; 6275e3dd157SKalle Valo } 6285e3dd157SKalle Valo 629f6dc2095SMichal Kazior struct rfc1042_hdr { 630f6dc2095SMichal Kazior u8 llc_dsap; 631f6dc2095SMichal Kazior u8 llc_ssap; 632f6dc2095SMichal Kazior u8 llc_ctrl; 633f6dc2095SMichal Kazior u8 snap_oui[3]; 634f6dc2095SMichal Kazior __be16 snap_type; 635f6dc2095SMichal Kazior } __packed; 636f6dc2095SMichal Kazior 637f6dc2095SMichal Kazior struct amsdu_subframe_hdr { 638f6dc2095SMichal Kazior u8 dst[ETH_ALEN]; 639f6dc2095SMichal Kazior u8 src[ETH_ALEN]; 640f6dc2095SMichal Kazior __be16 len; 641f6dc2095SMichal Kazior } __packed; 642f6dc2095SMichal Kazior 64373539b40SJanusz Dziedzic static const u8 rx_legacy_rate_idx[] = { 64473539b40SJanusz Dziedzic 3, /* 0x00 - 11Mbps */ 64573539b40SJanusz Dziedzic 2, /* 0x01 - 5.5Mbps */ 64673539b40SJanusz Dziedzic 1, /* 0x02 - 2Mbps */ 64773539b40SJanusz Dziedzic 0, /* 0x03 - 1Mbps */ 64873539b40SJanusz Dziedzic 3, /* 0x04 - 11Mbps */ 64973539b40SJanusz Dziedzic 2, /* 0x05 - 5.5Mbps */ 65073539b40SJanusz Dziedzic 1, /* 0x06 - 2Mbps */ 65173539b40SJanusz Dziedzic 0, /* 0x07 - 1Mbps */ 65273539b40SJanusz Dziedzic 10, /* 0x08 - 48Mbps */ 65373539b40SJanusz Dziedzic 8, /* 0x09 - 24Mbps */ 65473539b40SJanusz Dziedzic 6, /* 0x0A - 12Mbps */ 65573539b40SJanusz Dziedzic 4, /* 0x0B - 6Mbps */ 65673539b40SJanusz Dziedzic 11, /* 0x0C - 54Mbps */ 65773539b40SJanusz Dziedzic 9, /* 0x0D - 36Mbps */ 65873539b40SJanusz Dziedzic 7, /* 0x0E - 18Mbps */ 65973539b40SJanusz Dziedzic 5, /* 0x0F - 9Mbps */ 66073539b40SJanusz Dziedzic }; 66173539b40SJanusz Dziedzic 66287326c97SJanusz Dziedzic static void ath10k_htt_rx_h_rates(struct ath10k *ar, 66373539b40SJanusz Dziedzic enum ieee80211_band band, 66487326c97SJanusz Dziedzic u8 info0, u32 info1, u32 info2, 66573539b40SJanusz Dziedzic struct ieee80211_rx_status *status) 66673539b40SJanusz Dziedzic { 66773539b40SJanusz Dziedzic u8 cck, rate, rate_idx, bw, sgi, mcs, nss; 66873539b40SJanusz Dziedzic u8 preamble = 0; 66973539b40SJanusz Dziedzic 67073539b40SJanusz Dziedzic /* Check if valid fields */ 67173539b40SJanusz Dziedzic if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID)) 67273539b40SJanusz Dziedzic return; 67373539b40SJanusz Dziedzic 67473539b40SJanusz Dziedzic preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE); 67573539b40SJanusz Dziedzic 67673539b40SJanusz Dziedzic switch (preamble) { 67773539b40SJanusz Dziedzic case HTT_RX_LEGACY: 67873539b40SJanusz Dziedzic cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK; 67973539b40SJanusz Dziedzic rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE); 68073539b40SJanusz Dziedzic rate_idx = 0; 68173539b40SJanusz Dziedzic 68273539b40SJanusz Dziedzic if (rate < 0x08 || rate > 0x0F) 68373539b40SJanusz Dziedzic break; 68473539b40SJanusz Dziedzic 68573539b40SJanusz Dziedzic switch (band) { 68673539b40SJanusz Dziedzic case IEEE80211_BAND_2GHZ: 68773539b40SJanusz Dziedzic if (cck) 68873539b40SJanusz Dziedzic rate &= ~BIT(3); 68973539b40SJanusz Dziedzic rate_idx = rx_legacy_rate_idx[rate]; 69073539b40SJanusz Dziedzic break; 69173539b40SJanusz Dziedzic case IEEE80211_BAND_5GHZ: 69273539b40SJanusz Dziedzic rate_idx = rx_legacy_rate_idx[rate]; 69373539b40SJanusz Dziedzic /* We are using same rate table registering 69473539b40SJanusz Dziedzic HW - ath10k_rates[]. In case of 5GHz skip 69573539b40SJanusz Dziedzic CCK rates, so -4 here */ 69673539b40SJanusz Dziedzic rate_idx -= 4; 69773539b40SJanusz Dziedzic break; 69873539b40SJanusz Dziedzic default: 69973539b40SJanusz Dziedzic break; 70073539b40SJanusz Dziedzic } 70173539b40SJanusz Dziedzic 70273539b40SJanusz Dziedzic status->rate_idx = rate_idx; 70373539b40SJanusz Dziedzic break; 70473539b40SJanusz Dziedzic case HTT_RX_HT: 70573539b40SJanusz Dziedzic case HTT_RX_HT_WITH_TXBF: 70673539b40SJanusz Dziedzic /* HT-SIG - Table 20-11 in info1 and info2 */ 70773539b40SJanusz Dziedzic mcs = info1 & 0x1F; 70873539b40SJanusz Dziedzic nss = mcs >> 3; 70973539b40SJanusz Dziedzic bw = (info1 >> 7) & 1; 71073539b40SJanusz Dziedzic sgi = (info2 >> 7) & 1; 71173539b40SJanusz Dziedzic 71273539b40SJanusz Dziedzic status->rate_idx = mcs; 71373539b40SJanusz Dziedzic status->flag |= RX_FLAG_HT; 71473539b40SJanusz Dziedzic if (sgi) 71573539b40SJanusz Dziedzic status->flag |= RX_FLAG_SHORT_GI; 71673539b40SJanusz Dziedzic if (bw) 71773539b40SJanusz Dziedzic status->flag |= RX_FLAG_40MHZ; 71873539b40SJanusz Dziedzic break; 71973539b40SJanusz Dziedzic case HTT_RX_VHT: 72073539b40SJanusz Dziedzic case HTT_RX_VHT_WITH_TXBF: 72173539b40SJanusz Dziedzic /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2 72273539b40SJanusz Dziedzic TODO check this */ 72373539b40SJanusz Dziedzic mcs = (info2 >> 4) & 0x0F; 72473539b40SJanusz Dziedzic nss = ((info1 >> 10) & 0x07) + 1; 72573539b40SJanusz Dziedzic bw = info1 & 3; 72673539b40SJanusz Dziedzic sgi = info2 & 1; 72773539b40SJanusz Dziedzic 72873539b40SJanusz Dziedzic status->rate_idx = mcs; 72973539b40SJanusz Dziedzic status->vht_nss = nss; 73073539b40SJanusz Dziedzic 73173539b40SJanusz Dziedzic if (sgi) 73273539b40SJanusz Dziedzic status->flag |= RX_FLAG_SHORT_GI; 73373539b40SJanusz Dziedzic 73473539b40SJanusz Dziedzic switch (bw) { 73573539b40SJanusz Dziedzic /* 20MHZ */ 73673539b40SJanusz Dziedzic case 0: 73773539b40SJanusz Dziedzic break; 73873539b40SJanusz Dziedzic /* 40MHZ */ 73973539b40SJanusz Dziedzic case 1: 74073539b40SJanusz Dziedzic status->flag |= RX_FLAG_40MHZ; 74173539b40SJanusz Dziedzic break; 74273539b40SJanusz Dziedzic /* 80MHZ */ 74373539b40SJanusz Dziedzic case 2: 74473539b40SJanusz Dziedzic status->vht_flag |= RX_VHT_FLAG_80MHZ; 74573539b40SJanusz Dziedzic } 74673539b40SJanusz Dziedzic 74773539b40SJanusz Dziedzic status->flag |= RX_FLAG_VHT; 74873539b40SJanusz Dziedzic break; 74973539b40SJanusz Dziedzic default: 75073539b40SJanusz Dziedzic break; 75173539b40SJanusz Dziedzic } 75273539b40SJanusz Dziedzic } 75373539b40SJanusz Dziedzic 75487326c97SJanusz Dziedzic static void ath10k_htt_rx_h_protected(struct ath10k_htt *htt, 75585f6d7cfSJanusz Dziedzic struct ieee80211_rx_status *rx_status, 75685f6d7cfSJanusz Dziedzic struct sk_buff *skb, 75787326c97SJanusz Dziedzic enum htt_rx_mpdu_encrypt_type enctype) 75887326c97SJanusz Dziedzic { 75985f6d7cfSJanusz Dziedzic struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 76087326c97SJanusz Dziedzic 76187326c97SJanusz Dziedzic 76287326c97SJanusz Dziedzic if (enctype == HTT_RX_MPDU_ENCRYPT_NONE) { 76385f6d7cfSJanusz Dziedzic rx_status->flag &= ~(RX_FLAG_DECRYPTED | 76487326c97SJanusz Dziedzic RX_FLAG_IV_STRIPPED | 76587326c97SJanusz Dziedzic RX_FLAG_MMIC_STRIPPED); 76687326c97SJanusz Dziedzic return; 76787326c97SJanusz Dziedzic } 76887326c97SJanusz Dziedzic 76985f6d7cfSJanusz Dziedzic rx_status->flag |= RX_FLAG_DECRYPTED | 77087326c97SJanusz Dziedzic RX_FLAG_IV_STRIPPED | 77187326c97SJanusz Dziedzic RX_FLAG_MMIC_STRIPPED; 77287326c97SJanusz Dziedzic hdr->frame_control = __cpu_to_le16(__le16_to_cpu(hdr->frame_control) & 77387326c97SJanusz Dziedzic ~IEEE80211_FCTL_PROTECTED); 77487326c97SJanusz Dziedzic } 77587326c97SJanusz Dziedzic 77636653f05SJanusz Dziedzic static bool ath10k_htt_rx_h_channel(struct ath10k *ar, 77736653f05SJanusz Dziedzic struct ieee80211_rx_status *status) 77836653f05SJanusz Dziedzic { 77936653f05SJanusz Dziedzic struct ieee80211_channel *ch; 78036653f05SJanusz Dziedzic 78136653f05SJanusz Dziedzic spin_lock_bh(&ar->data_lock); 78236653f05SJanusz Dziedzic ch = ar->scan_channel; 78336653f05SJanusz Dziedzic if (!ch) 78436653f05SJanusz Dziedzic ch = ar->rx_channel; 78536653f05SJanusz Dziedzic spin_unlock_bh(&ar->data_lock); 78636653f05SJanusz Dziedzic 78736653f05SJanusz Dziedzic if (!ch) 78836653f05SJanusz Dziedzic return false; 78936653f05SJanusz Dziedzic 79036653f05SJanusz Dziedzic status->band = ch->band; 79136653f05SJanusz Dziedzic status->freq = ch->center_freq; 79236653f05SJanusz Dziedzic 79336653f05SJanusz Dziedzic return true; 79436653f05SJanusz Dziedzic } 79536653f05SJanusz Dziedzic 79685f6d7cfSJanusz Dziedzic static void ath10k_process_rx(struct ath10k *ar, 79785f6d7cfSJanusz Dziedzic struct ieee80211_rx_status *rx_status, 79885f6d7cfSJanusz Dziedzic struct sk_buff *skb) 79973539b40SJanusz Dziedzic { 80073539b40SJanusz Dziedzic struct ieee80211_rx_status *status; 80173539b40SJanusz Dziedzic 80285f6d7cfSJanusz Dziedzic status = IEEE80211_SKB_RXCB(skb); 80385f6d7cfSJanusz Dziedzic *status = *rx_status; 80473539b40SJanusz Dziedzic 80573539b40SJanusz Dziedzic ath10k_dbg(ATH10K_DBG_DATA, 80678433f96SJanusz Dziedzic "rx skb %p len %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %imic-err %i\n", 80785f6d7cfSJanusz Dziedzic skb, 80885f6d7cfSJanusz Dziedzic skb->len, 80973539b40SJanusz Dziedzic status->flag == 0 ? "legacy" : "", 81073539b40SJanusz Dziedzic status->flag & RX_FLAG_HT ? "ht" : "", 81173539b40SJanusz Dziedzic status->flag & RX_FLAG_VHT ? "vht" : "", 81273539b40SJanusz Dziedzic status->flag & RX_FLAG_40MHZ ? "40" : "", 81373539b40SJanusz Dziedzic status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "", 81473539b40SJanusz Dziedzic status->flag & RX_FLAG_SHORT_GI ? "sgi " : "", 81573539b40SJanusz Dziedzic status->rate_idx, 81673539b40SJanusz Dziedzic status->vht_nss, 81773539b40SJanusz Dziedzic status->freq, 81887326c97SJanusz Dziedzic status->band, status->flag, 81978433f96SJanusz Dziedzic !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 82078433f96SJanusz Dziedzic !!(status->flag & RX_FLAG_MMIC_ERROR)); 82173539b40SJanusz Dziedzic ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ", 82285f6d7cfSJanusz Dziedzic skb->data, skb->len); 82373539b40SJanusz Dziedzic 82485f6d7cfSJanusz Dziedzic ieee80211_rx(ar->hw, skb); 82573539b40SJanusz Dziedzic } 82673539b40SJanusz Dziedzic 827d960c369SMichal Kazior static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr) 828d960c369SMichal Kazior { 829d960c369SMichal Kazior /* nwifi header is padded to 4 bytes. this fixes 4addr rx */ 830d960c369SMichal Kazior return round_up(ieee80211_hdrlen(hdr->frame_control), 4); 831d960c369SMichal Kazior } 832d960c369SMichal Kazior 833f6dc2095SMichal Kazior static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt, 83485f6d7cfSJanusz Dziedzic struct ieee80211_rx_status *rx_status, 83585f6d7cfSJanusz Dziedzic struct sk_buff *skb_in) 8365e3dd157SKalle Valo { 8375e3dd157SKalle Valo struct htt_rx_desc *rxd; 83885f6d7cfSJanusz Dziedzic struct sk_buff *skb = skb_in; 8395e3dd157SKalle Valo struct sk_buff *first; 8405e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 8415e3dd157SKalle Valo enum htt_rx_mpdu_encrypt_type enctype; 842f6dc2095SMichal Kazior struct ieee80211_hdr *hdr; 843784f69d3SMichal Kazior u8 hdr_buf[64], addr[ETH_ALEN], *qos; 8445e3dd157SKalle Valo unsigned int hdr_len; 8455e3dd157SKalle Valo 8465e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 8475e3dd157SKalle Valo enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), 8485e3dd157SKalle Valo RX_MPDU_START_INFO0_ENCRYPT_TYPE); 8495e3dd157SKalle Valo 850f6dc2095SMichal Kazior hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; 851f6dc2095SMichal Kazior hdr_len = ieee80211_hdrlen(hdr->frame_control); 852f6dc2095SMichal Kazior memcpy(hdr_buf, hdr, hdr_len); 853f6dc2095SMichal Kazior hdr = (struct ieee80211_hdr *)hdr_buf; 8545e3dd157SKalle Valo 8555e3dd157SKalle Valo first = skb; 8565e3dd157SKalle Valo while (skb) { 8575e3dd157SKalle Valo void *decap_hdr; 858f6dc2095SMichal Kazior int len; 8595e3dd157SKalle Valo 8605e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 8615e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 8625e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 8635e3dd157SKalle Valo decap_hdr = (void *)rxd->rx_hdr_status; 8645e3dd157SKalle Valo 865f6dc2095SMichal Kazior skb->ip_summed = ath10k_htt_rx_get_csum_state(skb); 866f6dc2095SMichal Kazior 867f6dc2095SMichal Kazior /* First frame in an A-MSDU chain has more decapped data. */ 8685e3dd157SKalle Valo if (skb == first) { 869f6dc2095SMichal Kazior len = round_up(ieee80211_hdrlen(hdr->frame_control), 4); 870f6dc2095SMichal Kazior len += round_up(ath10k_htt_rx_crypto_param_len(enctype), 871f6dc2095SMichal Kazior 4); 872f6dc2095SMichal Kazior decap_hdr += len; 8735e3dd157SKalle Valo } 8745e3dd157SKalle Valo 875f6dc2095SMichal Kazior switch (fmt) { 876f6dc2095SMichal Kazior case RX_MSDU_DECAP_RAW: 877e3fbf8d2SMichal Kazior /* remove trailing FCS */ 878f6dc2095SMichal Kazior skb_trim(skb, skb->len - FCS_LEN); 879f6dc2095SMichal Kazior break; 880f6dc2095SMichal Kazior case RX_MSDU_DECAP_NATIVE_WIFI: 881784f69d3SMichal Kazior /* pull decapped header and copy DA */ 882784f69d3SMichal Kazior hdr = (struct ieee80211_hdr *)skb->data; 883d960c369SMichal Kazior hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr); 884784f69d3SMichal Kazior memcpy(addr, ieee80211_get_DA(hdr), ETH_ALEN); 885784f69d3SMichal Kazior skb_pull(skb, hdr_len); 886784f69d3SMichal Kazior 887784f69d3SMichal Kazior /* push original 802.11 header */ 888784f69d3SMichal Kazior hdr = (struct ieee80211_hdr *)hdr_buf; 889784f69d3SMichal Kazior hdr_len = ieee80211_hdrlen(hdr->frame_control); 890784f69d3SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 891784f69d3SMichal Kazior 892784f69d3SMichal Kazior /* original A-MSDU header has the bit set but we're 893784f69d3SMichal Kazior * not including A-MSDU subframe header */ 894784f69d3SMichal Kazior hdr = (struct ieee80211_hdr *)skb->data; 895784f69d3SMichal Kazior qos = ieee80211_get_qos_ctl(hdr); 896784f69d3SMichal Kazior qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 897784f69d3SMichal Kazior 898784f69d3SMichal Kazior /* original 802.11 header has a different DA */ 899784f69d3SMichal Kazior memcpy(ieee80211_get_DA(hdr), addr, ETH_ALEN); 900f6dc2095SMichal Kazior break; 901f6dc2095SMichal Kazior case RX_MSDU_DECAP_ETHERNET2_DIX: 902e3fbf8d2SMichal Kazior /* strip ethernet header and insert decapped 802.11 903e3fbf8d2SMichal Kazior * header, amsdu subframe header and rfc1042 header */ 904e3fbf8d2SMichal Kazior 905f6dc2095SMichal Kazior len = 0; 906f6dc2095SMichal Kazior len += sizeof(struct rfc1042_hdr); 907f6dc2095SMichal Kazior len += sizeof(struct amsdu_subframe_hdr); 908dfa95b50SMichal Kazior 909f6dc2095SMichal Kazior skb_pull(skb, sizeof(struct ethhdr)); 910f6dc2095SMichal Kazior memcpy(skb_push(skb, len), decap_hdr, len); 911f6dc2095SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 912f6dc2095SMichal Kazior break; 913f6dc2095SMichal Kazior case RX_MSDU_DECAP_8023_SNAP_LLC: 914e3fbf8d2SMichal Kazior /* insert decapped 802.11 header making a singly 915e3fbf8d2SMichal Kazior * A-MSDU */ 916f6dc2095SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 917f6dc2095SMichal Kazior break; 9185e3dd157SKalle Valo } 9195e3dd157SKalle Valo 92085f6d7cfSJanusz Dziedzic skb_in = skb; 92185f6d7cfSJanusz Dziedzic ath10k_htt_rx_h_protected(htt, rx_status, skb_in, enctype); 922f6dc2095SMichal Kazior skb = skb->next; 92385f6d7cfSJanusz Dziedzic skb_in->next = NULL; 9245e3dd157SKalle Valo 925652de35eSKalle Valo if (skb) 92685f6d7cfSJanusz Dziedzic rx_status->flag |= RX_FLAG_AMSDU_MORE; 92787326c97SJanusz Dziedzic else 92885f6d7cfSJanusz Dziedzic rx_status->flag &= ~RX_FLAG_AMSDU_MORE; 929652de35eSKalle Valo 93085f6d7cfSJanusz Dziedzic ath10k_process_rx(htt->ar, rx_status, skb_in); 9315e3dd157SKalle Valo } 9325e3dd157SKalle Valo 933f6dc2095SMichal Kazior /* FIXME: It might be nice to re-assemble the A-MSDU when there's a 934f6dc2095SMichal Kazior * monitor interface active for sniffing purposes. */ 935f6dc2095SMichal Kazior } 936f6dc2095SMichal Kazior 93785f6d7cfSJanusz Dziedzic static void ath10k_htt_rx_msdu(struct ath10k_htt *htt, 93885f6d7cfSJanusz Dziedzic struct ieee80211_rx_status *rx_status, 93985f6d7cfSJanusz Dziedzic struct sk_buff *skb) 9405e3dd157SKalle Valo { 9415e3dd157SKalle Valo struct htt_rx_desc *rxd; 9425e3dd157SKalle Valo struct ieee80211_hdr *hdr; 9435e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 9445e3dd157SKalle Valo enum htt_rx_mpdu_encrypt_type enctype; 945e3fbf8d2SMichal Kazior int hdr_len; 946e3fbf8d2SMichal Kazior void *rfc1042; 9475e3dd157SKalle Valo 9485e3dd157SKalle Valo /* This shouldn't happen. If it does than it may be a FW bug. */ 9495e3dd157SKalle Valo if (skb->next) { 95075fb2f94SBen Greear ath10k_warn("htt rx received chained non A-MSDU frame\n"); 9515e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(skb->next); 9525e3dd157SKalle Valo skb->next = NULL; 9535e3dd157SKalle Valo } 9545e3dd157SKalle Valo 9555e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 9565e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 9575e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 9585e3dd157SKalle Valo enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), 9595e3dd157SKalle Valo RX_MPDU_START_INFO0_ENCRYPT_TYPE); 960e3fbf8d2SMichal Kazior hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; 961e3fbf8d2SMichal Kazior hdr_len = ieee80211_hdrlen(hdr->frame_control); 9625e3dd157SKalle Valo 963f6dc2095SMichal Kazior skb->ip_summed = ath10k_htt_rx_get_csum_state(skb); 964f6dc2095SMichal Kazior 9655e3dd157SKalle Valo switch (fmt) { 9665e3dd157SKalle Valo case RX_MSDU_DECAP_RAW: 9675e3dd157SKalle Valo /* remove trailing FCS */ 968e3fbf8d2SMichal Kazior skb_trim(skb, skb->len - FCS_LEN); 9695e3dd157SKalle Valo break; 9705e3dd157SKalle Valo case RX_MSDU_DECAP_NATIVE_WIFI: 971784f69d3SMichal Kazior /* Pull decapped header */ 972784f69d3SMichal Kazior hdr = (struct ieee80211_hdr *)skb->data; 973d960c369SMichal Kazior hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr); 974784f69d3SMichal Kazior skb_pull(skb, hdr_len); 975784f69d3SMichal Kazior 976784f69d3SMichal Kazior /* Push original header */ 977784f69d3SMichal Kazior hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status; 978784f69d3SMichal Kazior hdr_len = ieee80211_hdrlen(hdr->frame_control); 979784f69d3SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 9805e3dd157SKalle Valo break; 9815e3dd157SKalle Valo case RX_MSDU_DECAP_ETHERNET2_DIX: 982e3fbf8d2SMichal Kazior /* strip ethernet header and insert decapped 802.11 header and 983e3fbf8d2SMichal Kazior * rfc1042 header */ 984e3fbf8d2SMichal Kazior 985e3fbf8d2SMichal Kazior rfc1042 = hdr; 986e3fbf8d2SMichal Kazior rfc1042 += roundup(hdr_len, 4); 987e3fbf8d2SMichal Kazior rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(enctype), 4); 988e3fbf8d2SMichal Kazior 989e3fbf8d2SMichal Kazior skb_pull(skb, sizeof(struct ethhdr)); 990e3fbf8d2SMichal Kazior memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)), 991e3fbf8d2SMichal Kazior rfc1042, sizeof(struct rfc1042_hdr)); 992e3fbf8d2SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 9935e3dd157SKalle Valo break; 9945e3dd157SKalle Valo case RX_MSDU_DECAP_8023_SNAP_LLC: 995e3fbf8d2SMichal Kazior /* remove A-MSDU subframe header and insert 996e3fbf8d2SMichal Kazior * decapped 802.11 header. rfc1042 header is already there */ 997e3fbf8d2SMichal Kazior 998e3fbf8d2SMichal Kazior skb_pull(skb, sizeof(struct amsdu_subframe_hdr)); 999e3fbf8d2SMichal Kazior memcpy(skb_push(skb, hdr_len), hdr, hdr_len); 10005e3dd157SKalle Valo break; 10015e3dd157SKalle Valo } 10025e3dd157SKalle Valo 100385f6d7cfSJanusz Dziedzic ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype); 1004f6dc2095SMichal Kazior 100585f6d7cfSJanusz Dziedzic ath10k_process_rx(htt->ar, rx_status, skb); 10065e3dd157SKalle Valo } 10075e3dd157SKalle Valo 1008605f81aaSMichal Kazior static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb) 1009605f81aaSMichal Kazior { 1010605f81aaSMichal Kazior struct htt_rx_desc *rxd; 1011605f81aaSMichal Kazior u32 flags, info; 1012605f81aaSMichal Kazior bool is_ip4, is_ip6; 1013605f81aaSMichal Kazior bool is_tcp, is_udp; 1014605f81aaSMichal Kazior bool ip_csum_ok, tcpudp_csum_ok; 1015605f81aaSMichal Kazior 1016605f81aaSMichal Kazior rxd = (void *)skb->data - sizeof(*rxd); 1017605f81aaSMichal Kazior flags = __le32_to_cpu(rxd->attention.flags); 1018605f81aaSMichal Kazior info = __le32_to_cpu(rxd->msdu_start.info1); 1019605f81aaSMichal Kazior 1020605f81aaSMichal Kazior is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO); 1021605f81aaSMichal Kazior is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO); 1022605f81aaSMichal Kazior is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO); 1023605f81aaSMichal Kazior is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO); 1024605f81aaSMichal Kazior ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL); 1025605f81aaSMichal Kazior tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL); 1026605f81aaSMichal Kazior 1027605f81aaSMichal Kazior if (!is_ip4 && !is_ip6) 1028605f81aaSMichal Kazior return CHECKSUM_NONE; 1029605f81aaSMichal Kazior if (!is_tcp && !is_udp) 1030605f81aaSMichal Kazior return CHECKSUM_NONE; 1031605f81aaSMichal Kazior if (!ip_csum_ok) 1032605f81aaSMichal Kazior return CHECKSUM_NONE; 1033605f81aaSMichal Kazior if (!tcpudp_csum_ok) 1034605f81aaSMichal Kazior return CHECKSUM_NONE; 1035605f81aaSMichal Kazior 1036605f81aaSMichal Kazior return CHECKSUM_UNNECESSARY; 1037605f81aaSMichal Kazior } 1038605f81aaSMichal Kazior 1039bfa35368SBen Greear static int ath10k_unchain_msdu(struct sk_buff *msdu_head) 1040bfa35368SBen Greear { 1041bfa35368SBen Greear struct sk_buff *next = msdu_head->next; 1042bfa35368SBen Greear struct sk_buff *to_free = next; 1043bfa35368SBen Greear int space; 1044bfa35368SBen Greear int total_len = 0; 1045bfa35368SBen Greear 1046bfa35368SBen Greear /* TODO: Might could optimize this by using 1047bfa35368SBen Greear * skb_try_coalesce or similar method to 1048bfa35368SBen Greear * decrease copying, or maybe get mac80211 to 1049bfa35368SBen Greear * provide a way to just receive a list of 1050bfa35368SBen Greear * skb? 1051bfa35368SBen Greear */ 1052bfa35368SBen Greear 1053bfa35368SBen Greear msdu_head->next = NULL; 1054bfa35368SBen Greear 1055bfa35368SBen Greear /* Allocate total length all at once. */ 1056bfa35368SBen Greear while (next) { 1057bfa35368SBen Greear total_len += next->len; 1058bfa35368SBen Greear next = next->next; 1059bfa35368SBen Greear } 1060bfa35368SBen Greear 1061bfa35368SBen Greear space = total_len - skb_tailroom(msdu_head); 1062bfa35368SBen Greear if ((space > 0) && 1063bfa35368SBen Greear (pskb_expand_head(msdu_head, 0, space, GFP_ATOMIC) < 0)) { 1064bfa35368SBen Greear /* TODO: bump some rx-oom error stat */ 1065bfa35368SBen Greear /* put it back together so we can free the 1066bfa35368SBen Greear * whole list at once. 1067bfa35368SBen Greear */ 1068bfa35368SBen Greear msdu_head->next = to_free; 1069bfa35368SBen Greear return -1; 1070bfa35368SBen Greear } 1071bfa35368SBen Greear 1072bfa35368SBen Greear /* Walk list again, copying contents into 1073bfa35368SBen Greear * msdu_head 1074bfa35368SBen Greear */ 1075bfa35368SBen Greear next = to_free; 1076bfa35368SBen Greear while (next) { 1077bfa35368SBen Greear skb_copy_from_linear_data(next, skb_put(msdu_head, next->len), 1078bfa35368SBen Greear next->len); 1079bfa35368SBen Greear next = next->next; 1080bfa35368SBen Greear } 1081bfa35368SBen Greear 1082bfa35368SBen Greear /* If here, we have consolidated skb. Free the 1083bfa35368SBen Greear * fragments and pass the main skb on up the 1084bfa35368SBen Greear * stack. 1085bfa35368SBen Greear */ 1086bfa35368SBen Greear ath10k_htt_rx_free_msdu_chain(to_free); 1087bfa35368SBen Greear return 0; 1088bfa35368SBen Greear } 1089bfa35368SBen Greear 10902acc4eb2SJanusz Dziedzic static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt, 10912acc4eb2SJanusz Dziedzic struct sk_buff *head, 109287326c97SJanusz Dziedzic enum htt_rx_mpdu_status status, 109378433f96SJanusz Dziedzic bool channel_set, 109478433f96SJanusz Dziedzic u32 attention) 10952acc4eb2SJanusz Dziedzic { 10962acc4eb2SJanusz Dziedzic if (head->len == 0) { 10972acc4eb2SJanusz Dziedzic ath10k_dbg(ATH10K_DBG_HTT, 10982acc4eb2SJanusz Dziedzic "htt rx dropping due to zero-len\n"); 10992acc4eb2SJanusz Dziedzic return false; 11002acc4eb2SJanusz Dziedzic } 11012acc4eb2SJanusz Dziedzic 110278433f96SJanusz Dziedzic if (attention & RX_ATTENTION_FLAGS_DECRYPT_ERR) { 11032acc4eb2SJanusz Dziedzic ath10k_dbg(ATH10K_DBG_HTT, 11042acc4eb2SJanusz Dziedzic "htt rx dropping due to decrypt-err\n"); 11052acc4eb2SJanusz Dziedzic return false; 11062acc4eb2SJanusz Dziedzic } 11072acc4eb2SJanusz Dziedzic 110836653f05SJanusz Dziedzic if (!channel_set) { 110936653f05SJanusz Dziedzic ath10k_warn("no channel configured; ignoring frame!\n"); 111036653f05SJanusz Dziedzic return false; 111136653f05SJanusz Dziedzic } 111236653f05SJanusz Dziedzic 11132acc4eb2SJanusz Dziedzic /* Skip mgmt frames while we handle this in WMI */ 11142acc4eb2SJanusz Dziedzic if (status == HTT_RX_IND_MPDU_STATUS_MGMT_CTRL || 111578433f96SJanusz Dziedzic attention & RX_ATTENTION_FLAGS_MGMT_TYPE) { 11162acc4eb2SJanusz Dziedzic ath10k_dbg(ATH10K_DBG_HTT, "htt rx mgmt ctrl\n"); 11172acc4eb2SJanusz Dziedzic return false; 11182acc4eb2SJanusz Dziedzic } 11192acc4eb2SJanusz Dziedzic 11202acc4eb2SJanusz Dziedzic if (status != HTT_RX_IND_MPDU_STATUS_OK && 11212acc4eb2SJanusz Dziedzic status != HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR && 11222acc4eb2SJanusz Dziedzic status != HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER && 11231bbc0975SMichal Kazior !htt->ar->monitor_started) { 11242acc4eb2SJanusz Dziedzic ath10k_dbg(ATH10K_DBG_HTT, 11252acc4eb2SJanusz Dziedzic "htt rx ignoring frame w/ status %d\n", 11262acc4eb2SJanusz Dziedzic status); 11272acc4eb2SJanusz Dziedzic return false; 11282acc4eb2SJanusz Dziedzic } 11292acc4eb2SJanusz Dziedzic 11302acc4eb2SJanusz Dziedzic if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) { 11312acc4eb2SJanusz Dziedzic ath10k_dbg(ATH10K_DBG_HTT, 11322acc4eb2SJanusz Dziedzic "htt rx CAC running\n"); 11332acc4eb2SJanusz Dziedzic return false; 11342acc4eb2SJanusz Dziedzic } 11352acc4eb2SJanusz Dziedzic 11362acc4eb2SJanusz Dziedzic return true; 11372acc4eb2SJanusz Dziedzic } 11382acc4eb2SJanusz Dziedzic 11395e3dd157SKalle Valo static void ath10k_htt_rx_handler(struct ath10k_htt *htt, 11405e3dd157SKalle Valo struct htt_rx_indication *rx) 11415e3dd157SKalle Valo { 11426df92a3dSJanusz Dziedzic struct ieee80211_rx_status *rx_status = &htt->rx_status; 11435e3dd157SKalle Valo struct htt_rx_indication_mpdu_range *mpdu_ranges; 114478433f96SJanusz Dziedzic struct htt_rx_desc *rxd; 114587326c97SJanusz Dziedzic enum htt_rx_mpdu_status status; 11465e3dd157SKalle Valo struct ieee80211_hdr *hdr; 11475e3dd157SKalle Valo int num_mpdu_ranges; 114878433f96SJanusz Dziedzic u32 attention; 11495e3dd157SKalle Valo int fw_desc_len; 11505e3dd157SKalle Valo u8 *fw_desc; 115178433f96SJanusz Dziedzic bool channel_set; 11525e3dd157SKalle Valo int i, j; 1153d84dd60fSJanusz Dziedzic int ret; 11545e3dd157SKalle Valo 115545967089SMichal Kazior lockdep_assert_held(&htt->rx_ring.lock); 115645967089SMichal Kazior 11575e3dd157SKalle Valo fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes); 11585e3dd157SKalle Valo fw_desc = (u8 *)&rx->fw_desc; 11595e3dd157SKalle Valo 11605e3dd157SKalle Valo num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1), 11615e3dd157SKalle Valo HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES); 11625e3dd157SKalle Valo mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx); 11635e3dd157SKalle Valo 1164e8dc1a96SJanusz Dziedzic /* Fill this once, while this is per-ppdu */ 11652289188cSJanusz Dziedzic if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_START_VALID) { 11662289188cSJanusz Dziedzic memset(rx_status, 0, sizeof(*rx_status)); 11672289188cSJanusz Dziedzic rx_status->signal = ATH10K_DEFAULT_NOISE_FLOOR + 11682289188cSJanusz Dziedzic rx->ppdu.combined_rssi; 11692289188cSJanusz Dziedzic } 117087326c97SJanusz Dziedzic 117187326c97SJanusz Dziedzic if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_END_VALID) { 117287326c97SJanusz Dziedzic /* TSF available only in 32-bit */ 11736df92a3dSJanusz Dziedzic rx_status->mactime = __le32_to_cpu(rx->ppdu.tsf) & 0xffffffff; 11746df92a3dSJanusz Dziedzic rx_status->flag |= RX_FLAG_MACTIME_END; 117587326c97SJanusz Dziedzic } 1176e8dc1a96SJanusz Dziedzic 11776df92a3dSJanusz Dziedzic channel_set = ath10k_htt_rx_h_channel(htt->ar, rx_status); 117836653f05SJanusz Dziedzic 117987326c97SJanusz Dziedzic if (channel_set) { 11806df92a3dSJanusz Dziedzic ath10k_htt_rx_h_rates(htt->ar, rx_status->band, 118187326c97SJanusz Dziedzic rx->ppdu.info0, 118287326c97SJanusz Dziedzic __le32_to_cpu(rx->ppdu.info1), 118387326c97SJanusz Dziedzic __le32_to_cpu(rx->ppdu.info2), 11846df92a3dSJanusz Dziedzic rx_status); 118587326c97SJanusz Dziedzic } 1186e8dc1a96SJanusz Dziedzic 11875e3dd157SKalle Valo ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ", 11885e3dd157SKalle Valo rx, sizeof(*rx) + 11895e3dd157SKalle Valo (sizeof(struct htt_rx_indication_mpdu_range) * 11905e3dd157SKalle Valo num_mpdu_ranges)); 11915e3dd157SKalle Valo 11925e3dd157SKalle Valo for (i = 0; i < num_mpdu_ranges; i++) { 119387326c97SJanusz Dziedzic status = mpdu_ranges[i].mpdu_range_status; 11945e3dd157SKalle Valo 11955e3dd157SKalle Valo for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) { 11965e3dd157SKalle Valo struct sk_buff *msdu_head, *msdu_tail; 11975e3dd157SKalle Valo 11985e3dd157SKalle Valo msdu_head = NULL; 11995e3dd157SKalle Valo msdu_tail = NULL; 1200d84dd60fSJanusz Dziedzic ret = ath10k_htt_rx_amsdu_pop(htt, 12015e3dd157SKalle Valo &fw_desc, 12025e3dd157SKalle Valo &fw_desc_len, 12035e3dd157SKalle Valo &msdu_head, 12045e3dd157SKalle Valo &msdu_tail); 12055e3dd157SKalle Valo 1206d84dd60fSJanusz Dziedzic if (ret < 0) { 1207d84dd60fSJanusz Dziedzic ath10k_warn("failed to pop amsdu from htt rx ring %d\n", 1208d84dd60fSJanusz Dziedzic ret); 1209d84dd60fSJanusz Dziedzic ath10k_htt_rx_free_msdu_chain(msdu_head); 1210d84dd60fSJanusz Dziedzic continue; 1211d84dd60fSJanusz Dziedzic } 1212d84dd60fSJanusz Dziedzic 121378433f96SJanusz Dziedzic rxd = container_of((void *)msdu_head->data, 121478433f96SJanusz Dziedzic struct htt_rx_desc, 121578433f96SJanusz Dziedzic msdu_payload); 121678433f96SJanusz Dziedzic attention = __le32_to_cpu(rxd->attention.flags); 121778433f96SJanusz Dziedzic 12182acc4eb2SJanusz Dziedzic if (!ath10k_htt_rx_amsdu_allowed(htt, msdu_head, 121987326c97SJanusz Dziedzic status, 122078433f96SJanusz Dziedzic channel_set, 122178433f96SJanusz Dziedzic attention)) { 1222e8a50f8bSMarek Puzyniak ath10k_htt_rx_free_msdu_chain(msdu_head); 1223e8a50f8bSMarek Puzyniak continue; 1224e8a50f8bSMarek Puzyniak } 1225e8a50f8bSMarek Puzyniak 1226d84dd60fSJanusz Dziedzic if (ret > 0 && 1227d84dd60fSJanusz Dziedzic ath10k_unchain_msdu(msdu_head) < 0) { 12285e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(msdu_head); 12295e3dd157SKalle Valo continue; 12305e3dd157SKalle Valo } 12315e3dd157SKalle Valo 123278433f96SJanusz Dziedzic if (attention & RX_ATTENTION_FLAGS_FCS_ERR) 12336df92a3dSJanusz Dziedzic rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 123487326c97SJanusz Dziedzic else 12356df92a3dSJanusz Dziedzic rx_status->flag &= ~RX_FLAG_FAILED_FCS_CRC; 123687326c97SJanusz Dziedzic 123778433f96SJanusz Dziedzic if (attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR) 12386df92a3dSJanusz Dziedzic rx_status->flag |= RX_FLAG_MMIC_ERROR; 123987326c97SJanusz Dziedzic else 12406df92a3dSJanusz Dziedzic rx_status->flag &= ~RX_FLAG_MMIC_ERROR; 124187326c97SJanusz Dziedzic 12425e3dd157SKalle Valo hdr = ath10k_htt_rx_skb_get_hdr(msdu_head); 12435e3dd157SKalle Valo 12445e3dd157SKalle Valo if (ath10k_htt_rx_hdr_is_amsdu(hdr)) 12456df92a3dSJanusz Dziedzic ath10k_htt_rx_amsdu(htt, rx_status, msdu_head); 12465e3dd157SKalle Valo else 12476df92a3dSJanusz Dziedzic ath10k_htt_rx_msdu(htt, rx_status, msdu_head); 12485e3dd157SKalle Valo } 12495e3dd157SKalle Valo } 12505e3dd157SKalle Valo 12516e712d42SMichal Kazior tasklet_schedule(&htt->rx_replenish_task); 12525e3dd157SKalle Valo } 12535e3dd157SKalle Valo 12545e3dd157SKalle Valo static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt, 12555e3dd157SKalle Valo struct htt_rx_fragment_indication *frag) 12565e3dd157SKalle Valo { 12575e3dd157SKalle Valo struct sk_buff *msdu_head, *msdu_tail; 125887326c97SJanusz Dziedzic enum htt_rx_mpdu_encrypt_type enctype; 12595e3dd157SKalle Valo struct htt_rx_desc *rxd; 12605e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 12616df92a3dSJanusz Dziedzic struct ieee80211_rx_status *rx_status = &htt->rx_status; 12625e3dd157SKalle Valo struct ieee80211_hdr *hdr; 1263d84dd60fSJanusz Dziedzic int ret; 12645e3dd157SKalle Valo bool tkip_mic_err; 12655e3dd157SKalle Valo bool decrypt_err; 12665e3dd157SKalle Valo u8 *fw_desc; 12675e3dd157SKalle Valo int fw_desc_len, hdrlen, paramlen; 12685e3dd157SKalle Valo int trim; 12695e3dd157SKalle Valo 12705e3dd157SKalle Valo fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes); 12715e3dd157SKalle Valo fw_desc = (u8 *)frag->fw_msdu_rx_desc; 12725e3dd157SKalle Valo 12735e3dd157SKalle Valo msdu_head = NULL; 12745e3dd157SKalle Valo msdu_tail = NULL; 127545967089SMichal Kazior 127645967089SMichal Kazior spin_lock_bh(&htt->rx_ring.lock); 1277d84dd60fSJanusz Dziedzic ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len, 12785e3dd157SKalle Valo &msdu_head, &msdu_tail); 127945967089SMichal Kazior spin_unlock_bh(&htt->rx_ring.lock); 12805e3dd157SKalle Valo 12815e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n"); 12825e3dd157SKalle Valo 1283d84dd60fSJanusz Dziedzic if (ret) { 1284d84dd60fSJanusz Dziedzic ath10k_warn("failed to pop amsdu from httr rx ring for fragmented rx %d\n", 1285d84dd60fSJanusz Dziedzic ret); 12865e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(msdu_head); 12875e3dd157SKalle Valo return; 12885e3dd157SKalle Valo } 12895e3dd157SKalle Valo 12905e3dd157SKalle Valo /* FIXME: implement signal strength */ 12915e3dd157SKalle Valo 12925e3dd157SKalle Valo hdr = (struct ieee80211_hdr *)msdu_head->data; 12935e3dd157SKalle Valo rxd = (void *)msdu_head->data - sizeof(*rxd); 12945e3dd157SKalle Valo tkip_mic_err = !!(__le32_to_cpu(rxd->attention.flags) & 12955e3dd157SKalle Valo RX_ATTENTION_FLAGS_TKIP_MIC_ERR); 12965e3dd157SKalle Valo decrypt_err = !!(__le32_to_cpu(rxd->attention.flags) & 12975e3dd157SKalle Valo RX_ATTENTION_FLAGS_DECRYPT_ERR); 12985e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 12995e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 13005e3dd157SKalle Valo 13015e3dd157SKalle Valo if (fmt != RX_MSDU_DECAP_RAW) { 13025e3dd157SKalle Valo ath10k_warn("we dont support non-raw fragmented rx yet\n"); 13035e3dd157SKalle Valo dev_kfree_skb_any(msdu_head); 13045e3dd157SKalle Valo goto end; 13055e3dd157SKalle Valo } 13065e3dd157SKalle Valo 130787326c97SJanusz Dziedzic enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), 13085e3dd157SKalle Valo RX_MPDU_START_INFO0_ENCRYPT_TYPE); 13096df92a3dSJanusz Dziedzic ath10k_htt_rx_h_protected(htt, rx_status, msdu_head, enctype); 131085f6d7cfSJanusz Dziedzic msdu_head->ip_summed = ath10k_htt_rx_get_csum_state(msdu_head); 13115e3dd157SKalle Valo 131287326c97SJanusz Dziedzic if (tkip_mic_err) 13135e3dd157SKalle Valo ath10k_warn("tkip mic error\n"); 13145e3dd157SKalle Valo 13155e3dd157SKalle Valo if (decrypt_err) { 13165e3dd157SKalle Valo ath10k_warn("decryption err in fragmented rx\n"); 131785f6d7cfSJanusz Dziedzic dev_kfree_skb_any(msdu_head); 13185e3dd157SKalle Valo goto end; 13195e3dd157SKalle Valo } 13205e3dd157SKalle Valo 132187326c97SJanusz Dziedzic if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) { 13225e3dd157SKalle Valo hdrlen = ieee80211_hdrlen(hdr->frame_control); 132387326c97SJanusz Dziedzic paramlen = ath10k_htt_rx_crypto_param_len(enctype); 13245e3dd157SKalle Valo 13255e3dd157SKalle Valo /* It is more efficient to move the header than the payload */ 132685f6d7cfSJanusz Dziedzic memmove((void *)msdu_head->data + paramlen, 132785f6d7cfSJanusz Dziedzic (void *)msdu_head->data, 13285e3dd157SKalle Valo hdrlen); 132985f6d7cfSJanusz Dziedzic skb_pull(msdu_head, paramlen); 133085f6d7cfSJanusz Dziedzic hdr = (struct ieee80211_hdr *)msdu_head->data; 13315e3dd157SKalle Valo } 13325e3dd157SKalle Valo 13335e3dd157SKalle Valo /* remove trailing FCS */ 13345e3dd157SKalle Valo trim = 4; 13355e3dd157SKalle Valo 13365e3dd157SKalle Valo /* remove crypto trailer */ 133787326c97SJanusz Dziedzic trim += ath10k_htt_rx_crypto_tail_len(enctype); 13385e3dd157SKalle Valo 13395e3dd157SKalle Valo /* last fragment of TKIP frags has MIC */ 13405e3dd157SKalle Valo if (!ieee80211_has_morefrags(hdr->frame_control) && 134187326c97SJanusz Dziedzic enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA) 13425e3dd157SKalle Valo trim += 8; 13435e3dd157SKalle Valo 134485f6d7cfSJanusz Dziedzic if (trim > msdu_head->len) { 13455e3dd157SKalle Valo ath10k_warn("htt rx fragment: trailer longer than the frame itself? drop\n"); 134685f6d7cfSJanusz Dziedzic dev_kfree_skb_any(msdu_head); 13475e3dd157SKalle Valo goto end; 13485e3dd157SKalle Valo } 13495e3dd157SKalle Valo 135085f6d7cfSJanusz Dziedzic skb_trim(msdu_head, msdu_head->len - trim); 13515e3dd157SKalle Valo 135275fb2f94SBen Greear ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ", 135385f6d7cfSJanusz Dziedzic msdu_head->data, msdu_head->len); 13546df92a3dSJanusz Dziedzic ath10k_process_rx(htt->ar, rx_status, msdu_head); 13555e3dd157SKalle Valo 13565e3dd157SKalle Valo end: 13575e3dd157SKalle Valo if (fw_desc_len > 0) { 13585e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT, 13595e3dd157SKalle Valo "expecting more fragmented rx in one indication %d\n", 13605e3dd157SKalle Valo fw_desc_len); 13615e3dd157SKalle Valo } 13625e3dd157SKalle Valo } 13635e3dd157SKalle Valo 13646c5151a9SMichal Kazior static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar, 13656c5151a9SMichal Kazior struct sk_buff *skb) 13666c5151a9SMichal Kazior { 13676c5151a9SMichal Kazior struct ath10k_htt *htt = &ar->htt; 13686c5151a9SMichal Kazior struct htt_resp *resp = (struct htt_resp *)skb->data; 13696c5151a9SMichal Kazior struct htt_tx_done tx_done = {}; 13706c5151a9SMichal Kazior int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS); 13716c5151a9SMichal Kazior __le16 msdu_id; 13726c5151a9SMichal Kazior int i; 13736c5151a9SMichal Kazior 137445967089SMichal Kazior lockdep_assert_held(&htt->tx_lock); 137545967089SMichal Kazior 13766c5151a9SMichal Kazior switch (status) { 13776c5151a9SMichal Kazior case HTT_DATA_TX_STATUS_NO_ACK: 13786c5151a9SMichal Kazior tx_done.no_ack = true; 13796c5151a9SMichal Kazior break; 13806c5151a9SMichal Kazior case HTT_DATA_TX_STATUS_OK: 13816c5151a9SMichal Kazior break; 13826c5151a9SMichal Kazior case HTT_DATA_TX_STATUS_DISCARD: 13836c5151a9SMichal Kazior case HTT_DATA_TX_STATUS_POSTPONE: 13846c5151a9SMichal Kazior case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL: 13856c5151a9SMichal Kazior tx_done.discard = true; 13866c5151a9SMichal Kazior break; 13876c5151a9SMichal Kazior default: 13886c5151a9SMichal Kazior ath10k_warn("unhandled tx completion status %d\n", status); 13896c5151a9SMichal Kazior tx_done.discard = true; 13906c5151a9SMichal Kazior break; 13916c5151a9SMichal Kazior } 13926c5151a9SMichal Kazior 13936c5151a9SMichal Kazior ath10k_dbg(ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n", 13946c5151a9SMichal Kazior resp->data_tx_completion.num_msdus); 13956c5151a9SMichal Kazior 13966c5151a9SMichal Kazior for (i = 0; i < resp->data_tx_completion.num_msdus; i++) { 13976c5151a9SMichal Kazior msdu_id = resp->data_tx_completion.msdus[i]; 13986c5151a9SMichal Kazior tx_done.msdu_id = __le16_to_cpu(msdu_id); 13996c5151a9SMichal Kazior ath10k_txrx_tx_unref(htt, &tx_done); 14006c5151a9SMichal Kazior } 14016c5151a9SMichal Kazior } 14026c5151a9SMichal Kazior 14035e3dd157SKalle Valo void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb) 14045e3dd157SKalle Valo { 1405edb8236dSMichal Kazior struct ath10k_htt *htt = &ar->htt; 14065e3dd157SKalle Valo struct htt_resp *resp = (struct htt_resp *)skb->data; 14075e3dd157SKalle Valo 14085e3dd157SKalle Valo /* confirm alignment */ 14095e3dd157SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, 4)) 14105e3dd157SKalle Valo ath10k_warn("unaligned htt message, expect trouble\n"); 14115e3dd157SKalle Valo 141275fb2f94SBen Greear ath10k_dbg(ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n", 14135e3dd157SKalle Valo resp->hdr.msg_type); 14145e3dd157SKalle Valo switch (resp->hdr.msg_type) { 14155e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_VERSION_CONF: { 14165e3dd157SKalle Valo htt->target_version_major = resp->ver_resp.major; 14175e3dd157SKalle Valo htt->target_version_minor = resp->ver_resp.minor; 14185e3dd157SKalle Valo complete(&htt->target_version_received); 14195e3dd157SKalle Valo break; 14205e3dd157SKalle Valo } 14216c5151a9SMichal Kazior case HTT_T2H_MSG_TYPE_RX_IND: 142245967089SMichal Kazior spin_lock_bh(&htt->rx_ring.lock); 142345967089SMichal Kazior __skb_queue_tail(&htt->rx_compl_q, skb); 142445967089SMichal Kazior spin_unlock_bh(&htt->rx_ring.lock); 14256c5151a9SMichal Kazior tasklet_schedule(&htt->txrx_compl_task); 14266c5151a9SMichal Kazior return; 14275e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_PEER_MAP: { 14285e3dd157SKalle Valo struct htt_peer_map_event ev = { 14295e3dd157SKalle Valo .vdev_id = resp->peer_map.vdev_id, 14305e3dd157SKalle Valo .peer_id = __le16_to_cpu(resp->peer_map.peer_id), 14315e3dd157SKalle Valo }; 14325e3dd157SKalle Valo memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr)); 14335e3dd157SKalle Valo ath10k_peer_map_event(htt, &ev); 14345e3dd157SKalle Valo break; 14355e3dd157SKalle Valo } 14365e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_PEER_UNMAP: { 14375e3dd157SKalle Valo struct htt_peer_unmap_event ev = { 14385e3dd157SKalle Valo .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id), 14395e3dd157SKalle Valo }; 14405e3dd157SKalle Valo ath10k_peer_unmap_event(htt, &ev); 14415e3dd157SKalle Valo break; 14425e3dd157SKalle Valo } 14435e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: { 14445e3dd157SKalle Valo struct htt_tx_done tx_done = {}; 14455e3dd157SKalle Valo int status = __le32_to_cpu(resp->mgmt_tx_completion.status); 14465e3dd157SKalle Valo 14475e3dd157SKalle Valo tx_done.msdu_id = 14485e3dd157SKalle Valo __le32_to_cpu(resp->mgmt_tx_completion.desc_id); 14495e3dd157SKalle Valo 14505e3dd157SKalle Valo switch (status) { 14515e3dd157SKalle Valo case HTT_MGMT_TX_STATUS_OK: 14525e3dd157SKalle Valo break; 14535e3dd157SKalle Valo case HTT_MGMT_TX_STATUS_RETRY: 14545e3dd157SKalle Valo tx_done.no_ack = true; 14555e3dd157SKalle Valo break; 14565e3dd157SKalle Valo case HTT_MGMT_TX_STATUS_DROP: 14575e3dd157SKalle Valo tx_done.discard = true; 14585e3dd157SKalle Valo break; 14595e3dd157SKalle Valo } 14605e3dd157SKalle Valo 14616c5151a9SMichal Kazior spin_lock_bh(&htt->tx_lock); 14620a89f8a0SMichal Kazior ath10k_txrx_tx_unref(htt, &tx_done); 14636c5151a9SMichal Kazior spin_unlock_bh(&htt->tx_lock); 14645e3dd157SKalle Valo break; 14655e3dd157SKalle Valo } 14666c5151a9SMichal Kazior case HTT_T2H_MSG_TYPE_TX_COMPL_IND: 14676c5151a9SMichal Kazior spin_lock_bh(&htt->tx_lock); 14686c5151a9SMichal Kazior __skb_queue_tail(&htt->tx_compl_q, skb); 14696c5151a9SMichal Kazior spin_unlock_bh(&htt->tx_lock); 14706c5151a9SMichal Kazior tasklet_schedule(&htt->txrx_compl_task); 14716c5151a9SMichal Kazior return; 14725e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_SEC_IND: { 14735e3dd157SKalle Valo struct ath10k *ar = htt->ar; 14745e3dd157SKalle Valo struct htt_security_indication *ev = &resp->security_indication; 14755e3dd157SKalle Valo 14765e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT, 14775e3dd157SKalle Valo "sec ind peer_id %d unicast %d type %d\n", 14785e3dd157SKalle Valo __le16_to_cpu(ev->peer_id), 14795e3dd157SKalle Valo !!(ev->flags & HTT_SECURITY_IS_UNICAST), 14805e3dd157SKalle Valo MS(ev->flags, HTT_SECURITY_TYPE)); 14815e3dd157SKalle Valo complete(&ar->install_key_done); 14825e3dd157SKalle Valo break; 14835e3dd157SKalle Valo } 14845e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_FRAG_IND: { 14855e3dd157SKalle Valo ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ", 14865e3dd157SKalle Valo skb->data, skb->len); 14875e3dd157SKalle Valo ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind); 14885e3dd157SKalle Valo break; 14895e3dd157SKalle Valo } 14905e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_TEST: 14915e3dd157SKalle Valo /* FIX THIS */ 14925e3dd157SKalle Valo break; 14935e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_STATS_CONF: 1494a9bf0506SKalle Valo trace_ath10k_htt_stats(skb->data, skb->len); 1495a9bf0506SKalle Valo break; 1496a9bf0506SKalle Valo case HTT_T2H_MSG_TYPE_TX_INSPECT_IND: 14975e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_ADDBA: 14985e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_DELBA: 14995e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_FLUSH: 15005e3dd157SKalle Valo default: 15015e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT, "htt event (%d) not handled\n", 15025e3dd157SKalle Valo resp->hdr.msg_type); 15035e3dd157SKalle Valo ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ", 15045e3dd157SKalle Valo skb->data, skb->len); 15055e3dd157SKalle Valo break; 15065e3dd157SKalle Valo }; 15075e3dd157SKalle Valo 15085e3dd157SKalle Valo /* Free the indication buffer */ 15095e3dd157SKalle Valo dev_kfree_skb_any(skb); 15105e3dd157SKalle Valo } 15116c5151a9SMichal Kazior 15126c5151a9SMichal Kazior static void ath10k_htt_txrx_compl_task(unsigned long ptr) 15136c5151a9SMichal Kazior { 15146c5151a9SMichal Kazior struct ath10k_htt *htt = (struct ath10k_htt *)ptr; 15156c5151a9SMichal Kazior struct htt_resp *resp; 15166c5151a9SMichal Kazior struct sk_buff *skb; 15176c5151a9SMichal Kazior 151845967089SMichal Kazior spin_lock_bh(&htt->tx_lock); 151945967089SMichal Kazior while ((skb = __skb_dequeue(&htt->tx_compl_q))) { 15206c5151a9SMichal Kazior ath10k_htt_rx_frm_tx_compl(htt->ar, skb); 15216c5151a9SMichal Kazior dev_kfree_skb_any(skb); 15226c5151a9SMichal Kazior } 152345967089SMichal Kazior spin_unlock_bh(&htt->tx_lock); 15246c5151a9SMichal Kazior 152545967089SMichal Kazior spin_lock_bh(&htt->rx_ring.lock); 152645967089SMichal Kazior while ((skb = __skb_dequeue(&htt->rx_compl_q))) { 15276c5151a9SMichal Kazior resp = (struct htt_resp *)skb->data; 15286c5151a9SMichal Kazior ath10k_htt_rx_handler(htt, &resp->rx_ind); 15296c5151a9SMichal Kazior dev_kfree_skb_any(skb); 15306c5151a9SMichal Kazior } 153145967089SMichal Kazior spin_unlock_bh(&htt->rx_ring.lock); 15326c5151a9SMichal Kazior } 1533