15e3dd157SKalle Valo /* 25e3dd157SKalle Valo * Copyright (c) 2005-2011 Atheros Communications Inc. 35e3dd157SKalle Valo * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 45e3dd157SKalle Valo * 55e3dd157SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 65e3dd157SKalle Valo * purpose with or without fee is hereby granted, provided that the above 75e3dd157SKalle Valo * copyright notice and this permission notice appear in all copies. 85e3dd157SKalle Valo * 95e3dd157SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 105e3dd157SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 115e3dd157SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 125e3dd157SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 135e3dd157SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 145e3dd157SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 155e3dd157SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 165e3dd157SKalle Valo */ 175e3dd157SKalle Valo 18edb8236dSMichal Kazior #include "core.h" 195e3dd157SKalle Valo #include "htc.h" 205e3dd157SKalle Valo #include "htt.h" 215e3dd157SKalle Valo #include "txrx.h" 225e3dd157SKalle Valo #include "debug.h" 23a9bf0506SKalle Valo #include "trace.h" 245e3dd157SKalle Valo 255e3dd157SKalle Valo #include <linux/log2.h> 265e3dd157SKalle Valo 275e3dd157SKalle Valo /* slightly larger than one large A-MPDU */ 285e3dd157SKalle Valo #define HTT_RX_RING_SIZE_MIN 128 295e3dd157SKalle Valo 305e3dd157SKalle Valo /* roughly 20 ms @ 1 Gbps of 1500B MSDUs */ 315e3dd157SKalle Valo #define HTT_RX_RING_SIZE_MAX 2048 325e3dd157SKalle Valo 335e3dd157SKalle Valo #define HTT_RX_AVG_FRM_BYTES 1000 345e3dd157SKalle Valo 355e3dd157SKalle Valo /* ms, very conservative */ 365e3dd157SKalle Valo #define HTT_RX_HOST_LATENCY_MAX_MS 20 375e3dd157SKalle Valo 385e3dd157SKalle Valo /* ms, conservative */ 395e3dd157SKalle Valo #define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10 405e3dd157SKalle Valo 415e3dd157SKalle Valo /* when under memory pressure rx ring refill may fail and needs a retry */ 425e3dd157SKalle Valo #define HTT_RX_RING_REFILL_RETRY_MS 50 435e3dd157SKalle Valo 445e3dd157SKalle Valo static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt) 455e3dd157SKalle Valo { 465e3dd157SKalle Valo int size; 475e3dd157SKalle Valo 485e3dd157SKalle Valo /* 495e3dd157SKalle Valo * It is expected that the host CPU will typically be able to 505e3dd157SKalle Valo * service the rx indication from one A-MPDU before the rx 515e3dd157SKalle Valo * indication from the subsequent A-MPDU happens, roughly 1-2 ms 525e3dd157SKalle Valo * later. However, the rx ring should be sized very conservatively, 535e3dd157SKalle Valo * to accomodate the worst reasonable delay before the host CPU 545e3dd157SKalle Valo * services a rx indication interrupt. 555e3dd157SKalle Valo * 565e3dd157SKalle Valo * The rx ring need not be kept full of empty buffers. In theory, 575e3dd157SKalle Valo * the htt host SW can dynamically track the low-water mark in the 585e3dd157SKalle Valo * rx ring, and dynamically adjust the level to which the rx ring 595e3dd157SKalle Valo * is filled with empty buffers, to dynamically meet the desired 605e3dd157SKalle Valo * low-water mark. 615e3dd157SKalle Valo * 625e3dd157SKalle Valo * In contrast, it's difficult to resize the rx ring itself, once 635e3dd157SKalle Valo * it's in use. Thus, the ring itself should be sized very 645e3dd157SKalle Valo * conservatively, while the degree to which the ring is filled 655e3dd157SKalle Valo * with empty buffers should be sized moderately conservatively. 665e3dd157SKalle Valo */ 675e3dd157SKalle Valo 685e3dd157SKalle Valo /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */ 695e3dd157SKalle Valo size = 705e3dd157SKalle Valo htt->max_throughput_mbps + 715e3dd157SKalle Valo 1000 / 725e3dd157SKalle Valo (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS; 735e3dd157SKalle Valo 745e3dd157SKalle Valo if (size < HTT_RX_RING_SIZE_MIN) 755e3dd157SKalle Valo size = HTT_RX_RING_SIZE_MIN; 765e3dd157SKalle Valo 775e3dd157SKalle Valo if (size > HTT_RX_RING_SIZE_MAX) 785e3dd157SKalle Valo size = HTT_RX_RING_SIZE_MAX; 795e3dd157SKalle Valo 805e3dd157SKalle Valo size = roundup_pow_of_two(size); 815e3dd157SKalle Valo 825e3dd157SKalle Valo return size; 835e3dd157SKalle Valo } 845e3dd157SKalle Valo 855e3dd157SKalle Valo static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt) 865e3dd157SKalle Valo { 875e3dd157SKalle Valo int size; 885e3dd157SKalle Valo 895e3dd157SKalle Valo /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */ 905e3dd157SKalle Valo size = 915e3dd157SKalle Valo htt->max_throughput_mbps * 925e3dd157SKalle Valo 1000 / 935e3dd157SKalle Valo (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS; 945e3dd157SKalle Valo 955e3dd157SKalle Valo /* 965e3dd157SKalle Valo * Make sure the fill level is at least 1 less than the ring size. 975e3dd157SKalle Valo * Leaving 1 element empty allows the SW to easily distinguish 985e3dd157SKalle Valo * between a full ring vs. an empty ring. 995e3dd157SKalle Valo */ 1005e3dd157SKalle Valo if (size >= htt->rx_ring.size) 1015e3dd157SKalle Valo size = htt->rx_ring.size - 1; 1025e3dd157SKalle Valo 1035e3dd157SKalle Valo return size; 1045e3dd157SKalle Valo } 1055e3dd157SKalle Valo 1065e3dd157SKalle Valo static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt) 1075e3dd157SKalle Valo { 1085e3dd157SKalle Valo struct sk_buff *skb; 1095e3dd157SKalle Valo struct ath10k_skb_cb *cb; 1105e3dd157SKalle Valo int i; 1115e3dd157SKalle Valo 1125e3dd157SKalle Valo for (i = 0; i < htt->rx_ring.fill_cnt; i++) { 1135e3dd157SKalle Valo skb = htt->rx_ring.netbufs_ring[i]; 1145e3dd157SKalle Valo cb = ATH10K_SKB_CB(skb); 1155e3dd157SKalle Valo dma_unmap_single(htt->ar->dev, cb->paddr, 1165e3dd157SKalle Valo skb->len + skb_tailroom(skb), 1175e3dd157SKalle Valo DMA_FROM_DEVICE); 1185e3dd157SKalle Valo dev_kfree_skb_any(skb); 1195e3dd157SKalle Valo } 1205e3dd157SKalle Valo 1215e3dd157SKalle Valo htt->rx_ring.fill_cnt = 0; 1225e3dd157SKalle Valo } 1235e3dd157SKalle Valo 1245e3dd157SKalle Valo static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num) 1255e3dd157SKalle Valo { 1265e3dd157SKalle Valo struct htt_rx_desc *rx_desc; 1275e3dd157SKalle Valo struct sk_buff *skb; 1285e3dd157SKalle Valo dma_addr_t paddr; 1295e3dd157SKalle Valo int ret = 0, idx; 1305e3dd157SKalle Valo 1315e3dd157SKalle Valo idx = __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr)); 1325e3dd157SKalle Valo while (num > 0) { 1335e3dd157SKalle Valo skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN); 1345e3dd157SKalle Valo if (!skb) { 1355e3dd157SKalle Valo ret = -ENOMEM; 1365e3dd157SKalle Valo goto fail; 1375e3dd157SKalle Valo } 1385e3dd157SKalle Valo 1395e3dd157SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN)) 1405e3dd157SKalle Valo skb_pull(skb, 1415e3dd157SKalle Valo PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) - 1425e3dd157SKalle Valo skb->data); 1435e3dd157SKalle Valo 1445e3dd157SKalle Valo /* Clear rx_desc attention word before posting to Rx ring */ 1455e3dd157SKalle Valo rx_desc = (struct htt_rx_desc *)skb->data; 1465e3dd157SKalle Valo rx_desc->attention.flags = __cpu_to_le32(0); 1475e3dd157SKalle Valo 1485e3dd157SKalle Valo paddr = dma_map_single(htt->ar->dev, skb->data, 1495e3dd157SKalle Valo skb->len + skb_tailroom(skb), 1505e3dd157SKalle Valo DMA_FROM_DEVICE); 1515e3dd157SKalle Valo 1525e3dd157SKalle Valo if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) { 1535e3dd157SKalle Valo dev_kfree_skb_any(skb); 1545e3dd157SKalle Valo ret = -ENOMEM; 1555e3dd157SKalle Valo goto fail; 1565e3dd157SKalle Valo } 1575e3dd157SKalle Valo 1585e3dd157SKalle Valo ATH10K_SKB_CB(skb)->paddr = paddr; 1595e3dd157SKalle Valo htt->rx_ring.netbufs_ring[idx] = skb; 1605e3dd157SKalle Valo htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr); 1615e3dd157SKalle Valo htt->rx_ring.fill_cnt++; 1625e3dd157SKalle Valo 1635e3dd157SKalle Valo num--; 1645e3dd157SKalle Valo idx++; 1655e3dd157SKalle Valo idx &= htt->rx_ring.size_mask; 1665e3dd157SKalle Valo } 1675e3dd157SKalle Valo 1685e3dd157SKalle Valo fail: 1695e3dd157SKalle Valo *(htt->rx_ring.alloc_idx.vaddr) = __cpu_to_le32(idx); 1705e3dd157SKalle Valo return ret; 1715e3dd157SKalle Valo } 1725e3dd157SKalle Valo 1735e3dd157SKalle Valo static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num) 1745e3dd157SKalle Valo { 1755e3dd157SKalle Valo lockdep_assert_held(&htt->rx_ring.lock); 1765e3dd157SKalle Valo return __ath10k_htt_rx_ring_fill_n(htt, num); 1775e3dd157SKalle Valo } 1785e3dd157SKalle Valo 1795e3dd157SKalle Valo static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt) 1805e3dd157SKalle Valo { 1815e3dd157SKalle Valo int ret, num_to_fill; 1825e3dd157SKalle Valo 1835e3dd157SKalle Valo spin_lock_bh(&htt->rx_ring.lock); 1845e3dd157SKalle Valo num_to_fill = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt; 1855e3dd157SKalle Valo ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill); 1865e3dd157SKalle Valo if (ret == -ENOMEM) { 1875e3dd157SKalle Valo /* 1885e3dd157SKalle Valo * Failed to fill it to the desired level - 1895e3dd157SKalle Valo * we'll start a timer and try again next time. 1905e3dd157SKalle Valo * As long as enough buffers are left in the ring for 1915e3dd157SKalle Valo * another A-MPDU rx, no special recovery is needed. 1925e3dd157SKalle Valo */ 1935e3dd157SKalle Valo mod_timer(&htt->rx_ring.refill_retry_timer, jiffies + 1945e3dd157SKalle Valo msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS)); 1955e3dd157SKalle Valo } 1965e3dd157SKalle Valo spin_unlock_bh(&htt->rx_ring.lock); 1975e3dd157SKalle Valo } 1985e3dd157SKalle Valo 1995e3dd157SKalle Valo static void ath10k_htt_rx_ring_refill_retry(unsigned long arg) 2005e3dd157SKalle Valo { 2015e3dd157SKalle Valo struct ath10k_htt *htt = (struct ath10k_htt *)arg; 2025e3dd157SKalle Valo ath10k_htt_rx_msdu_buff_replenish(htt); 2035e3dd157SKalle Valo } 2045e3dd157SKalle Valo 2055e3dd157SKalle Valo static unsigned ath10k_htt_rx_ring_elems(struct ath10k_htt *htt) 2065e3dd157SKalle Valo { 2075e3dd157SKalle Valo return (__le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr) - 2085e3dd157SKalle Valo htt->rx_ring.sw_rd_idx.msdu_payld) & htt->rx_ring.size_mask; 2095e3dd157SKalle Valo } 2105e3dd157SKalle Valo 2115e3dd157SKalle Valo void ath10k_htt_rx_detach(struct ath10k_htt *htt) 2125e3dd157SKalle Valo { 2135e3dd157SKalle Valo int sw_rd_idx = htt->rx_ring.sw_rd_idx.msdu_payld; 2145e3dd157SKalle Valo 2155e3dd157SKalle Valo del_timer_sync(&htt->rx_ring.refill_retry_timer); 2165e3dd157SKalle Valo 2175e3dd157SKalle Valo while (sw_rd_idx != __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr))) { 2185e3dd157SKalle Valo struct sk_buff *skb = 2195e3dd157SKalle Valo htt->rx_ring.netbufs_ring[sw_rd_idx]; 2205e3dd157SKalle Valo struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 2215e3dd157SKalle Valo 2225e3dd157SKalle Valo dma_unmap_single(htt->ar->dev, cb->paddr, 2235e3dd157SKalle Valo skb->len + skb_tailroom(skb), 2245e3dd157SKalle Valo DMA_FROM_DEVICE); 2255e3dd157SKalle Valo dev_kfree_skb_any(htt->rx_ring.netbufs_ring[sw_rd_idx]); 2265e3dd157SKalle Valo sw_rd_idx++; 2275e3dd157SKalle Valo sw_rd_idx &= htt->rx_ring.size_mask; 2285e3dd157SKalle Valo } 2295e3dd157SKalle Valo 2305e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 2315e3dd157SKalle Valo (htt->rx_ring.size * 2325e3dd157SKalle Valo sizeof(htt->rx_ring.paddrs_ring)), 2335e3dd157SKalle Valo htt->rx_ring.paddrs_ring, 2345e3dd157SKalle Valo htt->rx_ring.base_paddr); 2355e3dd157SKalle Valo 2365e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 2375e3dd157SKalle Valo sizeof(*htt->rx_ring.alloc_idx.vaddr), 2385e3dd157SKalle Valo htt->rx_ring.alloc_idx.vaddr, 2395e3dd157SKalle Valo htt->rx_ring.alloc_idx.paddr); 2405e3dd157SKalle Valo 2415e3dd157SKalle Valo kfree(htt->rx_ring.netbufs_ring); 2425e3dd157SKalle Valo } 2435e3dd157SKalle Valo 2445e3dd157SKalle Valo static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt) 2455e3dd157SKalle Valo { 2465e3dd157SKalle Valo int idx; 2475e3dd157SKalle Valo struct sk_buff *msdu; 2485e3dd157SKalle Valo 2495e3dd157SKalle Valo spin_lock_bh(&htt->rx_ring.lock); 2505e3dd157SKalle Valo 2515e3dd157SKalle Valo if (ath10k_htt_rx_ring_elems(htt) == 0) 2525e3dd157SKalle Valo ath10k_warn("htt rx ring is empty!\n"); 2535e3dd157SKalle Valo 2545e3dd157SKalle Valo idx = htt->rx_ring.sw_rd_idx.msdu_payld; 2555e3dd157SKalle Valo msdu = htt->rx_ring.netbufs_ring[idx]; 2565e3dd157SKalle Valo 2575e3dd157SKalle Valo idx++; 2585e3dd157SKalle Valo idx &= htt->rx_ring.size_mask; 2595e3dd157SKalle Valo htt->rx_ring.sw_rd_idx.msdu_payld = idx; 2605e3dd157SKalle Valo htt->rx_ring.fill_cnt--; 2615e3dd157SKalle Valo 2625e3dd157SKalle Valo spin_unlock_bh(&htt->rx_ring.lock); 2635e3dd157SKalle Valo return msdu; 2645e3dd157SKalle Valo } 2655e3dd157SKalle Valo 2665e3dd157SKalle Valo static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb) 2675e3dd157SKalle Valo { 2685e3dd157SKalle Valo struct sk_buff *next; 2695e3dd157SKalle Valo 2705e3dd157SKalle Valo while (skb) { 2715e3dd157SKalle Valo next = skb->next; 2725e3dd157SKalle Valo dev_kfree_skb_any(skb); 2735e3dd157SKalle Valo skb = next; 2745e3dd157SKalle Valo } 2755e3dd157SKalle Valo } 2765e3dd157SKalle Valo 2775e3dd157SKalle Valo static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt, 2785e3dd157SKalle Valo u8 **fw_desc, int *fw_desc_len, 2795e3dd157SKalle Valo struct sk_buff **head_msdu, 2805e3dd157SKalle Valo struct sk_buff **tail_msdu) 2815e3dd157SKalle Valo { 2825e3dd157SKalle Valo int msdu_len, msdu_chaining = 0; 2835e3dd157SKalle Valo struct sk_buff *msdu; 2845e3dd157SKalle Valo struct htt_rx_desc *rx_desc; 2855e3dd157SKalle Valo 2865e3dd157SKalle Valo if (ath10k_htt_rx_ring_elems(htt) == 0) 2875e3dd157SKalle Valo ath10k_warn("htt rx ring is empty!\n"); 2885e3dd157SKalle Valo 2895e3dd157SKalle Valo if (htt->rx_confused) { 2905e3dd157SKalle Valo ath10k_warn("htt is confused. refusing rx\n"); 2915e3dd157SKalle Valo return 0; 2925e3dd157SKalle Valo } 2935e3dd157SKalle Valo 2945e3dd157SKalle Valo msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt); 2955e3dd157SKalle Valo while (msdu) { 2965e3dd157SKalle Valo int last_msdu, msdu_len_invalid, msdu_chained; 2975e3dd157SKalle Valo 2985e3dd157SKalle Valo dma_unmap_single(htt->ar->dev, 2995e3dd157SKalle Valo ATH10K_SKB_CB(msdu)->paddr, 3005e3dd157SKalle Valo msdu->len + skb_tailroom(msdu), 3015e3dd157SKalle Valo DMA_FROM_DEVICE); 3025e3dd157SKalle Valo 3035e3dd157SKalle Valo ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx: ", 3045e3dd157SKalle Valo msdu->data, msdu->len + skb_tailroom(msdu)); 3055e3dd157SKalle Valo 3065e3dd157SKalle Valo rx_desc = (struct htt_rx_desc *)msdu->data; 3075e3dd157SKalle Valo 3085e3dd157SKalle Valo /* FIXME: we must report msdu payload since this is what caller 3095e3dd157SKalle Valo * expects now */ 3105e3dd157SKalle Valo skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload)); 3115e3dd157SKalle Valo skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload)); 3125e3dd157SKalle Valo 3135e3dd157SKalle Valo /* 3145e3dd157SKalle Valo * Sanity check - confirm the HW is finished filling in the 3155e3dd157SKalle Valo * rx data. 3165e3dd157SKalle Valo * If the HW and SW are working correctly, then it's guaranteed 3175e3dd157SKalle Valo * that the HW's MAC DMA is done before this point in the SW. 3185e3dd157SKalle Valo * To prevent the case that we handle a stale Rx descriptor, 3195e3dd157SKalle Valo * just assert for now until we have a way to recover. 3205e3dd157SKalle Valo */ 3215e3dd157SKalle Valo if (!(__le32_to_cpu(rx_desc->attention.flags) 3225e3dd157SKalle Valo & RX_ATTENTION_FLAGS_MSDU_DONE)) { 3235e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(*head_msdu); 3245e3dd157SKalle Valo *head_msdu = NULL; 3255e3dd157SKalle Valo msdu = NULL; 3265e3dd157SKalle Valo ath10k_err("htt rx stopped. cannot recover\n"); 3275e3dd157SKalle Valo htt->rx_confused = true; 3285e3dd157SKalle Valo break; 3295e3dd157SKalle Valo } 3305e3dd157SKalle Valo 3315e3dd157SKalle Valo /* 3325e3dd157SKalle Valo * Copy the FW rx descriptor for this MSDU from the rx 3335e3dd157SKalle Valo * indication message into the MSDU's netbuf. HL uses the 3345e3dd157SKalle Valo * same rx indication message definition as LL, and simply 3355e3dd157SKalle Valo * appends new info (fields from the HW rx desc, and the 3365e3dd157SKalle Valo * MSDU payload itself). So, the offset into the rx 3375e3dd157SKalle Valo * indication message only has to account for the standard 3385e3dd157SKalle Valo * offset of the per-MSDU FW rx desc info within the 3395e3dd157SKalle Valo * message, and how many bytes of the per-MSDU FW rx desc 3405e3dd157SKalle Valo * info have already been consumed. (And the endianness of 3415e3dd157SKalle Valo * the host, since for a big-endian host, the rx ind 3425e3dd157SKalle Valo * message contents, including the per-MSDU rx desc bytes, 3435e3dd157SKalle Valo * were byteswapped during upload.) 3445e3dd157SKalle Valo */ 3455e3dd157SKalle Valo if (*fw_desc_len > 0) { 3465e3dd157SKalle Valo rx_desc->fw_desc.info0 = **fw_desc; 3475e3dd157SKalle Valo /* 3485e3dd157SKalle Valo * The target is expected to only provide the basic 3495e3dd157SKalle Valo * per-MSDU rx descriptors. Just to be sure, verify 3505e3dd157SKalle Valo * that the target has not attached extension data 3515e3dd157SKalle Valo * (e.g. LRO flow ID). 3525e3dd157SKalle Valo */ 3535e3dd157SKalle Valo 3545e3dd157SKalle Valo /* or more, if there's extension data */ 3555e3dd157SKalle Valo (*fw_desc)++; 3565e3dd157SKalle Valo (*fw_desc_len)--; 3575e3dd157SKalle Valo } else { 3585e3dd157SKalle Valo /* 3595e3dd157SKalle Valo * When an oversized AMSDU happened, FW will lost 3605e3dd157SKalle Valo * some of MSDU status - in this case, the FW 3615e3dd157SKalle Valo * descriptors provided will be less than the 3625e3dd157SKalle Valo * actual MSDUs inside this MPDU. Mark the FW 3635e3dd157SKalle Valo * descriptors so that it will still deliver to 3645e3dd157SKalle Valo * upper stack, if no CRC error for this MPDU. 3655e3dd157SKalle Valo * 3665e3dd157SKalle Valo * FIX THIS - the FW descriptors are actually for 3675e3dd157SKalle Valo * MSDUs in the end of this A-MSDU instead of the 3685e3dd157SKalle Valo * beginning. 3695e3dd157SKalle Valo */ 3705e3dd157SKalle Valo rx_desc->fw_desc.info0 = 0; 3715e3dd157SKalle Valo } 3725e3dd157SKalle Valo 3735e3dd157SKalle Valo msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags) 3745e3dd157SKalle Valo & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR | 3755e3dd157SKalle Valo RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR)); 3765e3dd157SKalle Valo msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0), 3775e3dd157SKalle Valo RX_MSDU_START_INFO0_MSDU_LENGTH); 3785e3dd157SKalle Valo msdu_chained = rx_desc->frag_info.ring2_more_count; 3795e3dd157SKalle Valo 3805e3dd157SKalle Valo if (msdu_len_invalid) 3815e3dd157SKalle Valo msdu_len = 0; 3825e3dd157SKalle Valo 3835e3dd157SKalle Valo skb_trim(msdu, 0); 3845e3dd157SKalle Valo skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE)); 3855e3dd157SKalle Valo msdu_len -= msdu->len; 3865e3dd157SKalle Valo 3875e3dd157SKalle Valo /* FIXME: Do chained buffers include htt_rx_desc or not? */ 3885e3dd157SKalle Valo while (msdu_chained--) { 3895e3dd157SKalle Valo struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt); 3905e3dd157SKalle Valo 3915e3dd157SKalle Valo dma_unmap_single(htt->ar->dev, 3925e3dd157SKalle Valo ATH10K_SKB_CB(next)->paddr, 3935e3dd157SKalle Valo next->len + skb_tailroom(next), 3945e3dd157SKalle Valo DMA_FROM_DEVICE); 3955e3dd157SKalle Valo 3965e3dd157SKalle Valo ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx: ", 3975e3dd157SKalle Valo next->data, 3985e3dd157SKalle Valo next->len + skb_tailroom(next)); 3995e3dd157SKalle Valo 4005e3dd157SKalle Valo skb_trim(next, 0); 4015e3dd157SKalle Valo skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE)); 4025e3dd157SKalle Valo msdu_len -= next->len; 4035e3dd157SKalle Valo 4045e3dd157SKalle Valo msdu->next = next; 4055e3dd157SKalle Valo msdu = next; 4065e3dd157SKalle Valo msdu_chaining = 1; 4075e3dd157SKalle Valo } 4085e3dd157SKalle Valo 4095e3dd157SKalle Valo if (msdu_len > 0) { 4105e3dd157SKalle Valo /* This may suggest FW bug? */ 4115e3dd157SKalle Valo ath10k_warn("htt rx msdu len not consumed (%d)\n", 4125e3dd157SKalle Valo msdu_len); 4135e3dd157SKalle Valo } 4145e3dd157SKalle Valo 4155e3dd157SKalle Valo last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) & 4165e3dd157SKalle Valo RX_MSDU_END_INFO0_LAST_MSDU; 4175e3dd157SKalle Valo 4185e3dd157SKalle Valo if (last_msdu) { 4195e3dd157SKalle Valo msdu->next = NULL; 4205e3dd157SKalle Valo break; 4215e3dd157SKalle Valo } else { 4225e3dd157SKalle Valo struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt); 4235e3dd157SKalle Valo msdu->next = next; 4245e3dd157SKalle Valo msdu = next; 4255e3dd157SKalle Valo } 4265e3dd157SKalle Valo } 4275e3dd157SKalle Valo *tail_msdu = msdu; 4285e3dd157SKalle Valo 4295e3dd157SKalle Valo /* 4305e3dd157SKalle Valo * Don't refill the ring yet. 4315e3dd157SKalle Valo * 4325e3dd157SKalle Valo * First, the elements popped here are still in use - it is not 4335e3dd157SKalle Valo * safe to overwrite them until the matching call to 4345e3dd157SKalle Valo * mpdu_desc_list_next. Second, for efficiency it is preferable to 4355e3dd157SKalle Valo * refill the rx ring with 1 PPDU's worth of rx buffers (something 4365e3dd157SKalle Valo * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers 4375e3dd157SKalle Valo * (something like 3 buffers). Consequently, we'll rely on the txrx 4385e3dd157SKalle Valo * SW to tell us when it is done pulling all the PPDU's rx buffers 4395e3dd157SKalle Valo * out of the rx ring, and then refill it just once. 4405e3dd157SKalle Valo */ 4415e3dd157SKalle Valo 4425e3dd157SKalle Valo return msdu_chaining; 4435e3dd157SKalle Valo } 4445e3dd157SKalle Valo 4455e3dd157SKalle Valo int ath10k_htt_rx_attach(struct ath10k_htt *htt) 4465e3dd157SKalle Valo { 4475e3dd157SKalle Valo dma_addr_t paddr; 4485e3dd157SKalle Valo void *vaddr; 4495e3dd157SKalle Valo struct timer_list *timer = &htt->rx_ring.refill_retry_timer; 4505e3dd157SKalle Valo 4515e3dd157SKalle Valo htt->rx_ring.size = ath10k_htt_rx_ring_size(htt); 4525e3dd157SKalle Valo if (!is_power_of_2(htt->rx_ring.size)) { 4535e3dd157SKalle Valo ath10k_warn("htt rx ring size is not power of 2\n"); 4545e3dd157SKalle Valo return -EINVAL; 4555e3dd157SKalle Valo } 4565e3dd157SKalle Valo 4575e3dd157SKalle Valo htt->rx_ring.size_mask = htt->rx_ring.size - 1; 4585e3dd157SKalle Valo 4595e3dd157SKalle Valo /* 4605e3dd157SKalle Valo * Set the initial value for the level to which the rx ring 4615e3dd157SKalle Valo * should be filled, based on the max throughput and the 4625e3dd157SKalle Valo * worst likely latency for the host to fill the rx ring 4635e3dd157SKalle Valo * with new buffers. In theory, this fill level can be 4645e3dd157SKalle Valo * dynamically adjusted from the initial value set here, to 4655e3dd157SKalle Valo * reflect the actual host latency rather than a 4665e3dd157SKalle Valo * conservative assumption about the host latency. 4675e3dd157SKalle Valo */ 4685e3dd157SKalle Valo htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt); 4695e3dd157SKalle Valo 4705e3dd157SKalle Valo htt->rx_ring.netbufs_ring = 4715e3dd157SKalle Valo kmalloc(htt->rx_ring.size * sizeof(struct sk_buff *), 4725e3dd157SKalle Valo GFP_KERNEL); 4735e3dd157SKalle Valo if (!htt->rx_ring.netbufs_ring) 4745e3dd157SKalle Valo goto err_netbuf; 4755e3dd157SKalle Valo 4765e3dd157SKalle Valo vaddr = dma_alloc_coherent(htt->ar->dev, 4775e3dd157SKalle Valo (htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring)), 4785e3dd157SKalle Valo &paddr, GFP_DMA); 4795e3dd157SKalle Valo if (!vaddr) 4805e3dd157SKalle Valo goto err_dma_ring; 4815e3dd157SKalle Valo 4825e3dd157SKalle Valo htt->rx_ring.paddrs_ring = vaddr; 4835e3dd157SKalle Valo htt->rx_ring.base_paddr = paddr; 4845e3dd157SKalle Valo 4855e3dd157SKalle Valo vaddr = dma_alloc_coherent(htt->ar->dev, 4865e3dd157SKalle Valo sizeof(*htt->rx_ring.alloc_idx.vaddr), 4875e3dd157SKalle Valo &paddr, GFP_DMA); 4885e3dd157SKalle Valo if (!vaddr) 4895e3dd157SKalle Valo goto err_dma_idx; 4905e3dd157SKalle Valo 4915e3dd157SKalle Valo htt->rx_ring.alloc_idx.vaddr = vaddr; 4925e3dd157SKalle Valo htt->rx_ring.alloc_idx.paddr = paddr; 4935e3dd157SKalle Valo htt->rx_ring.sw_rd_idx.msdu_payld = 0; 4945e3dd157SKalle Valo *htt->rx_ring.alloc_idx.vaddr = 0; 4955e3dd157SKalle Valo 4965e3dd157SKalle Valo /* Initialize the Rx refill retry timer */ 4975e3dd157SKalle Valo setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt); 4985e3dd157SKalle Valo 4995e3dd157SKalle Valo spin_lock_init(&htt->rx_ring.lock); 5005e3dd157SKalle Valo 5015e3dd157SKalle Valo htt->rx_ring.fill_cnt = 0; 5025e3dd157SKalle Valo if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level)) 5035e3dd157SKalle Valo goto err_fill_ring; 5045e3dd157SKalle Valo 505aad0b65fSKalle Valo ath10k_dbg(ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n", 5065e3dd157SKalle Valo htt->rx_ring.size, htt->rx_ring.fill_level); 5075e3dd157SKalle Valo return 0; 5085e3dd157SKalle Valo 5095e3dd157SKalle Valo err_fill_ring: 5105e3dd157SKalle Valo ath10k_htt_rx_ring_free(htt); 5115e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 5125e3dd157SKalle Valo sizeof(*htt->rx_ring.alloc_idx.vaddr), 5135e3dd157SKalle Valo htt->rx_ring.alloc_idx.vaddr, 5145e3dd157SKalle Valo htt->rx_ring.alloc_idx.paddr); 5155e3dd157SKalle Valo err_dma_idx: 5165e3dd157SKalle Valo dma_free_coherent(htt->ar->dev, 5175e3dd157SKalle Valo (htt->rx_ring.size * 5185e3dd157SKalle Valo sizeof(htt->rx_ring.paddrs_ring)), 5195e3dd157SKalle Valo htt->rx_ring.paddrs_ring, 5205e3dd157SKalle Valo htt->rx_ring.base_paddr); 5215e3dd157SKalle Valo err_dma_ring: 5225e3dd157SKalle Valo kfree(htt->rx_ring.netbufs_ring); 5235e3dd157SKalle Valo err_netbuf: 5245e3dd157SKalle Valo return -ENOMEM; 5255e3dd157SKalle Valo } 5265e3dd157SKalle Valo 5275e3dd157SKalle Valo static int ath10k_htt_rx_crypto_param_len(enum htt_rx_mpdu_encrypt_type type) 5285e3dd157SKalle Valo { 5295e3dd157SKalle Valo switch (type) { 5305e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP40: 5315e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP104: 5325e3dd157SKalle Valo return 4; 5335e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC: 5345e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP128: /* not tested */ 5355e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WPA: 5365e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WAPI: /* not tested */ 5375e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2: 5385e3dd157SKalle Valo return 8; 5395e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_NONE: 5405e3dd157SKalle Valo return 0; 5415e3dd157SKalle Valo } 5425e3dd157SKalle Valo 5435e3dd157SKalle Valo ath10k_warn("unknown encryption type %d\n", type); 5445e3dd157SKalle Valo return 0; 5455e3dd157SKalle Valo } 5465e3dd157SKalle Valo 5475e3dd157SKalle Valo static int ath10k_htt_rx_crypto_tail_len(enum htt_rx_mpdu_encrypt_type type) 5485e3dd157SKalle Valo { 5495e3dd157SKalle Valo switch (type) { 5505e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_NONE: 5515e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP40: 5525e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP104: 5535e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WEP128: 5545e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_WAPI: 5555e3dd157SKalle Valo return 0; 5565e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC: 5575e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_TKIP_WPA: 5585e3dd157SKalle Valo return 4; 5595e3dd157SKalle Valo case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2: 5605e3dd157SKalle Valo return 8; 5615e3dd157SKalle Valo } 5625e3dd157SKalle Valo 5635e3dd157SKalle Valo ath10k_warn("unknown encryption type %d\n", type); 5645e3dd157SKalle Valo return 0; 5655e3dd157SKalle Valo } 5665e3dd157SKalle Valo 5675e3dd157SKalle Valo /* Applies for first msdu in chain, before altering it. */ 5685e3dd157SKalle Valo static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb) 5695e3dd157SKalle Valo { 5705e3dd157SKalle Valo struct htt_rx_desc *rxd; 5715e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 5725e3dd157SKalle Valo 5735e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 5745e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 5755e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 5765e3dd157SKalle Valo 5775e3dd157SKalle Valo if (fmt == RX_MSDU_DECAP_RAW) 5785e3dd157SKalle Valo return (void *)skb->data; 5795e3dd157SKalle Valo else 5805e3dd157SKalle Valo return (void *)skb->data - RX_HTT_HDR_STATUS_LEN; 5815e3dd157SKalle Valo } 5825e3dd157SKalle Valo 5835e3dd157SKalle Valo /* This function only applies for first msdu in an msdu chain */ 5845e3dd157SKalle Valo static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr) 5855e3dd157SKalle Valo { 5865e3dd157SKalle Valo if (ieee80211_is_data_qos(hdr->frame_control)) { 5875e3dd157SKalle Valo u8 *qc = ieee80211_get_qos_ctl(hdr); 5885e3dd157SKalle Valo if (qc[0] & 0x80) 5895e3dd157SKalle Valo return true; 5905e3dd157SKalle Valo } 5915e3dd157SKalle Valo return false; 5925e3dd157SKalle Valo } 5935e3dd157SKalle Valo 5945e3dd157SKalle Valo static int ath10k_htt_rx_amsdu(struct ath10k_htt *htt, 5955e3dd157SKalle Valo struct htt_rx_info *info) 5965e3dd157SKalle Valo { 5975e3dd157SKalle Valo struct htt_rx_desc *rxd; 5985e3dd157SKalle Valo struct sk_buff *amsdu; 5995e3dd157SKalle Valo struct sk_buff *first; 6005e3dd157SKalle Valo struct ieee80211_hdr *hdr; 6015e3dd157SKalle Valo struct sk_buff *skb = info->skb; 6025e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 6035e3dd157SKalle Valo enum htt_rx_mpdu_encrypt_type enctype; 6045e3dd157SKalle Valo unsigned int hdr_len; 6055e3dd157SKalle Valo int crypto_len; 6065e3dd157SKalle Valo 6075e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 6085e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 6095e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 6105e3dd157SKalle Valo enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), 6115e3dd157SKalle Valo RX_MPDU_START_INFO0_ENCRYPT_TYPE); 6125e3dd157SKalle Valo 6135e3dd157SKalle Valo /* FIXME: No idea what assumptions are safe here. Need logs */ 614dfa95b50SMichal Kazior if ((fmt == RX_MSDU_DECAP_RAW && skb->next)) { 6155e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(skb->next); 6165e3dd157SKalle Valo skb->next = NULL; 6175e3dd157SKalle Valo return -ENOTSUPP; 6185e3dd157SKalle Valo } 6195e3dd157SKalle Valo 6205e3dd157SKalle Valo /* A-MSDU max is a little less than 8K */ 6215e3dd157SKalle Valo amsdu = dev_alloc_skb(8*1024); 6225e3dd157SKalle Valo if (!amsdu) { 6235e3dd157SKalle Valo ath10k_warn("A-MSDU allocation failed\n"); 6245e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(skb->next); 6255e3dd157SKalle Valo skb->next = NULL; 6265e3dd157SKalle Valo return -ENOMEM; 6275e3dd157SKalle Valo } 6285e3dd157SKalle Valo 6295e3dd157SKalle Valo if (fmt >= RX_MSDU_DECAP_NATIVE_WIFI) { 6305e3dd157SKalle Valo int hdrlen; 6315e3dd157SKalle Valo 6325e3dd157SKalle Valo hdr = (void *)rxd->rx_hdr_status; 6335e3dd157SKalle Valo hdrlen = ieee80211_hdrlen(hdr->frame_control); 6345e3dd157SKalle Valo memcpy(skb_put(amsdu, hdrlen), hdr, hdrlen); 6355e3dd157SKalle Valo } 6365e3dd157SKalle Valo 6375e3dd157SKalle Valo first = skb; 6385e3dd157SKalle Valo while (skb) { 6395e3dd157SKalle Valo void *decap_hdr; 6405e3dd157SKalle Valo int decap_len = 0; 6415e3dd157SKalle Valo 6425e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 6435e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 6445e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 6455e3dd157SKalle Valo decap_hdr = (void *)rxd->rx_hdr_status; 6465e3dd157SKalle Valo 6475e3dd157SKalle Valo if (skb == first) { 6485e3dd157SKalle Valo /* We receive linked A-MSDU subframe skbuffs. The 6495e3dd157SKalle Valo * first one contains the original 802.11 header (and 6505e3dd157SKalle Valo * possible crypto param) in the RX descriptor. The 6515e3dd157SKalle Valo * A-MSDU subframe header follows that. Each part is 6525e3dd157SKalle Valo * aligned to 4 byte boundary. */ 6535e3dd157SKalle Valo 6545e3dd157SKalle Valo hdr = (void *)amsdu->data; 6555e3dd157SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 6565e3dd157SKalle Valo crypto_len = ath10k_htt_rx_crypto_param_len(enctype); 6575e3dd157SKalle Valo 6585e3dd157SKalle Valo decap_hdr += roundup(hdr_len, 4); 6595e3dd157SKalle Valo decap_hdr += roundup(crypto_len, 4); 6605e3dd157SKalle Valo } 6615e3dd157SKalle Valo 662dfa95b50SMichal Kazior /* When fmt == RX_MSDU_DECAP_8023_SNAP_LLC: 663dfa95b50SMichal Kazior * 664dfa95b50SMichal Kazior * SNAP 802.3 consists of: 665dfa95b50SMichal Kazior * [dst:6][src:6][len:2][dsap:1][ssap:1][ctl:1][snap:5] 666dfa95b50SMichal Kazior * [data][fcs:4]. 667dfa95b50SMichal Kazior * 668dfa95b50SMichal Kazior * Since this overlaps with A-MSDU header (da, sa, len) 669dfa95b50SMichal Kazior * there's nothing extra to do. */ 670dfa95b50SMichal Kazior 6715e3dd157SKalle Valo if (fmt == RX_MSDU_DECAP_ETHERNET2_DIX) { 6725e3dd157SKalle Valo /* Ethernet2 decap inserts ethernet header in place of 6735e3dd157SKalle Valo * A-MSDU subframe header. */ 6745e3dd157SKalle Valo skb_pull(skb, 6 + 6 + 2); 6755e3dd157SKalle Valo 6765e3dd157SKalle Valo /* A-MSDU subframe header length */ 6775e3dd157SKalle Valo decap_len += 6 + 6 + 2; 6785e3dd157SKalle Valo 6795e3dd157SKalle Valo /* Ethernet2 decap also strips the LLC/SNAP so we need 6805e3dd157SKalle Valo * to re-insert it. The LLC/SNAP follows A-MSDU 6815e3dd157SKalle Valo * subframe header. */ 6825e3dd157SKalle Valo /* FIXME: Not all LLCs are 8 bytes long */ 6835e3dd157SKalle Valo decap_len += 8; 6845e3dd157SKalle Valo 6855e3dd157SKalle Valo memcpy(skb_put(amsdu, decap_len), decap_hdr, decap_len); 6865e3dd157SKalle Valo } 6875e3dd157SKalle Valo 6885e3dd157SKalle Valo if (fmt == RX_MSDU_DECAP_NATIVE_WIFI) { 6895e3dd157SKalle Valo /* Native Wifi decap inserts regular 802.11 header 6905e3dd157SKalle Valo * in place of A-MSDU subframe header. */ 6915e3dd157SKalle Valo hdr = (struct ieee80211_hdr *)skb->data; 6925e3dd157SKalle Valo skb_pull(skb, ieee80211_hdrlen(hdr->frame_control)); 6935e3dd157SKalle Valo 6945e3dd157SKalle Valo /* A-MSDU subframe header length */ 6955e3dd157SKalle Valo decap_len += 6 + 6 + 2; 6965e3dd157SKalle Valo 6975e3dd157SKalle Valo memcpy(skb_put(amsdu, decap_len), decap_hdr, decap_len); 6985e3dd157SKalle Valo } 6995e3dd157SKalle Valo 7005e3dd157SKalle Valo if (fmt == RX_MSDU_DECAP_RAW) 7015e3dd157SKalle Valo skb_trim(skb, skb->len - 4); /* remove FCS */ 7025e3dd157SKalle Valo 7035e3dd157SKalle Valo memcpy(skb_put(amsdu, skb->len), skb->data, skb->len); 7045e3dd157SKalle Valo 7055e3dd157SKalle Valo /* A-MSDU subframes are padded to 4bytes 7065e3dd157SKalle Valo * but relative to first subframe, not the whole MPDU */ 7075e3dd157SKalle Valo if (skb->next && ((decap_len + skb->len) & 3)) { 7085e3dd157SKalle Valo int padlen = 4 - ((decap_len + skb->len) & 3); 7095e3dd157SKalle Valo memset(skb_put(amsdu, padlen), 0, padlen); 7105e3dd157SKalle Valo } 7115e3dd157SKalle Valo 7125e3dd157SKalle Valo skb = skb->next; 7135e3dd157SKalle Valo } 7145e3dd157SKalle Valo 7155e3dd157SKalle Valo info->skb = amsdu; 7165e3dd157SKalle Valo info->encrypt_type = enctype; 7175e3dd157SKalle Valo 7185e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(first); 7195e3dd157SKalle Valo 7205e3dd157SKalle Valo return 0; 7215e3dd157SKalle Valo } 7225e3dd157SKalle Valo 7235e3dd157SKalle Valo static int ath10k_htt_rx_msdu(struct ath10k_htt *htt, struct htt_rx_info *info) 7245e3dd157SKalle Valo { 7255e3dd157SKalle Valo struct sk_buff *skb = info->skb; 7265e3dd157SKalle Valo struct htt_rx_desc *rxd; 7275e3dd157SKalle Valo struct ieee80211_hdr *hdr; 7285e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 7295e3dd157SKalle Valo enum htt_rx_mpdu_encrypt_type enctype; 7305e3dd157SKalle Valo 7315e3dd157SKalle Valo /* This shouldn't happen. If it does than it may be a FW bug. */ 7325e3dd157SKalle Valo if (skb->next) { 7335e3dd157SKalle Valo ath10k_warn("received chained non A-MSDU frame\n"); 7345e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(skb->next); 7355e3dd157SKalle Valo skb->next = NULL; 7365e3dd157SKalle Valo } 7375e3dd157SKalle Valo 7385e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 7395e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 7405e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 7415e3dd157SKalle Valo enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), 7425e3dd157SKalle Valo RX_MPDU_START_INFO0_ENCRYPT_TYPE); 7435e3dd157SKalle Valo hdr = (void *)skb->data - RX_HTT_HDR_STATUS_LEN; 7445e3dd157SKalle Valo 7455e3dd157SKalle Valo switch (fmt) { 7465e3dd157SKalle Valo case RX_MSDU_DECAP_RAW: 7475e3dd157SKalle Valo /* remove trailing FCS */ 7485e3dd157SKalle Valo skb_trim(skb, skb->len - 4); 7495e3dd157SKalle Valo break; 7505e3dd157SKalle Valo case RX_MSDU_DECAP_NATIVE_WIFI: 7515e3dd157SKalle Valo /* nothing to do here */ 7525e3dd157SKalle Valo break; 7535e3dd157SKalle Valo case RX_MSDU_DECAP_ETHERNET2_DIX: 7545e3dd157SKalle Valo /* macaddr[6] + macaddr[6] + ethertype[2] */ 7555e3dd157SKalle Valo skb_pull(skb, 6 + 6 + 2); 7565e3dd157SKalle Valo break; 7575e3dd157SKalle Valo case RX_MSDU_DECAP_8023_SNAP_LLC: 7585e3dd157SKalle Valo /* macaddr[6] + macaddr[6] + len[2] */ 7595e3dd157SKalle Valo /* we don't need this for non-A-MSDU */ 7605e3dd157SKalle Valo skb_pull(skb, 6 + 6 + 2); 7615e3dd157SKalle Valo break; 7625e3dd157SKalle Valo } 7635e3dd157SKalle Valo 7645e3dd157SKalle Valo if (fmt == RX_MSDU_DECAP_ETHERNET2_DIX) { 7655e3dd157SKalle Valo void *llc; 7665e3dd157SKalle Valo int llclen; 7675e3dd157SKalle Valo 7685e3dd157SKalle Valo llclen = 8; 7695e3dd157SKalle Valo llc = hdr; 7705e3dd157SKalle Valo llc += roundup(ieee80211_hdrlen(hdr->frame_control), 4); 7715e3dd157SKalle Valo llc += roundup(ath10k_htt_rx_crypto_param_len(enctype), 4); 7725e3dd157SKalle Valo 7735e3dd157SKalle Valo skb_push(skb, llclen); 7745e3dd157SKalle Valo memcpy(skb->data, llc, llclen); 7755e3dd157SKalle Valo } 7765e3dd157SKalle Valo 7775e3dd157SKalle Valo if (fmt >= RX_MSDU_DECAP_ETHERNET2_DIX) { 7785e3dd157SKalle Valo int len = ieee80211_hdrlen(hdr->frame_control); 7795e3dd157SKalle Valo skb_push(skb, len); 7805e3dd157SKalle Valo memcpy(skb->data, hdr, len); 7815e3dd157SKalle Valo } 7825e3dd157SKalle Valo 7835e3dd157SKalle Valo info->skb = skb; 7845e3dd157SKalle Valo info->encrypt_type = enctype; 7855e3dd157SKalle Valo return 0; 7865e3dd157SKalle Valo } 7875e3dd157SKalle Valo 7885e3dd157SKalle Valo static bool ath10k_htt_rx_has_decrypt_err(struct sk_buff *skb) 7895e3dd157SKalle Valo { 7905e3dd157SKalle Valo struct htt_rx_desc *rxd; 7915e3dd157SKalle Valo u32 flags; 7925e3dd157SKalle Valo 7935e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 7945e3dd157SKalle Valo flags = __le32_to_cpu(rxd->attention.flags); 7955e3dd157SKalle Valo 7965e3dd157SKalle Valo if (flags & RX_ATTENTION_FLAGS_DECRYPT_ERR) 7975e3dd157SKalle Valo return true; 7985e3dd157SKalle Valo 7995e3dd157SKalle Valo return false; 8005e3dd157SKalle Valo } 8015e3dd157SKalle Valo 8025e3dd157SKalle Valo static bool ath10k_htt_rx_has_fcs_err(struct sk_buff *skb) 8035e3dd157SKalle Valo { 8045e3dd157SKalle Valo struct htt_rx_desc *rxd; 8055e3dd157SKalle Valo u32 flags; 8065e3dd157SKalle Valo 8075e3dd157SKalle Valo rxd = (void *)skb->data - sizeof(*rxd); 8085e3dd157SKalle Valo flags = __le32_to_cpu(rxd->attention.flags); 8095e3dd157SKalle Valo 8105e3dd157SKalle Valo if (flags & RX_ATTENTION_FLAGS_FCS_ERR) 8115e3dd157SKalle Valo return true; 8125e3dd157SKalle Valo 8135e3dd157SKalle Valo return false; 8145e3dd157SKalle Valo } 8155e3dd157SKalle Valo 816605f81aaSMichal Kazior static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb) 817605f81aaSMichal Kazior { 818605f81aaSMichal Kazior struct htt_rx_desc *rxd; 819605f81aaSMichal Kazior u32 flags, info; 820605f81aaSMichal Kazior bool is_ip4, is_ip6; 821605f81aaSMichal Kazior bool is_tcp, is_udp; 822605f81aaSMichal Kazior bool ip_csum_ok, tcpudp_csum_ok; 823605f81aaSMichal Kazior 824605f81aaSMichal Kazior rxd = (void *)skb->data - sizeof(*rxd); 825605f81aaSMichal Kazior flags = __le32_to_cpu(rxd->attention.flags); 826605f81aaSMichal Kazior info = __le32_to_cpu(rxd->msdu_start.info1); 827605f81aaSMichal Kazior 828605f81aaSMichal Kazior is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO); 829605f81aaSMichal Kazior is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO); 830605f81aaSMichal Kazior is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO); 831605f81aaSMichal Kazior is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO); 832605f81aaSMichal Kazior ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL); 833605f81aaSMichal Kazior tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL); 834605f81aaSMichal Kazior 835605f81aaSMichal Kazior if (!is_ip4 && !is_ip6) 836605f81aaSMichal Kazior return CHECKSUM_NONE; 837605f81aaSMichal Kazior if (!is_tcp && !is_udp) 838605f81aaSMichal Kazior return CHECKSUM_NONE; 839605f81aaSMichal Kazior if (!ip_csum_ok) 840605f81aaSMichal Kazior return CHECKSUM_NONE; 841605f81aaSMichal Kazior if (!tcpudp_csum_ok) 842605f81aaSMichal Kazior return CHECKSUM_NONE; 843605f81aaSMichal Kazior 844605f81aaSMichal Kazior return CHECKSUM_UNNECESSARY; 845605f81aaSMichal Kazior } 846605f81aaSMichal Kazior 8475e3dd157SKalle Valo static void ath10k_htt_rx_handler(struct ath10k_htt *htt, 8485e3dd157SKalle Valo struct htt_rx_indication *rx) 8495e3dd157SKalle Valo { 8505e3dd157SKalle Valo struct htt_rx_info info; 8515e3dd157SKalle Valo struct htt_rx_indication_mpdu_range *mpdu_ranges; 8525e3dd157SKalle Valo struct ieee80211_hdr *hdr; 8535e3dd157SKalle Valo int num_mpdu_ranges; 8545e3dd157SKalle Valo int fw_desc_len; 8555e3dd157SKalle Valo u8 *fw_desc; 8565e3dd157SKalle Valo int i, j; 8575e3dd157SKalle Valo int ret; 858605f81aaSMichal Kazior int ip_summed; 8595e3dd157SKalle Valo 8605e3dd157SKalle Valo memset(&info, 0, sizeof(info)); 8615e3dd157SKalle Valo 8625e3dd157SKalle Valo fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes); 8635e3dd157SKalle Valo fw_desc = (u8 *)&rx->fw_desc; 8645e3dd157SKalle Valo 8655e3dd157SKalle Valo num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1), 8665e3dd157SKalle Valo HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES); 8675e3dd157SKalle Valo mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx); 8685e3dd157SKalle Valo 8695e3dd157SKalle Valo ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ", 8705e3dd157SKalle Valo rx, sizeof(*rx) + 8715e3dd157SKalle Valo (sizeof(struct htt_rx_indication_mpdu_range) * 8725e3dd157SKalle Valo num_mpdu_ranges)); 8735e3dd157SKalle Valo 8745e3dd157SKalle Valo for (i = 0; i < num_mpdu_ranges; i++) { 8755e3dd157SKalle Valo info.status = mpdu_ranges[i].mpdu_range_status; 8765e3dd157SKalle Valo 8775e3dd157SKalle Valo for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) { 8785e3dd157SKalle Valo struct sk_buff *msdu_head, *msdu_tail; 8795e3dd157SKalle Valo enum htt_rx_mpdu_status status; 8805e3dd157SKalle Valo int msdu_chaining; 8815e3dd157SKalle Valo 8825e3dd157SKalle Valo msdu_head = NULL; 8835e3dd157SKalle Valo msdu_tail = NULL; 8845e3dd157SKalle Valo msdu_chaining = ath10k_htt_rx_amsdu_pop(htt, 8855e3dd157SKalle Valo &fw_desc, 8865e3dd157SKalle Valo &fw_desc_len, 8875e3dd157SKalle Valo &msdu_head, 8885e3dd157SKalle Valo &msdu_tail); 8895e3dd157SKalle Valo 8905e3dd157SKalle Valo if (!msdu_head) { 8915e3dd157SKalle Valo ath10k_warn("htt rx no data!\n"); 8925e3dd157SKalle Valo continue; 8935e3dd157SKalle Valo } 8945e3dd157SKalle Valo 8955e3dd157SKalle Valo if (msdu_head->len == 0) { 8965e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT, 8975e3dd157SKalle Valo "htt rx dropping due to zero-len\n"); 8985e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(msdu_head); 8995e3dd157SKalle Valo continue; 9005e3dd157SKalle Valo } 9015e3dd157SKalle Valo 9025e3dd157SKalle Valo if (ath10k_htt_rx_has_decrypt_err(msdu_head)) { 9035e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(msdu_head); 9045e3dd157SKalle Valo continue; 9055e3dd157SKalle Valo } 9065e3dd157SKalle Valo 9075e3dd157SKalle Valo status = info.status; 9085e3dd157SKalle Valo 9095e3dd157SKalle Valo /* Skip mgmt frames while we handle this in WMI */ 9105e3dd157SKalle Valo if (status == HTT_RX_IND_MPDU_STATUS_MGMT_CTRL) { 9115e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(msdu_head); 9125e3dd157SKalle Valo continue; 9135e3dd157SKalle Valo } 9145e3dd157SKalle Valo 9155e3dd157SKalle Valo if (status != HTT_RX_IND_MPDU_STATUS_OK && 9165e3dd157SKalle Valo status != HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR && 9175e3dd157SKalle Valo !htt->ar->monitor_enabled) { 9185e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT, 9195e3dd157SKalle Valo "htt rx ignoring frame w/ status %d\n", 9205e3dd157SKalle Valo status); 9215e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(msdu_head); 9225e3dd157SKalle Valo continue; 9235e3dd157SKalle Valo } 9245e3dd157SKalle Valo 9255e3dd157SKalle Valo /* FIXME: we do not support chaining yet. 9265e3dd157SKalle Valo * this needs investigation */ 9275e3dd157SKalle Valo if (msdu_chaining) { 9285e3dd157SKalle Valo ath10k_warn("msdu_chaining is true\n"); 9295e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(msdu_head); 9305e3dd157SKalle Valo continue; 9315e3dd157SKalle Valo } 9325e3dd157SKalle Valo 933605f81aaSMichal Kazior /* The skb is not yet processed and it may be 934605f81aaSMichal Kazior * reallocated. Since the offload is in the original 935605f81aaSMichal Kazior * skb extract the checksum now and assign it later */ 936605f81aaSMichal Kazior ip_summed = ath10k_htt_rx_get_csum_state(msdu_head); 937605f81aaSMichal Kazior 9385e3dd157SKalle Valo info.skb = msdu_head; 9395e3dd157SKalle Valo info.fcs_err = ath10k_htt_rx_has_fcs_err(msdu_head); 9405e3dd157SKalle Valo info.signal = ATH10K_DEFAULT_NOISE_FLOOR; 9415e3dd157SKalle Valo info.signal += rx->ppdu.combined_rssi; 9425e3dd157SKalle Valo 9435e3dd157SKalle Valo info.rate.info0 = rx->ppdu.info0; 9445e3dd157SKalle Valo info.rate.info1 = __le32_to_cpu(rx->ppdu.info1); 9455e3dd157SKalle Valo info.rate.info2 = __le32_to_cpu(rx->ppdu.info2); 9465e3dd157SKalle Valo 9475e3dd157SKalle Valo hdr = ath10k_htt_rx_skb_get_hdr(msdu_head); 9485e3dd157SKalle Valo 9495e3dd157SKalle Valo if (ath10k_htt_rx_hdr_is_amsdu(hdr)) 9505e3dd157SKalle Valo ret = ath10k_htt_rx_amsdu(htt, &info); 9515e3dd157SKalle Valo else 9525e3dd157SKalle Valo ret = ath10k_htt_rx_msdu(htt, &info); 9535e3dd157SKalle Valo 9545e3dd157SKalle Valo if (ret && !info.fcs_err) { 9555e3dd157SKalle Valo ath10k_warn("error processing msdus %d\n", ret); 9565e3dd157SKalle Valo dev_kfree_skb_any(info.skb); 9575e3dd157SKalle Valo continue; 9585e3dd157SKalle Valo } 9595e3dd157SKalle Valo 9605e3dd157SKalle Valo if (ath10k_htt_rx_hdr_is_amsdu((void *)info.skb->data)) 9615e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT, "htt mpdu is amsdu\n"); 9625e3dd157SKalle Valo 963605f81aaSMichal Kazior info.skb->ip_summed = ip_summed; 964605f81aaSMichal Kazior 9655e3dd157SKalle Valo ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt mpdu: ", 9665e3dd157SKalle Valo info.skb->data, info.skb->len); 9675e3dd157SKalle Valo ath10k_process_rx(htt->ar, &info); 9685e3dd157SKalle Valo } 9695e3dd157SKalle Valo } 9705e3dd157SKalle Valo 9715e3dd157SKalle Valo ath10k_htt_rx_msdu_buff_replenish(htt); 9725e3dd157SKalle Valo } 9735e3dd157SKalle Valo 9745e3dd157SKalle Valo static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt, 9755e3dd157SKalle Valo struct htt_rx_fragment_indication *frag) 9765e3dd157SKalle Valo { 9775e3dd157SKalle Valo struct sk_buff *msdu_head, *msdu_tail; 9785e3dd157SKalle Valo struct htt_rx_desc *rxd; 9795e3dd157SKalle Valo enum rx_msdu_decap_format fmt; 9805e3dd157SKalle Valo struct htt_rx_info info = {}; 9815e3dd157SKalle Valo struct ieee80211_hdr *hdr; 9825e3dd157SKalle Valo int msdu_chaining; 9835e3dd157SKalle Valo bool tkip_mic_err; 9845e3dd157SKalle Valo bool decrypt_err; 9855e3dd157SKalle Valo u8 *fw_desc; 9865e3dd157SKalle Valo int fw_desc_len, hdrlen, paramlen; 9875e3dd157SKalle Valo int trim; 9885e3dd157SKalle Valo 9895e3dd157SKalle Valo fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes); 9905e3dd157SKalle Valo fw_desc = (u8 *)frag->fw_msdu_rx_desc; 9915e3dd157SKalle Valo 9925e3dd157SKalle Valo msdu_head = NULL; 9935e3dd157SKalle Valo msdu_tail = NULL; 9945e3dd157SKalle Valo msdu_chaining = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len, 9955e3dd157SKalle Valo &msdu_head, &msdu_tail); 9965e3dd157SKalle Valo 9975e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n"); 9985e3dd157SKalle Valo 9995e3dd157SKalle Valo if (!msdu_head) { 10005e3dd157SKalle Valo ath10k_warn("htt rx frag no data\n"); 10015e3dd157SKalle Valo return; 10025e3dd157SKalle Valo } 10035e3dd157SKalle Valo 10045e3dd157SKalle Valo if (msdu_chaining || msdu_head != msdu_tail) { 10055e3dd157SKalle Valo ath10k_warn("aggregation with fragmentation?!\n"); 10065e3dd157SKalle Valo ath10k_htt_rx_free_msdu_chain(msdu_head); 10075e3dd157SKalle Valo return; 10085e3dd157SKalle Valo } 10095e3dd157SKalle Valo 10105e3dd157SKalle Valo /* FIXME: implement signal strength */ 10115e3dd157SKalle Valo 10125e3dd157SKalle Valo hdr = (struct ieee80211_hdr *)msdu_head->data; 10135e3dd157SKalle Valo rxd = (void *)msdu_head->data - sizeof(*rxd); 10145e3dd157SKalle Valo tkip_mic_err = !!(__le32_to_cpu(rxd->attention.flags) & 10155e3dd157SKalle Valo RX_ATTENTION_FLAGS_TKIP_MIC_ERR); 10165e3dd157SKalle Valo decrypt_err = !!(__le32_to_cpu(rxd->attention.flags) & 10175e3dd157SKalle Valo RX_ATTENTION_FLAGS_DECRYPT_ERR); 10185e3dd157SKalle Valo fmt = MS(__le32_to_cpu(rxd->msdu_start.info1), 10195e3dd157SKalle Valo RX_MSDU_START_INFO1_DECAP_FORMAT); 10205e3dd157SKalle Valo 10215e3dd157SKalle Valo if (fmt != RX_MSDU_DECAP_RAW) { 10225e3dd157SKalle Valo ath10k_warn("we dont support non-raw fragmented rx yet\n"); 10235e3dd157SKalle Valo dev_kfree_skb_any(msdu_head); 10245e3dd157SKalle Valo goto end; 10255e3dd157SKalle Valo } 10265e3dd157SKalle Valo 10275e3dd157SKalle Valo info.skb = msdu_head; 10285e3dd157SKalle Valo info.status = HTT_RX_IND_MPDU_STATUS_OK; 10295e3dd157SKalle Valo info.encrypt_type = MS(__le32_to_cpu(rxd->mpdu_start.info0), 10305e3dd157SKalle Valo RX_MPDU_START_INFO0_ENCRYPT_TYPE); 1031605f81aaSMichal Kazior info.skb->ip_summed = ath10k_htt_rx_get_csum_state(info.skb); 10325e3dd157SKalle Valo 10335e3dd157SKalle Valo if (tkip_mic_err) { 10345e3dd157SKalle Valo ath10k_warn("tkip mic error\n"); 10355e3dd157SKalle Valo info.status = HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR; 10365e3dd157SKalle Valo } 10375e3dd157SKalle Valo 10385e3dd157SKalle Valo if (decrypt_err) { 10395e3dd157SKalle Valo ath10k_warn("decryption err in fragmented rx\n"); 10405e3dd157SKalle Valo dev_kfree_skb_any(info.skb); 10415e3dd157SKalle Valo goto end; 10425e3dd157SKalle Valo } 10435e3dd157SKalle Valo 10445e3dd157SKalle Valo if (info.encrypt_type != HTT_RX_MPDU_ENCRYPT_NONE) { 10455e3dd157SKalle Valo hdrlen = ieee80211_hdrlen(hdr->frame_control); 10465e3dd157SKalle Valo paramlen = ath10k_htt_rx_crypto_param_len(info.encrypt_type); 10475e3dd157SKalle Valo 10485e3dd157SKalle Valo /* It is more efficient to move the header than the payload */ 10495e3dd157SKalle Valo memmove((void *)info.skb->data + paramlen, 10505e3dd157SKalle Valo (void *)info.skb->data, 10515e3dd157SKalle Valo hdrlen); 10525e3dd157SKalle Valo skb_pull(info.skb, paramlen); 10535e3dd157SKalle Valo hdr = (struct ieee80211_hdr *)info.skb->data; 10545e3dd157SKalle Valo } 10555e3dd157SKalle Valo 10565e3dd157SKalle Valo /* remove trailing FCS */ 10575e3dd157SKalle Valo trim = 4; 10585e3dd157SKalle Valo 10595e3dd157SKalle Valo /* remove crypto trailer */ 10605e3dd157SKalle Valo trim += ath10k_htt_rx_crypto_tail_len(info.encrypt_type); 10615e3dd157SKalle Valo 10625e3dd157SKalle Valo /* last fragment of TKIP frags has MIC */ 10635e3dd157SKalle Valo if (!ieee80211_has_morefrags(hdr->frame_control) && 10645e3dd157SKalle Valo info.encrypt_type == HTT_RX_MPDU_ENCRYPT_TKIP_WPA) 10655e3dd157SKalle Valo trim += 8; 10665e3dd157SKalle Valo 10675e3dd157SKalle Valo if (trim > info.skb->len) { 10685e3dd157SKalle Valo ath10k_warn("htt rx fragment: trailer longer than the frame itself? drop\n"); 10695e3dd157SKalle Valo dev_kfree_skb_any(info.skb); 10705e3dd157SKalle Valo goto end; 10715e3dd157SKalle Valo } 10725e3dd157SKalle Valo 10735e3dd157SKalle Valo skb_trim(info.skb, info.skb->len - trim); 10745e3dd157SKalle Valo 10755e3dd157SKalle Valo ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt frag mpdu: ", 10765e3dd157SKalle Valo info.skb->data, info.skb->len); 10775e3dd157SKalle Valo ath10k_process_rx(htt->ar, &info); 10785e3dd157SKalle Valo 10795e3dd157SKalle Valo end: 10805e3dd157SKalle Valo if (fw_desc_len > 0) { 10815e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT, 10825e3dd157SKalle Valo "expecting more fragmented rx in one indication %d\n", 10835e3dd157SKalle Valo fw_desc_len); 10845e3dd157SKalle Valo } 10855e3dd157SKalle Valo } 10865e3dd157SKalle Valo 10875e3dd157SKalle Valo void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb) 10885e3dd157SKalle Valo { 1089edb8236dSMichal Kazior struct ath10k_htt *htt = &ar->htt; 10905e3dd157SKalle Valo struct htt_resp *resp = (struct htt_resp *)skb->data; 10915e3dd157SKalle Valo 10925e3dd157SKalle Valo /* confirm alignment */ 10935e3dd157SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, 4)) 10945e3dd157SKalle Valo ath10k_warn("unaligned htt message, expect trouble\n"); 10955e3dd157SKalle Valo 10965e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT, "HTT RX, msg_type: 0x%0X\n", 10975e3dd157SKalle Valo resp->hdr.msg_type); 10985e3dd157SKalle Valo switch (resp->hdr.msg_type) { 10995e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_VERSION_CONF: { 11005e3dd157SKalle Valo htt->target_version_major = resp->ver_resp.major; 11015e3dd157SKalle Valo htt->target_version_minor = resp->ver_resp.minor; 11025e3dd157SKalle Valo complete(&htt->target_version_received); 11035e3dd157SKalle Valo break; 11045e3dd157SKalle Valo } 11055e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_IND: { 11065e3dd157SKalle Valo ath10k_htt_rx_handler(htt, &resp->rx_ind); 11075e3dd157SKalle Valo break; 11085e3dd157SKalle Valo } 11095e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_PEER_MAP: { 11105e3dd157SKalle Valo struct htt_peer_map_event ev = { 11115e3dd157SKalle Valo .vdev_id = resp->peer_map.vdev_id, 11125e3dd157SKalle Valo .peer_id = __le16_to_cpu(resp->peer_map.peer_id), 11135e3dd157SKalle Valo }; 11145e3dd157SKalle Valo memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr)); 11155e3dd157SKalle Valo ath10k_peer_map_event(htt, &ev); 11165e3dd157SKalle Valo break; 11175e3dd157SKalle Valo } 11185e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_PEER_UNMAP: { 11195e3dd157SKalle Valo struct htt_peer_unmap_event ev = { 11205e3dd157SKalle Valo .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id), 11215e3dd157SKalle Valo }; 11225e3dd157SKalle Valo ath10k_peer_unmap_event(htt, &ev); 11235e3dd157SKalle Valo break; 11245e3dd157SKalle Valo } 11255e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: { 11265e3dd157SKalle Valo struct htt_tx_done tx_done = {}; 11275e3dd157SKalle Valo int status = __le32_to_cpu(resp->mgmt_tx_completion.status); 11285e3dd157SKalle Valo 11295e3dd157SKalle Valo tx_done.msdu_id = 11305e3dd157SKalle Valo __le32_to_cpu(resp->mgmt_tx_completion.desc_id); 11315e3dd157SKalle Valo 11325e3dd157SKalle Valo switch (status) { 11335e3dd157SKalle Valo case HTT_MGMT_TX_STATUS_OK: 11345e3dd157SKalle Valo break; 11355e3dd157SKalle Valo case HTT_MGMT_TX_STATUS_RETRY: 11365e3dd157SKalle Valo tx_done.no_ack = true; 11375e3dd157SKalle Valo break; 11385e3dd157SKalle Valo case HTT_MGMT_TX_STATUS_DROP: 11395e3dd157SKalle Valo tx_done.discard = true; 11405e3dd157SKalle Valo break; 11415e3dd157SKalle Valo } 11425e3dd157SKalle Valo 11430a89f8a0SMichal Kazior ath10k_txrx_tx_unref(htt, &tx_done); 11445e3dd157SKalle Valo break; 11455e3dd157SKalle Valo } 11465e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_TX_COMPL_IND: { 11475e3dd157SKalle Valo struct htt_tx_done tx_done = {}; 11485e3dd157SKalle Valo int status = MS(resp->data_tx_completion.flags, 11495e3dd157SKalle Valo HTT_DATA_TX_STATUS); 11505e3dd157SKalle Valo __le16 msdu_id; 11515e3dd157SKalle Valo int i; 11525e3dd157SKalle Valo 11535e3dd157SKalle Valo switch (status) { 11545e3dd157SKalle Valo case HTT_DATA_TX_STATUS_NO_ACK: 11555e3dd157SKalle Valo tx_done.no_ack = true; 11565e3dd157SKalle Valo break; 11575e3dd157SKalle Valo case HTT_DATA_TX_STATUS_OK: 11585e3dd157SKalle Valo break; 11595e3dd157SKalle Valo case HTT_DATA_TX_STATUS_DISCARD: 11605e3dd157SKalle Valo case HTT_DATA_TX_STATUS_POSTPONE: 11615e3dd157SKalle Valo case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL: 11625e3dd157SKalle Valo tx_done.discard = true; 11635e3dd157SKalle Valo break; 11645e3dd157SKalle Valo default: 11655e3dd157SKalle Valo ath10k_warn("unhandled tx completion status %d\n", 11665e3dd157SKalle Valo status); 11675e3dd157SKalle Valo tx_done.discard = true; 11685e3dd157SKalle Valo break; 11695e3dd157SKalle Valo } 11705e3dd157SKalle Valo 11715e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n", 11725e3dd157SKalle Valo resp->data_tx_completion.num_msdus); 11735e3dd157SKalle Valo 11745e3dd157SKalle Valo for (i = 0; i < resp->data_tx_completion.num_msdus; i++) { 11755e3dd157SKalle Valo msdu_id = resp->data_tx_completion.msdus[i]; 11765e3dd157SKalle Valo tx_done.msdu_id = __le16_to_cpu(msdu_id); 11770a89f8a0SMichal Kazior ath10k_txrx_tx_unref(htt, &tx_done); 11785e3dd157SKalle Valo } 11795e3dd157SKalle Valo break; 11805e3dd157SKalle Valo } 11815e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_SEC_IND: { 11825e3dd157SKalle Valo struct ath10k *ar = htt->ar; 11835e3dd157SKalle Valo struct htt_security_indication *ev = &resp->security_indication; 11845e3dd157SKalle Valo 11855e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT, 11865e3dd157SKalle Valo "sec ind peer_id %d unicast %d type %d\n", 11875e3dd157SKalle Valo __le16_to_cpu(ev->peer_id), 11885e3dd157SKalle Valo !!(ev->flags & HTT_SECURITY_IS_UNICAST), 11895e3dd157SKalle Valo MS(ev->flags, HTT_SECURITY_TYPE)); 11905e3dd157SKalle Valo complete(&ar->install_key_done); 11915e3dd157SKalle Valo break; 11925e3dd157SKalle Valo } 11935e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_FRAG_IND: { 11945e3dd157SKalle Valo ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ", 11955e3dd157SKalle Valo skb->data, skb->len); 11965e3dd157SKalle Valo ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind); 11975e3dd157SKalle Valo break; 11985e3dd157SKalle Valo } 11995e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_TEST: 12005e3dd157SKalle Valo /* FIX THIS */ 12015e3dd157SKalle Valo break; 12025e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_STATS_CONF: 1203a9bf0506SKalle Valo trace_ath10k_htt_stats(skb->data, skb->len); 1204a9bf0506SKalle Valo break; 1205a9bf0506SKalle Valo case HTT_T2H_MSG_TYPE_TX_INSPECT_IND: 12065e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_ADDBA: 12075e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_DELBA: 12085e3dd157SKalle Valo case HTT_T2H_MSG_TYPE_RX_FLUSH: 12095e3dd157SKalle Valo default: 12105e3dd157SKalle Valo ath10k_dbg(ATH10K_DBG_HTT, "htt event (%d) not handled\n", 12115e3dd157SKalle Valo resp->hdr.msg_type); 12125e3dd157SKalle Valo ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ", 12135e3dd157SKalle Valo skb->data, skb->len); 12145e3dd157SKalle Valo break; 12155e3dd157SKalle Valo }; 12165e3dd157SKalle Valo 12175e3dd157SKalle Valo /* Free the indication buffer */ 12185e3dd157SKalle Valo dev_kfree_skb_any(skb); 12195e3dd157SKalle Valo } 1220