1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HTT_H_ 19 #define _HTT_H_ 20 21 #include <linux/bug.h> 22 23 #include "htc.h" 24 #include "rx_desc.h" 25 26 #define HTT_CURRENT_VERSION_MAJOR 2 27 #define HTT_CURRENT_VERSION_MINOR 1 28 29 enum htt_dbg_stats_type { 30 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 31 HTT_DBG_STATS_RX_REORDER = 1 << 1, 32 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 33 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 34 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 35 /* bits 5-23 currently reserved */ 36 37 HTT_DBG_NUM_STATS /* keep this last */ 38 }; 39 40 enum htt_h2t_msg_type { /* host-to-target */ 41 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 42 HTT_H2T_MSG_TYPE_TX_FRM = 1, 43 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 44 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 45 HTT_H2T_MSG_TYPE_SYNC = 4, 46 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 47 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 48 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 49 50 HTT_H2T_NUM_MSGS /* keep this last */ 51 }; 52 53 struct htt_cmd_hdr { 54 u8 msg_type; 55 } __packed; 56 57 struct htt_ver_req { 58 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 59 } __packed; 60 61 /* 62 * HTT tx MSDU descriptor 63 * 64 * The HTT tx MSDU descriptor is created by the host HTT SW for each 65 * tx MSDU. The HTT tx MSDU descriptor contains the information that 66 * the target firmware needs for the FW's tx processing, particularly 67 * for creating the HW msdu descriptor. 68 * The same HTT tx descriptor is used for HL and LL systems, though 69 * a few fields within the tx descriptor are used only by LL or 70 * only by HL. 71 * The HTT tx descriptor is defined in two manners: by a struct with 72 * bitfields, and by a series of [dword offset, bit mask, bit shift] 73 * definitions. 74 * The target should use the struct def, for simplicitly and clarity, 75 * but the host shall use the bit-mast + bit-shift defs, to be endian- 76 * neutral. Specifically, the host shall use the get/set macros built 77 * around the mask + shift defs. 78 */ 79 struct htt_data_tx_desc_frag { 80 __le32 paddr; 81 __le32 len; 82 } __packed; 83 84 enum htt_data_tx_desc_flags0 { 85 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 86 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 87 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 88 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 89 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 90 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 91 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 92 }; 93 94 enum htt_data_tx_desc_flags1 { 95 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 96 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 97 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 98 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 99 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 100 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 101 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 102 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 103 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 104 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 105 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 106 }; 107 108 enum htt_data_tx_ext_tid { 109 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 110 HTT_DATA_TX_EXT_TID_MGMT = 17, 111 HTT_DATA_TX_EXT_TID_INVALID = 31 112 }; 113 114 #define HTT_INVALID_PEERID 0xFFFF 115 116 /* 117 * htt_data_tx_desc - used for data tx path 118 * 119 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 120 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 121 * for special kinds of tids 122 * postponed: only for HL hosts. indicates if this is a resend 123 * (HL hosts manage queues on the host ) 124 * more_in_batch: only for HL hosts. indicates if more packets are 125 * pending. this allows target to wait and aggregate 126 */ 127 struct htt_data_tx_desc { 128 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 129 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 130 __le16 len; 131 __le16 id; 132 __le32 frags_paddr; 133 __le32 peerid; 134 u8 prefetch[0]; /* start of frame, for FW classification engine */ 135 } __packed; 136 137 enum htt_rx_ring_flags { 138 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 139 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 140 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 141 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 142 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 143 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 144 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 145 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 146 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 147 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 148 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 149 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 150 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 151 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 152 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 153 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 154 }; 155 156 struct htt_rx_ring_setup_ring { 157 __le32 fw_idx_shadow_reg_paddr; 158 __le32 rx_ring_base_paddr; 159 __le16 rx_ring_len; /* in 4-byte words */ 160 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 161 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 162 __le16 fw_idx_init_val; 163 164 /* the following offsets are in 4-byte units */ 165 __le16 mac80211_hdr_offset; 166 __le16 msdu_payload_offset; 167 __le16 ppdu_start_offset; 168 __le16 ppdu_end_offset; 169 __le16 mpdu_start_offset; 170 __le16 mpdu_end_offset; 171 __le16 msdu_start_offset; 172 __le16 msdu_end_offset; 173 __le16 rx_attention_offset; 174 __le16 frag_info_offset; 175 } __packed; 176 177 struct htt_rx_ring_setup_hdr { 178 u8 num_rings; /* supported values: 1, 2 */ 179 __le16 rsvd0; 180 } __packed; 181 182 struct htt_rx_ring_setup { 183 struct htt_rx_ring_setup_hdr hdr; 184 struct htt_rx_ring_setup_ring rings[0]; 185 } __packed; 186 187 /* 188 * htt_stats_req - request target to send specified statistics 189 * 190 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 191 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 192 * so make sure its little-endian. 193 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 194 * so make sure its little-endian. 195 * @cfg_val: stat_type specific configuration 196 * @stat_type: see %htt_dbg_stats_type 197 * @cookie_lsb: used for confirmation message from target->host 198 * @cookie_msb: ditto as %cookie 199 */ 200 struct htt_stats_req { 201 u8 upload_types[3]; 202 u8 rsvd0; 203 u8 reset_types[3]; 204 struct { 205 u8 mpdu_bytes; 206 u8 mpdu_num_msdus; 207 u8 msdu_bytes; 208 } __packed; 209 u8 stat_type; 210 __le32 cookie_lsb; 211 __le32 cookie_msb; 212 } __packed; 213 214 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 215 216 /* 217 * htt_oob_sync_req - request out-of-band sync 218 * 219 * The HTT SYNC tells the target to suspend processing of subsequent 220 * HTT host-to-target messages until some other target agent locally 221 * informs the target HTT FW that the current sync counter is equal to 222 * or greater than (in a modulo sense) the sync counter specified in 223 * the SYNC message. 224 * 225 * This allows other host-target components to synchronize their operation 226 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 227 * security key has been downloaded to and activated by the target. 228 * In the absence of any explicit synchronization counter value 229 * specification, the target HTT FW will use zero as the default current 230 * sync value. 231 * 232 * The HTT target FW will suspend its host->target message processing as long 233 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 234 */ 235 struct htt_oob_sync_req { 236 u8 sync_count; 237 __le16 rsvd0; 238 } __packed; 239 240 #define HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_MASK 0x1F 241 #define HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_LSB 0 242 243 struct htt_aggr_conf { 244 u8 max_num_ampdu_subframes; 245 union { 246 /* dont use bitfields; undefined behaviour */ 247 u8 flags; /* see %HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_ */ 248 u8 max_num_amsdu_subframes:5; 249 } __packed; 250 } __packed; 251 252 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 253 254 struct htt_mgmt_tx_desc { 255 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 256 __le32 msdu_paddr; 257 __le32 desc_id; 258 __le32 len; 259 __le32 vdev_id; 260 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 261 } __packed; 262 263 enum htt_mgmt_tx_status { 264 HTT_MGMT_TX_STATUS_OK = 0, 265 HTT_MGMT_TX_STATUS_RETRY = 1, 266 HTT_MGMT_TX_STATUS_DROP = 2 267 }; 268 269 /*=== target -> host messages ===============================================*/ 270 271 272 enum htt_t2h_msg_type { 273 HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0, 274 HTT_T2H_MSG_TYPE_RX_IND = 0x1, 275 HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2, 276 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 277 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 278 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 279 HTT_T2H_MSG_TYPE_RX_DELBA = 0x6, 280 HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 281 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 282 HTT_T2H_MSG_TYPE_STATS_CONF = 0x9, 283 HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 284 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 285 HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 286 HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 287 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION = 0xe, 288 HTT_T2H_MSG_TYPE_TEST, 289 /* keep this last */ 290 HTT_T2H_NUM_MSGS 291 }; 292 293 /* 294 * htt_resp_hdr - header for target-to-host messages 295 * 296 * msg_type: see htt_t2h_msg_type 297 */ 298 struct htt_resp_hdr { 299 u8 msg_type; 300 } __packed; 301 302 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 303 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 304 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 305 306 /* htt_ver_resp - response sent for htt_ver_req */ 307 struct htt_ver_resp { 308 u8 minor; 309 u8 major; 310 u8 rsvd0; 311 } __packed; 312 313 struct htt_mgmt_tx_completion { 314 u8 rsvd0; 315 u8 rsvd1; 316 u8 rsvd2; 317 __le32 desc_id; 318 __le32 status; 319 } __packed; 320 321 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x3F) 322 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 323 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 6) 324 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 7) 325 326 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 327 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 328 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 329 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 330 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 331 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 332 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 333 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 334 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 335 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 336 337 struct htt_rx_indication_hdr { 338 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 339 __le16 peer_id; 340 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 341 } __packed; 342 343 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 344 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 345 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 346 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 347 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 348 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 349 350 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 351 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 352 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 353 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 354 355 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 356 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 357 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 358 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 359 360 enum htt_rx_legacy_rate { 361 HTT_RX_OFDM_48 = 0, 362 HTT_RX_OFDM_24 = 1, 363 HTT_RX_OFDM_12, 364 HTT_RX_OFDM_6, 365 HTT_RX_OFDM_54, 366 HTT_RX_OFDM_36, 367 HTT_RX_OFDM_18, 368 HTT_RX_OFDM_9, 369 370 /* long preamble */ 371 HTT_RX_CCK_11_LP = 0, 372 HTT_RX_CCK_5_5_LP = 1, 373 HTT_RX_CCK_2_LP, 374 HTT_RX_CCK_1_LP, 375 /* short preamble */ 376 HTT_RX_CCK_11_SP, 377 HTT_RX_CCK_5_5_SP, 378 HTT_RX_CCK_2_SP 379 }; 380 381 enum htt_rx_legacy_rate_type { 382 HTT_RX_LEGACY_RATE_OFDM = 0, 383 HTT_RX_LEGACY_RATE_CCK 384 }; 385 386 enum htt_rx_preamble_type { 387 HTT_RX_LEGACY = 0x4, 388 HTT_RX_HT = 0x8, 389 HTT_RX_HT_WITH_TXBF = 0x9, 390 HTT_RX_VHT = 0xC, 391 HTT_RX_VHT_WITH_TXBF = 0xD, 392 }; 393 394 /* 395 * Fields: phy_err_valid, phy_err_code, tsf, 396 * usec_timestamp, sub_usec_timestamp 397 * ..are valid only if end_valid == 1. 398 * 399 * Fields: rssi_chains, legacy_rate_type, 400 * legacy_rate_cck, preamble_type, service, 401 * vht_sig_* 402 * ..are valid only if start_valid == 1; 403 */ 404 struct htt_rx_indication_ppdu { 405 u8 combined_rssi; 406 u8 sub_usec_timestamp; 407 u8 phy_err_code; 408 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 409 struct { 410 u8 pri20_db; 411 u8 ext20_db; 412 u8 ext40_db; 413 u8 ext80_db; 414 } __packed rssi_chains[4]; 415 __le32 tsf; 416 __le32 usec_timestamp; 417 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 418 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 419 } __packed; 420 421 enum htt_rx_mpdu_status { 422 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 423 HTT_RX_IND_MPDU_STATUS_OK, 424 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 425 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 426 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 427 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 428 /* only accept EAPOL frames */ 429 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 430 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 431 /* Non-data in promiscous mode */ 432 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 433 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 434 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 435 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 436 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 437 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 438 439 /* 440 * MISC: discard for unspecified reasons. 441 * Leave this enum value last. 442 */ 443 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 444 }; 445 446 struct htt_rx_indication_mpdu_range { 447 u8 mpdu_count; 448 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 449 u8 pad0; 450 u8 pad1; 451 } __packed; 452 453 struct htt_rx_indication_prefix { 454 __le16 fw_rx_desc_bytes; 455 u8 pad0; 456 u8 pad1; 457 }; 458 459 struct htt_rx_indication { 460 struct htt_rx_indication_hdr hdr; 461 struct htt_rx_indication_ppdu ppdu; 462 struct htt_rx_indication_prefix prefix; 463 464 /* 465 * the following fields are both dynamically sized, so 466 * take care addressing them 467 */ 468 469 /* the size of this is %fw_rx_desc_bytes */ 470 struct fw_rx_desc_base fw_desc; 471 472 /* 473 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 474 * and has %num_mpdu_ranges elements. 475 */ 476 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 477 } __packed; 478 479 static inline struct htt_rx_indication_mpdu_range * 480 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 481 { 482 void *ptr = rx_ind; 483 484 ptr += sizeof(rx_ind->hdr) 485 + sizeof(rx_ind->ppdu) 486 + sizeof(rx_ind->prefix) 487 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 488 return ptr; 489 } 490 491 enum htt_rx_flush_mpdu_status { 492 HTT_RX_FLUSH_MPDU_DISCARD = 0, 493 HTT_RX_FLUSH_MPDU_REORDER = 1, 494 }; 495 496 /* 497 * htt_rx_flush - discard or reorder given range of mpdus 498 * 499 * Note: host must check if all sequence numbers between 500 * [seq_num_start, seq_num_end-1] are valid. 501 */ 502 struct htt_rx_flush { 503 __le16 peer_id; 504 u8 tid; 505 u8 rsvd0; 506 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 507 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 508 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 509 }; 510 511 struct htt_rx_peer_map { 512 u8 vdev_id; 513 __le16 peer_id; 514 u8 addr[6]; 515 u8 rsvd0; 516 u8 rsvd1; 517 } __packed; 518 519 struct htt_rx_peer_unmap { 520 u8 rsvd0; 521 __le16 peer_id; 522 } __packed; 523 524 enum htt_security_types { 525 HTT_SECURITY_NONE, 526 HTT_SECURITY_WEP128, 527 HTT_SECURITY_WEP104, 528 HTT_SECURITY_WEP40, 529 HTT_SECURITY_TKIP, 530 HTT_SECURITY_TKIP_NOMIC, 531 HTT_SECURITY_AES_CCMP, 532 HTT_SECURITY_WAPI, 533 534 HTT_NUM_SECURITY_TYPES /* keep this last! */ 535 }; 536 537 enum htt_security_flags { 538 #define HTT_SECURITY_TYPE_MASK 0x7F 539 #define HTT_SECURITY_TYPE_LSB 0 540 HTT_SECURITY_IS_UNICAST = 1 << 7 541 }; 542 543 struct htt_security_indication { 544 union { 545 /* dont use bitfields; undefined behaviour */ 546 u8 flags; /* %htt_security_flags */ 547 struct { 548 u8 security_type:7, /* %htt_security_types */ 549 is_unicast:1; 550 } __packed; 551 } __packed; 552 __le16 peer_id; 553 u8 michael_key[8]; 554 u8 wapi_rsc[16]; 555 } __packed; 556 557 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 558 #define HTT_RX_BA_INFO0_TID_LSB 0 559 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 560 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 561 562 struct htt_rx_addba { 563 u8 window_size; 564 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 565 } __packed; 566 567 struct htt_rx_delba { 568 u8 rsvd0; 569 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 570 } __packed; 571 572 enum htt_data_tx_status { 573 HTT_DATA_TX_STATUS_OK = 0, 574 HTT_DATA_TX_STATUS_DISCARD = 1, 575 HTT_DATA_TX_STATUS_NO_ACK = 2, 576 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 577 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 578 }; 579 580 enum htt_data_tx_flags { 581 #define HTT_DATA_TX_STATUS_MASK 0x07 582 #define HTT_DATA_TX_STATUS_LSB 0 583 #define HTT_DATA_TX_TID_MASK 0x78 584 #define HTT_DATA_TX_TID_LSB 3 585 HTT_DATA_TX_TID_INVALID = 1 << 7 586 }; 587 588 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 589 590 struct htt_data_tx_completion { 591 union { 592 u8 flags; 593 struct { 594 u8 status:3, 595 tid:4, 596 tid_invalid:1; 597 } __packed; 598 } __packed; 599 u8 num_msdus; 600 u8 rsvd0; 601 __le16 msdus[0]; /* variable length based on %num_msdus */ 602 } __packed; 603 604 struct htt_tx_compl_ind_base { 605 u32 hdr; 606 u16 payload[1/*or more*/]; 607 } __packed; 608 609 struct htt_rc_tx_done_params { 610 u32 rate_code; 611 u32 rate_code_flags; 612 u32 flags; 613 u32 num_enqued; /* 1 for non-AMPDU */ 614 u32 num_retries; 615 u32 num_failed; /* for AMPDU */ 616 u32 ack_rssi; 617 u32 time_stamp; 618 u32 is_probe; 619 }; 620 621 struct htt_rc_update { 622 u8 vdev_id; 623 __le16 peer_id; 624 u8 addr[6]; 625 u8 num_elems; 626 u8 rsvd0; 627 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 628 } __packed; 629 630 /* see htt_rx_indication for similar fields and descriptions */ 631 struct htt_rx_fragment_indication { 632 union { 633 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 634 struct { 635 u8 ext_tid:5, 636 flush_valid:1; 637 } __packed; 638 } __packed; 639 __le16 peer_id; 640 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 641 __le16 fw_rx_desc_bytes; 642 __le16 rsvd0; 643 644 u8 fw_msdu_rx_desc[0]; 645 } __packed; 646 647 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 648 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 649 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 650 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 651 652 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 653 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 654 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 655 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 656 657 /* 658 * target -> host test message definition 659 * 660 * The following field definitions describe the format of the test 661 * message sent from the target to the host. 662 * The message consists of a 4-octet header, followed by a variable 663 * number of 32-bit integer values, followed by a variable number 664 * of 8-bit character values. 665 * 666 * |31 16|15 8|7 0| 667 * |-----------------------------------------------------------| 668 * | num chars | num ints | msg type | 669 * |-----------------------------------------------------------| 670 * | int 0 | 671 * |-----------------------------------------------------------| 672 * | int 1 | 673 * |-----------------------------------------------------------| 674 * | ... | 675 * |-----------------------------------------------------------| 676 * | char 3 | char 2 | char 1 | char 0 | 677 * |-----------------------------------------------------------| 678 * | | | ... | char 4 | 679 * |-----------------------------------------------------------| 680 * - MSG_TYPE 681 * Bits 7:0 682 * Purpose: identifies this as a test message 683 * Value: HTT_MSG_TYPE_TEST 684 * - NUM_INTS 685 * Bits 15:8 686 * Purpose: indicate how many 32-bit integers follow the message header 687 * - NUM_CHARS 688 * Bits 31:16 689 * Purpose: indicate how many 8-bit charaters follow the series of integers 690 */ 691 struct htt_rx_test { 692 u8 num_ints; 693 __le16 num_chars; 694 695 /* payload consists of 2 lists: 696 * a) num_ints * sizeof(__le32) 697 * b) num_chars * sizeof(u8) aligned to 4bytes */ 698 u8 payload[0]; 699 } __packed; 700 701 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 702 { 703 return (__le32 *)rx_test->payload; 704 } 705 706 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 707 { 708 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 709 } 710 711 /* 712 * target -> host packet log message 713 * 714 * The following field definitions describe the format of the packet log 715 * message sent from the target to the host. 716 * The message consists of a 4-octet header,followed by a variable number 717 * of 32-bit character values. 718 * 719 * |31 24|23 16|15 8|7 0| 720 * |-----------------------------------------------------------| 721 * | | | | msg type | 722 * |-----------------------------------------------------------| 723 * | payload | 724 * |-----------------------------------------------------------| 725 * - MSG_TYPE 726 * Bits 7:0 727 * Purpose: identifies this as a test message 728 * Value: HTT_MSG_TYPE_PACKETLOG 729 */ 730 struct htt_pktlog_msg { 731 u8 pad[3]; 732 __le32 payload[1 /* or more */]; 733 } __packed; 734 735 struct htt_dbg_stats_rx_reorder_stats { 736 /* Non QoS MPDUs received */ 737 __le32 deliver_non_qos; 738 739 /* MPDUs received in-order */ 740 __le32 deliver_in_order; 741 742 /* Flush due to reorder timer expired */ 743 __le32 deliver_flush_timeout; 744 745 /* Flush due to move out of window */ 746 __le32 deliver_flush_oow; 747 748 /* Flush due to DELBA */ 749 __le32 deliver_flush_delba; 750 751 /* MPDUs dropped due to FCS error */ 752 __le32 fcs_error; 753 754 /* MPDUs dropped due to monitor mode non-data packet */ 755 __le32 mgmt_ctrl; 756 757 /* MPDUs dropped due to invalid peer */ 758 __le32 invalid_peer; 759 760 /* MPDUs dropped due to duplication (non aggregation) */ 761 __le32 dup_non_aggr; 762 763 /* MPDUs dropped due to processed before */ 764 __le32 dup_past; 765 766 /* MPDUs dropped due to duplicate in reorder queue */ 767 __le32 dup_in_reorder; 768 769 /* Reorder timeout happened */ 770 __le32 reorder_timeout; 771 772 /* invalid bar ssn */ 773 __le32 invalid_bar_ssn; 774 775 /* reorder reset due to bar ssn */ 776 __le32 ssn_reset; 777 }; 778 779 struct htt_dbg_stats_wal_tx_stats { 780 /* Num HTT cookies queued to dispatch list */ 781 __le32 comp_queued; 782 783 /* Num HTT cookies dispatched */ 784 __le32 comp_delivered; 785 786 /* Num MSDU queued to WAL */ 787 __le32 msdu_enqued; 788 789 /* Num MPDU queue to WAL */ 790 __le32 mpdu_enqued; 791 792 /* Num MSDUs dropped by WMM limit */ 793 __le32 wmm_drop; 794 795 /* Num Local frames queued */ 796 __le32 local_enqued; 797 798 /* Num Local frames done */ 799 __le32 local_freed; 800 801 /* Num queued to HW */ 802 __le32 hw_queued; 803 804 /* Num PPDU reaped from HW */ 805 __le32 hw_reaped; 806 807 /* Num underruns */ 808 __le32 underrun; 809 810 /* Num PPDUs cleaned up in TX abort */ 811 __le32 tx_abort; 812 813 /* Num MPDUs requed by SW */ 814 __le32 mpdus_requed; 815 816 /* excessive retries */ 817 __le32 tx_ko; 818 819 /* data hw rate code */ 820 __le32 data_rc; 821 822 /* Scheduler self triggers */ 823 __le32 self_triggers; 824 825 /* frames dropped due to excessive sw retries */ 826 __le32 sw_retry_failure; 827 828 /* illegal rate phy errors */ 829 __le32 illgl_rate_phy_err; 830 831 /* wal pdev continous xretry */ 832 __le32 pdev_cont_xretry; 833 834 /* wal pdev continous xretry */ 835 __le32 pdev_tx_timeout; 836 837 /* wal pdev resets */ 838 __le32 pdev_resets; 839 840 __le32 phy_underrun; 841 842 /* MPDU is more than txop limit */ 843 __le32 txop_ovf; 844 } __packed; 845 846 struct htt_dbg_stats_wal_rx_stats { 847 /* Cnts any change in ring routing mid-ppdu */ 848 __le32 mid_ppdu_route_change; 849 850 /* Total number of statuses processed */ 851 __le32 status_rcvd; 852 853 /* Extra frags on rings 0-3 */ 854 __le32 r0_frags; 855 __le32 r1_frags; 856 __le32 r2_frags; 857 __le32 r3_frags; 858 859 /* MSDUs / MPDUs delivered to HTT */ 860 __le32 htt_msdus; 861 __le32 htt_mpdus; 862 863 /* MSDUs / MPDUs delivered to local stack */ 864 __le32 loc_msdus; 865 __le32 loc_mpdus; 866 867 /* AMSDUs that have more MSDUs than the status ring size */ 868 __le32 oversize_amsdu; 869 870 /* Number of PHY errors */ 871 __le32 phy_errs; 872 873 /* Number of PHY errors drops */ 874 __le32 phy_err_drop; 875 876 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 877 __le32 mpdu_errs; 878 } __packed; 879 880 struct htt_dbg_stats_wal_peer_stats { 881 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 882 } __packed; 883 884 struct htt_dbg_stats_wal_pdev_txrx { 885 struct htt_dbg_stats_wal_tx_stats tx_stats; 886 struct htt_dbg_stats_wal_rx_stats rx_stats; 887 struct htt_dbg_stats_wal_peer_stats peer_stats; 888 } __packed; 889 890 struct htt_dbg_stats_rx_rate_info { 891 __le32 mcs[10]; 892 __le32 sgi[10]; 893 __le32 nss[4]; 894 __le32 stbc[10]; 895 __le32 bw[3]; 896 __le32 pream[6]; 897 __le32 ldpc; 898 __le32 txbf; 899 }; 900 901 /* 902 * htt_dbg_stats_status - 903 * present - The requested stats have been delivered in full. 904 * This indicates that either the stats information was contained 905 * in its entirety within this message, or else this message 906 * completes the delivery of the requested stats info that was 907 * partially delivered through earlier STATS_CONF messages. 908 * partial - The requested stats have been delivered in part. 909 * One or more subsequent STATS_CONF messages with the same 910 * cookie value will be sent to deliver the remainder of the 911 * information. 912 * error - The requested stats could not be delivered, for example due 913 * to a shortage of memory to construct a message holding the 914 * requested stats. 915 * invalid - The requested stat type is either not recognized, or the 916 * target is configured to not gather the stats type in question. 917 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 918 * series_done - This special value indicates that no further stats info 919 * elements are present within a series of stats info elems 920 * (within a stats upload confirmation message). 921 */ 922 enum htt_dbg_stats_status { 923 HTT_DBG_STATS_STATUS_PRESENT = 0, 924 HTT_DBG_STATS_STATUS_PARTIAL = 1, 925 HTT_DBG_STATS_STATUS_ERROR = 2, 926 HTT_DBG_STATS_STATUS_INVALID = 3, 927 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 928 }; 929 930 /* 931 * target -> host statistics upload 932 * 933 * The following field definitions describe the format of the HTT target 934 * to host stats upload confirmation message. 935 * The message contains a cookie echoed from the HTT host->target stats 936 * upload request, which identifies which request the confirmation is 937 * for, and a series of tag-length-value stats information elements. 938 * The tag-length header for each stats info element also includes a 939 * status field, to indicate whether the request for the stat type in 940 * question was fully met, partially met, unable to be met, or invalid 941 * (if the stat type in question is disabled in the target). 942 * A special value of all 1's in this status field is used to indicate 943 * the end of the series of stats info elements. 944 * 945 * 946 * |31 16|15 8|7 5|4 0| 947 * |------------------------------------------------------------| 948 * | reserved | msg type | 949 * |------------------------------------------------------------| 950 * | cookie LSBs | 951 * |------------------------------------------------------------| 952 * | cookie MSBs | 953 * |------------------------------------------------------------| 954 * | stats entry length | reserved | S |stat type| 955 * |------------------------------------------------------------| 956 * | | 957 * | type-specific stats info | 958 * | | 959 * |------------------------------------------------------------| 960 * | stats entry length | reserved | S |stat type| 961 * |------------------------------------------------------------| 962 * | | 963 * | type-specific stats info | 964 * | | 965 * |------------------------------------------------------------| 966 * | n/a | reserved | 111 | n/a | 967 * |------------------------------------------------------------| 968 * Header fields: 969 * - MSG_TYPE 970 * Bits 7:0 971 * Purpose: identifies this is a statistics upload confirmation message 972 * Value: 0x9 973 * - COOKIE_LSBS 974 * Bits 31:0 975 * Purpose: Provide a mechanism to match a target->host stats confirmation 976 * message with its preceding host->target stats request message. 977 * Value: LSBs of the opaque cookie specified by the host-side requestor 978 * - COOKIE_MSBS 979 * Bits 31:0 980 * Purpose: Provide a mechanism to match a target->host stats confirmation 981 * message with its preceding host->target stats request message. 982 * Value: MSBs of the opaque cookie specified by the host-side requestor 983 * 984 * Stats Information Element tag-length header fields: 985 * - STAT_TYPE 986 * Bits 4:0 987 * Purpose: identifies the type of statistics info held in the 988 * following information element 989 * Value: htt_dbg_stats_type 990 * - STATUS 991 * Bits 7:5 992 * Purpose: indicate whether the requested stats are present 993 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 994 * the completion of the stats entry series 995 * - LENGTH 996 * Bits 31:16 997 * Purpose: indicate the stats information size 998 * Value: This field specifies the number of bytes of stats information 999 * that follows the element tag-length header. 1000 * It is expected but not required that this length is a multiple of 1001 * 4 bytes. Even if the length is not an integer multiple of 4, the 1002 * subsequent stats entry header will begin on a 4-byte aligned 1003 * boundary. 1004 */ 1005 1006 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1007 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1008 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1009 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1010 1011 struct htt_stats_conf_item { 1012 union { 1013 u8 info; 1014 struct { 1015 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1016 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1017 } __packed; 1018 } __packed; 1019 u8 pad; 1020 __le16 length; 1021 u8 payload[0]; /* roundup(length, 4) long */ 1022 } __packed; 1023 1024 struct htt_stats_conf { 1025 u8 pad[3]; 1026 __le32 cookie_lsb; 1027 __le32 cookie_msb; 1028 1029 /* each item has variable length! */ 1030 struct htt_stats_conf_item items[0]; 1031 } __packed; 1032 1033 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1034 const struct htt_stats_conf_item *item) 1035 { 1036 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1037 } 1038 /* 1039 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1040 * 1041 * The following field definitions describe the format of the HTT host 1042 * to target frag_desc/msdu_ext bank configuration message. 1043 * The message contains the based address and the min and max id of the 1044 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1045 * MSDU_EXT/FRAG_DESC. 1046 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1047 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1048 * the hardware does the mapping/translation. 1049 * 1050 * Total banks that can be configured is configured to 16. 1051 * 1052 * This should be called before any TX has be initiated by the HTT 1053 * 1054 * |31 16|15 8|7 5|4 0| 1055 * |------------------------------------------------------------| 1056 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1057 * |------------------------------------------------------------| 1058 * | BANK0_BASE_ADDRESS | 1059 * |------------------------------------------------------------| 1060 * | ... | 1061 * |------------------------------------------------------------| 1062 * | BANK15_BASE_ADDRESS | 1063 * |------------------------------------------------------------| 1064 * | BANK0_MAX_ID | BANK0_MIN_ID | 1065 * |------------------------------------------------------------| 1066 * | ... | 1067 * |------------------------------------------------------------| 1068 * | BANK15_MAX_ID | BANK15_MIN_ID | 1069 * |------------------------------------------------------------| 1070 * Header fields: 1071 * - MSG_TYPE 1072 * Bits 7:0 1073 * Value: 0x6 1074 * - BANKx_BASE_ADDRESS 1075 * Bits 31:0 1076 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1077 * bank physical/bus address. 1078 * - BANKx_MIN_ID 1079 * Bits 15:0 1080 * Purpose: Provide a mechanism to specify the min index that needs to 1081 * mapped. 1082 * - BANKx_MAX_ID 1083 * Bits 31:16 1084 * Purpose: Provide a mechanism to specify the max index that needs to 1085 * 1086 */ 1087 struct htt_frag_desc_bank_id { 1088 __le16 bank_min_id; 1089 __le16 bank_max_id; 1090 } __packed; 1091 1092 /* real is 16 but it wouldn't fit in the max htt message size 1093 * so we use a conservatively safe value for now */ 1094 #define HTT_FRAG_DESC_BANK_MAX 4 1095 1096 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1097 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1098 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP (1 << 2) 1099 1100 struct htt_frag_desc_bank_cfg { 1101 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1102 u8 num_banks; 1103 u8 desc_size; 1104 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1105 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1106 } __packed; 1107 1108 union htt_rx_pn_t { 1109 /* WEP: 24-bit PN */ 1110 u32 pn24; 1111 1112 /* TKIP or CCMP: 48-bit PN */ 1113 u_int64_t pn48; 1114 1115 /* WAPI: 128-bit PN */ 1116 u_int64_t pn128[2]; 1117 }; 1118 1119 struct htt_cmd { 1120 struct htt_cmd_hdr hdr; 1121 union { 1122 struct htt_ver_req ver_req; 1123 struct htt_mgmt_tx_desc mgmt_tx; 1124 struct htt_data_tx_desc data_tx; 1125 struct htt_rx_ring_setup rx_setup; 1126 struct htt_stats_req stats_req; 1127 struct htt_oob_sync_req oob_sync_req; 1128 struct htt_aggr_conf aggr_conf; 1129 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg; 1130 }; 1131 } __packed; 1132 1133 struct htt_resp { 1134 struct htt_resp_hdr hdr; 1135 union { 1136 struct htt_ver_resp ver_resp; 1137 struct htt_mgmt_tx_completion mgmt_tx_completion; 1138 struct htt_data_tx_completion data_tx_completion; 1139 struct htt_rx_indication rx_ind; 1140 struct htt_rx_fragment_indication rx_frag_ind; 1141 struct htt_rx_peer_map peer_map; 1142 struct htt_rx_peer_unmap peer_unmap; 1143 struct htt_rx_flush rx_flush; 1144 struct htt_rx_addba rx_addba; 1145 struct htt_rx_delba rx_delba; 1146 struct htt_security_indication security_indication; 1147 struct htt_rc_update rc_update; 1148 struct htt_rx_test rx_test; 1149 struct htt_pktlog_msg pktlog_msg; 1150 struct htt_stats_conf stats_conf; 1151 }; 1152 } __packed; 1153 1154 1155 /*** host side structures follow ***/ 1156 1157 struct htt_tx_done { 1158 u32 msdu_id; 1159 bool discard; 1160 bool no_ack; 1161 }; 1162 1163 struct htt_peer_map_event { 1164 u8 vdev_id; 1165 u16 peer_id; 1166 u8 addr[ETH_ALEN]; 1167 }; 1168 1169 struct htt_peer_unmap_event { 1170 u16 peer_id; 1171 }; 1172 1173 struct htt_rx_info { 1174 struct sk_buff *skb; 1175 enum htt_rx_mpdu_status status; 1176 enum htt_rx_mpdu_encrypt_type encrypt_type; 1177 s8 signal; 1178 struct { 1179 u8 info0; 1180 u32 info1; 1181 u32 info2; 1182 } rate; 1183 bool fcs_err; 1184 }; 1185 1186 struct ath10k_htt { 1187 struct ath10k *ar; 1188 enum ath10k_htc_ep_id eid; 1189 1190 int max_throughput_mbps; 1191 u8 target_version_major; 1192 u8 target_version_minor; 1193 struct completion target_version_received; 1194 1195 struct { 1196 /* 1197 * Ring of network buffer objects - This ring is 1198 * used exclusively by the host SW. This ring 1199 * mirrors the dev_addrs_ring that is shared 1200 * between the host SW and the MAC HW. The host SW 1201 * uses this netbufs ring to locate the network 1202 * buffer objects whose data buffers the HW has 1203 * filled. 1204 */ 1205 struct sk_buff **netbufs_ring; 1206 /* 1207 * Ring of buffer addresses - 1208 * This ring holds the "physical" device address of the 1209 * rx buffers the host SW provides for the MAC HW to 1210 * fill. 1211 */ 1212 __le32 *paddrs_ring; 1213 1214 /* 1215 * Base address of ring, as a "physical" device address 1216 * rather than a CPU address. 1217 */ 1218 dma_addr_t base_paddr; 1219 1220 /* how many elems in the ring (power of 2) */ 1221 int size; 1222 1223 /* size - 1 */ 1224 unsigned size_mask; 1225 1226 /* how many rx buffers to keep in the ring */ 1227 int fill_level; 1228 1229 /* how many rx buffers (full+empty) are in the ring */ 1230 int fill_cnt; 1231 1232 /* 1233 * alloc_idx - where HTT SW has deposited empty buffers 1234 * This is allocated in consistent mem, so that the FW can 1235 * read this variable, and program the HW's FW_IDX reg with 1236 * the value of this shadow register. 1237 */ 1238 struct { 1239 __le32 *vaddr; 1240 dma_addr_t paddr; 1241 } alloc_idx; 1242 1243 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1244 struct { 1245 unsigned msdu_payld; 1246 } sw_rd_idx; 1247 1248 /* 1249 * refill_retry_timer - timer triggered when the ring is 1250 * not refilled to the level expected 1251 */ 1252 struct timer_list refill_retry_timer; 1253 1254 /* Protects access to all rx ring buffer state variables */ 1255 spinlock_t lock; 1256 } rx_ring; 1257 1258 unsigned int prefetch_len; 1259 1260 /* Protects access to %pending_tx, %used_msdu_ids */ 1261 spinlock_t tx_lock; 1262 int max_num_pending_tx; 1263 int num_pending_tx; 1264 struct sk_buff **pending_tx; 1265 unsigned long *used_msdu_ids; /* bitmap */ 1266 wait_queue_head_t empty_tx_wq; 1267 1268 /* set if host-fw communication goes haywire 1269 * used to avoid further failures */ 1270 bool rx_confused; 1271 }; 1272 1273 #define RX_HTT_HDR_STATUS_LEN 64 1274 1275 /* This structure layout is programmed via rx ring setup 1276 * so that FW knows how to transfer the rx descriptor to the host. 1277 * Buffers like this are placed on the rx ring. */ 1278 struct htt_rx_desc { 1279 union { 1280 /* This field is filled on the host using the msdu buffer 1281 * from htt_rx_indication */ 1282 struct fw_rx_desc_base fw_desc; 1283 u32 pad; 1284 } __packed; 1285 struct { 1286 struct rx_attention attention; 1287 struct rx_frag_info frag_info; 1288 struct rx_mpdu_start mpdu_start; 1289 struct rx_msdu_start msdu_start; 1290 struct rx_msdu_end msdu_end; 1291 struct rx_mpdu_end mpdu_end; 1292 struct rx_ppdu_start ppdu_start; 1293 struct rx_ppdu_end ppdu_end; 1294 } __packed; 1295 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1296 u8 msdu_payload[0]; 1297 }; 1298 1299 #define HTT_RX_DESC_ALIGN 8 1300 1301 #define HTT_MAC_ADDR_LEN 6 1302 1303 /* 1304 * FIX THIS 1305 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 1306 * rounded up to a cache line size. 1307 */ 1308 #define HTT_RX_BUF_SIZE 1920 1309 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 1310 1311 /* 1312 * DMA_MAP expects the buffer to be an integral number of cache lines. 1313 * Rather than checking the actual cache line size, this code makes a 1314 * conservative estimate of what the cache line size could be. 1315 */ 1316 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 1317 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 1318 1319 int ath10k_htt_attach(struct ath10k *ar); 1320 int ath10k_htt_attach_target(struct ath10k_htt *htt); 1321 void ath10k_htt_detach(struct ath10k_htt *htt); 1322 1323 int ath10k_htt_tx_attach(struct ath10k_htt *htt); 1324 void ath10k_htt_tx_detach(struct ath10k_htt *htt); 1325 int ath10k_htt_rx_attach(struct ath10k_htt *htt); 1326 void ath10k_htt_rx_detach(struct ath10k_htt *htt); 1327 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1328 void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1329 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 1330 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt); 1331 1332 void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 1333 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt); 1334 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 1335 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *); 1336 int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *); 1337 #endif 1338