1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HTT_H_ 19 #define _HTT_H_ 20 21 #include <linux/bug.h> 22 #include <linux/interrupt.h> 23 #include <linux/dmapool.h> 24 #include <linux/hashtable.h> 25 #include <net/mac80211.h> 26 27 #include "htc.h" 28 #include "hw.h" 29 #include "rx_desc.h" 30 #include "hw.h" 31 32 enum htt_dbg_stats_type { 33 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 34 HTT_DBG_STATS_RX_REORDER = 1 << 1, 35 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 36 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 37 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 38 /* bits 5-23 currently reserved */ 39 40 HTT_DBG_NUM_STATS /* keep this last */ 41 }; 42 43 enum htt_h2t_msg_type { /* host-to-target */ 44 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 45 HTT_H2T_MSG_TYPE_TX_FRM = 1, 46 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 47 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 48 HTT_H2T_MSG_TYPE_SYNC = 4, 49 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 50 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 51 52 /* This command is used for sending management frames in HTT < 3.0. 53 * HTT >= 3.0 uses TX_FRM for everything. */ 54 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 55 56 HTT_H2T_NUM_MSGS /* keep this last */ 57 }; 58 59 struct htt_cmd_hdr { 60 u8 msg_type; 61 } __packed; 62 63 struct htt_ver_req { 64 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 65 } __packed; 66 67 /* 68 * HTT tx MSDU descriptor 69 * 70 * The HTT tx MSDU descriptor is created by the host HTT SW for each 71 * tx MSDU. The HTT tx MSDU descriptor contains the information that 72 * the target firmware needs for the FW's tx processing, particularly 73 * for creating the HW msdu descriptor. 74 * The same HTT tx descriptor is used for HL and LL systems, though 75 * a few fields within the tx descriptor are used only by LL or 76 * only by HL. 77 * The HTT tx descriptor is defined in two manners: by a struct with 78 * bitfields, and by a series of [dword offset, bit mask, bit shift] 79 * definitions. 80 * The target should use the struct def, for simplicitly and clarity, 81 * but the host shall use the bit-mast + bit-shift defs, to be endian- 82 * neutral. Specifically, the host shall use the get/set macros built 83 * around the mask + shift defs. 84 */ 85 struct htt_data_tx_desc_frag { 86 __le32 paddr; 87 __le32 len; 88 } __packed; 89 90 enum htt_data_tx_desc_flags0 { 91 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 92 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 93 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 94 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 95 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 96 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 97 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 98 }; 99 100 enum htt_data_tx_desc_flags1 { 101 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 102 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 103 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 104 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 105 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 106 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 107 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 108 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 109 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 110 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 111 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 112 }; 113 114 enum htt_data_tx_ext_tid { 115 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 116 HTT_DATA_TX_EXT_TID_MGMT = 17, 117 HTT_DATA_TX_EXT_TID_INVALID = 31 118 }; 119 120 #define HTT_INVALID_PEERID 0xFFFF 121 122 /* 123 * htt_data_tx_desc - used for data tx path 124 * 125 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 126 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 127 * for special kinds of tids 128 * postponed: only for HL hosts. indicates if this is a resend 129 * (HL hosts manage queues on the host ) 130 * more_in_batch: only for HL hosts. indicates if more packets are 131 * pending. this allows target to wait and aggregate 132 * freq: 0 means home channel of given vdev. intended for offchannel 133 */ 134 struct htt_data_tx_desc { 135 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 136 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 137 __le16 len; 138 __le16 id; 139 __le32 frags_paddr; 140 __le16 peerid; 141 __le16 freq; 142 u8 prefetch[0]; /* start of frame, for FW classification engine */ 143 } __packed; 144 145 enum htt_rx_ring_flags { 146 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 147 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 148 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 149 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 150 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 151 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 152 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 153 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 154 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 155 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 156 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 157 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 158 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 159 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 160 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 161 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 162 }; 163 164 #define HTT_RX_RING_SIZE_MIN 128 165 #define HTT_RX_RING_SIZE_MAX 2048 166 167 struct htt_rx_ring_setup_ring { 168 __le32 fw_idx_shadow_reg_paddr; 169 __le32 rx_ring_base_paddr; 170 __le16 rx_ring_len; /* in 4-byte words */ 171 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 172 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 173 __le16 fw_idx_init_val; 174 175 /* the following offsets are in 4-byte units */ 176 __le16 mac80211_hdr_offset; 177 __le16 msdu_payload_offset; 178 __le16 ppdu_start_offset; 179 __le16 ppdu_end_offset; 180 __le16 mpdu_start_offset; 181 __le16 mpdu_end_offset; 182 __le16 msdu_start_offset; 183 __le16 msdu_end_offset; 184 __le16 rx_attention_offset; 185 __le16 frag_info_offset; 186 } __packed; 187 188 struct htt_rx_ring_setup_hdr { 189 u8 num_rings; /* supported values: 1, 2 */ 190 __le16 rsvd0; 191 } __packed; 192 193 struct htt_rx_ring_setup { 194 struct htt_rx_ring_setup_hdr hdr; 195 struct htt_rx_ring_setup_ring rings[0]; 196 } __packed; 197 198 /* 199 * htt_stats_req - request target to send specified statistics 200 * 201 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 202 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 203 * so make sure its little-endian. 204 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 205 * so make sure its little-endian. 206 * @cfg_val: stat_type specific configuration 207 * @stat_type: see %htt_dbg_stats_type 208 * @cookie_lsb: used for confirmation message from target->host 209 * @cookie_msb: ditto as %cookie 210 */ 211 struct htt_stats_req { 212 u8 upload_types[3]; 213 u8 rsvd0; 214 u8 reset_types[3]; 215 struct { 216 u8 mpdu_bytes; 217 u8 mpdu_num_msdus; 218 u8 msdu_bytes; 219 } __packed; 220 u8 stat_type; 221 __le32 cookie_lsb; 222 __le32 cookie_msb; 223 } __packed; 224 225 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 226 227 /* 228 * htt_oob_sync_req - request out-of-band sync 229 * 230 * The HTT SYNC tells the target to suspend processing of subsequent 231 * HTT host-to-target messages until some other target agent locally 232 * informs the target HTT FW that the current sync counter is equal to 233 * or greater than (in a modulo sense) the sync counter specified in 234 * the SYNC message. 235 * 236 * This allows other host-target components to synchronize their operation 237 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 238 * security key has been downloaded to and activated by the target. 239 * In the absence of any explicit synchronization counter value 240 * specification, the target HTT FW will use zero as the default current 241 * sync value. 242 * 243 * The HTT target FW will suspend its host->target message processing as long 244 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 245 */ 246 struct htt_oob_sync_req { 247 u8 sync_count; 248 __le16 rsvd0; 249 } __packed; 250 251 struct htt_aggr_conf { 252 u8 max_num_ampdu_subframes; 253 /* amsdu_subframes is limited by 0x1F mask */ 254 u8 max_num_amsdu_subframes; 255 } __packed; 256 257 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 258 259 struct htt_mgmt_tx_desc { 260 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 261 __le32 msdu_paddr; 262 __le32 desc_id; 263 __le32 len; 264 __le32 vdev_id; 265 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 266 } __packed; 267 268 enum htt_mgmt_tx_status { 269 HTT_MGMT_TX_STATUS_OK = 0, 270 HTT_MGMT_TX_STATUS_RETRY = 1, 271 HTT_MGMT_TX_STATUS_DROP = 2 272 }; 273 274 /*=== target -> host messages ===============================================*/ 275 276 enum htt_main_t2h_msg_type { 277 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0, 278 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1, 279 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2, 280 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3, 281 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 282 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5, 283 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6, 284 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 285 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8, 286 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9, 287 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 288 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb, 289 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 290 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 291 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 292 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10, 293 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 294 HTT_MAIN_T2H_MSG_TYPE_TEST, 295 /* keep this last */ 296 HTT_MAIN_T2H_NUM_MSGS 297 }; 298 299 enum htt_10x_t2h_msg_type { 300 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0, 301 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1, 302 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2, 303 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3, 304 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 305 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5, 306 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6, 307 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 308 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8, 309 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9, 310 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 311 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb, 312 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 313 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 314 HTT_10X_T2H_MSG_TYPE_TEST = 0xe, 315 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 316 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11, 317 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12, 318 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13, 319 /* keep this last */ 320 HTT_10X_T2H_NUM_MSGS 321 }; 322 323 enum htt_tlv_t2h_msg_type { 324 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0, 325 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1, 326 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2, 327 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3, 328 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 329 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5, 330 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6, 331 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 332 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8, 333 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9, 334 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 335 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb, 336 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */ 337 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 338 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 339 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 340 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10, 341 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 342 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 343 /* 0x13 reservd */ 344 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 345 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 346 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 347 HTT_TLV_T2H_MSG_TYPE_TEST, 348 /* keep this last */ 349 HTT_TLV_T2H_NUM_MSGS 350 }; 351 352 enum htt_t2h_msg_type { 353 HTT_T2H_MSG_TYPE_VERSION_CONF, 354 HTT_T2H_MSG_TYPE_RX_IND, 355 HTT_T2H_MSG_TYPE_RX_FLUSH, 356 HTT_T2H_MSG_TYPE_PEER_MAP, 357 HTT_T2H_MSG_TYPE_PEER_UNMAP, 358 HTT_T2H_MSG_TYPE_RX_ADDBA, 359 HTT_T2H_MSG_TYPE_RX_DELBA, 360 HTT_T2H_MSG_TYPE_TX_COMPL_IND, 361 HTT_T2H_MSG_TYPE_PKTLOG, 362 HTT_T2H_MSG_TYPE_STATS_CONF, 363 HTT_T2H_MSG_TYPE_RX_FRAG_IND, 364 HTT_T2H_MSG_TYPE_SEC_IND, 365 HTT_T2H_MSG_TYPE_RC_UPDATE_IND, 366 HTT_T2H_MSG_TYPE_TX_INSPECT_IND, 367 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION, 368 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, 369 HTT_T2H_MSG_TYPE_RX_PN_IND, 370 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND, 371 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND, 372 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE, 373 HTT_T2H_MSG_TYPE_CHAN_CHANGE, 374 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR, 375 HTT_T2H_MSG_TYPE_AGGR_CONF, 376 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, 377 HTT_T2H_MSG_TYPE_TEST, 378 /* keep this last */ 379 HTT_T2H_NUM_MSGS 380 }; 381 382 /* 383 * htt_resp_hdr - header for target-to-host messages 384 * 385 * msg_type: see htt_t2h_msg_type 386 */ 387 struct htt_resp_hdr { 388 u8 msg_type; 389 } __packed; 390 391 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 392 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 393 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 394 395 /* htt_ver_resp - response sent for htt_ver_req */ 396 struct htt_ver_resp { 397 u8 minor; 398 u8 major; 399 u8 rsvd0; 400 } __packed; 401 402 struct htt_mgmt_tx_completion { 403 u8 rsvd0; 404 u8 rsvd1; 405 u8 rsvd2; 406 __le32 desc_id; 407 __le32 status; 408 } __packed; 409 410 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x3F) 411 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 412 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 6) 413 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 7) 414 415 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 416 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 417 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 418 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 419 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 420 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 421 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 422 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 423 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 424 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 425 426 struct htt_rx_indication_hdr { 427 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 428 __le16 peer_id; 429 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 430 } __packed; 431 432 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 433 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 434 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 435 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 436 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 437 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 438 439 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 440 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 441 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 442 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 443 444 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 445 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 446 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 447 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 448 449 enum htt_rx_legacy_rate { 450 HTT_RX_OFDM_48 = 0, 451 HTT_RX_OFDM_24 = 1, 452 HTT_RX_OFDM_12, 453 HTT_RX_OFDM_6, 454 HTT_RX_OFDM_54, 455 HTT_RX_OFDM_36, 456 HTT_RX_OFDM_18, 457 HTT_RX_OFDM_9, 458 459 /* long preamble */ 460 HTT_RX_CCK_11_LP = 0, 461 HTT_RX_CCK_5_5_LP = 1, 462 HTT_RX_CCK_2_LP, 463 HTT_RX_CCK_1_LP, 464 /* short preamble */ 465 HTT_RX_CCK_11_SP, 466 HTT_RX_CCK_5_5_SP, 467 HTT_RX_CCK_2_SP 468 }; 469 470 enum htt_rx_legacy_rate_type { 471 HTT_RX_LEGACY_RATE_OFDM = 0, 472 HTT_RX_LEGACY_RATE_CCK 473 }; 474 475 enum htt_rx_preamble_type { 476 HTT_RX_LEGACY = 0x4, 477 HTT_RX_HT = 0x8, 478 HTT_RX_HT_WITH_TXBF = 0x9, 479 HTT_RX_VHT = 0xC, 480 HTT_RX_VHT_WITH_TXBF = 0xD, 481 }; 482 483 /* 484 * Fields: phy_err_valid, phy_err_code, tsf, 485 * usec_timestamp, sub_usec_timestamp 486 * ..are valid only if end_valid == 1. 487 * 488 * Fields: rssi_chains, legacy_rate_type, 489 * legacy_rate_cck, preamble_type, service, 490 * vht_sig_* 491 * ..are valid only if start_valid == 1; 492 */ 493 struct htt_rx_indication_ppdu { 494 u8 combined_rssi; 495 u8 sub_usec_timestamp; 496 u8 phy_err_code; 497 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 498 struct { 499 u8 pri20_db; 500 u8 ext20_db; 501 u8 ext40_db; 502 u8 ext80_db; 503 } __packed rssi_chains[4]; 504 __le32 tsf; 505 __le32 usec_timestamp; 506 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 507 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 508 } __packed; 509 510 enum htt_rx_mpdu_status { 511 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 512 HTT_RX_IND_MPDU_STATUS_OK, 513 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 514 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 515 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 516 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 517 /* only accept EAPOL frames */ 518 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 519 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 520 /* Non-data in promiscous mode */ 521 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 522 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 523 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 524 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 525 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 526 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 527 528 /* 529 * MISC: discard for unspecified reasons. 530 * Leave this enum value last. 531 */ 532 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 533 }; 534 535 struct htt_rx_indication_mpdu_range { 536 u8 mpdu_count; 537 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 538 u8 pad0; 539 u8 pad1; 540 } __packed; 541 542 struct htt_rx_indication_prefix { 543 __le16 fw_rx_desc_bytes; 544 u8 pad0; 545 u8 pad1; 546 }; 547 548 struct htt_rx_indication { 549 struct htt_rx_indication_hdr hdr; 550 struct htt_rx_indication_ppdu ppdu; 551 struct htt_rx_indication_prefix prefix; 552 553 /* 554 * the following fields are both dynamically sized, so 555 * take care addressing them 556 */ 557 558 /* the size of this is %fw_rx_desc_bytes */ 559 struct fw_rx_desc_base fw_desc; 560 561 /* 562 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 563 * and has %num_mpdu_ranges elements. 564 */ 565 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 566 } __packed; 567 568 static inline struct htt_rx_indication_mpdu_range * 569 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 570 { 571 void *ptr = rx_ind; 572 573 ptr += sizeof(rx_ind->hdr) 574 + sizeof(rx_ind->ppdu) 575 + sizeof(rx_ind->prefix) 576 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 577 return ptr; 578 } 579 580 enum htt_rx_flush_mpdu_status { 581 HTT_RX_FLUSH_MPDU_DISCARD = 0, 582 HTT_RX_FLUSH_MPDU_REORDER = 1, 583 }; 584 585 /* 586 * htt_rx_flush - discard or reorder given range of mpdus 587 * 588 * Note: host must check if all sequence numbers between 589 * [seq_num_start, seq_num_end-1] are valid. 590 */ 591 struct htt_rx_flush { 592 __le16 peer_id; 593 u8 tid; 594 u8 rsvd0; 595 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 596 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 597 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 598 }; 599 600 struct htt_rx_peer_map { 601 u8 vdev_id; 602 __le16 peer_id; 603 u8 addr[6]; 604 u8 rsvd0; 605 u8 rsvd1; 606 } __packed; 607 608 struct htt_rx_peer_unmap { 609 u8 rsvd0; 610 __le16 peer_id; 611 } __packed; 612 613 enum htt_security_types { 614 HTT_SECURITY_NONE, 615 HTT_SECURITY_WEP128, 616 HTT_SECURITY_WEP104, 617 HTT_SECURITY_WEP40, 618 HTT_SECURITY_TKIP, 619 HTT_SECURITY_TKIP_NOMIC, 620 HTT_SECURITY_AES_CCMP, 621 HTT_SECURITY_WAPI, 622 623 HTT_NUM_SECURITY_TYPES /* keep this last! */ 624 }; 625 626 enum htt_security_flags { 627 #define HTT_SECURITY_TYPE_MASK 0x7F 628 #define HTT_SECURITY_TYPE_LSB 0 629 HTT_SECURITY_IS_UNICAST = 1 << 7 630 }; 631 632 struct htt_security_indication { 633 union { 634 /* dont use bitfields; undefined behaviour */ 635 u8 flags; /* %htt_security_flags */ 636 struct { 637 u8 security_type:7, /* %htt_security_types */ 638 is_unicast:1; 639 } __packed; 640 } __packed; 641 __le16 peer_id; 642 u8 michael_key[8]; 643 u8 wapi_rsc[16]; 644 } __packed; 645 646 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 647 #define HTT_RX_BA_INFO0_TID_LSB 0 648 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 649 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 650 651 struct htt_rx_addba { 652 u8 window_size; 653 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 654 } __packed; 655 656 struct htt_rx_delba { 657 u8 rsvd0; 658 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 659 } __packed; 660 661 enum htt_data_tx_status { 662 HTT_DATA_TX_STATUS_OK = 0, 663 HTT_DATA_TX_STATUS_DISCARD = 1, 664 HTT_DATA_TX_STATUS_NO_ACK = 2, 665 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 666 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 667 }; 668 669 enum htt_data_tx_flags { 670 #define HTT_DATA_TX_STATUS_MASK 0x07 671 #define HTT_DATA_TX_STATUS_LSB 0 672 #define HTT_DATA_TX_TID_MASK 0x78 673 #define HTT_DATA_TX_TID_LSB 3 674 HTT_DATA_TX_TID_INVALID = 1 << 7 675 }; 676 677 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 678 679 struct htt_data_tx_completion { 680 union { 681 u8 flags; 682 struct { 683 u8 status:3, 684 tid:4, 685 tid_invalid:1; 686 } __packed; 687 } __packed; 688 u8 num_msdus; 689 u8 rsvd0; 690 __le16 msdus[0]; /* variable length based on %num_msdus */ 691 } __packed; 692 693 struct htt_tx_compl_ind_base { 694 u32 hdr; 695 u16 payload[1/*or more*/]; 696 } __packed; 697 698 struct htt_rc_tx_done_params { 699 u32 rate_code; 700 u32 rate_code_flags; 701 u32 flags; 702 u32 num_enqued; /* 1 for non-AMPDU */ 703 u32 num_retries; 704 u32 num_failed; /* for AMPDU */ 705 u32 ack_rssi; 706 u32 time_stamp; 707 u32 is_probe; 708 }; 709 710 struct htt_rc_update { 711 u8 vdev_id; 712 __le16 peer_id; 713 u8 addr[6]; 714 u8 num_elems; 715 u8 rsvd0; 716 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 717 } __packed; 718 719 /* see htt_rx_indication for similar fields and descriptions */ 720 struct htt_rx_fragment_indication { 721 union { 722 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 723 struct { 724 u8 ext_tid:5, 725 flush_valid:1; 726 } __packed; 727 } __packed; 728 __le16 peer_id; 729 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 730 __le16 fw_rx_desc_bytes; 731 __le16 rsvd0; 732 733 u8 fw_msdu_rx_desc[0]; 734 } __packed; 735 736 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 737 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 738 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 739 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 740 741 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 742 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 743 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 744 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 745 746 struct htt_rx_pn_ind { 747 __le16 peer_id; 748 u8 tid; 749 u8 seqno_start; 750 u8 seqno_end; 751 u8 pn_ie_count; 752 u8 reserved; 753 u8 pn_ies[0]; 754 } __packed; 755 756 struct htt_rx_offload_msdu { 757 __le16 msdu_len; 758 __le16 peer_id; 759 u8 vdev_id; 760 u8 tid; 761 u8 fw_desc; 762 u8 payload[0]; 763 } __packed; 764 765 struct htt_rx_offload_ind { 766 u8 reserved; 767 __le16 msdu_count; 768 } __packed; 769 770 struct htt_rx_in_ord_msdu_desc { 771 __le32 msdu_paddr; 772 __le16 msdu_len; 773 u8 fw_desc; 774 u8 reserved; 775 } __packed; 776 777 struct htt_rx_in_ord_ind { 778 u8 info; 779 __le16 peer_id; 780 u8 vdev_id; 781 u8 reserved; 782 __le16 msdu_count; 783 struct htt_rx_in_ord_msdu_desc msdu_descs[0]; 784 } __packed; 785 786 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f 787 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 788 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020 789 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 790 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040 791 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 792 793 /* 794 * target -> host test message definition 795 * 796 * The following field definitions describe the format of the test 797 * message sent from the target to the host. 798 * The message consists of a 4-octet header, followed by a variable 799 * number of 32-bit integer values, followed by a variable number 800 * of 8-bit character values. 801 * 802 * |31 16|15 8|7 0| 803 * |-----------------------------------------------------------| 804 * | num chars | num ints | msg type | 805 * |-----------------------------------------------------------| 806 * | int 0 | 807 * |-----------------------------------------------------------| 808 * | int 1 | 809 * |-----------------------------------------------------------| 810 * | ... | 811 * |-----------------------------------------------------------| 812 * | char 3 | char 2 | char 1 | char 0 | 813 * |-----------------------------------------------------------| 814 * | | | ... | char 4 | 815 * |-----------------------------------------------------------| 816 * - MSG_TYPE 817 * Bits 7:0 818 * Purpose: identifies this as a test message 819 * Value: HTT_MSG_TYPE_TEST 820 * - NUM_INTS 821 * Bits 15:8 822 * Purpose: indicate how many 32-bit integers follow the message header 823 * - NUM_CHARS 824 * Bits 31:16 825 * Purpose: indicate how many 8-bit charaters follow the series of integers 826 */ 827 struct htt_rx_test { 828 u8 num_ints; 829 __le16 num_chars; 830 831 /* payload consists of 2 lists: 832 * a) num_ints * sizeof(__le32) 833 * b) num_chars * sizeof(u8) aligned to 4bytes */ 834 u8 payload[0]; 835 } __packed; 836 837 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 838 { 839 return (__le32 *)rx_test->payload; 840 } 841 842 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 843 { 844 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 845 } 846 847 /* 848 * target -> host packet log message 849 * 850 * The following field definitions describe the format of the packet log 851 * message sent from the target to the host. 852 * The message consists of a 4-octet header,followed by a variable number 853 * of 32-bit character values. 854 * 855 * |31 24|23 16|15 8|7 0| 856 * |-----------------------------------------------------------| 857 * | | | | msg type | 858 * |-----------------------------------------------------------| 859 * | payload | 860 * |-----------------------------------------------------------| 861 * - MSG_TYPE 862 * Bits 7:0 863 * Purpose: identifies this as a test message 864 * Value: HTT_MSG_TYPE_PACKETLOG 865 */ 866 struct htt_pktlog_msg { 867 u8 pad[3]; 868 u8 payload[0]; 869 } __packed; 870 871 struct htt_dbg_stats_rx_reorder_stats { 872 /* Non QoS MPDUs received */ 873 __le32 deliver_non_qos; 874 875 /* MPDUs received in-order */ 876 __le32 deliver_in_order; 877 878 /* Flush due to reorder timer expired */ 879 __le32 deliver_flush_timeout; 880 881 /* Flush due to move out of window */ 882 __le32 deliver_flush_oow; 883 884 /* Flush due to DELBA */ 885 __le32 deliver_flush_delba; 886 887 /* MPDUs dropped due to FCS error */ 888 __le32 fcs_error; 889 890 /* MPDUs dropped due to monitor mode non-data packet */ 891 __le32 mgmt_ctrl; 892 893 /* MPDUs dropped due to invalid peer */ 894 __le32 invalid_peer; 895 896 /* MPDUs dropped due to duplication (non aggregation) */ 897 __le32 dup_non_aggr; 898 899 /* MPDUs dropped due to processed before */ 900 __le32 dup_past; 901 902 /* MPDUs dropped due to duplicate in reorder queue */ 903 __le32 dup_in_reorder; 904 905 /* Reorder timeout happened */ 906 __le32 reorder_timeout; 907 908 /* invalid bar ssn */ 909 __le32 invalid_bar_ssn; 910 911 /* reorder reset due to bar ssn */ 912 __le32 ssn_reset; 913 }; 914 915 struct htt_dbg_stats_wal_tx_stats { 916 /* Num HTT cookies queued to dispatch list */ 917 __le32 comp_queued; 918 919 /* Num HTT cookies dispatched */ 920 __le32 comp_delivered; 921 922 /* Num MSDU queued to WAL */ 923 __le32 msdu_enqued; 924 925 /* Num MPDU queue to WAL */ 926 __le32 mpdu_enqued; 927 928 /* Num MSDUs dropped by WMM limit */ 929 __le32 wmm_drop; 930 931 /* Num Local frames queued */ 932 __le32 local_enqued; 933 934 /* Num Local frames done */ 935 __le32 local_freed; 936 937 /* Num queued to HW */ 938 __le32 hw_queued; 939 940 /* Num PPDU reaped from HW */ 941 __le32 hw_reaped; 942 943 /* Num underruns */ 944 __le32 underrun; 945 946 /* Num PPDUs cleaned up in TX abort */ 947 __le32 tx_abort; 948 949 /* Num MPDUs requed by SW */ 950 __le32 mpdus_requed; 951 952 /* excessive retries */ 953 __le32 tx_ko; 954 955 /* data hw rate code */ 956 __le32 data_rc; 957 958 /* Scheduler self triggers */ 959 __le32 self_triggers; 960 961 /* frames dropped due to excessive sw retries */ 962 __le32 sw_retry_failure; 963 964 /* illegal rate phy errors */ 965 __le32 illgl_rate_phy_err; 966 967 /* wal pdev continous xretry */ 968 __le32 pdev_cont_xretry; 969 970 /* wal pdev continous xretry */ 971 __le32 pdev_tx_timeout; 972 973 /* wal pdev resets */ 974 __le32 pdev_resets; 975 976 __le32 phy_underrun; 977 978 /* MPDU is more than txop limit */ 979 __le32 txop_ovf; 980 } __packed; 981 982 struct htt_dbg_stats_wal_rx_stats { 983 /* Cnts any change in ring routing mid-ppdu */ 984 __le32 mid_ppdu_route_change; 985 986 /* Total number of statuses processed */ 987 __le32 status_rcvd; 988 989 /* Extra frags on rings 0-3 */ 990 __le32 r0_frags; 991 __le32 r1_frags; 992 __le32 r2_frags; 993 __le32 r3_frags; 994 995 /* MSDUs / MPDUs delivered to HTT */ 996 __le32 htt_msdus; 997 __le32 htt_mpdus; 998 999 /* MSDUs / MPDUs delivered to local stack */ 1000 __le32 loc_msdus; 1001 __le32 loc_mpdus; 1002 1003 /* AMSDUs that have more MSDUs than the status ring size */ 1004 __le32 oversize_amsdu; 1005 1006 /* Number of PHY errors */ 1007 __le32 phy_errs; 1008 1009 /* Number of PHY errors drops */ 1010 __le32 phy_err_drop; 1011 1012 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1013 __le32 mpdu_errs; 1014 } __packed; 1015 1016 struct htt_dbg_stats_wal_peer_stats { 1017 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 1018 } __packed; 1019 1020 struct htt_dbg_stats_wal_pdev_txrx { 1021 struct htt_dbg_stats_wal_tx_stats tx_stats; 1022 struct htt_dbg_stats_wal_rx_stats rx_stats; 1023 struct htt_dbg_stats_wal_peer_stats peer_stats; 1024 } __packed; 1025 1026 struct htt_dbg_stats_rx_rate_info { 1027 __le32 mcs[10]; 1028 __le32 sgi[10]; 1029 __le32 nss[4]; 1030 __le32 stbc[10]; 1031 __le32 bw[3]; 1032 __le32 pream[6]; 1033 __le32 ldpc; 1034 __le32 txbf; 1035 }; 1036 1037 /* 1038 * htt_dbg_stats_status - 1039 * present - The requested stats have been delivered in full. 1040 * This indicates that either the stats information was contained 1041 * in its entirety within this message, or else this message 1042 * completes the delivery of the requested stats info that was 1043 * partially delivered through earlier STATS_CONF messages. 1044 * partial - The requested stats have been delivered in part. 1045 * One or more subsequent STATS_CONF messages with the same 1046 * cookie value will be sent to deliver the remainder of the 1047 * information. 1048 * error - The requested stats could not be delivered, for example due 1049 * to a shortage of memory to construct a message holding the 1050 * requested stats. 1051 * invalid - The requested stat type is either not recognized, or the 1052 * target is configured to not gather the stats type in question. 1053 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1054 * series_done - This special value indicates that no further stats info 1055 * elements are present within a series of stats info elems 1056 * (within a stats upload confirmation message). 1057 */ 1058 enum htt_dbg_stats_status { 1059 HTT_DBG_STATS_STATUS_PRESENT = 0, 1060 HTT_DBG_STATS_STATUS_PARTIAL = 1, 1061 HTT_DBG_STATS_STATUS_ERROR = 2, 1062 HTT_DBG_STATS_STATUS_INVALID = 3, 1063 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 1064 }; 1065 1066 /* 1067 * target -> host statistics upload 1068 * 1069 * The following field definitions describe the format of the HTT target 1070 * to host stats upload confirmation message. 1071 * The message contains a cookie echoed from the HTT host->target stats 1072 * upload request, which identifies which request the confirmation is 1073 * for, and a series of tag-length-value stats information elements. 1074 * The tag-length header for each stats info element also includes a 1075 * status field, to indicate whether the request for the stat type in 1076 * question was fully met, partially met, unable to be met, or invalid 1077 * (if the stat type in question is disabled in the target). 1078 * A special value of all 1's in this status field is used to indicate 1079 * the end of the series of stats info elements. 1080 * 1081 * 1082 * |31 16|15 8|7 5|4 0| 1083 * |------------------------------------------------------------| 1084 * | reserved | msg type | 1085 * |------------------------------------------------------------| 1086 * | cookie LSBs | 1087 * |------------------------------------------------------------| 1088 * | cookie MSBs | 1089 * |------------------------------------------------------------| 1090 * | stats entry length | reserved | S |stat type| 1091 * |------------------------------------------------------------| 1092 * | | 1093 * | type-specific stats info | 1094 * | | 1095 * |------------------------------------------------------------| 1096 * | stats entry length | reserved | S |stat type| 1097 * |------------------------------------------------------------| 1098 * | | 1099 * | type-specific stats info | 1100 * | | 1101 * |------------------------------------------------------------| 1102 * | n/a | reserved | 111 | n/a | 1103 * |------------------------------------------------------------| 1104 * Header fields: 1105 * - MSG_TYPE 1106 * Bits 7:0 1107 * Purpose: identifies this is a statistics upload confirmation message 1108 * Value: 0x9 1109 * - COOKIE_LSBS 1110 * Bits 31:0 1111 * Purpose: Provide a mechanism to match a target->host stats confirmation 1112 * message with its preceding host->target stats request message. 1113 * Value: LSBs of the opaque cookie specified by the host-side requestor 1114 * - COOKIE_MSBS 1115 * Bits 31:0 1116 * Purpose: Provide a mechanism to match a target->host stats confirmation 1117 * message with its preceding host->target stats request message. 1118 * Value: MSBs of the opaque cookie specified by the host-side requestor 1119 * 1120 * Stats Information Element tag-length header fields: 1121 * - STAT_TYPE 1122 * Bits 4:0 1123 * Purpose: identifies the type of statistics info held in the 1124 * following information element 1125 * Value: htt_dbg_stats_type 1126 * - STATUS 1127 * Bits 7:5 1128 * Purpose: indicate whether the requested stats are present 1129 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 1130 * the completion of the stats entry series 1131 * - LENGTH 1132 * Bits 31:16 1133 * Purpose: indicate the stats information size 1134 * Value: This field specifies the number of bytes of stats information 1135 * that follows the element tag-length header. 1136 * It is expected but not required that this length is a multiple of 1137 * 4 bytes. Even if the length is not an integer multiple of 4, the 1138 * subsequent stats entry header will begin on a 4-byte aligned 1139 * boundary. 1140 */ 1141 1142 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1143 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1144 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1145 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1146 1147 struct htt_stats_conf_item { 1148 union { 1149 u8 info; 1150 struct { 1151 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1152 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1153 } __packed; 1154 } __packed; 1155 u8 pad; 1156 __le16 length; 1157 u8 payload[0]; /* roundup(length, 4) long */ 1158 } __packed; 1159 1160 struct htt_stats_conf { 1161 u8 pad[3]; 1162 __le32 cookie_lsb; 1163 __le32 cookie_msb; 1164 1165 /* each item has variable length! */ 1166 struct htt_stats_conf_item items[0]; 1167 } __packed; 1168 1169 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1170 const struct htt_stats_conf_item *item) 1171 { 1172 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1173 } 1174 1175 /* 1176 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1177 * 1178 * The following field definitions describe the format of the HTT host 1179 * to target frag_desc/msdu_ext bank configuration message. 1180 * The message contains the based address and the min and max id of the 1181 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1182 * MSDU_EXT/FRAG_DESC. 1183 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1184 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1185 * the hardware does the mapping/translation. 1186 * 1187 * Total banks that can be configured is configured to 16. 1188 * 1189 * This should be called before any TX has be initiated by the HTT 1190 * 1191 * |31 16|15 8|7 5|4 0| 1192 * |------------------------------------------------------------| 1193 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1194 * |------------------------------------------------------------| 1195 * | BANK0_BASE_ADDRESS | 1196 * |------------------------------------------------------------| 1197 * | ... | 1198 * |------------------------------------------------------------| 1199 * | BANK15_BASE_ADDRESS | 1200 * |------------------------------------------------------------| 1201 * | BANK0_MAX_ID | BANK0_MIN_ID | 1202 * |------------------------------------------------------------| 1203 * | ... | 1204 * |------------------------------------------------------------| 1205 * | BANK15_MAX_ID | BANK15_MIN_ID | 1206 * |------------------------------------------------------------| 1207 * Header fields: 1208 * - MSG_TYPE 1209 * Bits 7:0 1210 * Value: 0x6 1211 * - BANKx_BASE_ADDRESS 1212 * Bits 31:0 1213 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1214 * bank physical/bus address. 1215 * - BANKx_MIN_ID 1216 * Bits 15:0 1217 * Purpose: Provide a mechanism to specify the min index that needs to 1218 * mapped. 1219 * - BANKx_MAX_ID 1220 * Bits 31:16 1221 * Purpose: Provide a mechanism to specify the max index that needs to 1222 * 1223 */ 1224 struct htt_frag_desc_bank_id { 1225 __le16 bank_min_id; 1226 __le16 bank_max_id; 1227 } __packed; 1228 1229 /* real is 16 but it wouldn't fit in the max htt message size 1230 * so we use a conservatively safe value for now */ 1231 #define HTT_FRAG_DESC_BANK_MAX 4 1232 1233 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1234 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1235 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP (1 << 2) 1236 1237 struct htt_frag_desc_bank_cfg { 1238 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1239 u8 num_banks; 1240 u8 desc_size; 1241 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1242 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1243 } __packed; 1244 1245 union htt_rx_pn_t { 1246 /* WEP: 24-bit PN */ 1247 u32 pn24; 1248 1249 /* TKIP or CCMP: 48-bit PN */ 1250 u_int64_t pn48; 1251 1252 /* WAPI: 128-bit PN */ 1253 u_int64_t pn128[2]; 1254 }; 1255 1256 struct htt_cmd { 1257 struct htt_cmd_hdr hdr; 1258 union { 1259 struct htt_ver_req ver_req; 1260 struct htt_mgmt_tx_desc mgmt_tx; 1261 struct htt_data_tx_desc data_tx; 1262 struct htt_rx_ring_setup rx_setup; 1263 struct htt_stats_req stats_req; 1264 struct htt_oob_sync_req oob_sync_req; 1265 struct htt_aggr_conf aggr_conf; 1266 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg; 1267 }; 1268 } __packed; 1269 1270 struct htt_resp { 1271 struct htt_resp_hdr hdr; 1272 union { 1273 struct htt_ver_resp ver_resp; 1274 struct htt_mgmt_tx_completion mgmt_tx_completion; 1275 struct htt_data_tx_completion data_tx_completion; 1276 struct htt_rx_indication rx_ind; 1277 struct htt_rx_fragment_indication rx_frag_ind; 1278 struct htt_rx_peer_map peer_map; 1279 struct htt_rx_peer_unmap peer_unmap; 1280 struct htt_rx_flush rx_flush; 1281 struct htt_rx_addba rx_addba; 1282 struct htt_rx_delba rx_delba; 1283 struct htt_security_indication security_indication; 1284 struct htt_rc_update rc_update; 1285 struct htt_rx_test rx_test; 1286 struct htt_pktlog_msg pktlog_msg; 1287 struct htt_stats_conf stats_conf; 1288 struct htt_rx_pn_ind rx_pn_ind; 1289 struct htt_rx_offload_ind rx_offload_ind; 1290 struct htt_rx_in_ord_ind rx_in_ord_ind; 1291 }; 1292 } __packed; 1293 1294 /*** host side structures follow ***/ 1295 1296 struct htt_tx_done { 1297 u32 msdu_id; 1298 bool discard; 1299 bool no_ack; 1300 bool success; 1301 }; 1302 1303 struct htt_peer_map_event { 1304 u8 vdev_id; 1305 u16 peer_id; 1306 u8 addr[ETH_ALEN]; 1307 }; 1308 1309 struct htt_peer_unmap_event { 1310 u16 peer_id; 1311 }; 1312 1313 struct ath10k_htt_txbuf { 1314 struct htt_data_tx_desc_frag frags[2]; 1315 struct ath10k_htc_hdr htc_hdr; 1316 struct htt_cmd_hdr cmd_hdr; 1317 struct htt_data_tx_desc cmd_tx; 1318 } __packed; 1319 1320 struct ath10k_htt { 1321 struct ath10k *ar; 1322 enum ath10k_htc_ep_id eid; 1323 1324 u8 target_version_major; 1325 u8 target_version_minor; 1326 struct completion target_version_received; 1327 enum ath10k_fw_htt_op_version op_version; 1328 1329 const enum htt_t2h_msg_type *t2h_msg_types; 1330 u32 t2h_msg_types_max; 1331 1332 struct { 1333 /* 1334 * Ring of network buffer objects - This ring is 1335 * used exclusively by the host SW. This ring 1336 * mirrors the dev_addrs_ring that is shared 1337 * between the host SW and the MAC HW. The host SW 1338 * uses this netbufs ring to locate the network 1339 * buffer objects whose data buffers the HW has 1340 * filled. 1341 */ 1342 struct sk_buff **netbufs_ring; 1343 1344 /* This is used only with firmware supporting IN_ORD_IND. 1345 * 1346 * With Full Rx Reorder the HTT Rx Ring is more of a temporary 1347 * buffer ring from which buffer addresses are copied by the 1348 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND 1349 * pointing to specific (re-ordered) buffers. 1350 * 1351 * FIXME: With kernel generic hashing functions there's a lot 1352 * of hash collisions for sk_buffs. 1353 */ 1354 bool in_ord_rx; 1355 DECLARE_HASHTABLE(skb_table, 4); 1356 1357 /* 1358 * Ring of buffer addresses - 1359 * This ring holds the "physical" device address of the 1360 * rx buffers the host SW provides for the MAC HW to 1361 * fill. 1362 */ 1363 __le32 *paddrs_ring; 1364 1365 /* 1366 * Base address of ring, as a "physical" device address 1367 * rather than a CPU address. 1368 */ 1369 dma_addr_t base_paddr; 1370 1371 /* how many elems in the ring (power of 2) */ 1372 int size; 1373 1374 /* size - 1 */ 1375 unsigned size_mask; 1376 1377 /* how many rx buffers to keep in the ring */ 1378 int fill_level; 1379 1380 /* how many rx buffers (full+empty) are in the ring */ 1381 int fill_cnt; 1382 1383 /* 1384 * alloc_idx - where HTT SW has deposited empty buffers 1385 * This is allocated in consistent mem, so that the FW can 1386 * read this variable, and program the HW's FW_IDX reg with 1387 * the value of this shadow register. 1388 */ 1389 struct { 1390 __le32 *vaddr; 1391 dma_addr_t paddr; 1392 } alloc_idx; 1393 1394 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1395 struct { 1396 unsigned msdu_payld; 1397 } sw_rd_idx; 1398 1399 /* 1400 * refill_retry_timer - timer triggered when the ring is 1401 * not refilled to the level expected 1402 */ 1403 struct timer_list refill_retry_timer; 1404 1405 /* Protects access to all rx ring buffer state variables */ 1406 spinlock_t lock; 1407 } rx_ring; 1408 1409 unsigned int prefetch_len; 1410 1411 /* Protects access to pending_tx, num_pending_tx */ 1412 spinlock_t tx_lock; 1413 int max_num_pending_tx; 1414 int num_pending_tx; 1415 struct idr pending_tx; 1416 wait_queue_head_t empty_tx_wq; 1417 struct dma_pool *tx_pool; 1418 1419 /* set if host-fw communication goes haywire 1420 * used to avoid further failures */ 1421 bool rx_confused; 1422 struct tasklet_struct rx_replenish_task; 1423 1424 /* This is used to group tx/rx completions separately and process them 1425 * in batches to reduce cache stalls */ 1426 struct tasklet_struct txrx_compl_task; 1427 struct sk_buff_head tx_compl_q; 1428 struct sk_buff_head rx_compl_q; 1429 struct sk_buff_head rx_in_ord_compl_q; 1430 1431 /* rx_status template */ 1432 struct ieee80211_rx_status rx_status; 1433 }; 1434 1435 #define RX_HTT_HDR_STATUS_LEN 64 1436 1437 /* This structure layout is programmed via rx ring setup 1438 * so that FW knows how to transfer the rx descriptor to the host. 1439 * Buffers like this are placed on the rx ring. */ 1440 struct htt_rx_desc { 1441 union { 1442 /* This field is filled on the host using the msdu buffer 1443 * from htt_rx_indication */ 1444 struct fw_rx_desc_base fw_desc; 1445 u32 pad; 1446 } __packed; 1447 struct { 1448 struct rx_attention attention; 1449 struct rx_frag_info frag_info; 1450 struct rx_mpdu_start mpdu_start; 1451 struct rx_msdu_start msdu_start; 1452 struct rx_msdu_end msdu_end; 1453 struct rx_mpdu_end mpdu_end; 1454 struct rx_ppdu_start ppdu_start; 1455 struct rx_ppdu_end ppdu_end; 1456 } __packed; 1457 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1458 u8 msdu_payload[0]; 1459 }; 1460 1461 #define HTT_RX_DESC_ALIGN 8 1462 1463 #define HTT_MAC_ADDR_LEN 6 1464 1465 /* 1466 * FIX THIS 1467 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 1468 * rounded up to a cache line size. 1469 */ 1470 #define HTT_RX_BUF_SIZE 1920 1471 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 1472 1473 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 1474 * aggregated traffic more nicely. */ 1475 #define ATH10K_HTT_MAX_NUM_REFILL 16 1476 1477 /* 1478 * DMA_MAP expects the buffer to be an integral number of cache lines. 1479 * Rather than checking the actual cache line size, this code makes a 1480 * conservative estimate of what the cache line size could be. 1481 */ 1482 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 1483 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 1484 1485 int ath10k_htt_connect(struct ath10k_htt *htt); 1486 int ath10k_htt_init(struct ath10k *ar); 1487 int ath10k_htt_setup(struct ath10k_htt *htt); 1488 1489 int ath10k_htt_tx_alloc(struct ath10k_htt *htt); 1490 void ath10k_htt_tx_free(struct ath10k_htt *htt); 1491 1492 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 1493 int ath10k_htt_rx_ring_refill(struct ath10k *ar); 1494 void ath10k_htt_rx_free(struct ath10k_htt *htt); 1495 1496 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1497 void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1498 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 1499 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 1500 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt); 1501 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 1502 u8 max_subfrms_ampdu, 1503 u8 max_subfrms_amsdu); 1504 1505 void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 1506 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); 1507 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 1508 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *); 1509 int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *); 1510 1511 #endif 1512