1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HTT_H_ 19 #define _HTT_H_ 20 21 #include <linux/bug.h> 22 #include <linux/interrupt.h> 23 #include <linux/dmapool.h> 24 #include <linux/hashtable.h> 25 #include <net/mac80211.h> 26 27 #include "htc.h" 28 #include "hw.h" 29 #include "rx_desc.h" 30 #include "hw.h" 31 32 enum htt_dbg_stats_type { 33 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 34 HTT_DBG_STATS_RX_REORDER = 1 << 1, 35 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 36 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 37 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 38 /* bits 5-23 currently reserved */ 39 40 HTT_DBG_NUM_STATS /* keep this last */ 41 }; 42 43 enum htt_h2t_msg_type { /* host-to-target */ 44 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 45 HTT_H2T_MSG_TYPE_TX_FRM = 1, 46 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 47 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 48 HTT_H2T_MSG_TYPE_SYNC = 4, 49 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 50 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 51 52 /* This command is used for sending management frames in HTT < 3.0. 53 * HTT >= 3.0 uses TX_FRM for everything. */ 54 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 55 56 HTT_H2T_NUM_MSGS /* keep this last */ 57 }; 58 59 struct htt_cmd_hdr { 60 u8 msg_type; 61 } __packed; 62 63 struct htt_ver_req { 64 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 65 } __packed; 66 67 /* 68 * HTT tx MSDU descriptor 69 * 70 * The HTT tx MSDU descriptor is created by the host HTT SW for each 71 * tx MSDU. The HTT tx MSDU descriptor contains the information that 72 * the target firmware needs for the FW's tx processing, particularly 73 * for creating the HW msdu descriptor. 74 * The same HTT tx descriptor is used for HL and LL systems, though 75 * a few fields within the tx descriptor are used only by LL or 76 * only by HL. 77 * The HTT tx descriptor is defined in two manners: by a struct with 78 * bitfields, and by a series of [dword offset, bit mask, bit shift] 79 * definitions. 80 * The target should use the struct def, for simplicitly and clarity, 81 * but the host shall use the bit-mast + bit-shift defs, to be endian- 82 * neutral. Specifically, the host shall use the get/set macros built 83 * around the mask + shift defs. 84 */ 85 struct htt_data_tx_desc_frag { 86 __le32 paddr; 87 __le32 len; 88 } __packed; 89 90 struct htt_msdu_ext_desc { 91 __le32 tso_flag[4]; 92 struct htt_data_tx_desc_frag frags[6]; 93 }; 94 95 enum htt_data_tx_desc_flags0 { 96 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 97 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 98 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 99 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 100 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 101 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 102 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 103 }; 104 105 enum htt_data_tx_desc_flags1 { 106 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 107 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 108 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 109 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 110 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 111 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 112 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 113 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 114 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 115 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 116 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 117 }; 118 119 enum htt_data_tx_ext_tid { 120 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 121 HTT_DATA_TX_EXT_TID_MGMT = 17, 122 HTT_DATA_TX_EXT_TID_INVALID = 31 123 }; 124 125 #define HTT_INVALID_PEERID 0xFFFF 126 127 /* 128 * htt_data_tx_desc - used for data tx path 129 * 130 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 131 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 132 * for special kinds of tids 133 * postponed: only for HL hosts. indicates if this is a resend 134 * (HL hosts manage queues on the host ) 135 * more_in_batch: only for HL hosts. indicates if more packets are 136 * pending. this allows target to wait and aggregate 137 * freq: 0 means home channel of given vdev. intended for offchannel 138 */ 139 struct htt_data_tx_desc { 140 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 141 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 142 __le16 len; 143 __le16 id; 144 __le32 frags_paddr; 145 __le16 peerid; 146 __le16 freq; 147 u8 prefetch[0]; /* start of frame, for FW classification engine */ 148 } __packed; 149 150 enum htt_rx_ring_flags { 151 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 152 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 153 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 154 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 155 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 156 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 157 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 158 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 159 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 160 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 161 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 162 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 163 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 164 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 165 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 166 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 167 }; 168 169 #define HTT_RX_RING_SIZE_MIN 128 170 #define HTT_RX_RING_SIZE_MAX 2048 171 172 struct htt_rx_ring_setup_ring { 173 __le32 fw_idx_shadow_reg_paddr; 174 __le32 rx_ring_base_paddr; 175 __le16 rx_ring_len; /* in 4-byte words */ 176 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 177 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 178 __le16 fw_idx_init_val; 179 180 /* the following offsets are in 4-byte units */ 181 __le16 mac80211_hdr_offset; 182 __le16 msdu_payload_offset; 183 __le16 ppdu_start_offset; 184 __le16 ppdu_end_offset; 185 __le16 mpdu_start_offset; 186 __le16 mpdu_end_offset; 187 __le16 msdu_start_offset; 188 __le16 msdu_end_offset; 189 __le16 rx_attention_offset; 190 __le16 frag_info_offset; 191 } __packed; 192 193 struct htt_rx_ring_setup_hdr { 194 u8 num_rings; /* supported values: 1, 2 */ 195 __le16 rsvd0; 196 } __packed; 197 198 struct htt_rx_ring_setup { 199 struct htt_rx_ring_setup_hdr hdr; 200 struct htt_rx_ring_setup_ring rings[0]; 201 } __packed; 202 203 /* 204 * htt_stats_req - request target to send specified statistics 205 * 206 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 207 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 208 * so make sure its little-endian. 209 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 210 * so make sure its little-endian. 211 * @cfg_val: stat_type specific configuration 212 * @stat_type: see %htt_dbg_stats_type 213 * @cookie_lsb: used for confirmation message from target->host 214 * @cookie_msb: ditto as %cookie 215 */ 216 struct htt_stats_req { 217 u8 upload_types[3]; 218 u8 rsvd0; 219 u8 reset_types[3]; 220 struct { 221 u8 mpdu_bytes; 222 u8 mpdu_num_msdus; 223 u8 msdu_bytes; 224 } __packed; 225 u8 stat_type; 226 __le32 cookie_lsb; 227 __le32 cookie_msb; 228 } __packed; 229 230 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 231 232 /* 233 * htt_oob_sync_req - request out-of-band sync 234 * 235 * The HTT SYNC tells the target to suspend processing of subsequent 236 * HTT host-to-target messages until some other target agent locally 237 * informs the target HTT FW that the current sync counter is equal to 238 * or greater than (in a modulo sense) the sync counter specified in 239 * the SYNC message. 240 * 241 * This allows other host-target components to synchronize their operation 242 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 243 * security key has been downloaded to and activated by the target. 244 * In the absence of any explicit synchronization counter value 245 * specification, the target HTT FW will use zero as the default current 246 * sync value. 247 * 248 * The HTT target FW will suspend its host->target message processing as long 249 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 250 */ 251 struct htt_oob_sync_req { 252 u8 sync_count; 253 __le16 rsvd0; 254 } __packed; 255 256 struct htt_aggr_conf { 257 u8 max_num_ampdu_subframes; 258 /* amsdu_subframes is limited by 0x1F mask */ 259 u8 max_num_amsdu_subframes; 260 } __packed; 261 262 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 263 264 struct htt_mgmt_tx_desc { 265 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 266 __le32 msdu_paddr; 267 __le32 desc_id; 268 __le32 len; 269 __le32 vdev_id; 270 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 271 } __packed; 272 273 enum htt_mgmt_tx_status { 274 HTT_MGMT_TX_STATUS_OK = 0, 275 HTT_MGMT_TX_STATUS_RETRY = 1, 276 HTT_MGMT_TX_STATUS_DROP = 2 277 }; 278 279 /*=== target -> host messages ===============================================*/ 280 281 enum htt_main_t2h_msg_type { 282 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0, 283 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1, 284 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2, 285 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3, 286 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 287 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5, 288 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6, 289 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 290 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8, 291 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9, 292 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 293 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb, 294 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 295 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 296 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 297 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10, 298 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 299 HTT_MAIN_T2H_MSG_TYPE_TEST, 300 /* keep this last */ 301 HTT_MAIN_T2H_NUM_MSGS 302 }; 303 304 enum htt_10x_t2h_msg_type { 305 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0, 306 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1, 307 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2, 308 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3, 309 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 310 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5, 311 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6, 312 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 313 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8, 314 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9, 315 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 316 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb, 317 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 318 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 319 HTT_10X_T2H_MSG_TYPE_TEST = 0xe, 320 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 321 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11, 322 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12, 323 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13, 324 /* keep this last */ 325 HTT_10X_T2H_NUM_MSGS 326 }; 327 328 enum htt_tlv_t2h_msg_type { 329 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0, 330 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1, 331 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2, 332 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3, 333 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 334 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5, 335 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6, 336 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 337 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8, 338 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9, 339 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 340 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb, 341 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */ 342 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 343 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 344 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 345 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10, 346 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 347 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 348 /* 0x13 reservd */ 349 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 350 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 351 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 352 HTT_TLV_T2H_MSG_TYPE_TEST, 353 /* keep this last */ 354 HTT_TLV_T2H_NUM_MSGS 355 }; 356 357 enum htt_10_4_t2h_msg_type { 358 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0, 359 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1, 360 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2, 361 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3, 362 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 363 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5, 364 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6, 365 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 366 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8, 367 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9, 368 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 369 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb, 370 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 371 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 372 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 373 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 374 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10, 375 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11, 376 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12, 377 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13, 378 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14, 379 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15, 380 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16, 381 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONF = 0x17, 382 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18, 383 /* 0x19 to 0x2f are reserved */ 384 HTT_10_4_T2H_MSG_TYPE_TX_LOW_LATENCY_IND = 0x30, 385 /* keep this last */ 386 HTT_10_4_T2H_NUM_MSGS 387 }; 388 389 enum htt_t2h_msg_type { 390 HTT_T2H_MSG_TYPE_VERSION_CONF, 391 HTT_T2H_MSG_TYPE_RX_IND, 392 HTT_T2H_MSG_TYPE_RX_FLUSH, 393 HTT_T2H_MSG_TYPE_PEER_MAP, 394 HTT_T2H_MSG_TYPE_PEER_UNMAP, 395 HTT_T2H_MSG_TYPE_RX_ADDBA, 396 HTT_T2H_MSG_TYPE_RX_DELBA, 397 HTT_T2H_MSG_TYPE_TX_COMPL_IND, 398 HTT_T2H_MSG_TYPE_PKTLOG, 399 HTT_T2H_MSG_TYPE_STATS_CONF, 400 HTT_T2H_MSG_TYPE_RX_FRAG_IND, 401 HTT_T2H_MSG_TYPE_SEC_IND, 402 HTT_T2H_MSG_TYPE_RC_UPDATE_IND, 403 HTT_T2H_MSG_TYPE_TX_INSPECT_IND, 404 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION, 405 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, 406 HTT_T2H_MSG_TYPE_RX_PN_IND, 407 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND, 408 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND, 409 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE, 410 HTT_T2H_MSG_TYPE_CHAN_CHANGE, 411 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR, 412 HTT_T2H_MSG_TYPE_AGGR_CONF, 413 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, 414 HTT_T2H_MSG_TYPE_TEST, 415 HTT_T2H_MSG_TYPE_EN_STATS, 416 HTT_T2H_MSG_TYPE_TX_FETCH_IND, 417 HTT_T2H_MSG_TYPE_TX_FETCH_CONF, 418 HTT_T2H_MSG_TYPE_TX_LOW_LATENCY_IND, 419 /* keep this last */ 420 HTT_T2H_NUM_MSGS 421 }; 422 423 /* 424 * htt_resp_hdr - header for target-to-host messages 425 * 426 * msg_type: see htt_t2h_msg_type 427 */ 428 struct htt_resp_hdr { 429 u8 msg_type; 430 } __packed; 431 432 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 433 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 434 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 435 436 /* htt_ver_resp - response sent for htt_ver_req */ 437 struct htt_ver_resp { 438 u8 minor; 439 u8 major; 440 u8 rsvd0; 441 } __packed; 442 443 struct htt_mgmt_tx_completion { 444 u8 rsvd0; 445 u8 rsvd1; 446 u8 rsvd2; 447 __le32 desc_id; 448 __le32 status; 449 } __packed; 450 451 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x3F) 452 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 453 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 6) 454 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 7) 455 456 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 457 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 458 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 459 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 460 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 461 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 462 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 463 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 464 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 465 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 466 467 struct htt_rx_indication_hdr { 468 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 469 __le16 peer_id; 470 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 471 } __packed; 472 473 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 474 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 475 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 476 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 477 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 478 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 479 480 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 481 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 482 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 483 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 484 485 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 486 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 487 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 488 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 489 490 enum htt_rx_legacy_rate { 491 HTT_RX_OFDM_48 = 0, 492 HTT_RX_OFDM_24 = 1, 493 HTT_RX_OFDM_12, 494 HTT_RX_OFDM_6, 495 HTT_RX_OFDM_54, 496 HTT_RX_OFDM_36, 497 HTT_RX_OFDM_18, 498 HTT_RX_OFDM_9, 499 500 /* long preamble */ 501 HTT_RX_CCK_11_LP = 0, 502 HTT_RX_CCK_5_5_LP = 1, 503 HTT_RX_CCK_2_LP, 504 HTT_RX_CCK_1_LP, 505 /* short preamble */ 506 HTT_RX_CCK_11_SP, 507 HTT_RX_CCK_5_5_SP, 508 HTT_RX_CCK_2_SP 509 }; 510 511 enum htt_rx_legacy_rate_type { 512 HTT_RX_LEGACY_RATE_OFDM = 0, 513 HTT_RX_LEGACY_RATE_CCK 514 }; 515 516 enum htt_rx_preamble_type { 517 HTT_RX_LEGACY = 0x4, 518 HTT_RX_HT = 0x8, 519 HTT_RX_HT_WITH_TXBF = 0x9, 520 HTT_RX_VHT = 0xC, 521 HTT_RX_VHT_WITH_TXBF = 0xD, 522 }; 523 524 /* 525 * Fields: phy_err_valid, phy_err_code, tsf, 526 * usec_timestamp, sub_usec_timestamp 527 * ..are valid only if end_valid == 1. 528 * 529 * Fields: rssi_chains, legacy_rate_type, 530 * legacy_rate_cck, preamble_type, service, 531 * vht_sig_* 532 * ..are valid only if start_valid == 1; 533 */ 534 struct htt_rx_indication_ppdu { 535 u8 combined_rssi; 536 u8 sub_usec_timestamp; 537 u8 phy_err_code; 538 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 539 struct { 540 u8 pri20_db; 541 u8 ext20_db; 542 u8 ext40_db; 543 u8 ext80_db; 544 } __packed rssi_chains[4]; 545 __le32 tsf; 546 __le32 usec_timestamp; 547 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 548 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 549 } __packed; 550 551 enum htt_rx_mpdu_status { 552 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 553 HTT_RX_IND_MPDU_STATUS_OK, 554 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 555 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 556 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 557 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 558 /* only accept EAPOL frames */ 559 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 560 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 561 /* Non-data in promiscous mode */ 562 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 563 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 564 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 565 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 566 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 567 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 568 569 /* 570 * MISC: discard for unspecified reasons. 571 * Leave this enum value last. 572 */ 573 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 574 }; 575 576 struct htt_rx_indication_mpdu_range { 577 u8 mpdu_count; 578 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 579 u8 pad0; 580 u8 pad1; 581 } __packed; 582 583 struct htt_rx_indication_prefix { 584 __le16 fw_rx_desc_bytes; 585 u8 pad0; 586 u8 pad1; 587 }; 588 589 struct htt_rx_indication { 590 struct htt_rx_indication_hdr hdr; 591 struct htt_rx_indication_ppdu ppdu; 592 struct htt_rx_indication_prefix prefix; 593 594 /* 595 * the following fields are both dynamically sized, so 596 * take care addressing them 597 */ 598 599 /* the size of this is %fw_rx_desc_bytes */ 600 struct fw_rx_desc_base fw_desc; 601 602 /* 603 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 604 * and has %num_mpdu_ranges elements. 605 */ 606 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 607 } __packed; 608 609 static inline struct htt_rx_indication_mpdu_range * 610 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 611 { 612 void *ptr = rx_ind; 613 614 ptr += sizeof(rx_ind->hdr) 615 + sizeof(rx_ind->ppdu) 616 + sizeof(rx_ind->prefix) 617 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 618 return ptr; 619 } 620 621 enum htt_rx_flush_mpdu_status { 622 HTT_RX_FLUSH_MPDU_DISCARD = 0, 623 HTT_RX_FLUSH_MPDU_REORDER = 1, 624 }; 625 626 /* 627 * htt_rx_flush - discard or reorder given range of mpdus 628 * 629 * Note: host must check if all sequence numbers between 630 * [seq_num_start, seq_num_end-1] are valid. 631 */ 632 struct htt_rx_flush { 633 __le16 peer_id; 634 u8 tid; 635 u8 rsvd0; 636 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 637 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 638 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 639 }; 640 641 struct htt_rx_peer_map { 642 u8 vdev_id; 643 __le16 peer_id; 644 u8 addr[6]; 645 u8 rsvd0; 646 u8 rsvd1; 647 } __packed; 648 649 struct htt_rx_peer_unmap { 650 u8 rsvd0; 651 __le16 peer_id; 652 } __packed; 653 654 enum htt_security_types { 655 HTT_SECURITY_NONE, 656 HTT_SECURITY_WEP128, 657 HTT_SECURITY_WEP104, 658 HTT_SECURITY_WEP40, 659 HTT_SECURITY_TKIP, 660 HTT_SECURITY_TKIP_NOMIC, 661 HTT_SECURITY_AES_CCMP, 662 HTT_SECURITY_WAPI, 663 664 HTT_NUM_SECURITY_TYPES /* keep this last! */ 665 }; 666 667 enum htt_security_flags { 668 #define HTT_SECURITY_TYPE_MASK 0x7F 669 #define HTT_SECURITY_TYPE_LSB 0 670 HTT_SECURITY_IS_UNICAST = 1 << 7 671 }; 672 673 struct htt_security_indication { 674 union { 675 /* dont use bitfields; undefined behaviour */ 676 u8 flags; /* %htt_security_flags */ 677 struct { 678 u8 security_type:7, /* %htt_security_types */ 679 is_unicast:1; 680 } __packed; 681 } __packed; 682 __le16 peer_id; 683 u8 michael_key[8]; 684 u8 wapi_rsc[16]; 685 } __packed; 686 687 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 688 #define HTT_RX_BA_INFO0_TID_LSB 0 689 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 690 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 691 692 struct htt_rx_addba { 693 u8 window_size; 694 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 695 } __packed; 696 697 struct htt_rx_delba { 698 u8 rsvd0; 699 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 700 } __packed; 701 702 enum htt_data_tx_status { 703 HTT_DATA_TX_STATUS_OK = 0, 704 HTT_DATA_TX_STATUS_DISCARD = 1, 705 HTT_DATA_TX_STATUS_NO_ACK = 2, 706 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 707 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 708 }; 709 710 enum htt_data_tx_flags { 711 #define HTT_DATA_TX_STATUS_MASK 0x07 712 #define HTT_DATA_TX_STATUS_LSB 0 713 #define HTT_DATA_TX_TID_MASK 0x78 714 #define HTT_DATA_TX_TID_LSB 3 715 HTT_DATA_TX_TID_INVALID = 1 << 7 716 }; 717 718 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 719 720 struct htt_data_tx_completion { 721 union { 722 u8 flags; 723 struct { 724 u8 status:3, 725 tid:4, 726 tid_invalid:1; 727 } __packed; 728 } __packed; 729 u8 num_msdus; 730 u8 rsvd0; 731 __le16 msdus[0]; /* variable length based on %num_msdus */ 732 } __packed; 733 734 struct htt_tx_compl_ind_base { 735 u32 hdr; 736 u16 payload[1/*or more*/]; 737 } __packed; 738 739 struct htt_rc_tx_done_params { 740 u32 rate_code; 741 u32 rate_code_flags; 742 u32 flags; 743 u32 num_enqued; /* 1 for non-AMPDU */ 744 u32 num_retries; 745 u32 num_failed; /* for AMPDU */ 746 u32 ack_rssi; 747 u32 time_stamp; 748 u32 is_probe; 749 }; 750 751 struct htt_rc_update { 752 u8 vdev_id; 753 __le16 peer_id; 754 u8 addr[6]; 755 u8 num_elems; 756 u8 rsvd0; 757 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 758 } __packed; 759 760 /* see htt_rx_indication for similar fields and descriptions */ 761 struct htt_rx_fragment_indication { 762 union { 763 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 764 struct { 765 u8 ext_tid:5, 766 flush_valid:1; 767 } __packed; 768 } __packed; 769 __le16 peer_id; 770 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 771 __le16 fw_rx_desc_bytes; 772 __le16 rsvd0; 773 774 u8 fw_msdu_rx_desc[0]; 775 } __packed; 776 777 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 778 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 779 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 780 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 781 782 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 783 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 784 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 785 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 786 787 struct htt_rx_pn_ind { 788 __le16 peer_id; 789 u8 tid; 790 u8 seqno_start; 791 u8 seqno_end; 792 u8 pn_ie_count; 793 u8 reserved; 794 u8 pn_ies[0]; 795 } __packed; 796 797 struct htt_rx_offload_msdu { 798 __le16 msdu_len; 799 __le16 peer_id; 800 u8 vdev_id; 801 u8 tid; 802 u8 fw_desc; 803 u8 payload[0]; 804 } __packed; 805 806 struct htt_rx_offload_ind { 807 u8 reserved; 808 __le16 msdu_count; 809 } __packed; 810 811 struct htt_rx_in_ord_msdu_desc { 812 __le32 msdu_paddr; 813 __le16 msdu_len; 814 u8 fw_desc; 815 u8 reserved; 816 } __packed; 817 818 struct htt_rx_in_ord_ind { 819 u8 info; 820 __le16 peer_id; 821 u8 vdev_id; 822 u8 reserved; 823 __le16 msdu_count; 824 struct htt_rx_in_ord_msdu_desc msdu_descs[0]; 825 } __packed; 826 827 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f 828 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 829 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020 830 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 831 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040 832 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 833 834 /* 835 * target -> host test message definition 836 * 837 * The following field definitions describe the format of the test 838 * message sent from the target to the host. 839 * The message consists of a 4-octet header, followed by a variable 840 * number of 32-bit integer values, followed by a variable number 841 * of 8-bit character values. 842 * 843 * |31 16|15 8|7 0| 844 * |-----------------------------------------------------------| 845 * | num chars | num ints | msg type | 846 * |-----------------------------------------------------------| 847 * | int 0 | 848 * |-----------------------------------------------------------| 849 * | int 1 | 850 * |-----------------------------------------------------------| 851 * | ... | 852 * |-----------------------------------------------------------| 853 * | char 3 | char 2 | char 1 | char 0 | 854 * |-----------------------------------------------------------| 855 * | | | ... | char 4 | 856 * |-----------------------------------------------------------| 857 * - MSG_TYPE 858 * Bits 7:0 859 * Purpose: identifies this as a test message 860 * Value: HTT_MSG_TYPE_TEST 861 * - NUM_INTS 862 * Bits 15:8 863 * Purpose: indicate how many 32-bit integers follow the message header 864 * - NUM_CHARS 865 * Bits 31:16 866 * Purpose: indicate how many 8-bit charaters follow the series of integers 867 */ 868 struct htt_rx_test { 869 u8 num_ints; 870 __le16 num_chars; 871 872 /* payload consists of 2 lists: 873 * a) num_ints * sizeof(__le32) 874 * b) num_chars * sizeof(u8) aligned to 4bytes */ 875 u8 payload[0]; 876 } __packed; 877 878 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 879 { 880 return (__le32 *)rx_test->payload; 881 } 882 883 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 884 { 885 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 886 } 887 888 /* 889 * target -> host packet log message 890 * 891 * The following field definitions describe the format of the packet log 892 * message sent from the target to the host. 893 * The message consists of a 4-octet header,followed by a variable number 894 * of 32-bit character values. 895 * 896 * |31 24|23 16|15 8|7 0| 897 * |-----------------------------------------------------------| 898 * | | | | msg type | 899 * |-----------------------------------------------------------| 900 * | payload | 901 * |-----------------------------------------------------------| 902 * - MSG_TYPE 903 * Bits 7:0 904 * Purpose: identifies this as a test message 905 * Value: HTT_MSG_TYPE_PACKETLOG 906 */ 907 struct htt_pktlog_msg { 908 u8 pad[3]; 909 u8 payload[0]; 910 } __packed; 911 912 struct htt_dbg_stats_rx_reorder_stats { 913 /* Non QoS MPDUs received */ 914 __le32 deliver_non_qos; 915 916 /* MPDUs received in-order */ 917 __le32 deliver_in_order; 918 919 /* Flush due to reorder timer expired */ 920 __le32 deliver_flush_timeout; 921 922 /* Flush due to move out of window */ 923 __le32 deliver_flush_oow; 924 925 /* Flush due to DELBA */ 926 __le32 deliver_flush_delba; 927 928 /* MPDUs dropped due to FCS error */ 929 __le32 fcs_error; 930 931 /* MPDUs dropped due to monitor mode non-data packet */ 932 __le32 mgmt_ctrl; 933 934 /* MPDUs dropped due to invalid peer */ 935 __le32 invalid_peer; 936 937 /* MPDUs dropped due to duplication (non aggregation) */ 938 __le32 dup_non_aggr; 939 940 /* MPDUs dropped due to processed before */ 941 __le32 dup_past; 942 943 /* MPDUs dropped due to duplicate in reorder queue */ 944 __le32 dup_in_reorder; 945 946 /* Reorder timeout happened */ 947 __le32 reorder_timeout; 948 949 /* invalid bar ssn */ 950 __le32 invalid_bar_ssn; 951 952 /* reorder reset due to bar ssn */ 953 __le32 ssn_reset; 954 }; 955 956 struct htt_dbg_stats_wal_tx_stats { 957 /* Num HTT cookies queued to dispatch list */ 958 __le32 comp_queued; 959 960 /* Num HTT cookies dispatched */ 961 __le32 comp_delivered; 962 963 /* Num MSDU queued to WAL */ 964 __le32 msdu_enqued; 965 966 /* Num MPDU queue to WAL */ 967 __le32 mpdu_enqued; 968 969 /* Num MSDUs dropped by WMM limit */ 970 __le32 wmm_drop; 971 972 /* Num Local frames queued */ 973 __le32 local_enqued; 974 975 /* Num Local frames done */ 976 __le32 local_freed; 977 978 /* Num queued to HW */ 979 __le32 hw_queued; 980 981 /* Num PPDU reaped from HW */ 982 __le32 hw_reaped; 983 984 /* Num underruns */ 985 __le32 underrun; 986 987 /* Num PPDUs cleaned up in TX abort */ 988 __le32 tx_abort; 989 990 /* Num MPDUs requed by SW */ 991 __le32 mpdus_requed; 992 993 /* excessive retries */ 994 __le32 tx_ko; 995 996 /* data hw rate code */ 997 __le32 data_rc; 998 999 /* Scheduler self triggers */ 1000 __le32 self_triggers; 1001 1002 /* frames dropped due to excessive sw retries */ 1003 __le32 sw_retry_failure; 1004 1005 /* illegal rate phy errors */ 1006 __le32 illgl_rate_phy_err; 1007 1008 /* wal pdev continous xretry */ 1009 __le32 pdev_cont_xretry; 1010 1011 /* wal pdev continous xretry */ 1012 __le32 pdev_tx_timeout; 1013 1014 /* wal pdev resets */ 1015 __le32 pdev_resets; 1016 1017 __le32 phy_underrun; 1018 1019 /* MPDU is more than txop limit */ 1020 __le32 txop_ovf; 1021 } __packed; 1022 1023 struct htt_dbg_stats_wal_rx_stats { 1024 /* Cnts any change in ring routing mid-ppdu */ 1025 __le32 mid_ppdu_route_change; 1026 1027 /* Total number of statuses processed */ 1028 __le32 status_rcvd; 1029 1030 /* Extra frags on rings 0-3 */ 1031 __le32 r0_frags; 1032 __le32 r1_frags; 1033 __le32 r2_frags; 1034 __le32 r3_frags; 1035 1036 /* MSDUs / MPDUs delivered to HTT */ 1037 __le32 htt_msdus; 1038 __le32 htt_mpdus; 1039 1040 /* MSDUs / MPDUs delivered to local stack */ 1041 __le32 loc_msdus; 1042 __le32 loc_mpdus; 1043 1044 /* AMSDUs that have more MSDUs than the status ring size */ 1045 __le32 oversize_amsdu; 1046 1047 /* Number of PHY errors */ 1048 __le32 phy_errs; 1049 1050 /* Number of PHY errors drops */ 1051 __le32 phy_err_drop; 1052 1053 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1054 __le32 mpdu_errs; 1055 } __packed; 1056 1057 struct htt_dbg_stats_wal_peer_stats { 1058 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 1059 } __packed; 1060 1061 struct htt_dbg_stats_wal_pdev_txrx { 1062 struct htt_dbg_stats_wal_tx_stats tx_stats; 1063 struct htt_dbg_stats_wal_rx_stats rx_stats; 1064 struct htt_dbg_stats_wal_peer_stats peer_stats; 1065 } __packed; 1066 1067 struct htt_dbg_stats_rx_rate_info { 1068 __le32 mcs[10]; 1069 __le32 sgi[10]; 1070 __le32 nss[4]; 1071 __le32 stbc[10]; 1072 __le32 bw[3]; 1073 __le32 pream[6]; 1074 __le32 ldpc; 1075 __le32 txbf; 1076 }; 1077 1078 /* 1079 * htt_dbg_stats_status - 1080 * present - The requested stats have been delivered in full. 1081 * This indicates that either the stats information was contained 1082 * in its entirety within this message, or else this message 1083 * completes the delivery of the requested stats info that was 1084 * partially delivered through earlier STATS_CONF messages. 1085 * partial - The requested stats have been delivered in part. 1086 * One or more subsequent STATS_CONF messages with the same 1087 * cookie value will be sent to deliver the remainder of the 1088 * information. 1089 * error - The requested stats could not be delivered, for example due 1090 * to a shortage of memory to construct a message holding the 1091 * requested stats. 1092 * invalid - The requested stat type is either not recognized, or the 1093 * target is configured to not gather the stats type in question. 1094 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1095 * series_done - This special value indicates that no further stats info 1096 * elements are present within a series of stats info elems 1097 * (within a stats upload confirmation message). 1098 */ 1099 enum htt_dbg_stats_status { 1100 HTT_DBG_STATS_STATUS_PRESENT = 0, 1101 HTT_DBG_STATS_STATUS_PARTIAL = 1, 1102 HTT_DBG_STATS_STATUS_ERROR = 2, 1103 HTT_DBG_STATS_STATUS_INVALID = 3, 1104 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 1105 }; 1106 1107 /* 1108 * target -> host statistics upload 1109 * 1110 * The following field definitions describe the format of the HTT target 1111 * to host stats upload confirmation message. 1112 * The message contains a cookie echoed from the HTT host->target stats 1113 * upload request, which identifies which request the confirmation is 1114 * for, and a series of tag-length-value stats information elements. 1115 * The tag-length header for each stats info element also includes a 1116 * status field, to indicate whether the request for the stat type in 1117 * question was fully met, partially met, unable to be met, or invalid 1118 * (if the stat type in question is disabled in the target). 1119 * A special value of all 1's in this status field is used to indicate 1120 * the end of the series of stats info elements. 1121 * 1122 * 1123 * |31 16|15 8|7 5|4 0| 1124 * |------------------------------------------------------------| 1125 * | reserved | msg type | 1126 * |------------------------------------------------------------| 1127 * | cookie LSBs | 1128 * |------------------------------------------------------------| 1129 * | cookie MSBs | 1130 * |------------------------------------------------------------| 1131 * | stats entry length | reserved | S |stat type| 1132 * |------------------------------------------------------------| 1133 * | | 1134 * | type-specific stats info | 1135 * | | 1136 * |------------------------------------------------------------| 1137 * | stats entry length | reserved | S |stat type| 1138 * |------------------------------------------------------------| 1139 * | | 1140 * | type-specific stats info | 1141 * | | 1142 * |------------------------------------------------------------| 1143 * | n/a | reserved | 111 | n/a | 1144 * |------------------------------------------------------------| 1145 * Header fields: 1146 * - MSG_TYPE 1147 * Bits 7:0 1148 * Purpose: identifies this is a statistics upload confirmation message 1149 * Value: 0x9 1150 * - COOKIE_LSBS 1151 * Bits 31:0 1152 * Purpose: Provide a mechanism to match a target->host stats confirmation 1153 * message with its preceding host->target stats request message. 1154 * Value: LSBs of the opaque cookie specified by the host-side requestor 1155 * - COOKIE_MSBS 1156 * Bits 31:0 1157 * Purpose: Provide a mechanism to match a target->host stats confirmation 1158 * message with its preceding host->target stats request message. 1159 * Value: MSBs of the opaque cookie specified by the host-side requestor 1160 * 1161 * Stats Information Element tag-length header fields: 1162 * - STAT_TYPE 1163 * Bits 4:0 1164 * Purpose: identifies the type of statistics info held in the 1165 * following information element 1166 * Value: htt_dbg_stats_type 1167 * - STATUS 1168 * Bits 7:5 1169 * Purpose: indicate whether the requested stats are present 1170 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 1171 * the completion of the stats entry series 1172 * - LENGTH 1173 * Bits 31:16 1174 * Purpose: indicate the stats information size 1175 * Value: This field specifies the number of bytes of stats information 1176 * that follows the element tag-length header. 1177 * It is expected but not required that this length is a multiple of 1178 * 4 bytes. Even if the length is not an integer multiple of 4, the 1179 * subsequent stats entry header will begin on a 4-byte aligned 1180 * boundary. 1181 */ 1182 1183 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1184 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1185 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1186 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1187 1188 struct htt_stats_conf_item { 1189 union { 1190 u8 info; 1191 struct { 1192 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1193 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1194 } __packed; 1195 } __packed; 1196 u8 pad; 1197 __le16 length; 1198 u8 payload[0]; /* roundup(length, 4) long */ 1199 } __packed; 1200 1201 struct htt_stats_conf { 1202 u8 pad[3]; 1203 __le32 cookie_lsb; 1204 __le32 cookie_msb; 1205 1206 /* each item has variable length! */ 1207 struct htt_stats_conf_item items[0]; 1208 } __packed; 1209 1210 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1211 const struct htt_stats_conf_item *item) 1212 { 1213 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1214 } 1215 1216 /* 1217 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1218 * 1219 * The following field definitions describe the format of the HTT host 1220 * to target frag_desc/msdu_ext bank configuration message. 1221 * The message contains the based address and the min and max id of the 1222 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1223 * MSDU_EXT/FRAG_DESC. 1224 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1225 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1226 * the hardware does the mapping/translation. 1227 * 1228 * Total banks that can be configured is configured to 16. 1229 * 1230 * This should be called before any TX has be initiated by the HTT 1231 * 1232 * |31 16|15 8|7 5|4 0| 1233 * |------------------------------------------------------------| 1234 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1235 * |------------------------------------------------------------| 1236 * | BANK0_BASE_ADDRESS | 1237 * |------------------------------------------------------------| 1238 * | ... | 1239 * |------------------------------------------------------------| 1240 * | BANK15_BASE_ADDRESS | 1241 * |------------------------------------------------------------| 1242 * | BANK0_MAX_ID | BANK0_MIN_ID | 1243 * |------------------------------------------------------------| 1244 * | ... | 1245 * |------------------------------------------------------------| 1246 * | BANK15_MAX_ID | BANK15_MIN_ID | 1247 * |------------------------------------------------------------| 1248 * Header fields: 1249 * - MSG_TYPE 1250 * Bits 7:0 1251 * Value: 0x6 1252 * - BANKx_BASE_ADDRESS 1253 * Bits 31:0 1254 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1255 * bank physical/bus address. 1256 * - BANKx_MIN_ID 1257 * Bits 15:0 1258 * Purpose: Provide a mechanism to specify the min index that needs to 1259 * mapped. 1260 * - BANKx_MAX_ID 1261 * Bits 31:16 1262 * Purpose: Provide a mechanism to specify the max index that needs to 1263 * 1264 */ 1265 struct htt_frag_desc_bank_id { 1266 __le16 bank_min_id; 1267 __le16 bank_max_id; 1268 } __packed; 1269 1270 /* real is 16 but it wouldn't fit in the max htt message size 1271 * so we use a conservatively safe value for now */ 1272 #define HTT_FRAG_DESC_BANK_MAX 4 1273 1274 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1275 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1276 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP (1 << 2) 1277 1278 struct htt_frag_desc_bank_cfg { 1279 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1280 u8 num_banks; 1281 u8 desc_size; 1282 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1283 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1284 } __packed; 1285 1286 union htt_rx_pn_t { 1287 /* WEP: 24-bit PN */ 1288 u32 pn24; 1289 1290 /* TKIP or CCMP: 48-bit PN */ 1291 u_int64_t pn48; 1292 1293 /* WAPI: 128-bit PN */ 1294 u_int64_t pn128[2]; 1295 }; 1296 1297 struct htt_cmd { 1298 struct htt_cmd_hdr hdr; 1299 union { 1300 struct htt_ver_req ver_req; 1301 struct htt_mgmt_tx_desc mgmt_tx; 1302 struct htt_data_tx_desc data_tx; 1303 struct htt_rx_ring_setup rx_setup; 1304 struct htt_stats_req stats_req; 1305 struct htt_oob_sync_req oob_sync_req; 1306 struct htt_aggr_conf aggr_conf; 1307 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg; 1308 }; 1309 } __packed; 1310 1311 struct htt_resp { 1312 struct htt_resp_hdr hdr; 1313 union { 1314 struct htt_ver_resp ver_resp; 1315 struct htt_mgmt_tx_completion mgmt_tx_completion; 1316 struct htt_data_tx_completion data_tx_completion; 1317 struct htt_rx_indication rx_ind; 1318 struct htt_rx_fragment_indication rx_frag_ind; 1319 struct htt_rx_peer_map peer_map; 1320 struct htt_rx_peer_unmap peer_unmap; 1321 struct htt_rx_flush rx_flush; 1322 struct htt_rx_addba rx_addba; 1323 struct htt_rx_delba rx_delba; 1324 struct htt_security_indication security_indication; 1325 struct htt_rc_update rc_update; 1326 struct htt_rx_test rx_test; 1327 struct htt_pktlog_msg pktlog_msg; 1328 struct htt_stats_conf stats_conf; 1329 struct htt_rx_pn_ind rx_pn_ind; 1330 struct htt_rx_offload_ind rx_offload_ind; 1331 struct htt_rx_in_ord_ind rx_in_ord_ind; 1332 }; 1333 } __packed; 1334 1335 /*** host side structures follow ***/ 1336 1337 struct htt_tx_done { 1338 u32 msdu_id; 1339 bool discard; 1340 bool no_ack; 1341 bool success; 1342 }; 1343 1344 struct htt_peer_map_event { 1345 u8 vdev_id; 1346 u16 peer_id; 1347 u8 addr[ETH_ALEN]; 1348 }; 1349 1350 struct htt_peer_unmap_event { 1351 u16 peer_id; 1352 }; 1353 1354 struct ath10k_htt_txbuf { 1355 struct htt_data_tx_desc_frag frags[2]; 1356 struct ath10k_htc_hdr htc_hdr; 1357 struct htt_cmd_hdr cmd_hdr; 1358 struct htt_data_tx_desc cmd_tx; 1359 } __packed; 1360 1361 struct ath10k_htt { 1362 struct ath10k *ar; 1363 enum ath10k_htc_ep_id eid; 1364 1365 u8 target_version_major; 1366 u8 target_version_minor; 1367 struct completion target_version_received; 1368 enum ath10k_fw_htt_op_version op_version; 1369 1370 const enum htt_t2h_msg_type *t2h_msg_types; 1371 u32 t2h_msg_types_max; 1372 1373 struct { 1374 /* 1375 * Ring of network buffer objects - This ring is 1376 * used exclusively by the host SW. This ring 1377 * mirrors the dev_addrs_ring that is shared 1378 * between the host SW and the MAC HW. The host SW 1379 * uses this netbufs ring to locate the network 1380 * buffer objects whose data buffers the HW has 1381 * filled. 1382 */ 1383 struct sk_buff **netbufs_ring; 1384 1385 /* This is used only with firmware supporting IN_ORD_IND. 1386 * 1387 * With Full Rx Reorder the HTT Rx Ring is more of a temporary 1388 * buffer ring from which buffer addresses are copied by the 1389 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND 1390 * pointing to specific (re-ordered) buffers. 1391 * 1392 * FIXME: With kernel generic hashing functions there's a lot 1393 * of hash collisions for sk_buffs. 1394 */ 1395 bool in_ord_rx; 1396 DECLARE_HASHTABLE(skb_table, 4); 1397 1398 /* 1399 * Ring of buffer addresses - 1400 * This ring holds the "physical" device address of the 1401 * rx buffers the host SW provides for the MAC HW to 1402 * fill. 1403 */ 1404 __le32 *paddrs_ring; 1405 1406 /* 1407 * Base address of ring, as a "physical" device address 1408 * rather than a CPU address. 1409 */ 1410 dma_addr_t base_paddr; 1411 1412 /* how many elems in the ring (power of 2) */ 1413 int size; 1414 1415 /* size - 1 */ 1416 unsigned size_mask; 1417 1418 /* how many rx buffers to keep in the ring */ 1419 int fill_level; 1420 1421 /* how many rx buffers (full+empty) are in the ring */ 1422 int fill_cnt; 1423 1424 /* 1425 * alloc_idx - where HTT SW has deposited empty buffers 1426 * This is allocated in consistent mem, so that the FW can 1427 * read this variable, and program the HW's FW_IDX reg with 1428 * the value of this shadow register. 1429 */ 1430 struct { 1431 __le32 *vaddr; 1432 dma_addr_t paddr; 1433 } alloc_idx; 1434 1435 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1436 struct { 1437 unsigned msdu_payld; 1438 } sw_rd_idx; 1439 1440 /* 1441 * refill_retry_timer - timer triggered when the ring is 1442 * not refilled to the level expected 1443 */ 1444 struct timer_list refill_retry_timer; 1445 1446 /* Protects access to all rx ring buffer state variables */ 1447 spinlock_t lock; 1448 } rx_ring; 1449 1450 unsigned int prefetch_len; 1451 1452 /* Protects access to pending_tx, num_pending_tx */ 1453 spinlock_t tx_lock; 1454 int max_num_pending_tx; 1455 int num_pending_tx; 1456 struct idr pending_tx; 1457 wait_queue_head_t empty_tx_wq; 1458 struct dma_pool *tx_pool; 1459 1460 /* set if host-fw communication goes haywire 1461 * used to avoid further failures */ 1462 bool rx_confused; 1463 struct tasklet_struct rx_replenish_task; 1464 1465 /* This is used to group tx/rx completions separately and process them 1466 * in batches to reduce cache stalls */ 1467 struct tasklet_struct txrx_compl_task; 1468 struct sk_buff_head tx_compl_q; 1469 struct sk_buff_head rx_compl_q; 1470 struct sk_buff_head rx_in_ord_compl_q; 1471 1472 /* rx_status template */ 1473 struct ieee80211_rx_status rx_status; 1474 1475 struct { 1476 dma_addr_t paddr; 1477 struct htt_msdu_ext_desc *vaddr; 1478 } frag_desc; 1479 }; 1480 1481 #define RX_HTT_HDR_STATUS_LEN 64 1482 1483 /* This structure layout is programmed via rx ring setup 1484 * so that FW knows how to transfer the rx descriptor to the host. 1485 * Buffers like this are placed on the rx ring. */ 1486 struct htt_rx_desc { 1487 union { 1488 /* This field is filled on the host using the msdu buffer 1489 * from htt_rx_indication */ 1490 struct fw_rx_desc_base fw_desc; 1491 u32 pad; 1492 } __packed; 1493 struct { 1494 struct rx_attention attention; 1495 struct rx_frag_info frag_info; 1496 struct rx_mpdu_start mpdu_start; 1497 struct rx_msdu_start msdu_start; 1498 struct rx_msdu_end msdu_end; 1499 struct rx_mpdu_end mpdu_end; 1500 struct rx_ppdu_start ppdu_start; 1501 struct rx_ppdu_end ppdu_end; 1502 } __packed; 1503 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1504 u8 msdu_payload[0]; 1505 }; 1506 1507 #define HTT_RX_DESC_ALIGN 8 1508 1509 #define HTT_MAC_ADDR_LEN 6 1510 1511 /* 1512 * FIX THIS 1513 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 1514 * rounded up to a cache line size. 1515 */ 1516 #define HTT_RX_BUF_SIZE 1920 1517 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 1518 1519 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 1520 * aggregated traffic more nicely. */ 1521 #define ATH10K_HTT_MAX_NUM_REFILL 16 1522 1523 /* 1524 * DMA_MAP expects the buffer to be an integral number of cache lines. 1525 * Rather than checking the actual cache line size, this code makes a 1526 * conservative estimate of what the cache line size could be. 1527 */ 1528 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 1529 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 1530 1531 int ath10k_htt_connect(struct ath10k_htt *htt); 1532 int ath10k_htt_init(struct ath10k *ar); 1533 int ath10k_htt_setup(struct ath10k_htt *htt); 1534 1535 int ath10k_htt_tx_alloc(struct ath10k_htt *htt); 1536 void ath10k_htt_tx_free(struct ath10k_htt *htt); 1537 1538 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 1539 int ath10k_htt_rx_ring_refill(struct ath10k *ar); 1540 void ath10k_htt_rx_free(struct ath10k_htt *htt); 1541 1542 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1543 void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1544 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 1545 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 1546 int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt); 1547 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt); 1548 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 1549 u8 max_subfrms_ampdu, 1550 u8 max_subfrms_amsdu); 1551 1552 void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 1553 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); 1554 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 1555 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *); 1556 int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *); 1557 1558 #endif 1559