1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HTT_H_ 20 #define _HTT_H_ 21 22 #include <linux/bug.h> 23 #include <linux/interrupt.h> 24 #include <linux/dmapool.h> 25 #include <linux/hashtable.h> 26 #include <linux/kfifo.h> 27 #include <net/mac80211.h> 28 29 #include "htc.h" 30 #include "hw.h" 31 #include "rx_desc.h" 32 #include "hw.h" 33 34 enum htt_dbg_stats_type { 35 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 36 HTT_DBG_STATS_RX_REORDER = 1 << 1, 37 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 38 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 39 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 40 /* bits 5-23 currently reserved */ 41 42 HTT_DBG_NUM_STATS /* keep this last */ 43 }; 44 45 enum htt_h2t_msg_type { /* host-to-target */ 46 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 47 HTT_H2T_MSG_TYPE_TX_FRM = 1, 48 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 49 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 50 HTT_H2T_MSG_TYPE_SYNC = 4, 51 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 52 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 53 54 /* This command is used for sending management frames in HTT < 3.0. 55 * HTT >= 3.0 uses TX_FRM for everything. 56 */ 57 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 58 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11, 59 60 HTT_H2T_NUM_MSGS /* keep this last */ 61 }; 62 63 struct htt_cmd_hdr { 64 u8 msg_type; 65 } __packed; 66 67 struct htt_ver_req { 68 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 69 } __packed; 70 71 /* 72 * HTT tx MSDU descriptor 73 * 74 * The HTT tx MSDU descriptor is created by the host HTT SW for each 75 * tx MSDU. The HTT tx MSDU descriptor contains the information that 76 * the target firmware needs for the FW's tx processing, particularly 77 * for creating the HW msdu descriptor. 78 * The same HTT tx descriptor is used for HL and LL systems, though 79 * a few fields within the tx descriptor are used only by LL or 80 * only by HL. 81 * The HTT tx descriptor is defined in two manners: by a struct with 82 * bitfields, and by a series of [dword offset, bit mask, bit shift] 83 * definitions. 84 * The target should use the struct def, for simplicitly and clarity, 85 * but the host shall use the bit-mast + bit-shift defs, to be endian- 86 * neutral. Specifically, the host shall use the get/set macros built 87 * around the mask + shift defs. 88 */ 89 struct htt_data_tx_desc_frag { 90 union { 91 struct double_word_addr { 92 __le32 paddr; 93 __le32 len; 94 } __packed dword_addr; 95 struct triple_word_addr { 96 __le32 paddr_lo; 97 __le16 paddr_hi; 98 __le16 len_16; 99 } __packed tword_addr; 100 } __packed; 101 } __packed; 102 103 struct htt_msdu_ext_desc { 104 __le32 tso_flag[3]; 105 __le16 ip_identification; 106 u8 flags; 107 u8 reserved; 108 struct htt_data_tx_desc_frag frags[6]; 109 }; 110 111 struct htt_msdu_ext_desc_64 { 112 __le32 tso_flag[5]; 113 __le16 ip_identification; 114 u8 flags; 115 u8 reserved; 116 struct htt_data_tx_desc_frag frags[6]; 117 }; 118 119 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0) 120 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1) 121 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2) 122 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3) 123 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4) 124 125 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \ 126 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \ 127 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \ 128 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \ 129 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE) 130 131 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16) 132 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17) 133 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18) 134 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19) 135 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20) 136 #define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21) 137 138 #define HTT_MSDU_CHECKSUM_ENABLE_64 (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 \ 139 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 \ 140 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 \ 141 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 \ 142 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64) 143 144 enum htt_data_tx_desc_flags0 { 145 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 146 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 147 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 148 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 149 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 150 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 151 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 152 }; 153 154 enum htt_data_tx_desc_flags1 { 155 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 156 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 157 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 158 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 159 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 160 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 161 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 162 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 163 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 164 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 165 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 166 }; 167 168 enum htt_data_tx_ext_tid { 169 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 170 HTT_DATA_TX_EXT_TID_MGMT = 17, 171 HTT_DATA_TX_EXT_TID_INVALID = 31 172 }; 173 174 #define HTT_INVALID_PEERID 0xFFFF 175 176 /* 177 * htt_data_tx_desc - used for data tx path 178 * 179 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 180 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 181 * for special kinds of tids 182 * postponed: only for HL hosts. indicates if this is a resend 183 * (HL hosts manage queues on the host ) 184 * more_in_batch: only for HL hosts. indicates if more packets are 185 * pending. this allows target to wait and aggregate 186 * freq: 0 means home channel of given vdev. intended for offchannel 187 */ 188 struct htt_data_tx_desc { 189 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 190 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 191 __le16 len; 192 __le16 id; 193 __le32 frags_paddr; 194 union { 195 __le32 peerid; 196 struct { 197 __le16 peerid; 198 __le16 freq; 199 } __packed offchan_tx; 200 } __packed; 201 u8 prefetch[0]; /* start of frame, for FW classification engine */ 202 } __packed; 203 204 struct htt_data_tx_desc_64 { 205 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 206 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 207 __le16 len; 208 __le16 id; 209 __le64 frags_paddr; 210 union { 211 __le32 peerid; 212 struct { 213 __le16 peerid; 214 __le16 freq; 215 } __packed offchan_tx; 216 } __packed; 217 u8 prefetch[0]; /* start of frame, for FW classification engine */ 218 } __packed; 219 220 enum htt_rx_ring_flags { 221 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 222 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 223 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 224 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 225 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 226 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 227 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 228 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 229 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 230 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 231 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 232 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 233 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 234 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 235 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 236 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 237 }; 238 239 #define HTT_RX_RING_SIZE_MIN 128 240 #define HTT_RX_RING_SIZE_MAX 2048 241 #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX 242 #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1) 243 #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1) 244 245 struct htt_rx_ring_setup_ring32 { 246 __le32 fw_idx_shadow_reg_paddr; 247 __le32 rx_ring_base_paddr; 248 __le16 rx_ring_len; /* in 4-byte words */ 249 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 250 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 251 __le16 fw_idx_init_val; 252 253 /* the following offsets are in 4-byte units */ 254 __le16 mac80211_hdr_offset; 255 __le16 msdu_payload_offset; 256 __le16 ppdu_start_offset; 257 __le16 ppdu_end_offset; 258 __le16 mpdu_start_offset; 259 __le16 mpdu_end_offset; 260 __le16 msdu_start_offset; 261 __le16 msdu_end_offset; 262 __le16 rx_attention_offset; 263 __le16 frag_info_offset; 264 } __packed; 265 266 struct htt_rx_ring_setup_ring64 { 267 __le64 fw_idx_shadow_reg_paddr; 268 __le64 rx_ring_base_paddr; 269 __le16 rx_ring_len; /* in 4-byte words */ 270 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 271 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 272 __le16 fw_idx_init_val; 273 274 /* the following offsets are in 4-byte units */ 275 __le16 mac80211_hdr_offset; 276 __le16 msdu_payload_offset; 277 __le16 ppdu_start_offset; 278 __le16 ppdu_end_offset; 279 __le16 mpdu_start_offset; 280 __le16 mpdu_end_offset; 281 __le16 msdu_start_offset; 282 __le16 msdu_end_offset; 283 __le16 rx_attention_offset; 284 __le16 frag_info_offset; 285 } __packed; 286 287 struct htt_rx_ring_setup_hdr { 288 u8 num_rings; /* supported values: 1, 2 */ 289 __le16 rsvd0; 290 } __packed; 291 292 struct htt_rx_ring_setup_32 { 293 struct htt_rx_ring_setup_hdr hdr; 294 struct htt_rx_ring_setup_ring32 rings[0]; 295 } __packed; 296 297 struct htt_rx_ring_setup_64 { 298 struct htt_rx_ring_setup_hdr hdr; 299 struct htt_rx_ring_setup_ring64 rings[0]; 300 } __packed; 301 302 /* 303 * htt_stats_req - request target to send specified statistics 304 * 305 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 306 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 307 * so make sure its little-endian. 308 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 309 * so make sure its little-endian. 310 * @cfg_val: stat_type specific configuration 311 * @stat_type: see %htt_dbg_stats_type 312 * @cookie_lsb: used for confirmation message from target->host 313 * @cookie_msb: ditto as %cookie 314 */ 315 struct htt_stats_req { 316 u8 upload_types[3]; 317 u8 rsvd0; 318 u8 reset_types[3]; 319 struct { 320 u8 mpdu_bytes; 321 u8 mpdu_num_msdus; 322 u8 msdu_bytes; 323 } __packed; 324 u8 stat_type; 325 __le32 cookie_lsb; 326 __le32 cookie_msb; 327 } __packed; 328 329 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 330 331 /* 332 * htt_oob_sync_req - request out-of-band sync 333 * 334 * The HTT SYNC tells the target to suspend processing of subsequent 335 * HTT host-to-target messages until some other target agent locally 336 * informs the target HTT FW that the current sync counter is equal to 337 * or greater than (in a modulo sense) the sync counter specified in 338 * the SYNC message. 339 * 340 * This allows other host-target components to synchronize their operation 341 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 342 * security key has been downloaded to and activated by the target. 343 * In the absence of any explicit synchronization counter value 344 * specification, the target HTT FW will use zero as the default current 345 * sync value. 346 * 347 * The HTT target FW will suspend its host->target message processing as long 348 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 349 */ 350 struct htt_oob_sync_req { 351 u8 sync_count; 352 __le16 rsvd0; 353 } __packed; 354 355 struct htt_aggr_conf { 356 u8 max_num_ampdu_subframes; 357 /* amsdu_subframes is limited by 0x1F mask */ 358 u8 max_num_amsdu_subframes; 359 } __packed; 360 361 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 362 struct htt_mgmt_tx_desc_qca99x0 { 363 __le32 rate; 364 } __packed; 365 366 struct htt_mgmt_tx_desc { 367 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 368 __le32 msdu_paddr; 369 __le32 desc_id; 370 __le32 len; 371 __le32 vdev_id; 372 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 373 union { 374 struct htt_mgmt_tx_desc_qca99x0 qca99x0; 375 } __packed; 376 } __packed; 377 378 enum htt_mgmt_tx_status { 379 HTT_MGMT_TX_STATUS_OK = 0, 380 HTT_MGMT_TX_STATUS_RETRY = 1, 381 HTT_MGMT_TX_STATUS_DROP = 2 382 }; 383 384 /*=== target -> host messages ===============================================*/ 385 386 enum htt_main_t2h_msg_type { 387 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0, 388 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1, 389 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2, 390 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3, 391 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 392 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5, 393 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6, 394 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 395 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8, 396 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9, 397 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 398 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb, 399 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 400 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 401 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 402 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10, 403 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 404 HTT_MAIN_T2H_MSG_TYPE_TEST, 405 /* keep this last */ 406 HTT_MAIN_T2H_NUM_MSGS 407 }; 408 409 enum htt_10x_t2h_msg_type { 410 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0, 411 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1, 412 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2, 413 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3, 414 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 415 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5, 416 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6, 417 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 418 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8, 419 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9, 420 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 421 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb, 422 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 423 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 424 HTT_10X_T2H_MSG_TYPE_TEST = 0xe, 425 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 426 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11, 427 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12, 428 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13, 429 /* keep this last */ 430 HTT_10X_T2H_NUM_MSGS 431 }; 432 433 enum htt_tlv_t2h_msg_type { 434 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0, 435 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1, 436 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2, 437 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3, 438 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 439 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5, 440 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6, 441 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 442 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8, 443 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9, 444 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 445 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb, 446 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */ 447 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 448 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 449 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 450 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10, 451 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 452 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 453 /* 0x13 reservd */ 454 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 455 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 456 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 457 HTT_TLV_T2H_MSG_TYPE_TEST, 458 /* keep this last */ 459 HTT_TLV_T2H_NUM_MSGS 460 }; 461 462 enum htt_10_4_t2h_msg_type { 463 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0, 464 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1, 465 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2, 466 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3, 467 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 468 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5, 469 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6, 470 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 471 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8, 472 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9, 473 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 474 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb, 475 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 476 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 477 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 478 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 479 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10, 480 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11, 481 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12, 482 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13, 483 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14, 484 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15, 485 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16, 486 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17, 487 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18, 488 /* 0x19 to 0x2f are reserved */ 489 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30, 490 HTT_10_4_T2H_MSG_TYPE_PEER_STATS = 0x31, 491 /* keep this last */ 492 HTT_10_4_T2H_NUM_MSGS 493 }; 494 495 enum htt_t2h_msg_type { 496 HTT_T2H_MSG_TYPE_VERSION_CONF, 497 HTT_T2H_MSG_TYPE_RX_IND, 498 HTT_T2H_MSG_TYPE_RX_FLUSH, 499 HTT_T2H_MSG_TYPE_PEER_MAP, 500 HTT_T2H_MSG_TYPE_PEER_UNMAP, 501 HTT_T2H_MSG_TYPE_RX_ADDBA, 502 HTT_T2H_MSG_TYPE_RX_DELBA, 503 HTT_T2H_MSG_TYPE_TX_COMPL_IND, 504 HTT_T2H_MSG_TYPE_PKTLOG, 505 HTT_T2H_MSG_TYPE_STATS_CONF, 506 HTT_T2H_MSG_TYPE_RX_FRAG_IND, 507 HTT_T2H_MSG_TYPE_SEC_IND, 508 HTT_T2H_MSG_TYPE_RC_UPDATE_IND, 509 HTT_T2H_MSG_TYPE_TX_INSPECT_IND, 510 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION, 511 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, 512 HTT_T2H_MSG_TYPE_RX_PN_IND, 513 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND, 514 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND, 515 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE, 516 HTT_T2H_MSG_TYPE_CHAN_CHANGE, 517 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR, 518 HTT_T2H_MSG_TYPE_AGGR_CONF, 519 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, 520 HTT_T2H_MSG_TYPE_TEST, 521 HTT_T2H_MSG_TYPE_EN_STATS, 522 HTT_T2H_MSG_TYPE_TX_FETCH_IND, 523 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM, 524 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND, 525 HTT_T2H_MSG_TYPE_PEER_STATS, 526 /* keep this last */ 527 HTT_T2H_NUM_MSGS 528 }; 529 530 /* 531 * htt_resp_hdr - header for target-to-host messages 532 * 533 * msg_type: see htt_t2h_msg_type 534 */ 535 struct htt_resp_hdr { 536 u8 msg_type; 537 } __packed; 538 539 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 540 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 541 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 542 543 /* htt_ver_resp - response sent for htt_ver_req */ 544 struct htt_ver_resp { 545 u8 minor; 546 u8 major; 547 u8 rsvd0; 548 } __packed; 549 550 #define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI BIT(0) 551 552 #define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK GENMASK(7, 0) 553 554 struct htt_mgmt_tx_completion { 555 u8 rsvd0; 556 u8 rsvd1; 557 u8 flags; 558 __le32 desc_id; 559 __le32 status; 560 __le32 ppdu_id; 561 __le32 info; 562 } __packed; 563 564 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F) 565 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 566 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5) 567 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6) 568 569 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 570 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 571 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 572 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 573 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 574 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 575 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 576 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 577 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 578 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 579 580 struct htt_rx_indication_hdr { 581 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 582 __le16 peer_id; 583 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 584 } __packed; 585 586 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 587 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 588 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 589 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 590 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 591 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 592 593 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 594 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 595 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 596 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 597 598 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 599 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 600 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 601 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 602 603 enum htt_rx_legacy_rate { 604 HTT_RX_OFDM_48 = 0, 605 HTT_RX_OFDM_24 = 1, 606 HTT_RX_OFDM_12, 607 HTT_RX_OFDM_6, 608 HTT_RX_OFDM_54, 609 HTT_RX_OFDM_36, 610 HTT_RX_OFDM_18, 611 HTT_RX_OFDM_9, 612 613 /* long preamble */ 614 HTT_RX_CCK_11_LP = 0, 615 HTT_RX_CCK_5_5_LP = 1, 616 HTT_RX_CCK_2_LP, 617 HTT_RX_CCK_1_LP, 618 /* short preamble */ 619 HTT_RX_CCK_11_SP, 620 HTT_RX_CCK_5_5_SP, 621 HTT_RX_CCK_2_SP 622 }; 623 624 enum htt_rx_legacy_rate_type { 625 HTT_RX_LEGACY_RATE_OFDM = 0, 626 HTT_RX_LEGACY_RATE_CCK 627 }; 628 629 enum htt_rx_preamble_type { 630 HTT_RX_LEGACY = 0x4, 631 HTT_RX_HT = 0x8, 632 HTT_RX_HT_WITH_TXBF = 0x9, 633 HTT_RX_VHT = 0xC, 634 HTT_RX_VHT_WITH_TXBF = 0xD, 635 }; 636 637 /* 638 * Fields: phy_err_valid, phy_err_code, tsf, 639 * usec_timestamp, sub_usec_timestamp 640 * ..are valid only if end_valid == 1. 641 * 642 * Fields: rssi_chains, legacy_rate_type, 643 * legacy_rate_cck, preamble_type, service, 644 * vht_sig_* 645 * ..are valid only if start_valid == 1; 646 */ 647 struct htt_rx_indication_ppdu { 648 u8 combined_rssi; 649 u8 sub_usec_timestamp; 650 u8 phy_err_code; 651 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 652 struct { 653 u8 pri20_db; 654 u8 ext20_db; 655 u8 ext40_db; 656 u8 ext80_db; 657 } __packed rssi_chains[4]; 658 __le32 tsf; 659 __le32 usec_timestamp; 660 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 661 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 662 } __packed; 663 664 enum htt_rx_mpdu_status { 665 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 666 HTT_RX_IND_MPDU_STATUS_OK, 667 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 668 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 669 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 670 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 671 /* only accept EAPOL frames */ 672 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 673 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 674 /* Non-data in promiscuous mode */ 675 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 676 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 677 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 678 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 679 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 680 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 681 682 /* 683 * MISC: discard for unspecified reasons. 684 * Leave this enum value last. 685 */ 686 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 687 }; 688 689 struct htt_rx_indication_mpdu_range { 690 u8 mpdu_count; 691 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 692 u8 pad0; 693 u8 pad1; 694 } __packed; 695 696 struct htt_rx_indication_prefix { 697 __le16 fw_rx_desc_bytes; 698 u8 pad0; 699 u8 pad1; 700 }; 701 702 struct htt_rx_indication { 703 struct htt_rx_indication_hdr hdr; 704 struct htt_rx_indication_ppdu ppdu; 705 struct htt_rx_indication_prefix prefix; 706 707 /* 708 * the following fields are both dynamically sized, so 709 * take care addressing them 710 */ 711 712 /* the size of this is %fw_rx_desc_bytes */ 713 struct fw_rx_desc_base fw_desc; 714 715 /* 716 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 717 * and has %num_mpdu_ranges elements. 718 */ 719 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 720 } __packed; 721 722 static inline struct htt_rx_indication_mpdu_range * 723 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 724 { 725 void *ptr = rx_ind; 726 727 ptr += sizeof(rx_ind->hdr) 728 + sizeof(rx_ind->ppdu) 729 + sizeof(rx_ind->prefix) 730 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 731 return ptr; 732 } 733 734 enum htt_rx_flush_mpdu_status { 735 HTT_RX_FLUSH_MPDU_DISCARD = 0, 736 HTT_RX_FLUSH_MPDU_REORDER = 1, 737 }; 738 739 /* 740 * htt_rx_flush - discard or reorder given range of mpdus 741 * 742 * Note: host must check if all sequence numbers between 743 * [seq_num_start, seq_num_end-1] are valid. 744 */ 745 struct htt_rx_flush { 746 __le16 peer_id; 747 u8 tid; 748 u8 rsvd0; 749 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 750 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 751 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 752 }; 753 754 struct htt_rx_peer_map { 755 u8 vdev_id; 756 __le16 peer_id; 757 u8 addr[6]; 758 u8 rsvd0; 759 u8 rsvd1; 760 } __packed; 761 762 struct htt_rx_peer_unmap { 763 u8 rsvd0; 764 __le16 peer_id; 765 } __packed; 766 767 enum htt_security_types { 768 HTT_SECURITY_NONE, 769 HTT_SECURITY_WEP128, 770 HTT_SECURITY_WEP104, 771 HTT_SECURITY_WEP40, 772 HTT_SECURITY_TKIP, 773 HTT_SECURITY_TKIP_NOMIC, 774 HTT_SECURITY_AES_CCMP, 775 HTT_SECURITY_WAPI, 776 777 HTT_NUM_SECURITY_TYPES /* keep this last! */ 778 }; 779 780 enum htt_security_flags { 781 #define HTT_SECURITY_TYPE_MASK 0x7F 782 #define HTT_SECURITY_TYPE_LSB 0 783 HTT_SECURITY_IS_UNICAST = 1 << 7 784 }; 785 786 struct htt_security_indication { 787 union { 788 /* dont use bitfields; undefined behaviour */ 789 u8 flags; /* %htt_security_flags */ 790 struct { 791 u8 security_type:7, /* %htt_security_types */ 792 is_unicast:1; 793 } __packed; 794 } __packed; 795 __le16 peer_id; 796 u8 michael_key[8]; 797 u8 wapi_rsc[16]; 798 } __packed; 799 800 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 801 #define HTT_RX_BA_INFO0_TID_LSB 0 802 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 803 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 804 805 struct htt_rx_addba { 806 u8 window_size; 807 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 808 } __packed; 809 810 struct htt_rx_delba { 811 u8 rsvd0; 812 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 813 } __packed; 814 815 enum htt_data_tx_status { 816 HTT_DATA_TX_STATUS_OK = 0, 817 HTT_DATA_TX_STATUS_DISCARD = 1, 818 HTT_DATA_TX_STATUS_NO_ACK = 2, 819 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 820 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 821 }; 822 823 enum htt_data_tx_flags { 824 #define HTT_DATA_TX_STATUS_MASK 0x07 825 #define HTT_DATA_TX_STATUS_LSB 0 826 #define HTT_DATA_TX_TID_MASK 0x78 827 #define HTT_DATA_TX_TID_LSB 3 828 HTT_DATA_TX_TID_INVALID = 1 << 7 829 }; 830 831 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 832 833 struct htt_data_tx_completion { 834 union { 835 u8 flags; 836 struct { 837 u8 status:3, 838 tid:4, 839 tid_invalid:1; 840 } __packed; 841 } __packed; 842 u8 num_msdus; 843 u8 rsvd0; 844 __le16 msdus[0]; /* variable length based on %num_msdus */ 845 } __packed; 846 847 struct htt_tx_compl_ind_base { 848 u32 hdr; 849 u16 payload[1/*or more*/]; 850 } __packed; 851 852 struct htt_rc_tx_done_params { 853 u32 rate_code; 854 u32 rate_code_flags; 855 u32 flags; 856 u32 num_enqued; /* 1 for non-AMPDU */ 857 u32 num_retries; 858 u32 num_failed; /* for AMPDU */ 859 u32 ack_rssi; 860 u32 time_stamp; 861 u32 is_probe; 862 }; 863 864 struct htt_rc_update { 865 u8 vdev_id; 866 __le16 peer_id; 867 u8 addr[6]; 868 u8 num_elems; 869 u8 rsvd0; 870 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 871 } __packed; 872 873 /* see htt_rx_indication for similar fields and descriptions */ 874 struct htt_rx_fragment_indication { 875 union { 876 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 877 struct { 878 u8 ext_tid:5, 879 flush_valid:1; 880 } __packed; 881 } __packed; 882 __le16 peer_id; 883 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 884 __le16 fw_rx_desc_bytes; 885 __le16 rsvd0; 886 887 u8 fw_msdu_rx_desc[0]; 888 } __packed; 889 890 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 891 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 892 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 893 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 894 895 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 896 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 897 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 898 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 899 900 struct htt_rx_pn_ind { 901 __le16 peer_id; 902 u8 tid; 903 u8 seqno_start; 904 u8 seqno_end; 905 u8 pn_ie_count; 906 u8 reserved; 907 u8 pn_ies[0]; 908 } __packed; 909 910 struct htt_rx_offload_msdu { 911 __le16 msdu_len; 912 __le16 peer_id; 913 u8 vdev_id; 914 u8 tid; 915 u8 fw_desc; 916 u8 payload[0]; 917 } __packed; 918 919 struct htt_rx_offload_ind { 920 u8 reserved; 921 __le16 msdu_count; 922 } __packed; 923 924 struct htt_rx_in_ord_msdu_desc { 925 __le32 msdu_paddr; 926 __le16 msdu_len; 927 u8 fw_desc; 928 u8 reserved; 929 } __packed; 930 931 struct htt_rx_in_ord_msdu_desc_ext { 932 __le64 msdu_paddr; 933 __le16 msdu_len; 934 u8 fw_desc; 935 u8 reserved; 936 } __packed; 937 938 struct htt_rx_in_ord_ind { 939 u8 info; 940 __le16 peer_id; 941 u8 vdev_id; 942 u8 reserved; 943 __le16 msdu_count; 944 union { 945 struct htt_rx_in_ord_msdu_desc msdu_descs32[0]; 946 struct htt_rx_in_ord_msdu_desc_ext msdu_descs64[0]; 947 } __packed; 948 } __packed; 949 950 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f 951 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 952 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020 953 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 954 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040 955 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 956 957 /* 958 * target -> host test message definition 959 * 960 * The following field definitions describe the format of the test 961 * message sent from the target to the host. 962 * The message consists of a 4-octet header, followed by a variable 963 * number of 32-bit integer values, followed by a variable number 964 * of 8-bit character values. 965 * 966 * |31 16|15 8|7 0| 967 * |-----------------------------------------------------------| 968 * | num chars | num ints | msg type | 969 * |-----------------------------------------------------------| 970 * | int 0 | 971 * |-----------------------------------------------------------| 972 * | int 1 | 973 * |-----------------------------------------------------------| 974 * | ... | 975 * |-----------------------------------------------------------| 976 * | char 3 | char 2 | char 1 | char 0 | 977 * |-----------------------------------------------------------| 978 * | | | ... | char 4 | 979 * |-----------------------------------------------------------| 980 * - MSG_TYPE 981 * Bits 7:0 982 * Purpose: identifies this as a test message 983 * Value: HTT_MSG_TYPE_TEST 984 * - NUM_INTS 985 * Bits 15:8 986 * Purpose: indicate how many 32-bit integers follow the message header 987 * - NUM_CHARS 988 * Bits 31:16 989 * Purpose: indicate how many 8-bit characters follow the series of integers 990 */ 991 struct htt_rx_test { 992 u8 num_ints; 993 __le16 num_chars; 994 995 /* payload consists of 2 lists: 996 * a) num_ints * sizeof(__le32) 997 * b) num_chars * sizeof(u8) aligned to 4bytes 998 */ 999 u8 payload[0]; 1000 } __packed; 1001 1002 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 1003 { 1004 return (__le32 *)rx_test->payload; 1005 } 1006 1007 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 1008 { 1009 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 1010 } 1011 1012 /* 1013 * target -> host packet log message 1014 * 1015 * The following field definitions describe the format of the packet log 1016 * message sent from the target to the host. 1017 * The message consists of a 4-octet header,followed by a variable number 1018 * of 32-bit character values. 1019 * 1020 * |31 24|23 16|15 8|7 0| 1021 * |-----------------------------------------------------------| 1022 * | | | | msg type | 1023 * |-----------------------------------------------------------| 1024 * | payload | 1025 * |-----------------------------------------------------------| 1026 * - MSG_TYPE 1027 * Bits 7:0 1028 * Purpose: identifies this as a test message 1029 * Value: HTT_MSG_TYPE_PACKETLOG 1030 */ 1031 struct htt_pktlog_msg { 1032 u8 pad[3]; 1033 u8 payload[0]; 1034 } __packed; 1035 1036 struct htt_dbg_stats_rx_reorder_stats { 1037 /* Non QoS MPDUs received */ 1038 __le32 deliver_non_qos; 1039 1040 /* MPDUs received in-order */ 1041 __le32 deliver_in_order; 1042 1043 /* Flush due to reorder timer expired */ 1044 __le32 deliver_flush_timeout; 1045 1046 /* Flush due to move out of window */ 1047 __le32 deliver_flush_oow; 1048 1049 /* Flush due to DELBA */ 1050 __le32 deliver_flush_delba; 1051 1052 /* MPDUs dropped due to FCS error */ 1053 __le32 fcs_error; 1054 1055 /* MPDUs dropped due to monitor mode non-data packet */ 1056 __le32 mgmt_ctrl; 1057 1058 /* MPDUs dropped due to invalid peer */ 1059 __le32 invalid_peer; 1060 1061 /* MPDUs dropped due to duplication (non aggregation) */ 1062 __le32 dup_non_aggr; 1063 1064 /* MPDUs dropped due to processed before */ 1065 __le32 dup_past; 1066 1067 /* MPDUs dropped due to duplicate in reorder queue */ 1068 __le32 dup_in_reorder; 1069 1070 /* Reorder timeout happened */ 1071 __le32 reorder_timeout; 1072 1073 /* invalid bar ssn */ 1074 __le32 invalid_bar_ssn; 1075 1076 /* reorder reset due to bar ssn */ 1077 __le32 ssn_reset; 1078 }; 1079 1080 struct htt_dbg_stats_wal_tx_stats { 1081 /* Num HTT cookies queued to dispatch list */ 1082 __le32 comp_queued; 1083 1084 /* Num HTT cookies dispatched */ 1085 __le32 comp_delivered; 1086 1087 /* Num MSDU queued to WAL */ 1088 __le32 msdu_enqued; 1089 1090 /* Num MPDU queue to WAL */ 1091 __le32 mpdu_enqued; 1092 1093 /* Num MSDUs dropped by WMM limit */ 1094 __le32 wmm_drop; 1095 1096 /* Num Local frames queued */ 1097 __le32 local_enqued; 1098 1099 /* Num Local frames done */ 1100 __le32 local_freed; 1101 1102 /* Num queued to HW */ 1103 __le32 hw_queued; 1104 1105 /* Num PPDU reaped from HW */ 1106 __le32 hw_reaped; 1107 1108 /* Num underruns */ 1109 __le32 underrun; 1110 1111 /* Num PPDUs cleaned up in TX abort */ 1112 __le32 tx_abort; 1113 1114 /* Num MPDUs requed by SW */ 1115 __le32 mpdus_requed; 1116 1117 /* excessive retries */ 1118 __le32 tx_ko; 1119 1120 /* data hw rate code */ 1121 __le32 data_rc; 1122 1123 /* Scheduler self triggers */ 1124 __le32 self_triggers; 1125 1126 /* frames dropped due to excessive sw retries */ 1127 __le32 sw_retry_failure; 1128 1129 /* illegal rate phy errors */ 1130 __le32 illgl_rate_phy_err; 1131 1132 /* wal pdev continuous xretry */ 1133 __le32 pdev_cont_xretry; 1134 1135 /* wal pdev continuous xretry */ 1136 __le32 pdev_tx_timeout; 1137 1138 /* wal pdev resets */ 1139 __le32 pdev_resets; 1140 1141 __le32 phy_underrun; 1142 1143 /* MPDU is more than txop limit */ 1144 __le32 txop_ovf; 1145 } __packed; 1146 1147 struct htt_dbg_stats_wal_rx_stats { 1148 /* Cnts any change in ring routing mid-ppdu */ 1149 __le32 mid_ppdu_route_change; 1150 1151 /* Total number of statuses processed */ 1152 __le32 status_rcvd; 1153 1154 /* Extra frags on rings 0-3 */ 1155 __le32 r0_frags; 1156 __le32 r1_frags; 1157 __le32 r2_frags; 1158 __le32 r3_frags; 1159 1160 /* MSDUs / MPDUs delivered to HTT */ 1161 __le32 htt_msdus; 1162 __le32 htt_mpdus; 1163 1164 /* MSDUs / MPDUs delivered to local stack */ 1165 __le32 loc_msdus; 1166 __le32 loc_mpdus; 1167 1168 /* AMSDUs that have more MSDUs than the status ring size */ 1169 __le32 oversize_amsdu; 1170 1171 /* Number of PHY errors */ 1172 __le32 phy_errs; 1173 1174 /* Number of PHY errors drops */ 1175 __le32 phy_err_drop; 1176 1177 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1178 __le32 mpdu_errs; 1179 } __packed; 1180 1181 struct htt_dbg_stats_wal_peer_stats { 1182 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 1183 } __packed; 1184 1185 struct htt_dbg_stats_wal_pdev_txrx { 1186 struct htt_dbg_stats_wal_tx_stats tx_stats; 1187 struct htt_dbg_stats_wal_rx_stats rx_stats; 1188 struct htt_dbg_stats_wal_peer_stats peer_stats; 1189 } __packed; 1190 1191 struct htt_dbg_stats_rx_rate_info { 1192 __le32 mcs[10]; 1193 __le32 sgi[10]; 1194 __le32 nss[4]; 1195 __le32 stbc[10]; 1196 __le32 bw[3]; 1197 __le32 pream[6]; 1198 __le32 ldpc; 1199 __le32 txbf; 1200 }; 1201 1202 /* 1203 * htt_dbg_stats_status - 1204 * present - The requested stats have been delivered in full. 1205 * This indicates that either the stats information was contained 1206 * in its entirety within this message, or else this message 1207 * completes the delivery of the requested stats info that was 1208 * partially delivered through earlier STATS_CONF messages. 1209 * partial - The requested stats have been delivered in part. 1210 * One or more subsequent STATS_CONF messages with the same 1211 * cookie value will be sent to deliver the remainder of the 1212 * information. 1213 * error - The requested stats could not be delivered, for example due 1214 * to a shortage of memory to construct a message holding the 1215 * requested stats. 1216 * invalid - The requested stat type is either not recognized, or the 1217 * target is configured to not gather the stats type in question. 1218 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1219 * series_done - This special value indicates that no further stats info 1220 * elements are present within a series of stats info elems 1221 * (within a stats upload confirmation message). 1222 */ 1223 enum htt_dbg_stats_status { 1224 HTT_DBG_STATS_STATUS_PRESENT = 0, 1225 HTT_DBG_STATS_STATUS_PARTIAL = 1, 1226 HTT_DBG_STATS_STATUS_ERROR = 2, 1227 HTT_DBG_STATS_STATUS_INVALID = 3, 1228 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 1229 }; 1230 1231 /* 1232 * target -> host statistics upload 1233 * 1234 * The following field definitions describe the format of the HTT target 1235 * to host stats upload confirmation message. 1236 * The message contains a cookie echoed from the HTT host->target stats 1237 * upload request, which identifies which request the confirmation is 1238 * for, and a series of tag-length-value stats information elements. 1239 * The tag-length header for each stats info element also includes a 1240 * status field, to indicate whether the request for the stat type in 1241 * question was fully met, partially met, unable to be met, or invalid 1242 * (if the stat type in question is disabled in the target). 1243 * A special value of all 1's in this status field is used to indicate 1244 * the end of the series of stats info elements. 1245 * 1246 * 1247 * |31 16|15 8|7 5|4 0| 1248 * |------------------------------------------------------------| 1249 * | reserved | msg type | 1250 * |------------------------------------------------------------| 1251 * | cookie LSBs | 1252 * |------------------------------------------------------------| 1253 * | cookie MSBs | 1254 * |------------------------------------------------------------| 1255 * | stats entry length | reserved | S |stat type| 1256 * |------------------------------------------------------------| 1257 * | | 1258 * | type-specific stats info | 1259 * | | 1260 * |------------------------------------------------------------| 1261 * | stats entry length | reserved | S |stat type| 1262 * |------------------------------------------------------------| 1263 * | | 1264 * | type-specific stats info | 1265 * | | 1266 * |------------------------------------------------------------| 1267 * | n/a | reserved | 111 | n/a | 1268 * |------------------------------------------------------------| 1269 * Header fields: 1270 * - MSG_TYPE 1271 * Bits 7:0 1272 * Purpose: identifies this is a statistics upload confirmation message 1273 * Value: 0x9 1274 * - COOKIE_LSBS 1275 * Bits 31:0 1276 * Purpose: Provide a mechanism to match a target->host stats confirmation 1277 * message with its preceding host->target stats request message. 1278 * Value: LSBs of the opaque cookie specified by the host-side requestor 1279 * - COOKIE_MSBS 1280 * Bits 31:0 1281 * Purpose: Provide a mechanism to match a target->host stats confirmation 1282 * message with its preceding host->target stats request message. 1283 * Value: MSBs of the opaque cookie specified by the host-side requestor 1284 * 1285 * Stats Information Element tag-length header fields: 1286 * - STAT_TYPE 1287 * Bits 4:0 1288 * Purpose: identifies the type of statistics info held in the 1289 * following information element 1290 * Value: htt_dbg_stats_type 1291 * - STATUS 1292 * Bits 7:5 1293 * Purpose: indicate whether the requested stats are present 1294 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 1295 * the completion of the stats entry series 1296 * - LENGTH 1297 * Bits 31:16 1298 * Purpose: indicate the stats information size 1299 * Value: This field specifies the number of bytes of stats information 1300 * that follows the element tag-length header. 1301 * It is expected but not required that this length is a multiple of 1302 * 4 bytes. Even if the length is not an integer multiple of 4, the 1303 * subsequent stats entry header will begin on a 4-byte aligned 1304 * boundary. 1305 */ 1306 1307 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1308 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1309 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1310 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1311 1312 struct htt_stats_conf_item { 1313 union { 1314 u8 info; 1315 struct { 1316 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1317 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1318 } __packed; 1319 } __packed; 1320 u8 pad; 1321 __le16 length; 1322 u8 payload[0]; /* roundup(length, 4) long */ 1323 } __packed; 1324 1325 struct htt_stats_conf { 1326 u8 pad[3]; 1327 __le32 cookie_lsb; 1328 __le32 cookie_msb; 1329 1330 /* each item has variable length! */ 1331 struct htt_stats_conf_item items[0]; 1332 } __packed; 1333 1334 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1335 const struct htt_stats_conf_item *item) 1336 { 1337 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1338 } 1339 1340 /* 1341 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1342 * 1343 * The following field definitions describe the format of the HTT host 1344 * to target frag_desc/msdu_ext bank configuration message. 1345 * The message contains the based address and the min and max id of the 1346 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1347 * MSDU_EXT/FRAG_DESC. 1348 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1349 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1350 * the hardware does the mapping/translation. 1351 * 1352 * Total banks that can be configured is configured to 16. 1353 * 1354 * This should be called before any TX has be initiated by the HTT 1355 * 1356 * |31 16|15 8|7 5|4 0| 1357 * |------------------------------------------------------------| 1358 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1359 * |------------------------------------------------------------| 1360 * | BANK0_BASE_ADDRESS | 1361 * |------------------------------------------------------------| 1362 * | ... | 1363 * |------------------------------------------------------------| 1364 * | BANK15_BASE_ADDRESS | 1365 * |------------------------------------------------------------| 1366 * | BANK0_MAX_ID | BANK0_MIN_ID | 1367 * |------------------------------------------------------------| 1368 * | ... | 1369 * |------------------------------------------------------------| 1370 * | BANK15_MAX_ID | BANK15_MIN_ID | 1371 * |------------------------------------------------------------| 1372 * Header fields: 1373 * - MSG_TYPE 1374 * Bits 7:0 1375 * Value: 0x6 1376 * - BANKx_BASE_ADDRESS 1377 * Bits 31:0 1378 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1379 * bank physical/bus address. 1380 * - BANKx_MIN_ID 1381 * Bits 15:0 1382 * Purpose: Provide a mechanism to specify the min index that needs to 1383 * mapped. 1384 * - BANKx_MAX_ID 1385 * Bits 31:16 1386 * Purpose: Provide a mechanism to specify the max index that needs to 1387 * 1388 */ 1389 struct htt_frag_desc_bank_id { 1390 __le16 bank_min_id; 1391 __le16 bank_max_id; 1392 } __packed; 1393 1394 /* real is 16 but it wouldn't fit in the max htt message size 1395 * so we use a conservatively safe value for now 1396 */ 1397 #define HTT_FRAG_DESC_BANK_MAX 4 1398 1399 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1400 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1401 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2) 1402 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3) 1403 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4) 1404 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4 1405 1406 enum htt_q_depth_type { 1407 HTT_Q_DEPTH_TYPE_BYTES = 0, 1408 HTT_Q_DEPTH_TYPE_MSDUS = 1, 1409 }; 1410 1411 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \ 1412 TARGET_10_4_NUM_VDEVS) 1413 #define HTT_TX_Q_STATE_NUM_TIDS 8 1414 #define HTT_TX_Q_STATE_ENTRY_SIZE 1 1415 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0 1416 1417 /** 1418 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config 1419 * 1420 * Defines host q state format and behavior. See htt_q_state. 1421 * 1422 * @record_size: Defines the size of each host q entry in bytes. In practice 1423 * however firmware (at least 10.4.3-00191) ignores this host 1424 * configuration value and uses hardcoded value of 1. 1425 * @record_multiplier: This is valid only when q depth type is MSDUs. It 1426 * defines the exponent for the power of 2 multiplication. 1427 */ 1428 struct htt_q_state_conf { 1429 __le32 paddr; 1430 __le16 num_peers; 1431 __le16 num_tids; 1432 u8 record_size; 1433 u8 record_multiplier; 1434 u8 pad[2]; 1435 } __packed; 1436 1437 struct htt_frag_desc_bank_cfg32 { 1438 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1439 u8 num_banks; 1440 u8 desc_size; 1441 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1442 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1443 struct htt_q_state_conf q_state; 1444 } __packed; 1445 1446 struct htt_frag_desc_bank_cfg64 { 1447 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1448 u8 num_banks; 1449 u8 desc_size; 1450 __le64 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1451 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1452 struct htt_q_state_conf q_state; 1453 } __packed; 1454 1455 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128 1456 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f 1457 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0 1458 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0 1459 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6 1460 1461 /** 1462 * htt_q_state - shared between host and firmware via DMA 1463 * 1464 * This structure is used for the host to expose it's software queue state to 1465 * firmware so that its rate control can schedule fetch requests for optimized 1466 * performance. This is most notably used for MU-MIMO aggregation when multiple 1467 * MU clients are connected. 1468 * 1469 * @count: Each element defines the host queue depth. When q depth type was 1470 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as: 1471 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and 1472 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as 1473 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 ** 1474 * record_multiplier (see htt_q_state_conf). 1475 * @map: Used by firmware to quickly check which host queues are not empty. It 1476 * is a bitmap simply saying. 1477 * @seq: Used by firmware to quickly check if the host queues were updated 1478 * since it last checked. 1479 * 1480 * FIXME: Is the q_state map[] size calculation really correct? 1481 */ 1482 struct htt_q_state { 1483 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS]; 1484 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32]; 1485 __le32 seq; 1486 } __packed; 1487 1488 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff 1489 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0 1490 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000 1491 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12 1492 1493 struct htt_tx_fetch_record { 1494 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */ 1495 __le16 num_msdus; 1496 __le32 num_bytes; 1497 } __packed; 1498 1499 struct htt_tx_fetch_ind { 1500 u8 pad0; 1501 __le16 fetch_seq_num; 1502 __le32 token; 1503 __le16 num_resp_ids; 1504 __le16 num_records; 1505 struct htt_tx_fetch_record records[0]; 1506 __le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */ 1507 } __packed; 1508 1509 static inline void * 1510 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind) 1511 { 1512 return (void *)&ind->records[le16_to_cpu(ind->num_records)]; 1513 } 1514 1515 struct htt_tx_fetch_resp { 1516 u8 pad0; 1517 __le16 resp_id; 1518 __le16 fetch_seq_num; 1519 __le16 num_records; 1520 __le32 token; 1521 struct htt_tx_fetch_record records[0]; 1522 } __packed; 1523 1524 struct htt_tx_fetch_confirm { 1525 u8 pad0; 1526 __le16 num_resp_ids; 1527 __le32 resp_ids[0]; 1528 } __packed; 1529 1530 enum htt_tx_mode_switch_mode { 1531 HTT_TX_MODE_SWITCH_PUSH = 0, 1532 HTT_TX_MODE_SWITCH_PUSH_PULL = 1, 1533 }; 1534 1535 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0) 1536 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe 1537 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1 1538 1539 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003 1540 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0 1541 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc 1542 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2 1543 1544 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff 1545 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0 1546 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000 1547 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12 1548 1549 struct htt_tx_mode_switch_record { 1550 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */ 1551 __le16 num_max_msdus; 1552 } __packed; 1553 1554 struct htt_tx_mode_switch_ind { 1555 u8 pad0; 1556 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */ 1557 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */ 1558 u8 pad1[2]; 1559 struct htt_tx_mode_switch_record records[0]; 1560 } __packed; 1561 1562 struct htt_channel_change { 1563 u8 pad[3]; 1564 __le32 freq; 1565 __le32 center_freq1; 1566 __le32 center_freq2; 1567 __le32 phymode; 1568 } __packed; 1569 1570 struct htt_per_peer_tx_stats_ind { 1571 __le32 succ_bytes; 1572 __le32 retry_bytes; 1573 __le32 failed_bytes; 1574 u8 ratecode; 1575 u8 flags; 1576 __le16 peer_id; 1577 __le16 succ_pkts; 1578 __le16 retry_pkts; 1579 __le16 failed_pkts; 1580 __le16 tx_duration; 1581 __le32 reserved1; 1582 __le32 reserved2; 1583 } __packed; 1584 1585 struct htt_peer_tx_stats { 1586 u8 num_ppdu; 1587 u8 ppdu_len; 1588 u8 version; 1589 u8 payload[0]; 1590 } __packed; 1591 1592 #define ATH10K_10_2_TX_STATS_OFFSET 136 1593 #define PEER_STATS_FOR_NO_OF_PPDUS 4 1594 1595 struct ath10k_10_2_peer_tx_stats { 1596 u8 ratecode[PEER_STATS_FOR_NO_OF_PPDUS]; 1597 u8 success_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1598 __le16 success_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1599 u8 retry_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1600 __le16 retry_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1601 u8 failed_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1602 __le16 failed_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1603 u8 flags[PEER_STATS_FOR_NO_OF_PPDUS]; 1604 __le32 tx_duration; 1605 u8 tx_ppdu_cnt; 1606 u8 peer_id; 1607 } __packed; 1608 1609 union htt_rx_pn_t { 1610 /* WEP: 24-bit PN */ 1611 u32 pn24; 1612 1613 /* TKIP or CCMP: 48-bit PN */ 1614 u64 pn48; 1615 1616 /* WAPI: 128-bit PN */ 1617 u64 pn128[2]; 1618 }; 1619 1620 struct htt_cmd { 1621 struct htt_cmd_hdr hdr; 1622 union { 1623 struct htt_ver_req ver_req; 1624 struct htt_mgmt_tx_desc mgmt_tx; 1625 struct htt_data_tx_desc data_tx; 1626 struct htt_rx_ring_setup_32 rx_setup_32; 1627 struct htt_rx_ring_setup_64 rx_setup_64; 1628 struct htt_stats_req stats_req; 1629 struct htt_oob_sync_req oob_sync_req; 1630 struct htt_aggr_conf aggr_conf; 1631 struct htt_frag_desc_bank_cfg32 frag_desc_bank_cfg32; 1632 struct htt_frag_desc_bank_cfg64 frag_desc_bank_cfg64; 1633 struct htt_tx_fetch_resp tx_fetch_resp; 1634 }; 1635 } __packed; 1636 1637 struct htt_resp { 1638 struct htt_resp_hdr hdr; 1639 union { 1640 struct htt_ver_resp ver_resp; 1641 struct htt_mgmt_tx_completion mgmt_tx_completion; 1642 struct htt_data_tx_completion data_tx_completion; 1643 struct htt_rx_indication rx_ind; 1644 struct htt_rx_fragment_indication rx_frag_ind; 1645 struct htt_rx_peer_map peer_map; 1646 struct htt_rx_peer_unmap peer_unmap; 1647 struct htt_rx_flush rx_flush; 1648 struct htt_rx_addba rx_addba; 1649 struct htt_rx_delba rx_delba; 1650 struct htt_security_indication security_indication; 1651 struct htt_rc_update rc_update; 1652 struct htt_rx_test rx_test; 1653 struct htt_pktlog_msg pktlog_msg; 1654 struct htt_stats_conf stats_conf; 1655 struct htt_rx_pn_ind rx_pn_ind; 1656 struct htt_rx_offload_ind rx_offload_ind; 1657 struct htt_rx_in_ord_ind rx_in_ord_ind; 1658 struct htt_tx_fetch_ind tx_fetch_ind; 1659 struct htt_tx_fetch_confirm tx_fetch_confirm; 1660 struct htt_tx_mode_switch_ind tx_mode_switch_ind; 1661 struct htt_channel_change chan_change; 1662 struct htt_peer_tx_stats peer_tx_stats; 1663 }; 1664 } __packed; 1665 1666 /*** host side structures follow ***/ 1667 1668 struct htt_tx_done { 1669 u16 msdu_id; 1670 u16 status; 1671 u8 ack_rssi; 1672 }; 1673 1674 enum htt_tx_compl_state { 1675 HTT_TX_COMPL_STATE_NONE, 1676 HTT_TX_COMPL_STATE_ACK, 1677 HTT_TX_COMPL_STATE_NOACK, 1678 HTT_TX_COMPL_STATE_DISCARD, 1679 }; 1680 1681 struct htt_peer_map_event { 1682 u8 vdev_id; 1683 u16 peer_id; 1684 u8 addr[ETH_ALEN]; 1685 }; 1686 1687 struct htt_peer_unmap_event { 1688 u16 peer_id; 1689 }; 1690 1691 struct ath10k_htt_txbuf_32 { 1692 struct htt_data_tx_desc_frag frags[2]; 1693 struct ath10k_htc_hdr htc_hdr; 1694 struct htt_cmd_hdr cmd_hdr; 1695 struct htt_data_tx_desc cmd_tx; 1696 } __packed; 1697 1698 struct ath10k_htt_txbuf_64 { 1699 struct htt_data_tx_desc_frag frags[2]; 1700 struct ath10k_htc_hdr htc_hdr; 1701 struct htt_cmd_hdr cmd_hdr; 1702 struct htt_data_tx_desc_64 cmd_tx; 1703 } __packed; 1704 1705 struct ath10k_htt { 1706 struct ath10k *ar; 1707 enum ath10k_htc_ep_id eid; 1708 1709 u8 target_version_major; 1710 u8 target_version_minor; 1711 struct completion target_version_received; 1712 u8 max_num_amsdu; 1713 u8 max_num_ampdu; 1714 1715 const enum htt_t2h_msg_type *t2h_msg_types; 1716 u32 t2h_msg_types_max; 1717 1718 struct { 1719 /* 1720 * Ring of network buffer objects - This ring is 1721 * used exclusively by the host SW. This ring 1722 * mirrors the dev_addrs_ring that is shared 1723 * between the host SW and the MAC HW. The host SW 1724 * uses this netbufs ring to locate the network 1725 * buffer objects whose data buffers the HW has 1726 * filled. 1727 */ 1728 struct sk_buff **netbufs_ring; 1729 1730 /* This is used only with firmware supporting IN_ORD_IND. 1731 * 1732 * With Full Rx Reorder the HTT Rx Ring is more of a temporary 1733 * buffer ring from which buffer addresses are copied by the 1734 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND 1735 * pointing to specific (re-ordered) buffers. 1736 * 1737 * FIXME: With kernel generic hashing functions there's a lot 1738 * of hash collisions for sk_buffs. 1739 */ 1740 bool in_ord_rx; 1741 DECLARE_HASHTABLE(skb_table, 4); 1742 1743 /* 1744 * Ring of buffer addresses - 1745 * This ring holds the "physical" device address of the 1746 * rx buffers the host SW provides for the MAC HW to 1747 * fill. 1748 */ 1749 union { 1750 __le64 *paddrs_ring_64; 1751 __le32 *paddrs_ring_32; 1752 }; 1753 1754 /* 1755 * Base address of ring, as a "physical" device address 1756 * rather than a CPU address. 1757 */ 1758 dma_addr_t base_paddr; 1759 1760 /* how many elems in the ring (power of 2) */ 1761 int size; 1762 1763 /* size - 1 */ 1764 unsigned int size_mask; 1765 1766 /* how many rx buffers to keep in the ring */ 1767 int fill_level; 1768 1769 /* how many rx buffers (full+empty) are in the ring */ 1770 int fill_cnt; 1771 1772 /* 1773 * alloc_idx - where HTT SW has deposited empty buffers 1774 * This is allocated in consistent mem, so that the FW can 1775 * read this variable, and program the HW's FW_IDX reg with 1776 * the value of this shadow register. 1777 */ 1778 struct { 1779 __le32 *vaddr; 1780 dma_addr_t paddr; 1781 } alloc_idx; 1782 1783 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1784 struct { 1785 unsigned int msdu_payld; 1786 } sw_rd_idx; 1787 1788 /* 1789 * refill_retry_timer - timer triggered when the ring is 1790 * not refilled to the level expected 1791 */ 1792 struct timer_list refill_retry_timer; 1793 1794 /* Protects access to all rx ring buffer state variables */ 1795 spinlock_t lock; 1796 } rx_ring; 1797 1798 unsigned int prefetch_len; 1799 1800 /* Protects access to pending_tx, num_pending_tx */ 1801 spinlock_t tx_lock; 1802 int max_num_pending_tx; 1803 int num_pending_tx; 1804 int num_pending_mgmt_tx; 1805 struct idr pending_tx; 1806 wait_queue_head_t empty_tx_wq; 1807 1808 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */ 1809 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done); 1810 1811 /* set if host-fw communication goes haywire 1812 * used to avoid further failures 1813 */ 1814 bool rx_confused; 1815 atomic_t num_mpdus_ready; 1816 1817 /* This is used to group tx/rx completions separately and process them 1818 * in batches to reduce cache stalls 1819 */ 1820 struct sk_buff_head rx_msdus_q; 1821 struct sk_buff_head rx_in_ord_compl_q; 1822 struct sk_buff_head tx_fetch_ind_q; 1823 1824 /* rx_status template */ 1825 struct ieee80211_rx_status rx_status; 1826 1827 struct { 1828 dma_addr_t paddr; 1829 union { 1830 struct htt_msdu_ext_desc *vaddr_desc_32; 1831 struct htt_msdu_ext_desc_64 *vaddr_desc_64; 1832 }; 1833 size_t size; 1834 } frag_desc; 1835 1836 struct { 1837 dma_addr_t paddr; 1838 union { 1839 struct ath10k_htt_txbuf_32 *vaddr_txbuff_32; 1840 struct ath10k_htt_txbuf_64 *vaddr_txbuff_64; 1841 }; 1842 size_t size; 1843 } txbuf; 1844 1845 struct { 1846 bool enabled; 1847 struct htt_q_state *vaddr; 1848 dma_addr_t paddr; 1849 u16 num_push_allowed; 1850 u16 num_peers; 1851 u16 num_tids; 1852 enum htt_tx_mode_switch_mode mode; 1853 enum htt_q_depth_type type; 1854 } tx_q_state; 1855 1856 bool tx_mem_allocated; 1857 const struct ath10k_htt_tx_ops *tx_ops; 1858 const struct ath10k_htt_rx_ops *rx_ops; 1859 }; 1860 1861 struct ath10k_htt_tx_ops { 1862 int (*htt_send_rx_ring_cfg)(struct ath10k_htt *htt); 1863 int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt); 1864 int (*htt_alloc_frag_desc)(struct ath10k_htt *htt); 1865 void (*htt_free_frag_desc)(struct ath10k_htt *htt); 1866 int (*htt_tx)(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 1867 struct sk_buff *msdu); 1868 int (*htt_alloc_txbuff)(struct ath10k_htt *htt); 1869 void (*htt_free_txbuff)(struct ath10k_htt *htt); 1870 }; 1871 1872 static inline int ath10k_htt_send_rx_ring_cfg(struct ath10k_htt *htt) 1873 { 1874 if (!htt->tx_ops->htt_send_rx_ring_cfg) 1875 return -EOPNOTSUPP; 1876 1877 return htt->tx_ops->htt_send_rx_ring_cfg(htt); 1878 } 1879 1880 static inline int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) 1881 { 1882 if (!htt->tx_ops->htt_send_frag_desc_bank_cfg) 1883 return -EOPNOTSUPP; 1884 1885 return htt->tx_ops->htt_send_frag_desc_bank_cfg(htt); 1886 } 1887 1888 static inline int ath10k_htt_alloc_frag_desc(struct ath10k_htt *htt) 1889 { 1890 if (!htt->tx_ops->htt_alloc_frag_desc) 1891 return -EOPNOTSUPP; 1892 1893 return htt->tx_ops->htt_alloc_frag_desc(htt); 1894 } 1895 1896 static inline void ath10k_htt_free_frag_desc(struct ath10k_htt *htt) 1897 { 1898 if (htt->tx_ops->htt_free_frag_desc) 1899 htt->tx_ops->htt_free_frag_desc(htt); 1900 } 1901 1902 static inline int ath10k_htt_tx(struct ath10k_htt *htt, 1903 enum ath10k_hw_txrx_mode txmode, 1904 struct sk_buff *msdu) 1905 { 1906 return htt->tx_ops->htt_tx(htt, txmode, msdu); 1907 } 1908 1909 static inline int ath10k_htt_alloc_txbuff(struct ath10k_htt *htt) 1910 { 1911 if (!htt->tx_ops->htt_alloc_txbuff) 1912 return -EOPNOTSUPP; 1913 1914 return htt->tx_ops->htt_alloc_txbuff(htt); 1915 } 1916 1917 static inline void ath10k_htt_free_txbuff(struct ath10k_htt *htt) 1918 { 1919 if (htt->tx_ops->htt_free_txbuff) 1920 htt->tx_ops->htt_free_txbuff(htt); 1921 } 1922 1923 struct ath10k_htt_rx_ops { 1924 size_t (*htt_get_rx_ring_size)(struct ath10k_htt *htt); 1925 void (*htt_config_paddrs_ring)(struct ath10k_htt *htt, void *vaddr); 1926 void (*htt_set_paddrs_ring)(struct ath10k_htt *htt, dma_addr_t paddr, 1927 int idx); 1928 void* (*htt_get_vaddr_ring)(struct ath10k_htt *htt); 1929 void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx); 1930 }; 1931 1932 static inline size_t ath10k_htt_get_rx_ring_size(struct ath10k_htt *htt) 1933 { 1934 if (!htt->rx_ops->htt_get_rx_ring_size) 1935 return 0; 1936 1937 return htt->rx_ops->htt_get_rx_ring_size(htt); 1938 } 1939 1940 static inline void ath10k_htt_config_paddrs_ring(struct ath10k_htt *htt, 1941 void *vaddr) 1942 { 1943 if (htt->rx_ops->htt_config_paddrs_ring) 1944 htt->rx_ops->htt_config_paddrs_ring(htt, vaddr); 1945 } 1946 1947 static inline void ath10k_htt_set_paddrs_ring(struct ath10k_htt *htt, 1948 dma_addr_t paddr, 1949 int idx) 1950 { 1951 if (htt->rx_ops->htt_set_paddrs_ring) 1952 htt->rx_ops->htt_set_paddrs_ring(htt, paddr, idx); 1953 } 1954 1955 static inline void *ath10k_htt_get_vaddr_ring(struct ath10k_htt *htt) 1956 { 1957 if (!htt->rx_ops->htt_get_vaddr_ring) 1958 return NULL; 1959 1960 return htt->rx_ops->htt_get_vaddr_ring(htt); 1961 } 1962 1963 static inline void ath10k_htt_reset_paddrs_ring(struct ath10k_htt *htt, int idx) 1964 { 1965 if (htt->rx_ops->htt_reset_paddrs_ring) 1966 htt->rx_ops->htt_reset_paddrs_ring(htt, idx); 1967 } 1968 1969 #define RX_HTT_HDR_STATUS_LEN 64 1970 1971 /* This structure layout is programmed via rx ring setup 1972 * so that FW knows how to transfer the rx descriptor to the host. 1973 * Buffers like this are placed on the rx ring. 1974 */ 1975 struct htt_rx_desc { 1976 union { 1977 /* This field is filled on the host using the msdu buffer 1978 * from htt_rx_indication 1979 */ 1980 struct fw_rx_desc_base fw_desc; 1981 u32 pad; 1982 } __packed; 1983 struct { 1984 struct rx_attention attention; 1985 struct rx_frag_info frag_info; 1986 struct rx_mpdu_start mpdu_start; 1987 struct rx_msdu_start msdu_start; 1988 struct rx_msdu_end msdu_end; 1989 struct rx_mpdu_end mpdu_end; 1990 struct rx_ppdu_start ppdu_start; 1991 struct rx_ppdu_end ppdu_end; 1992 } __packed; 1993 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1994 u8 msdu_payload[0]; 1995 }; 1996 1997 #define HTT_RX_DESC_ALIGN 8 1998 1999 #define HTT_MAC_ADDR_LEN 6 2000 2001 /* 2002 * FIX THIS 2003 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 2004 * rounded up to a cache line size. 2005 */ 2006 #define HTT_RX_BUF_SIZE 1920 2007 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 2008 2009 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 2010 * aggregated traffic more nicely. 2011 */ 2012 #define ATH10K_HTT_MAX_NUM_REFILL 100 2013 2014 /* 2015 * DMA_MAP expects the buffer to be an integral number of cache lines. 2016 * Rather than checking the actual cache line size, this code makes a 2017 * conservative estimate of what the cache line size could be. 2018 */ 2019 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 2020 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 2021 2022 /* These values are default in most firmware revisions and apparently are a 2023 * sweet spot performance wise. 2024 */ 2025 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3 2026 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64 2027 2028 int ath10k_htt_connect(struct ath10k_htt *htt); 2029 int ath10k_htt_init(struct ath10k *ar); 2030 int ath10k_htt_setup(struct ath10k_htt *htt); 2031 2032 int ath10k_htt_tx_start(struct ath10k_htt *htt); 2033 void ath10k_htt_tx_stop(struct ath10k_htt *htt); 2034 void ath10k_htt_tx_destroy(struct ath10k_htt *htt); 2035 void ath10k_htt_tx_free(struct ath10k_htt *htt); 2036 2037 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 2038 int ath10k_htt_rx_ring_refill(struct ath10k *ar); 2039 void ath10k_htt_rx_free(struct ath10k_htt *htt); 2040 2041 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 2042 void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 2043 bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 2044 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 2045 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 2046 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 2047 u8 max_subfrms_ampdu, 2048 u8 max_subfrms_amsdu); 2049 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb); 2050 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 2051 __le32 token, 2052 __le16 fetch_seq_num, 2053 struct htt_tx_fetch_record *records, 2054 size_t num_records); 2055 2056 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 2057 struct ieee80211_txq *txq); 2058 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 2059 struct ieee80211_txq *txq); 2060 void ath10k_htt_tx_txq_sync(struct ath10k *ar); 2061 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 2062 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt); 2063 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt); 2064 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 2065 bool is_presp); 2066 2067 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); 2068 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 2069 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu); 2070 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar, 2071 struct sk_buff *skb); 2072 int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget); 2073 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt); 2074 void ath10k_htt_set_rx_ops(struct ath10k_htt *htt); 2075 #endif 2076