1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HTT_H_ 19 #define _HTT_H_ 20 21 #include <linux/bug.h> 22 #include <linux/interrupt.h> 23 #include <linux/dmapool.h> 24 #include <linux/hashtable.h> 25 #include <linux/kfifo.h> 26 #include <net/mac80211.h> 27 28 #include "htc.h" 29 #include "hw.h" 30 #include "rx_desc.h" 31 #include "hw.h" 32 33 enum htt_dbg_stats_type { 34 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 35 HTT_DBG_STATS_RX_REORDER = 1 << 1, 36 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 37 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 38 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 39 /* bits 5-23 currently reserved */ 40 41 HTT_DBG_NUM_STATS /* keep this last */ 42 }; 43 44 enum htt_h2t_msg_type { /* host-to-target */ 45 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 46 HTT_H2T_MSG_TYPE_TX_FRM = 1, 47 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 48 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 49 HTT_H2T_MSG_TYPE_SYNC = 4, 50 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 51 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 52 53 /* This command is used for sending management frames in HTT < 3.0. 54 * HTT >= 3.0 uses TX_FRM for everything. 55 */ 56 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 57 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11, 58 59 HTT_H2T_NUM_MSGS /* keep this last */ 60 }; 61 62 struct htt_cmd_hdr { 63 u8 msg_type; 64 } __packed; 65 66 struct htt_ver_req { 67 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 68 } __packed; 69 70 /* 71 * HTT tx MSDU descriptor 72 * 73 * The HTT tx MSDU descriptor is created by the host HTT SW for each 74 * tx MSDU. The HTT tx MSDU descriptor contains the information that 75 * the target firmware needs for the FW's tx processing, particularly 76 * for creating the HW msdu descriptor. 77 * The same HTT tx descriptor is used for HL and LL systems, though 78 * a few fields within the tx descriptor are used only by LL or 79 * only by HL. 80 * The HTT tx descriptor is defined in two manners: by a struct with 81 * bitfields, and by a series of [dword offset, bit mask, bit shift] 82 * definitions. 83 * The target should use the struct def, for simplicitly and clarity, 84 * but the host shall use the bit-mast + bit-shift defs, to be endian- 85 * neutral. Specifically, the host shall use the get/set macros built 86 * around the mask + shift defs. 87 */ 88 struct htt_data_tx_desc_frag { 89 union { 90 struct double_word_addr { 91 __le32 paddr; 92 __le32 len; 93 } __packed dword_addr; 94 struct triple_word_addr { 95 __le32 paddr_lo; 96 __le16 paddr_hi; 97 __le16 len_16; 98 } __packed tword_addr; 99 } __packed; 100 } __packed; 101 102 struct htt_msdu_ext_desc { 103 __le32 tso_flag[3]; 104 __le16 ip_identification; 105 u8 flags; 106 u8 reserved; 107 struct htt_data_tx_desc_frag frags[6]; 108 }; 109 110 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0) 111 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1) 112 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2) 113 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3) 114 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4) 115 116 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \ 117 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \ 118 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \ 119 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \ 120 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE) 121 122 enum htt_data_tx_desc_flags0 { 123 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 124 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 125 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 126 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 127 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 128 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 129 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 130 }; 131 132 enum htt_data_tx_desc_flags1 { 133 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 134 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 135 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 136 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 137 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 138 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 139 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 140 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 141 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 142 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 143 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 144 }; 145 146 enum htt_data_tx_ext_tid { 147 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 148 HTT_DATA_TX_EXT_TID_MGMT = 17, 149 HTT_DATA_TX_EXT_TID_INVALID = 31 150 }; 151 152 #define HTT_INVALID_PEERID 0xFFFF 153 154 /* 155 * htt_data_tx_desc - used for data tx path 156 * 157 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 158 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 159 * for special kinds of tids 160 * postponed: only for HL hosts. indicates if this is a resend 161 * (HL hosts manage queues on the host ) 162 * more_in_batch: only for HL hosts. indicates if more packets are 163 * pending. this allows target to wait and aggregate 164 * freq: 0 means home channel of given vdev. intended for offchannel 165 */ 166 struct htt_data_tx_desc { 167 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 168 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 169 __le16 len; 170 __le16 id; 171 __le32 frags_paddr; 172 union { 173 __le32 peerid; 174 struct { 175 __le16 peerid; 176 __le16 freq; 177 } __packed offchan_tx; 178 } __packed; 179 u8 prefetch[0]; /* start of frame, for FW classification engine */ 180 } __packed; 181 182 enum htt_rx_ring_flags { 183 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 184 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 185 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 186 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 187 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 188 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 189 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 190 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 191 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 192 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 193 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 194 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 195 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 196 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 197 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 198 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 199 }; 200 201 #define HTT_RX_RING_SIZE_MIN 128 202 #define HTT_RX_RING_SIZE_MAX 2048 203 204 struct htt_rx_ring_setup_ring { 205 __le32 fw_idx_shadow_reg_paddr; 206 __le32 rx_ring_base_paddr; 207 __le16 rx_ring_len; /* in 4-byte words */ 208 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 209 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 210 __le16 fw_idx_init_val; 211 212 /* the following offsets are in 4-byte units */ 213 __le16 mac80211_hdr_offset; 214 __le16 msdu_payload_offset; 215 __le16 ppdu_start_offset; 216 __le16 ppdu_end_offset; 217 __le16 mpdu_start_offset; 218 __le16 mpdu_end_offset; 219 __le16 msdu_start_offset; 220 __le16 msdu_end_offset; 221 __le16 rx_attention_offset; 222 __le16 frag_info_offset; 223 } __packed; 224 225 struct htt_rx_ring_setup_hdr { 226 u8 num_rings; /* supported values: 1, 2 */ 227 __le16 rsvd0; 228 } __packed; 229 230 struct htt_rx_ring_setup { 231 struct htt_rx_ring_setup_hdr hdr; 232 struct htt_rx_ring_setup_ring rings[0]; 233 } __packed; 234 235 /* 236 * htt_stats_req - request target to send specified statistics 237 * 238 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 239 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 240 * so make sure its little-endian. 241 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 242 * so make sure its little-endian. 243 * @cfg_val: stat_type specific configuration 244 * @stat_type: see %htt_dbg_stats_type 245 * @cookie_lsb: used for confirmation message from target->host 246 * @cookie_msb: ditto as %cookie 247 */ 248 struct htt_stats_req { 249 u8 upload_types[3]; 250 u8 rsvd0; 251 u8 reset_types[3]; 252 struct { 253 u8 mpdu_bytes; 254 u8 mpdu_num_msdus; 255 u8 msdu_bytes; 256 } __packed; 257 u8 stat_type; 258 __le32 cookie_lsb; 259 __le32 cookie_msb; 260 } __packed; 261 262 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 263 264 /* 265 * htt_oob_sync_req - request out-of-band sync 266 * 267 * The HTT SYNC tells the target to suspend processing of subsequent 268 * HTT host-to-target messages until some other target agent locally 269 * informs the target HTT FW that the current sync counter is equal to 270 * or greater than (in a modulo sense) the sync counter specified in 271 * the SYNC message. 272 * 273 * This allows other host-target components to synchronize their operation 274 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 275 * security key has been downloaded to and activated by the target. 276 * In the absence of any explicit synchronization counter value 277 * specification, the target HTT FW will use zero as the default current 278 * sync value. 279 * 280 * The HTT target FW will suspend its host->target message processing as long 281 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 282 */ 283 struct htt_oob_sync_req { 284 u8 sync_count; 285 __le16 rsvd0; 286 } __packed; 287 288 struct htt_aggr_conf { 289 u8 max_num_ampdu_subframes; 290 /* amsdu_subframes is limited by 0x1F mask */ 291 u8 max_num_amsdu_subframes; 292 } __packed; 293 294 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 295 struct htt_mgmt_tx_desc_qca99x0 { 296 __le32 rate; 297 } __packed; 298 299 struct htt_mgmt_tx_desc { 300 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 301 __le32 msdu_paddr; 302 __le32 desc_id; 303 __le32 len; 304 __le32 vdev_id; 305 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 306 union { 307 struct htt_mgmt_tx_desc_qca99x0 qca99x0; 308 } __packed; 309 } __packed; 310 311 enum htt_mgmt_tx_status { 312 HTT_MGMT_TX_STATUS_OK = 0, 313 HTT_MGMT_TX_STATUS_RETRY = 1, 314 HTT_MGMT_TX_STATUS_DROP = 2 315 }; 316 317 /*=== target -> host messages ===============================================*/ 318 319 enum htt_main_t2h_msg_type { 320 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0, 321 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1, 322 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2, 323 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3, 324 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 325 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5, 326 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6, 327 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 328 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8, 329 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9, 330 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 331 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb, 332 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 333 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 334 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 335 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10, 336 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 337 HTT_MAIN_T2H_MSG_TYPE_TEST, 338 /* keep this last */ 339 HTT_MAIN_T2H_NUM_MSGS 340 }; 341 342 enum htt_10x_t2h_msg_type { 343 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0, 344 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1, 345 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2, 346 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3, 347 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 348 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5, 349 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6, 350 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 351 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8, 352 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9, 353 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 354 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb, 355 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 356 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 357 HTT_10X_T2H_MSG_TYPE_TEST = 0xe, 358 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 359 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11, 360 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12, 361 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13, 362 /* keep this last */ 363 HTT_10X_T2H_NUM_MSGS 364 }; 365 366 enum htt_tlv_t2h_msg_type { 367 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0, 368 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1, 369 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2, 370 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3, 371 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 372 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5, 373 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6, 374 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 375 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8, 376 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9, 377 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 378 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb, 379 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */ 380 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 381 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 382 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 383 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10, 384 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 385 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 386 /* 0x13 reservd */ 387 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 388 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 389 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 390 HTT_TLV_T2H_MSG_TYPE_TEST, 391 /* keep this last */ 392 HTT_TLV_T2H_NUM_MSGS 393 }; 394 395 enum htt_10_4_t2h_msg_type { 396 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0, 397 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1, 398 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2, 399 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3, 400 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 401 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5, 402 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6, 403 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 404 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8, 405 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9, 406 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 407 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb, 408 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 409 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 410 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 411 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 412 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10, 413 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11, 414 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12, 415 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13, 416 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14, 417 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15, 418 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16, 419 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17, 420 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18, 421 /* 0x19 to 0x2f are reserved */ 422 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30, 423 HTT_10_4_T2H_MSG_TYPE_PEER_STATS = 0x31, 424 /* keep this last */ 425 HTT_10_4_T2H_NUM_MSGS 426 }; 427 428 enum htt_t2h_msg_type { 429 HTT_T2H_MSG_TYPE_VERSION_CONF, 430 HTT_T2H_MSG_TYPE_RX_IND, 431 HTT_T2H_MSG_TYPE_RX_FLUSH, 432 HTT_T2H_MSG_TYPE_PEER_MAP, 433 HTT_T2H_MSG_TYPE_PEER_UNMAP, 434 HTT_T2H_MSG_TYPE_RX_ADDBA, 435 HTT_T2H_MSG_TYPE_RX_DELBA, 436 HTT_T2H_MSG_TYPE_TX_COMPL_IND, 437 HTT_T2H_MSG_TYPE_PKTLOG, 438 HTT_T2H_MSG_TYPE_STATS_CONF, 439 HTT_T2H_MSG_TYPE_RX_FRAG_IND, 440 HTT_T2H_MSG_TYPE_SEC_IND, 441 HTT_T2H_MSG_TYPE_RC_UPDATE_IND, 442 HTT_T2H_MSG_TYPE_TX_INSPECT_IND, 443 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION, 444 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, 445 HTT_T2H_MSG_TYPE_RX_PN_IND, 446 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND, 447 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND, 448 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE, 449 HTT_T2H_MSG_TYPE_CHAN_CHANGE, 450 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR, 451 HTT_T2H_MSG_TYPE_AGGR_CONF, 452 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, 453 HTT_T2H_MSG_TYPE_TEST, 454 HTT_T2H_MSG_TYPE_EN_STATS, 455 HTT_T2H_MSG_TYPE_TX_FETCH_IND, 456 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM, 457 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND, 458 HTT_T2H_MSG_TYPE_PEER_STATS, 459 /* keep this last */ 460 HTT_T2H_NUM_MSGS 461 }; 462 463 /* 464 * htt_resp_hdr - header for target-to-host messages 465 * 466 * msg_type: see htt_t2h_msg_type 467 */ 468 struct htt_resp_hdr { 469 u8 msg_type; 470 } __packed; 471 472 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 473 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 474 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 475 476 /* htt_ver_resp - response sent for htt_ver_req */ 477 struct htt_ver_resp { 478 u8 minor; 479 u8 major; 480 u8 rsvd0; 481 } __packed; 482 483 struct htt_mgmt_tx_completion { 484 u8 rsvd0; 485 u8 rsvd1; 486 u8 rsvd2; 487 __le32 desc_id; 488 __le32 status; 489 } __packed; 490 491 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F) 492 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 493 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5) 494 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6) 495 496 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 497 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 498 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 499 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 500 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 501 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 502 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 503 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 504 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 505 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 506 507 struct htt_rx_indication_hdr { 508 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 509 __le16 peer_id; 510 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 511 } __packed; 512 513 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 514 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 515 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 516 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 517 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 518 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 519 520 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 521 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 522 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 523 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 524 525 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 526 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 527 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 528 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 529 530 enum htt_rx_legacy_rate { 531 HTT_RX_OFDM_48 = 0, 532 HTT_RX_OFDM_24 = 1, 533 HTT_RX_OFDM_12, 534 HTT_RX_OFDM_6, 535 HTT_RX_OFDM_54, 536 HTT_RX_OFDM_36, 537 HTT_RX_OFDM_18, 538 HTT_RX_OFDM_9, 539 540 /* long preamble */ 541 HTT_RX_CCK_11_LP = 0, 542 HTT_RX_CCK_5_5_LP = 1, 543 HTT_RX_CCK_2_LP, 544 HTT_RX_CCK_1_LP, 545 /* short preamble */ 546 HTT_RX_CCK_11_SP, 547 HTT_RX_CCK_5_5_SP, 548 HTT_RX_CCK_2_SP 549 }; 550 551 enum htt_rx_legacy_rate_type { 552 HTT_RX_LEGACY_RATE_OFDM = 0, 553 HTT_RX_LEGACY_RATE_CCK 554 }; 555 556 enum htt_rx_preamble_type { 557 HTT_RX_LEGACY = 0x4, 558 HTT_RX_HT = 0x8, 559 HTT_RX_HT_WITH_TXBF = 0x9, 560 HTT_RX_VHT = 0xC, 561 HTT_RX_VHT_WITH_TXBF = 0xD, 562 }; 563 564 /* 565 * Fields: phy_err_valid, phy_err_code, tsf, 566 * usec_timestamp, sub_usec_timestamp 567 * ..are valid only if end_valid == 1. 568 * 569 * Fields: rssi_chains, legacy_rate_type, 570 * legacy_rate_cck, preamble_type, service, 571 * vht_sig_* 572 * ..are valid only if start_valid == 1; 573 */ 574 struct htt_rx_indication_ppdu { 575 u8 combined_rssi; 576 u8 sub_usec_timestamp; 577 u8 phy_err_code; 578 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 579 struct { 580 u8 pri20_db; 581 u8 ext20_db; 582 u8 ext40_db; 583 u8 ext80_db; 584 } __packed rssi_chains[4]; 585 __le32 tsf; 586 __le32 usec_timestamp; 587 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 588 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 589 } __packed; 590 591 enum htt_rx_mpdu_status { 592 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 593 HTT_RX_IND_MPDU_STATUS_OK, 594 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 595 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 596 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 597 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 598 /* only accept EAPOL frames */ 599 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 600 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 601 /* Non-data in promiscuous mode */ 602 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 603 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 604 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 605 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 606 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 607 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 608 609 /* 610 * MISC: discard for unspecified reasons. 611 * Leave this enum value last. 612 */ 613 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 614 }; 615 616 struct htt_rx_indication_mpdu_range { 617 u8 mpdu_count; 618 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 619 u8 pad0; 620 u8 pad1; 621 } __packed; 622 623 struct htt_rx_indication_prefix { 624 __le16 fw_rx_desc_bytes; 625 u8 pad0; 626 u8 pad1; 627 }; 628 629 struct htt_rx_indication { 630 struct htt_rx_indication_hdr hdr; 631 struct htt_rx_indication_ppdu ppdu; 632 struct htt_rx_indication_prefix prefix; 633 634 /* 635 * the following fields are both dynamically sized, so 636 * take care addressing them 637 */ 638 639 /* the size of this is %fw_rx_desc_bytes */ 640 struct fw_rx_desc_base fw_desc; 641 642 /* 643 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 644 * and has %num_mpdu_ranges elements. 645 */ 646 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 647 } __packed; 648 649 static inline struct htt_rx_indication_mpdu_range * 650 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 651 { 652 void *ptr = rx_ind; 653 654 ptr += sizeof(rx_ind->hdr) 655 + sizeof(rx_ind->ppdu) 656 + sizeof(rx_ind->prefix) 657 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 658 return ptr; 659 } 660 661 enum htt_rx_flush_mpdu_status { 662 HTT_RX_FLUSH_MPDU_DISCARD = 0, 663 HTT_RX_FLUSH_MPDU_REORDER = 1, 664 }; 665 666 /* 667 * htt_rx_flush - discard or reorder given range of mpdus 668 * 669 * Note: host must check if all sequence numbers between 670 * [seq_num_start, seq_num_end-1] are valid. 671 */ 672 struct htt_rx_flush { 673 __le16 peer_id; 674 u8 tid; 675 u8 rsvd0; 676 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 677 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 678 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 679 }; 680 681 struct htt_rx_peer_map { 682 u8 vdev_id; 683 __le16 peer_id; 684 u8 addr[6]; 685 u8 rsvd0; 686 u8 rsvd1; 687 } __packed; 688 689 struct htt_rx_peer_unmap { 690 u8 rsvd0; 691 __le16 peer_id; 692 } __packed; 693 694 enum htt_security_types { 695 HTT_SECURITY_NONE, 696 HTT_SECURITY_WEP128, 697 HTT_SECURITY_WEP104, 698 HTT_SECURITY_WEP40, 699 HTT_SECURITY_TKIP, 700 HTT_SECURITY_TKIP_NOMIC, 701 HTT_SECURITY_AES_CCMP, 702 HTT_SECURITY_WAPI, 703 704 HTT_NUM_SECURITY_TYPES /* keep this last! */ 705 }; 706 707 enum htt_security_flags { 708 #define HTT_SECURITY_TYPE_MASK 0x7F 709 #define HTT_SECURITY_TYPE_LSB 0 710 HTT_SECURITY_IS_UNICAST = 1 << 7 711 }; 712 713 struct htt_security_indication { 714 union { 715 /* dont use bitfields; undefined behaviour */ 716 u8 flags; /* %htt_security_flags */ 717 struct { 718 u8 security_type:7, /* %htt_security_types */ 719 is_unicast:1; 720 } __packed; 721 } __packed; 722 __le16 peer_id; 723 u8 michael_key[8]; 724 u8 wapi_rsc[16]; 725 } __packed; 726 727 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 728 #define HTT_RX_BA_INFO0_TID_LSB 0 729 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 730 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 731 732 struct htt_rx_addba { 733 u8 window_size; 734 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 735 } __packed; 736 737 struct htt_rx_delba { 738 u8 rsvd0; 739 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 740 } __packed; 741 742 enum htt_data_tx_status { 743 HTT_DATA_TX_STATUS_OK = 0, 744 HTT_DATA_TX_STATUS_DISCARD = 1, 745 HTT_DATA_TX_STATUS_NO_ACK = 2, 746 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 747 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 748 }; 749 750 enum htt_data_tx_flags { 751 #define HTT_DATA_TX_STATUS_MASK 0x07 752 #define HTT_DATA_TX_STATUS_LSB 0 753 #define HTT_DATA_TX_TID_MASK 0x78 754 #define HTT_DATA_TX_TID_LSB 3 755 HTT_DATA_TX_TID_INVALID = 1 << 7 756 }; 757 758 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 759 760 struct htt_data_tx_completion { 761 union { 762 u8 flags; 763 struct { 764 u8 status:3, 765 tid:4, 766 tid_invalid:1; 767 } __packed; 768 } __packed; 769 u8 num_msdus; 770 u8 rsvd0; 771 __le16 msdus[0]; /* variable length based on %num_msdus */ 772 } __packed; 773 774 struct htt_tx_compl_ind_base { 775 u32 hdr; 776 u16 payload[1/*or more*/]; 777 } __packed; 778 779 struct htt_rc_tx_done_params { 780 u32 rate_code; 781 u32 rate_code_flags; 782 u32 flags; 783 u32 num_enqued; /* 1 for non-AMPDU */ 784 u32 num_retries; 785 u32 num_failed; /* for AMPDU */ 786 u32 ack_rssi; 787 u32 time_stamp; 788 u32 is_probe; 789 }; 790 791 struct htt_rc_update { 792 u8 vdev_id; 793 __le16 peer_id; 794 u8 addr[6]; 795 u8 num_elems; 796 u8 rsvd0; 797 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 798 } __packed; 799 800 /* see htt_rx_indication for similar fields and descriptions */ 801 struct htt_rx_fragment_indication { 802 union { 803 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 804 struct { 805 u8 ext_tid:5, 806 flush_valid:1; 807 } __packed; 808 } __packed; 809 __le16 peer_id; 810 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 811 __le16 fw_rx_desc_bytes; 812 __le16 rsvd0; 813 814 u8 fw_msdu_rx_desc[0]; 815 } __packed; 816 817 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 818 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 819 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 820 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 821 822 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 823 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 824 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 825 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 826 827 struct htt_rx_pn_ind { 828 __le16 peer_id; 829 u8 tid; 830 u8 seqno_start; 831 u8 seqno_end; 832 u8 pn_ie_count; 833 u8 reserved; 834 u8 pn_ies[0]; 835 } __packed; 836 837 struct htt_rx_offload_msdu { 838 __le16 msdu_len; 839 __le16 peer_id; 840 u8 vdev_id; 841 u8 tid; 842 u8 fw_desc; 843 u8 payload[0]; 844 } __packed; 845 846 struct htt_rx_offload_ind { 847 u8 reserved; 848 __le16 msdu_count; 849 } __packed; 850 851 struct htt_rx_in_ord_msdu_desc { 852 __le32 msdu_paddr; 853 __le16 msdu_len; 854 u8 fw_desc; 855 u8 reserved; 856 } __packed; 857 858 struct htt_rx_in_ord_ind { 859 u8 info; 860 __le16 peer_id; 861 u8 vdev_id; 862 u8 reserved; 863 __le16 msdu_count; 864 struct htt_rx_in_ord_msdu_desc msdu_descs[0]; 865 } __packed; 866 867 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f 868 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 869 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020 870 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 871 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040 872 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 873 874 /* 875 * target -> host test message definition 876 * 877 * The following field definitions describe the format of the test 878 * message sent from the target to the host. 879 * The message consists of a 4-octet header, followed by a variable 880 * number of 32-bit integer values, followed by a variable number 881 * of 8-bit character values. 882 * 883 * |31 16|15 8|7 0| 884 * |-----------------------------------------------------------| 885 * | num chars | num ints | msg type | 886 * |-----------------------------------------------------------| 887 * | int 0 | 888 * |-----------------------------------------------------------| 889 * | int 1 | 890 * |-----------------------------------------------------------| 891 * | ... | 892 * |-----------------------------------------------------------| 893 * | char 3 | char 2 | char 1 | char 0 | 894 * |-----------------------------------------------------------| 895 * | | | ... | char 4 | 896 * |-----------------------------------------------------------| 897 * - MSG_TYPE 898 * Bits 7:0 899 * Purpose: identifies this as a test message 900 * Value: HTT_MSG_TYPE_TEST 901 * - NUM_INTS 902 * Bits 15:8 903 * Purpose: indicate how many 32-bit integers follow the message header 904 * - NUM_CHARS 905 * Bits 31:16 906 * Purpose: indicate how many 8-bit characters follow the series of integers 907 */ 908 struct htt_rx_test { 909 u8 num_ints; 910 __le16 num_chars; 911 912 /* payload consists of 2 lists: 913 * a) num_ints * sizeof(__le32) 914 * b) num_chars * sizeof(u8) aligned to 4bytes 915 */ 916 u8 payload[0]; 917 } __packed; 918 919 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 920 { 921 return (__le32 *)rx_test->payload; 922 } 923 924 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 925 { 926 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 927 } 928 929 /* 930 * target -> host packet log message 931 * 932 * The following field definitions describe the format of the packet log 933 * message sent from the target to the host. 934 * The message consists of a 4-octet header,followed by a variable number 935 * of 32-bit character values. 936 * 937 * |31 24|23 16|15 8|7 0| 938 * |-----------------------------------------------------------| 939 * | | | | msg type | 940 * |-----------------------------------------------------------| 941 * | payload | 942 * |-----------------------------------------------------------| 943 * - MSG_TYPE 944 * Bits 7:0 945 * Purpose: identifies this as a test message 946 * Value: HTT_MSG_TYPE_PACKETLOG 947 */ 948 struct htt_pktlog_msg { 949 u8 pad[3]; 950 u8 payload[0]; 951 } __packed; 952 953 struct htt_dbg_stats_rx_reorder_stats { 954 /* Non QoS MPDUs received */ 955 __le32 deliver_non_qos; 956 957 /* MPDUs received in-order */ 958 __le32 deliver_in_order; 959 960 /* Flush due to reorder timer expired */ 961 __le32 deliver_flush_timeout; 962 963 /* Flush due to move out of window */ 964 __le32 deliver_flush_oow; 965 966 /* Flush due to DELBA */ 967 __le32 deliver_flush_delba; 968 969 /* MPDUs dropped due to FCS error */ 970 __le32 fcs_error; 971 972 /* MPDUs dropped due to monitor mode non-data packet */ 973 __le32 mgmt_ctrl; 974 975 /* MPDUs dropped due to invalid peer */ 976 __le32 invalid_peer; 977 978 /* MPDUs dropped due to duplication (non aggregation) */ 979 __le32 dup_non_aggr; 980 981 /* MPDUs dropped due to processed before */ 982 __le32 dup_past; 983 984 /* MPDUs dropped due to duplicate in reorder queue */ 985 __le32 dup_in_reorder; 986 987 /* Reorder timeout happened */ 988 __le32 reorder_timeout; 989 990 /* invalid bar ssn */ 991 __le32 invalid_bar_ssn; 992 993 /* reorder reset due to bar ssn */ 994 __le32 ssn_reset; 995 }; 996 997 struct htt_dbg_stats_wal_tx_stats { 998 /* Num HTT cookies queued to dispatch list */ 999 __le32 comp_queued; 1000 1001 /* Num HTT cookies dispatched */ 1002 __le32 comp_delivered; 1003 1004 /* Num MSDU queued to WAL */ 1005 __le32 msdu_enqued; 1006 1007 /* Num MPDU queue to WAL */ 1008 __le32 mpdu_enqued; 1009 1010 /* Num MSDUs dropped by WMM limit */ 1011 __le32 wmm_drop; 1012 1013 /* Num Local frames queued */ 1014 __le32 local_enqued; 1015 1016 /* Num Local frames done */ 1017 __le32 local_freed; 1018 1019 /* Num queued to HW */ 1020 __le32 hw_queued; 1021 1022 /* Num PPDU reaped from HW */ 1023 __le32 hw_reaped; 1024 1025 /* Num underruns */ 1026 __le32 underrun; 1027 1028 /* Num PPDUs cleaned up in TX abort */ 1029 __le32 tx_abort; 1030 1031 /* Num MPDUs requed by SW */ 1032 __le32 mpdus_requed; 1033 1034 /* excessive retries */ 1035 __le32 tx_ko; 1036 1037 /* data hw rate code */ 1038 __le32 data_rc; 1039 1040 /* Scheduler self triggers */ 1041 __le32 self_triggers; 1042 1043 /* frames dropped due to excessive sw retries */ 1044 __le32 sw_retry_failure; 1045 1046 /* illegal rate phy errors */ 1047 __le32 illgl_rate_phy_err; 1048 1049 /* wal pdev continuous xretry */ 1050 __le32 pdev_cont_xretry; 1051 1052 /* wal pdev continuous xretry */ 1053 __le32 pdev_tx_timeout; 1054 1055 /* wal pdev resets */ 1056 __le32 pdev_resets; 1057 1058 __le32 phy_underrun; 1059 1060 /* MPDU is more than txop limit */ 1061 __le32 txop_ovf; 1062 } __packed; 1063 1064 struct htt_dbg_stats_wal_rx_stats { 1065 /* Cnts any change in ring routing mid-ppdu */ 1066 __le32 mid_ppdu_route_change; 1067 1068 /* Total number of statuses processed */ 1069 __le32 status_rcvd; 1070 1071 /* Extra frags on rings 0-3 */ 1072 __le32 r0_frags; 1073 __le32 r1_frags; 1074 __le32 r2_frags; 1075 __le32 r3_frags; 1076 1077 /* MSDUs / MPDUs delivered to HTT */ 1078 __le32 htt_msdus; 1079 __le32 htt_mpdus; 1080 1081 /* MSDUs / MPDUs delivered to local stack */ 1082 __le32 loc_msdus; 1083 __le32 loc_mpdus; 1084 1085 /* AMSDUs that have more MSDUs than the status ring size */ 1086 __le32 oversize_amsdu; 1087 1088 /* Number of PHY errors */ 1089 __le32 phy_errs; 1090 1091 /* Number of PHY errors drops */ 1092 __le32 phy_err_drop; 1093 1094 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1095 __le32 mpdu_errs; 1096 } __packed; 1097 1098 struct htt_dbg_stats_wal_peer_stats { 1099 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 1100 } __packed; 1101 1102 struct htt_dbg_stats_wal_pdev_txrx { 1103 struct htt_dbg_stats_wal_tx_stats tx_stats; 1104 struct htt_dbg_stats_wal_rx_stats rx_stats; 1105 struct htt_dbg_stats_wal_peer_stats peer_stats; 1106 } __packed; 1107 1108 struct htt_dbg_stats_rx_rate_info { 1109 __le32 mcs[10]; 1110 __le32 sgi[10]; 1111 __le32 nss[4]; 1112 __le32 stbc[10]; 1113 __le32 bw[3]; 1114 __le32 pream[6]; 1115 __le32 ldpc; 1116 __le32 txbf; 1117 }; 1118 1119 /* 1120 * htt_dbg_stats_status - 1121 * present - The requested stats have been delivered in full. 1122 * This indicates that either the stats information was contained 1123 * in its entirety within this message, or else this message 1124 * completes the delivery of the requested stats info that was 1125 * partially delivered through earlier STATS_CONF messages. 1126 * partial - The requested stats have been delivered in part. 1127 * One or more subsequent STATS_CONF messages with the same 1128 * cookie value will be sent to deliver the remainder of the 1129 * information. 1130 * error - The requested stats could not be delivered, for example due 1131 * to a shortage of memory to construct a message holding the 1132 * requested stats. 1133 * invalid - The requested stat type is either not recognized, or the 1134 * target is configured to not gather the stats type in question. 1135 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1136 * series_done - This special value indicates that no further stats info 1137 * elements are present within a series of stats info elems 1138 * (within a stats upload confirmation message). 1139 */ 1140 enum htt_dbg_stats_status { 1141 HTT_DBG_STATS_STATUS_PRESENT = 0, 1142 HTT_DBG_STATS_STATUS_PARTIAL = 1, 1143 HTT_DBG_STATS_STATUS_ERROR = 2, 1144 HTT_DBG_STATS_STATUS_INVALID = 3, 1145 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 1146 }; 1147 1148 /* 1149 * target -> host statistics upload 1150 * 1151 * The following field definitions describe the format of the HTT target 1152 * to host stats upload confirmation message. 1153 * The message contains a cookie echoed from the HTT host->target stats 1154 * upload request, which identifies which request the confirmation is 1155 * for, and a series of tag-length-value stats information elements. 1156 * The tag-length header for each stats info element also includes a 1157 * status field, to indicate whether the request for the stat type in 1158 * question was fully met, partially met, unable to be met, or invalid 1159 * (if the stat type in question is disabled in the target). 1160 * A special value of all 1's in this status field is used to indicate 1161 * the end of the series of stats info elements. 1162 * 1163 * 1164 * |31 16|15 8|7 5|4 0| 1165 * |------------------------------------------------------------| 1166 * | reserved | msg type | 1167 * |------------------------------------------------------------| 1168 * | cookie LSBs | 1169 * |------------------------------------------------------------| 1170 * | cookie MSBs | 1171 * |------------------------------------------------------------| 1172 * | stats entry length | reserved | S |stat type| 1173 * |------------------------------------------------------------| 1174 * | | 1175 * | type-specific stats info | 1176 * | | 1177 * |------------------------------------------------------------| 1178 * | stats entry length | reserved | S |stat type| 1179 * |------------------------------------------------------------| 1180 * | | 1181 * | type-specific stats info | 1182 * | | 1183 * |------------------------------------------------------------| 1184 * | n/a | reserved | 111 | n/a | 1185 * |------------------------------------------------------------| 1186 * Header fields: 1187 * - MSG_TYPE 1188 * Bits 7:0 1189 * Purpose: identifies this is a statistics upload confirmation message 1190 * Value: 0x9 1191 * - COOKIE_LSBS 1192 * Bits 31:0 1193 * Purpose: Provide a mechanism to match a target->host stats confirmation 1194 * message with its preceding host->target stats request message. 1195 * Value: LSBs of the opaque cookie specified by the host-side requestor 1196 * - COOKIE_MSBS 1197 * Bits 31:0 1198 * Purpose: Provide a mechanism to match a target->host stats confirmation 1199 * message with its preceding host->target stats request message. 1200 * Value: MSBs of the opaque cookie specified by the host-side requestor 1201 * 1202 * Stats Information Element tag-length header fields: 1203 * - STAT_TYPE 1204 * Bits 4:0 1205 * Purpose: identifies the type of statistics info held in the 1206 * following information element 1207 * Value: htt_dbg_stats_type 1208 * - STATUS 1209 * Bits 7:5 1210 * Purpose: indicate whether the requested stats are present 1211 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 1212 * the completion of the stats entry series 1213 * - LENGTH 1214 * Bits 31:16 1215 * Purpose: indicate the stats information size 1216 * Value: This field specifies the number of bytes of stats information 1217 * that follows the element tag-length header. 1218 * It is expected but not required that this length is a multiple of 1219 * 4 bytes. Even if the length is not an integer multiple of 4, the 1220 * subsequent stats entry header will begin on a 4-byte aligned 1221 * boundary. 1222 */ 1223 1224 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1225 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1226 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1227 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1228 1229 struct htt_stats_conf_item { 1230 union { 1231 u8 info; 1232 struct { 1233 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1234 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1235 } __packed; 1236 } __packed; 1237 u8 pad; 1238 __le16 length; 1239 u8 payload[0]; /* roundup(length, 4) long */ 1240 } __packed; 1241 1242 struct htt_stats_conf { 1243 u8 pad[3]; 1244 __le32 cookie_lsb; 1245 __le32 cookie_msb; 1246 1247 /* each item has variable length! */ 1248 struct htt_stats_conf_item items[0]; 1249 } __packed; 1250 1251 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1252 const struct htt_stats_conf_item *item) 1253 { 1254 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1255 } 1256 1257 /* 1258 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1259 * 1260 * The following field definitions describe the format of the HTT host 1261 * to target frag_desc/msdu_ext bank configuration message. 1262 * The message contains the based address and the min and max id of the 1263 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1264 * MSDU_EXT/FRAG_DESC. 1265 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1266 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1267 * the hardware does the mapping/translation. 1268 * 1269 * Total banks that can be configured is configured to 16. 1270 * 1271 * This should be called before any TX has be initiated by the HTT 1272 * 1273 * |31 16|15 8|7 5|4 0| 1274 * |------------------------------------------------------------| 1275 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1276 * |------------------------------------------------------------| 1277 * | BANK0_BASE_ADDRESS | 1278 * |------------------------------------------------------------| 1279 * | ... | 1280 * |------------------------------------------------------------| 1281 * | BANK15_BASE_ADDRESS | 1282 * |------------------------------------------------------------| 1283 * | BANK0_MAX_ID | BANK0_MIN_ID | 1284 * |------------------------------------------------------------| 1285 * | ... | 1286 * |------------------------------------------------------------| 1287 * | BANK15_MAX_ID | BANK15_MIN_ID | 1288 * |------------------------------------------------------------| 1289 * Header fields: 1290 * - MSG_TYPE 1291 * Bits 7:0 1292 * Value: 0x6 1293 * - BANKx_BASE_ADDRESS 1294 * Bits 31:0 1295 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1296 * bank physical/bus address. 1297 * - BANKx_MIN_ID 1298 * Bits 15:0 1299 * Purpose: Provide a mechanism to specify the min index that needs to 1300 * mapped. 1301 * - BANKx_MAX_ID 1302 * Bits 31:16 1303 * Purpose: Provide a mechanism to specify the max index that needs to 1304 * 1305 */ 1306 struct htt_frag_desc_bank_id { 1307 __le16 bank_min_id; 1308 __le16 bank_max_id; 1309 } __packed; 1310 1311 /* real is 16 but it wouldn't fit in the max htt message size 1312 * so we use a conservatively safe value for now 1313 */ 1314 #define HTT_FRAG_DESC_BANK_MAX 4 1315 1316 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1317 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1318 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2) 1319 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3) 1320 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4) 1321 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4 1322 1323 enum htt_q_depth_type { 1324 HTT_Q_DEPTH_TYPE_BYTES = 0, 1325 HTT_Q_DEPTH_TYPE_MSDUS = 1, 1326 }; 1327 1328 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \ 1329 TARGET_10_4_NUM_VDEVS) 1330 #define HTT_TX_Q_STATE_NUM_TIDS 8 1331 #define HTT_TX_Q_STATE_ENTRY_SIZE 1 1332 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0 1333 1334 /** 1335 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config 1336 * 1337 * Defines host q state format and behavior. See htt_q_state. 1338 * 1339 * @record_size: Defines the size of each host q entry in bytes. In practice 1340 * however firmware (at least 10.4.3-00191) ignores this host 1341 * configuration value and uses hardcoded value of 1. 1342 * @record_multiplier: This is valid only when q depth type is MSDUs. It 1343 * defines the exponent for the power of 2 multiplication. 1344 */ 1345 struct htt_q_state_conf { 1346 __le32 paddr; 1347 __le16 num_peers; 1348 __le16 num_tids; 1349 u8 record_size; 1350 u8 record_multiplier; 1351 u8 pad[2]; 1352 } __packed; 1353 1354 struct htt_frag_desc_bank_cfg { 1355 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1356 u8 num_banks; 1357 u8 desc_size; 1358 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1359 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1360 struct htt_q_state_conf q_state; 1361 } __packed; 1362 1363 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128 1364 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f 1365 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0 1366 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0 1367 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6 1368 1369 /** 1370 * htt_q_state - shared between host and firmware via DMA 1371 * 1372 * This structure is used for the host to expose it's software queue state to 1373 * firmware so that its rate control can schedule fetch requests for optimized 1374 * performance. This is most notably used for MU-MIMO aggregation when multiple 1375 * MU clients are connected. 1376 * 1377 * @count: Each element defines the host queue depth. When q depth type was 1378 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as: 1379 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and 1380 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as 1381 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 ** 1382 * record_multiplier (see htt_q_state_conf). 1383 * @map: Used by firmware to quickly check which host queues are not empty. It 1384 * is a bitmap simply saying. 1385 * @seq: Used by firmware to quickly check if the host queues were updated 1386 * since it last checked. 1387 * 1388 * FIXME: Is the q_state map[] size calculation really correct? 1389 */ 1390 struct htt_q_state { 1391 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS]; 1392 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32]; 1393 __le32 seq; 1394 } __packed; 1395 1396 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff 1397 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0 1398 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000 1399 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12 1400 1401 struct htt_tx_fetch_record { 1402 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */ 1403 __le16 num_msdus; 1404 __le32 num_bytes; 1405 } __packed; 1406 1407 struct htt_tx_fetch_ind { 1408 u8 pad0; 1409 __le16 fetch_seq_num; 1410 __le32 token; 1411 __le16 num_resp_ids; 1412 __le16 num_records; 1413 struct htt_tx_fetch_record records[0]; 1414 __le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */ 1415 } __packed; 1416 1417 static inline void * 1418 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind) 1419 { 1420 return (void *)&ind->records[le16_to_cpu(ind->num_records)]; 1421 } 1422 1423 struct htt_tx_fetch_resp { 1424 u8 pad0; 1425 __le16 resp_id; 1426 __le16 fetch_seq_num; 1427 __le16 num_records; 1428 __le32 token; 1429 struct htt_tx_fetch_record records[0]; 1430 } __packed; 1431 1432 struct htt_tx_fetch_confirm { 1433 u8 pad0; 1434 __le16 num_resp_ids; 1435 __le32 resp_ids[0]; 1436 } __packed; 1437 1438 enum htt_tx_mode_switch_mode { 1439 HTT_TX_MODE_SWITCH_PUSH = 0, 1440 HTT_TX_MODE_SWITCH_PUSH_PULL = 1, 1441 }; 1442 1443 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0) 1444 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe 1445 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1 1446 1447 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003 1448 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0 1449 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc 1450 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2 1451 1452 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff 1453 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0 1454 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000 1455 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12 1456 1457 struct htt_tx_mode_switch_record { 1458 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */ 1459 __le16 num_max_msdus; 1460 } __packed; 1461 1462 struct htt_tx_mode_switch_ind { 1463 u8 pad0; 1464 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */ 1465 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */ 1466 u8 pad1[2]; 1467 struct htt_tx_mode_switch_record records[0]; 1468 } __packed; 1469 1470 struct htt_channel_change { 1471 u8 pad[3]; 1472 __le32 freq; 1473 __le32 center_freq1; 1474 __le32 center_freq2; 1475 __le32 phymode; 1476 } __packed; 1477 1478 struct htt_per_peer_tx_stats_ind { 1479 __le32 succ_bytes; 1480 __le32 retry_bytes; 1481 __le32 failed_bytes; 1482 u8 ratecode; 1483 u8 flags; 1484 __le16 peer_id; 1485 __le16 succ_pkts; 1486 __le16 retry_pkts; 1487 __le16 failed_pkts; 1488 __le16 tx_duration; 1489 __le32 reserved1; 1490 __le32 reserved2; 1491 } __packed; 1492 1493 struct htt_peer_tx_stats { 1494 u8 num_ppdu; 1495 u8 ppdu_len; 1496 u8 version; 1497 u8 payload[0]; 1498 } __packed; 1499 1500 union htt_rx_pn_t { 1501 /* WEP: 24-bit PN */ 1502 u32 pn24; 1503 1504 /* TKIP or CCMP: 48-bit PN */ 1505 u64 pn48; 1506 1507 /* WAPI: 128-bit PN */ 1508 u64 pn128[2]; 1509 }; 1510 1511 struct htt_cmd { 1512 struct htt_cmd_hdr hdr; 1513 union { 1514 struct htt_ver_req ver_req; 1515 struct htt_mgmt_tx_desc mgmt_tx; 1516 struct htt_data_tx_desc data_tx; 1517 struct htt_rx_ring_setup rx_setup; 1518 struct htt_stats_req stats_req; 1519 struct htt_oob_sync_req oob_sync_req; 1520 struct htt_aggr_conf aggr_conf; 1521 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg; 1522 struct htt_tx_fetch_resp tx_fetch_resp; 1523 }; 1524 } __packed; 1525 1526 struct htt_resp { 1527 struct htt_resp_hdr hdr; 1528 union { 1529 struct htt_ver_resp ver_resp; 1530 struct htt_mgmt_tx_completion mgmt_tx_completion; 1531 struct htt_data_tx_completion data_tx_completion; 1532 struct htt_rx_indication rx_ind; 1533 struct htt_rx_fragment_indication rx_frag_ind; 1534 struct htt_rx_peer_map peer_map; 1535 struct htt_rx_peer_unmap peer_unmap; 1536 struct htt_rx_flush rx_flush; 1537 struct htt_rx_addba rx_addba; 1538 struct htt_rx_delba rx_delba; 1539 struct htt_security_indication security_indication; 1540 struct htt_rc_update rc_update; 1541 struct htt_rx_test rx_test; 1542 struct htt_pktlog_msg pktlog_msg; 1543 struct htt_stats_conf stats_conf; 1544 struct htt_rx_pn_ind rx_pn_ind; 1545 struct htt_rx_offload_ind rx_offload_ind; 1546 struct htt_rx_in_ord_ind rx_in_ord_ind; 1547 struct htt_tx_fetch_ind tx_fetch_ind; 1548 struct htt_tx_fetch_confirm tx_fetch_confirm; 1549 struct htt_tx_mode_switch_ind tx_mode_switch_ind; 1550 struct htt_channel_change chan_change; 1551 struct htt_peer_tx_stats peer_tx_stats; 1552 }; 1553 } __packed; 1554 1555 /*** host side structures follow ***/ 1556 1557 struct htt_tx_done { 1558 u16 msdu_id; 1559 u16 status; 1560 }; 1561 1562 enum htt_tx_compl_state { 1563 HTT_TX_COMPL_STATE_NONE, 1564 HTT_TX_COMPL_STATE_ACK, 1565 HTT_TX_COMPL_STATE_NOACK, 1566 HTT_TX_COMPL_STATE_DISCARD, 1567 }; 1568 1569 struct htt_peer_map_event { 1570 u8 vdev_id; 1571 u16 peer_id; 1572 u8 addr[ETH_ALEN]; 1573 }; 1574 1575 struct htt_peer_unmap_event { 1576 u16 peer_id; 1577 }; 1578 1579 struct ath10k_htt_txbuf { 1580 struct htt_data_tx_desc_frag frags[2]; 1581 struct ath10k_htc_hdr htc_hdr; 1582 struct htt_cmd_hdr cmd_hdr; 1583 struct htt_data_tx_desc cmd_tx; 1584 } __packed; 1585 1586 struct ath10k_htt { 1587 struct ath10k *ar; 1588 enum ath10k_htc_ep_id eid; 1589 1590 u8 target_version_major; 1591 u8 target_version_minor; 1592 struct completion target_version_received; 1593 u8 max_num_amsdu; 1594 u8 max_num_ampdu; 1595 1596 const enum htt_t2h_msg_type *t2h_msg_types; 1597 u32 t2h_msg_types_max; 1598 1599 struct { 1600 /* 1601 * Ring of network buffer objects - This ring is 1602 * used exclusively by the host SW. This ring 1603 * mirrors the dev_addrs_ring that is shared 1604 * between the host SW and the MAC HW. The host SW 1605 * uses this netbufs ring to locate the network 1606 * buffer objects whose data buffers the HW has 1607 * filled. 1608 */ 1609 struct sk_buff **netbufs_ring; 1610 1611 /* This is used only with firmware supporting IN_ORD_IND. 1612 * 1613 * With Full Rx Reorder the HTT Rx Ring is more of a temporary 1614 * buffer ring from which buffer addresses are copied by the 1615 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND 1616 * pointing to specific (re-ordered) buffers. 1617 * 1618 * FIXME: With kernel generic hashing functions there's a lot 1619 * of hash collisions for sk_buffs. 1620 */ 1621 bool in_ord_rx; 1622 DECLARE_HASHTABLE(skb_table, 4); 1623 1624 /* 1625 * Ring of buffer addresses - 1626 * This ring holds the "physical" device address of the 1627 * rx buffers the host SW provides for the MAC HW to 1628 * fill. 1629 */ 1630 __le32 *paddrs_ring; 1631 1632 /* 1633 * Base address of ring, as a "physical" device address 1634 * rather than a CPU address. 1635 */ 1636 dma_addr_t base_paddr; 1637 1638 /* how many elems in the ring (power of 2) */ 1639 int size; 1640 1641 /* size - 1 */ 1642 unsigned int size_mask; 1643 1644 /* how many rx buffers to keep in the ring */ 1645 int fill_level; 1646 1647 /* how many rx buffers (full+empty) are in the ring */ 1648 int fill_cnt; 1649 1650 /* 1651 * alloc_idx - where HTT SW has deposited empty buffers 1652 * This is allocated in consistent mem, so that the FW can 1653 * read this variable, and program the HW's FW_IDX reg with 1654 * the value of this shadow register. 1655 */ 1656 struct { 1657 __le32 *vaddr; 1658 dma_addr_t paddr; 1659 } alloc_idx; 1660 1661 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1662 struct { 1663 unsigned int msdu_payld; 1664 } sw_rd_idx; 1665 1666 /* 1667 * refill_retry_timer - timer triggered when the ring is 1668 * not refilled to the level expected 1669 */ 1670 struct timer_list refill_retry_timer; 1671 1672 /* Protects access to all rx ring buffer state variables */ 1673 spinlock_t lock; 1674 } rx_ring; 1675 1676 unsigned int prefetch_len; 1677 1678 /* Protects access to pending_tx, num_pending_tx */ 1679 spinlock_t tx_lock; 1680 int max_num_pending_tx; 1681 int num_pending_tx; 1682 int num_pending_mgmt_tx; 1683 struct idr pending_tx; 1684 wait_queue_head_t empty_tx_wq; 1685 1686 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */ 1687 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done); 1688 1689 /* set if host-fw communication goes haywire 1690 * used to avoid further failures 1691 */ 1692 bool rx_confused; 1693 atomic_t num_mpdus_ready; 1694 1695 /* This is used to group tx/rx completions separately and process them 1696 * in batches to reduce cache stalls 1697 */ 1698 struct sk_buff_head rx_compl_q; 1699 struct sk_buff_head rx_in_ord_compl_q; 1700 struct sk_buff_head tx_fetch_ind_q; 1701 1702 /* rx_status template */ 1703 struct ieee80211_rx_status rx_status; 1704 1705 struct { 1706 dma_addr_t paddr; 1707 struct htt_msdu_ext_desc *vaddr; 1708 } frag_desc; 1709 1710 struct { 1711 dma_addr_t paddr; 1712 struct ath10k_htt_txbuf *vaddr; 1713 } txbuf; 1714 1715 struct { 1716 bool enabled; 1717 struct htt_q_state *vaddr; 1718 dma_addr_t paddr; 1719 u16 num_push_allowed; 1720 u16 num_peers; 1721 u16 num_tids; 1722 enum htt_tx_mode_switch_mode mode; 1723 enum htt_q_depth_type type; 1724 } tx_q_state; 1725 1726 bool tx_mem_allocated; 1727 }; 1728 1729 #define RX_HTT_HDR_STATUS_LEN 64 1730 1731 /* This structure layout is programmed via rx ring setup 1732 * so that FW knows how to transfer the rx descriptor to the host. 1733 * Buffers like this are placed on the rx ring. 1734 */ 1735 struct htt_rx_desc { 1736 union { 1737 /* This field is filled on the host using the msdu buffer 1738 * from htt_rx_indication 1739 */ 1740 struct fw_rx_desc_base fw_desc; 1741 u32 pad; 1742 } __packed; 1743 struct { 1744 struct rx_attention attention; 1745 struct rx_frag_info frag_info; 1746 struct rx_mpdu_start mpdu_start; 1747 struct rx_msdu_start msdu_start; 1748 struct rx_msdu_end msdu_end; 1749 struct rx_mpdu_end mpdu_end; 1750 struct rx_ppdu_start ppdu_start; 1751 struct rx_ppdu_end ppdu_end; 1752 } __packed; 1753 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1754 u8 msdu_payload[0]; 1755 }; 1756 1757 #define HTT_RX_DESC_ALIGN 8 1758 1759 #define HTT_MAC_ADDR_LEN 6 1760 1761 /* 1762 * FIX THIS 1763 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 1764 * rounded up to a cache line size. 1765 */ 1766 #define HTT_RX_BUF_SIZE 1920 1767 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 1768 1769 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 1770 * aggregated traffic more nicely. 1771 */ 1772 #define ATH10K_HTT_MAX_NUM_REFILL 100 1773 1774 /* 1775 * DMA_MAP expects the buffer to be an integral number of cache lines. 1776 * Rather than checking the actual cache line size, this code makes a 1777 * conservative estimate of what the cache line size could be. 1778 */ 1779 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 1780 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 1781 1782 /* These values are default in most firmware revisions and apparently are a 1783 * sweet spot performance wise. 1784 */ 1785 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3 1786 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64 1787 1788 int ath10k_htt_connect(struct ath10k_htt *htt); 1789 int ath10k_htt_init(struct ath10k *ar); 1790 int ath10k_htt_setup(struct ath10k_htt *htt); 1791 1792 int ath10k_htt_tx_start(struct ath10k_htt *htt); 1793 void ath10k_htt_tx_stop(struct ath10k_htt *htt); 1794 void ath10k_htt_tx_destroy(struct ath10k_htt *htt); 1795 void ath10k_htt_tx_free(struct ath10k_htt *htt); 1796 1797 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 1798 int ath10k_htt_rx_ring_refill(struct ath10k *ar); 1799 void ath10k_htt_rx_free(struct ath10k_htt *htt); 1800 1801 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1802 void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1803 bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1804 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 1805 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 1806 int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt); 1807 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt); 1808 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 1809 u8 max_subfrms_ampdu, 1810 u8 max_subfrms_amsdu); 1811 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1812 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 1813 __le32 token, 1814 __le16 fetch_seq_num, 1815 struct htt_tx_fetch_record *records, 1816 size_t num_records); 1817 1818 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 1819 struct ieee80211_txq *txq); 1820 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 1821 struct ieee80211_txq *txq); 1822 void ath10k_htt_tx_txq_sync(struct ath10k *ar); 1823 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 1824 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt); 1825 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt); 1826 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 1827 bool is_presp); 1828 1829 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); 1830 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 1831 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu); 1832 int ath10k_htt_tx(struct ath10k_htt *htt, 1833 enum ath10k_hw_txrx_mode txmode, 1834 struct sk_buff *msdu); 1835 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar, 1836 struct sk_buff *skb); 1837 int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget); 1838 1839 #endif 1840