1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HTT_H_ 19 #define _HTT_H_ 20 21 #include <linux/bug.h> 22 #include <linux/interrupt.h> 23 #include <linux/dmapool.h> 24 #include <linux/hashtable.h> 25 #include <linux/kfifo.h> 26 #include <net/mac80211.h> 27 28 #include "htc.h" 29 #include "hw.h" 30 #include "rx_desc.h" 31 #include "hw.h" 32 33 enum htt_dbg_stats_type { 34 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 35 HTT_DBG_STATS_RX_REORDER = 1 << 1, 36 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 37 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 38 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 39 /* bits 5-23 currently reserved */ 40 41 HTT_DBG_NUM_STATS /* keep this last */ 42 }; 43 44 enum htt_h2t_msg_type { /* host-to-target */ 45 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 46 HTT_H2T_MSG_TYPE_TX_FRM = 1, 47 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 48 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 49 HTT_H2T_MSG_TYPE_SYNC = 4, 50 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 51 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 52 53 /* This command is used for sending management frames in HTT < 3.0. 54 * HTT >= 3.0 uses TX_FRM for everything. 55 */ 56 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 57 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11, 58 59 HTT_H2T_NUM_MSGS /* keep this last */ 60 }; 61 62 struct htt_cmd_hdr { 63 u8 msg_type; 64 } __packed; 65 66 struct htt_ver_req { 67 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 68 } __packed; 69 70 /* 71 * HTT tx MSDU descriptor 72 * 73 * The HTT tx MSDU descriptor is created by the host HTT SW for each 74 * tx MSDU. The HTT tx MSDU descriptor contains the information that 75 * the target firmware needs for the FW's tx processing, particularly 76 * for creating the HW msdu descriptor. 77 * The same HTT tx descriptor is used for HL and LL systems, though 78 * a few fields within the tx descriptor are used only by LL or 79 * only by HL. 80 * The HTT tx descriptor is defined in two manners: by a struct with 81 * bitfields, and by a series of [dword offset, bit mask, bit shift] 82 * definitions. 83 * The target should use the struct def, for simplicitly and clarity, 84 * but the host shall use the bit-mast + bit-shift defs, to be endian- 85 * neutral. Specifically, the host shall use the get/set macros built 86 * around the mask + shift defs. 87 */ 88 struct htt_data_tx_desc_frag { 89 union { 90 struct double_word_addr { 91 __le32 paddr; 92 __le32 len; 93 } __packed dword_addr; 94 struct triple_word_addr { 95 __le32 paddr_lo; 96 __le16 paddr_hi; 97 __le16 len_16; 98 } __packed tword_addr; 99 } __packed; 100 } __packed; 101 102 struct htt_msdu_ext_desc { 103 __le32 tso_flag[3]; 104 __le16 ip_identification; 105 u8 flags; 106 u8 reserved; 107 struct htt_data_tx_desc_frag frags[6]; 108 }; 109 110 struct htt_msdu_ext_desc_64 { 111 __le32 tso_flag[5]; 112 __le16 ip_identification; 113 u8 flags; 114 u8 reserved; 115 struct htt_data_tx_desc_frag frags[6]; 116 }; 117 118 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0) 119 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1) 120 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2) 121 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3) 122 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4) 123 124 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \ 125 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \ 126 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \ 127 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \ 128 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE) 129 130 enum htt_data_tx_desc_flags0 { 131 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 132 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 133 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 134 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 135 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 136 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 137 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 138 }; 139 140 enum htt_data_tx_desc_flags1 { 141 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 142 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 143 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 144 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 145 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 146 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 147 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 148 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 149 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 150 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 151 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 152 }; 153 154 enum htt_data_tx_ext_tid { 155 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 156 HTT_DATA_TX_EXT_TID_MGMT = 17, 157 HTT_DATA_TX_EXT_TID_INVALID = 31 158 }; 159 160 #define HTT_INVALID_PEERID 0xFFFF 161 162 /* 163 * htt_data_tx_desc - used for data tx path 164 * 165 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 166 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 167 * for special kinds of tids 168 * postponed: only for HL hosts. indicates if this is a resend 169 * (HL hosts manage queues on the host ) 170 * more_in_batch: only for HL hosts. indicates if more packets are 171 * pending. this allows target to wait and aggregate 172 * freq: 0 means home channel of given vdev. intended for offchannel 173 */ 174 struct htt_data_tx_desc { 175 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 176 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 177 __le16 len; 178 __le16 id; 179 __le32 frags_paddr; 180 union { 181 __le32 peerid; 182 struct { 183 __le16 peerid; 184 __le16 freq; 185 } __packed offchan_tx; 186 } __packed; 187 u8 prefetch[0]; /* start of frame, for FW classification engine */ 188 } __packed; 189 190 struct htt_data_tx_desc_64 { 191 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 192 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 193 __le16 len; 194 __le16 id; 195 __le64 frags_paddr; 196 union { 197 __le32 peerid; 198 struct { 199 __le16 peerid; 200 __le16 freq; 201 } __packed offchan_tx; 202 } __packed; 203 u8 prefetch[0]; /* start of frame, for FW classification engine */ 204 } __packed; 205 206 enum htt_rx_ring_flags { 207 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 208 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 209 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 210 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 211 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 212 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 213 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 214 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 215 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 216 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 217 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 218 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 219 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 220 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 221 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 222 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 223 }; 224 225 #define HTT_RX_RING_SIZE_MIN 128 226 #define HTT_RX_RING_SIZE_MAX 2048 227 #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX 228 #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1) 229 #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1) 230 231 struct htt_rx_ring_setup_ring32 { 232 __le32 fw_idx_shadow_reg_paddr; 233 __le32 rx_ring_base_paddr; 234 __le16 rx_ring_len; /* in 4-byte words */ 235 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 236 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 237 __le16 fw_idx_init_val; 238 239 /* the following offsets are in 4-byte units */ 240 __le16 mac80211_hdr_offset; 241 __le16 msdu_payload_offset; 242 __le16 ppdu_start_offset; 243 __le16 ppdu_end_offset; 244 __le16 mpdu_start_offset; 245 __le16 mpdu_end_offset; 246 __le16 msdu_start_offset; 247 __le16 msdu_end_offset; 248 __le16 rx_attention_offset; 249 __le16 frag_info_offset; 250 } __packed; 251 252 struct htt_rx_ring_setup_ring64 { 253 __le64 fw_idx_shadow_reg_paddr; 254 __le64 rx_ring_base_paddr; 255 __le16 rx_ring_len; /* in 4-byte words */ 256 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 257 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 258 __le16 fw_idx_init_val; 259 260 /* the following offsets are in 4-byte units */ 261 __le16 mac80211_hdr_offset; 262 __le16 msdu_payload_offset; 263 __le16 ppdu_start_offset; 264 __le16 ppdu_end_offset; 265 __le16 mpdu_start_offset; 266 __le16 mpdu_end_offset; 267 __le16 msdu_start_offset; 268 __le16 msdu_end_offset; 269 __le16 rx_attention_offset; 270 __le16 frag_info_offset; 271 } __packed; 272 273 struct htt_rx_ring_setup_hdr { 274 u8 num_rings; /* supported values: 1, 2 */ 275 __le16 rsvd0; 276 } __packed; 277 278 struct htt_rx_ring_setup_32 { 279 struct htt_rx_ring_setup_hdr hdr; 280 struct htt_rx_ring_setup_ring32 rings[0]; 281 } __packed; 282 283 struct htt_rx_ring_setup_64 { 284 struct htt_rx_ring_setup_hdr hdr; 285 struct htt_rx_ring_setup_ring64 rings[0]; 286 } __packed; 287 288 /* 289 * htt_stats_req - request target to send specified statistics 290 * 291 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 292 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 293 * so make sure its little-endian. 294 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 295 * so make sure its little-endian. 296 * @cfg_val: stat_type specific configuration 297 * @stat_type: see %htt_dbg_stats_type 298 * @cookie_lsb: used for confirmation message from target->host 299 * @cookie_msb: ditto as %cookie 300 */ 301 struct htt_stats_req { 302 u8 upload_types[3]; 303 u8 rsvd0; 304 u8 reset_types[3]; 305 struct { 306 u8 mpdu_bytes; 307 u8 mpdu_num_msdus; 308 u8 msdu_bytes; 309 } __packed; 310 u8 stat_type; 311 __le32 cookie_lsb; 312 __le32 cookie_msb; 313 } __packed; 314 315 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 316 317 /* 318 * htt_oob_sync_req - request out-of-band sync 319 * 320 * The HTT SYNC tells the target to suspend processing of subsequent 321 * HTT host-to-target messages until some other target agent locally 322 * informs the target HTT FW that the current sync counter is equal to 323 * or greater than (in a modulo sense) the sync counter specified in 324 * the SYNC message. 325 * 326 * This allows other host-target components to synchronize their operation 327 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 328 * security key has been downloaded to and activated by the target. 329 * In the absence of any explicit synchronization counter value 330 * specification, the target HTT FW will use zero as the default current 331 * sync value. 332 * 333 * The HTT target FW will suspend its host->target message processing as long 334 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 335 */ 336 struct htt_oob_sync_req { 337 u8 sync_count; 338 __le16 rsvd0; 339 } __packed; 340 341 struct htt_aggr_conf { 342 u8 max_num_ampdu_subframes; 343 /* amsdu_subframes is limited by 0x1F mask */ 344 u8 max_num_amsdu_subframes; 345 } __packed; 346 347 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 348 struct htt_mgmt_tx_desc_qca99x0 { 349 __le32 rate; 350 } __packed; 351 352 struct htt_mgmt_tx_desc { 353 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 354 __le32 msdu_paddr; 355 __le32 desc_id; 356 __le32 len; 357 __le32 vdev_id; 358 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 359 union { 360 struct htt_mgmt_tx_desc_qca99x0 qca99x0; 361 } __packed; 362 } __packed; 363 364 enum htt_mgmt_tx_status { 365 HTT_MGMT_TX_STATUS_OK = 0, 366 HTT_MGMT_TX_STATUS_RETRY = 1, 367 HTT_MGMT_TX_STATUS_DROP = 2 368 }; 369 370 /*=== target -> host messages ===============================================*/ 371 372 enum htt_main_t2h_msg_type { 373 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0, 374 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1, 375 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2, 376 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3, 377 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 378 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5, 379 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6, 380 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 381 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8, 382 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9, 383 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 384 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb, 385 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 386 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 387 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 388 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10, 389 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 390 HTT_MAIN_T2H_MSG_TYPE_TEST, 391 /* keep this last */ 392 HTT_MAIN_T2H_NUM_MSGS 393 }; 394 395 enum htt_10x_t2h_msg_type { 396 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0, 397 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1, 398 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2, 399 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3, 400 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 401 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5, 402 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6, 403 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 404 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8, 405 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9, 406 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 407 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb, 408 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 409 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 410 HTT_10X_T2H_MSG_TYPE_TEST = 0xe, 411 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 412 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11, 413 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12, 414 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13, 415 /* keep this last */ 416 HTT_10X_T2H_NUM_MSGS 417 }; 418 419 enum htt_tlv_t2h_msg_type { 420 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0, 421 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1, 422 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2, 423 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3, 424 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 425 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5, 426 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6, 427 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 428 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8, 429 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9, 430 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 431 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb, 432 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */ 433 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 434 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 435 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 436 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10, 437 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 438 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 439 /* 0x13 reservd */ 440 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 441 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 442 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 443 HTT_TLV_T2H_MSG_TYPE_TEST, 444 /* keep this last */ 445 HTT_TLV_T2H_NUM_MSGS 446 }; 447 448 enum htt_10_4_t2h_msg_type { 449 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0, 450 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1, 451 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2, 452 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3, 453 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 454 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5, 455 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6, 456 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 457 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8, 458 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9, 459 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 460 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb, 461 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 462 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 463 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 464 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 465 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10, 466 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11, 467 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12, 468 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13, 469 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14, 470 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15, 471 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16, 472 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17, 473 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18, 474 /* 0x19 to 0x2f are reserved */ 475 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30, 476 HTT_10_4_T2H_MSG_TYPE_PEER_STATS = 0x31, 477 /* keep this last */ 478 HTT_10_4_T2H_NUM_MSGS 479 }; 480 481 enum htt_t2h_msg_type { 482 HTT_T2H_MSG_TYPE_VERSION_CONF, 483 HTT_T2H_MSG_TYPE_RX_IND, 484 HTT_T2H_MSG_TYPE_RX_FLUSH, 485 HTT_T2H_MSG_TYPE_PEER_MAP, 486 HTT_T2H_MSG_TYPE_PEER_UNMAP, 487 HTT_T2H_MSG_TYPE_RX_ADDBA, 488 HTT_T2H_MSG_TYPE_RX_DELBA, 489 HTT_T2H_MSG_TYPE_TX_COMPL_IND, 490 HTT_T2H_MSG_TYPE_PKTLOG, 491 HTT_T2H_MSG_TYPE_STATS_CONF, 492 HTT_T2H_MSG_TYPE_RX_FRAG_IND, 493 HTT_T2H_MSG_TYPE_SEC_IND, 494 HTT_T2H_MSG_TYPE_RC_UPDATE_IND, 495 HTT_T2H_MSG_TYPE_TX_INSPECT_IND, 496 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION, 497 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, 498 HTT_T2H_MSG_TYPE_RX_PN_IND, 499 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND, 500 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND, 501 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE, 502 HTT_T2H_MSG_TYPE_CHAN_CHANGE, 503 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR, 504 HTT_T2H_MSG_TYPE_AGGR_CONF, 505 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, 506 HTT_T2H_MSG_TYPE_TEST, 507 HTT_T2H_MSG_TYPE_EN_STATS, 508 HTT_T2H_MSG_TYPE_TX_FETCH_IND, 509 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM, 510 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND, 511 HTT_T2H_MSG_TYPE_PEER_STATS, 512 /* keep this last */ 513 HTT_T2H_NUM_MSGS 514 }; 515 516 /* 517 * htt_resp_hdr - header for target-to-host messages 518 * 519 * msg_type: see htt_t2h_msg_type 520 */ 521 struct htt_resp_hdr { 522 u8 msg_type; 523 } __packed; 524 525 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 526 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 527 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 528 529 /* htt_ver_resp - response sent for htt_ver_req */ 530 struct htt_ver_resp { 531 u8 minor; 532 u8 major; 533 u8 rsvd0; 534 } __packed; 535 536 struct htt_mgmt_tx_completion { 537 u8 rsvd0; 538 u8 rsvd1; 539 u8 rsvd2; 540 __le32 desc_id; 541 __le32 status; 542 } __packed; 543 544 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F) 545 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 546 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5) 547 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6) 548 549 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 550 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 551 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 552 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 553 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 554 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 555 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 556 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 557 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 558 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 559 560 struct htt_rx_indication_hdr { 561 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 562 __le16 peer_id; 563 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 564 } __packed; 565 566 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 567 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 568 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 569 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 570 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 571 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 572 573 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 574 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 575 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 576 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 577 578 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 579 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 580 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 581 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 582 583 enum htt_rx_legacy_rate { 584 HTT_RX_OFDM_48 = 0, 585 HTT_RX_OFDM_24 = 1, 586 HTT_RX_OFDM_12, 587 HTT_RX_OFDM_6, 588 HTT_RX_OFDM_54, 589 HTT_RX_OFDM_36, 590 HTT_RX_OFDM_18, 591 HTT_RX_OFDM_9, 592 593 /* long preamble */ 594 HTT_RX_CCK_11_LP = 0, 595 HTT_RX_CCK_5_5_LP = 1, 596 HTT_RX_CCK_2_LP, 597 HTT_RX_CCK_1_LP, 598 /* short preamble */ 599 HTT_RX_CCK_11_SP, 600 HTT_RX_CCK_5_5_SP, 601 HTT_RX_CCK_2_SP 602 }; 603 604 enum htt_rx_legacy_rate_type { 605 HTT_RX_LEGACY_RATE_OFDM = 0, 606 HTT_RX_LEGACY_RATE_CCK 607 }; 608 609 enum htt_rx_preamble_type { 610 HTT_RX_LEGACY = 0x4, 611 HTT_RX_HT = 0x8, 612 HTT_RX_HT_WITH_TXBF = 0x9, 613 HTT_RX_VHT = 0xC, 614 HTT_RX_VHT_WITH_TXBF = 0xD, 615 }; 616 617 /* 618 * Fields: phy_err_valid, phy_err_code, tsf, 619 * usec_timestamp, sub_usec_timestamp 620 * ..are valid only if end_valid == 1. 621 * 622 * Fields: rssi_chains, legacy_rate_type, 623 * legacy_rate_cck, preamble_type, service, 624 * vht_sig_* 625 * ..are valid only if start_valid == 1; 626 */ 627 struct htt_rx_indication_ppdu { 628 u8 combined_rssi; 629 u8 sub_usec_timestamp; 630 u8 phy_err_code; 631 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 632 struct { 633 u8 pri20_db; 634 u8 ext20_db; 635 u8 ext40_db; 636 u8 ext80_db; 637 } __packed rssi_chains[4]; 638 __le32 tsf; 639 __le32 usec_timestamp; 640 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 641 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 642 } __packed; 643 644 enum htt_rx_mpdu_status { 645 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 646 HTT_RX_IND_MPDU_STATUS_OK, 647 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 648 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 649 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 650 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 651 /* only accept EAPOL frames */ 652 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 653 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 654 /* Non-data in promiscuous mode */ 655 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 656 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 657 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 658 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 659 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 660 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 661 662 /* 663 * MISC: discard for unspecified reasons. 664 * Leave this enum value last. 665 */ 666 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 667 }; 668 669 struct htt_rx_indication_mpdu_range { 670 u8 mpdu_count; 671 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 672 u8 pad0; 673 u8 pad1; 674 } __packed; 675 676 struct htt_rx_indication_prefix { 677 __le16 fw_rx_desc_bytes; 678 u8 pad0; 679 u8 pad1; 680 }; 681 682 struct htt_rx_indication { 683 struct htt_rx_indication_hdr hdr; 684 struct htt_rx_indication_ppdu ppdu; 685 struct htt_rx_indication_prefix prefix; 686 687 /* 688 * the following fields are both dynamically sized, so 689 * take care addressing them 690 */ 691 692 /* the size of this is %fw_rx_desc_bytes */ 693 struct fw_rx_desc_base fw_desc; 694 695 /* 696 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 697 * and has %num_mpdu_ranges elements. 698 */ 699 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 700 } __packed; 701 702 static inline struct htt_rx_indication_mpdu_range * 703 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 704 { 705 void *ptr = rx_ind; 706 707 ptr += sizeof(rx_ind->hdr) 708 + sizeof(rx_ind->ppdu) 709 + sizeof(rx_ind->prefix) 710 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 711 return ptr; 712 } 713 714 enum htt_rx_flush_mpdu_status { 715 HTT_RX_FLUSH_MPDU_DISCARD = 0, 716 HTT_RX_FLUSH_MPDU_REORDER = 1, 717 }; 718 719 /* 720 * htt_rx_flush - discard or reorder given range of mpdus 721 * 722 * Note: host must check if all sequence numbers between 723 * [seq_num_start, seq_num_end-1] are valid. 724 */ 725 struct htt_rx_flush { 726 __le16 peer_id; 727 u8 tid; 728 u8 rsvd0; 729 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 730 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 731 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 732 }; 733 734 struct htt_rx_peer_map { 735 u8 vdev_id; 736 __le16 peer_id; 737 u8 addr[6]; 738 u8 rsvd0; 739 u8 rsvd1; 740 } __packed; 741 742 struct htt_rx_peer_unmap { 743 u8 rsvd0; 744 __le16 peer_id; 745 } __packed; 746 747 enum htt_security_types { 748 HTT_SECURITY_NONE, 749 HTT_SECURITY_WEP128, 750 HTT_SECURITY_WEP104, 751 HTT_SECURITY_WEP40, 752 HTT_SECURITY_TKIP, 753 HTT_SECURITY_TKIP_NOMIC, 754 HTT_SECURITY_AES_CCMP, 755 HTT_SECURITY_WAPI, 756 757 HTT_NUM_SECURITY_TYPES /* keep this last! */ 758 }; 759 760 enum htt_security_flags { 761 #define HTT_SECURITY_TYPE_MASK 0x7F 762 #define HTT_SECURITY_TYPE_LSB 0 763 HTT_SECURITY_IS_UNICAST = 1 << 7 764 }; 765 766 struct htt_security_indication { 767 union { 768 /* dont use bitfields; undefined behaviour */ 769 u8 flags; /* %htt_security_flags */ 770 struct { 771 u8 security_type:7, /* %htt_security_types */ 772 is_unicast:1; 773 } __packed; 774 } __packed; 775 __le16 peer_id; 776 u8 michael_key[8]; 777 u8 wapi_rsc[16]; 778 } __packed; 779 780 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 781 #define HTT_RX_BA_INFO0_TID_LSB 0 782 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 783 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 784 785 struct htt_rx_addba { 786 u8 window_size; 787 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 788 } __packed; 789 790 struct htt_rx_delba { 791 u8 rsvd0; 792 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 793 } __packed; 794 795 enum htt_data_tx_status { 796 HTT_DATA_TX_STATUS_OK = 0, 797 HTT_DATA_TX_STATUS_DISCARD = 1, 798 HTT_DATA_TX_STATUS_NO_ACK = 2, 799 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 800 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 801 }; 802 803 enum htt_data_tx_flags { 804 #define HTT_DATA_TX_STATUS_MASK 0x07 805 #define HTT_DATA_TX_STATUS_LSB 0 806 #define HTT_DATA_TX_TID_MASK 0x78 807 #define HTT_DATA_TX_TID_LSB 3 808 HTT_DATA_TX_TID_INVALID = 1 << 7 809 }; 810 811 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 812 813 struct htt_data_tx_completion { 814 union { 815 u8 flags; 816 struct { 817 u8 status:3, 818 tid:4, 819 tid_invalid:1; 820 } __packed; 821 } __packed; 822 u8 num_msdus; 823 u8 rsvd0; 824 __le16 msdus[0]; /* variable length based on %num_msdus */ 825 } __packed; 826 827 struct htt_tx_compl_ind_base { 828 u32 hdr; 829 u16 payload[1/*or more*/]; 830 } __packed; 831 832 struct htt_rc_tx_done_params { 833 u32 rate_code; 834 u32 rate_code_flags; 835 u32 flags; 836 u32 num_enqued; /* 1 for non-AMPDU */ 837 u32 num_retries; 838 u32 num_failed; /* for AMPDU */ 839 u32 ack_rssi; 840 u32 time_stamp; 841 u32 is_probe; 842 }; 843 844 struct htt_rc_update { 845 u8 vdev_id; 846 __le16 peer_id; 847 u8 addr[6]; 848 u8 num_elems; 849 u8 rsvd0; 850 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 851 } __packed; 852 853 /* see htt_rx_indication for similar fields and descriptions */ 854 struct htt_rx_fragment_indication { 855 union { 856 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 857 struct { 858 u8 ext_tid:5, 859 flush_valid:1; 860 } __packed; 861 } __packed; 862 __le16 peer_id; 863 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 864 __le16 fw_rx_desc_bytes; 865 __le16 rsvd0; 866 867 u8 fw_msdu_rx_desc[0]; 868 } __packed; 869 870 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 871 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 872 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 873 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 874 875 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 876 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 877 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 878 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 879 880 struct htt_rx_pn_ind { 881 __le16 peer_id; 882 u8 tid; 883 u8 seqno_start; 884 u8 seqno_end; 885 u8 pn_ie_count; 886 u8 reserved; 887 u8 pn_ies[0]; 888 } __packed; 889 890 struct htt_rx_offload_msdu { 891 __le16 msdu_len; 892 __le16 peer_id; 893 u8 vdev_id; 894 u8 tid; 895 u8 fw_desc; 896 u8 payload[0]; 897 } __packed; 898 899 struct htt_rx_offload_ind { 900 u8 reserved; 901 __le16 msdu_count; 902 } __packed; 903 904 struct htt_rx_in_ord_msdu_desc { 905 __le32 msdu_paddr; 906 __le16 msdu_len; 907 u8 fw_desc; 908 u8 reserved; 909 } __packed; 910 911 struct htt_rx_in_ord_msdu_desc_ext { 912 __le64 msdu_paddr; 913 __le16 msdu_len; 914 u8 fw_desc; 915 u8 reserved; 916 } __packed; 917 918 struct htt_rx_in_ord_ind { 919 u8 info; 920 __le16 peer_id; 921 u8 vdev_id; 922 u8 reserved; 923 __le16 msdu_count; 924 union { 925 struct htt_rx_in_ord_msdu_desc msdu_descs32[0]; 926 struct htt_rx_in_ord_msdu_desc_ext msdu_descs64[0]; 927 } __packed; 928 } __packed; 929 930 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f 931 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 932 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020 933 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 934 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040 935 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 936 937 /* 938 * target -> host test message definition 939 * 940 * The following field definitions describe the format of the test 941 * message sent from the target to the host. 942 * The message consists of a 4-octet header, followed by a variable 943 * number of 32-bit integer values, followed by a variable number 944 * of 8-bit character values. 945 * 946 * |31 16|15 8|7 0| 947 * |-----------------------------------------------------------| 948 * | num chars | num ints | msg type | 949 * |-----------------------------------------------------------| 950 * | int 0 | 951 * |-----------------------------------------------------------| 952 * | int 1 | 953 * |-----------------------------------------------------------| 954 * | ... | 955 * |-----------------------------------------------------------| 956 * | char 3 | char 2 | char 1 | char 0 | 957 * |-----------------------------------------------------------| 958 * | | | ... | char 4 | 959 * |-----------------------------------------------------------| 960 * - MSG_TYPE 961 * Bits 7:0 962 * Purpose: identifies this as a test message 963 * Value: HTT_MSG_TYPE_TEST 964 * - NUM_INTS 965 * Bits 15:8 966 * Purpose: indicate how many 32-bit integers follow the message header 967 * - NUM_CHARS 968 * Bits 31:16 969 * Purpose: indicate how many 8-bit characters follow the series of integers 970 */ 971 struct htt_rx_test { 972 u8 num_ints; 973 __le16 num_chars; 974 975 /* payload consists of 2 lists: 976 * a) num_ints * sizeof(__le32) 977 * b) num_chars * sizeof(u8) aligned to 4bytes 978 */ 979 u8 payload[0]; 980 } __packed; 981 982 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 983 { 984 return (__le32 *)rx_test->payload; 985 } 986 987 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 988 { 989 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 990 } 991 992 /* 993 * target -> host packet log message 994 * 995 * The following field definitions describe the format of the packet log 996 * message sent from the target to the host. 997 * The message consists of a 4-octet header,followed by a variable number 998 * of 32-bit character values. 999 * 1000 * |31 24|23 16|15 8|7 0| 1001 * |-----------------------------------------------------------| 1002 * | | | | msg type | 1003 * |-----------------------------------------------------------| 1004 * | payload | 1005 * |-----------------------------------------------------------| 1006 * - MSG_TYPE 1007 * Bits 7:0 1008 * Purpose: identifies this as a test message 1009 * Value: HTT_MSG_TYPE_PACKETLOG 1010 */ 1011 struct htt_pktlog_msg { 1012 u8 pad[3]; 1013 u8 payload[0]; 1014 } __packed; 1015 1016 struct htt_dbg_stats_rx_reorder_stats { 1017 /* Non QoS MPDUs received */ 1018 __le32 deliver_non_qos; 1019 1020 /* MPDUs received in-order */ 1021 __le32 deliver_in_order; 1022 1023 /* Flush due to reorder timer expired */ 1024 __le32 deliver_flush_timeout; 1025 1026 /* Flush due to move out of window */ 1027 __le32 deliver_flush_oow; 1028 1029 /* Flush due to DELBA */ 1030 __le32 deliver_flush_delba; 1031 1032 /* MPDUs dropped due to FCS error */ 1033 __le32 fcs_error; 1034 1035 /* MPDUs dropped due to monitor mode non-data packet */ 1036 __le32 mgmt_ctrl; 1037 1038 /* MPDUs dropped due to invalid peer */ 1039 __le32 invalid_peer; 1040 1041 /* MPDUs dropped due to duplication (non aggregation) */ 1042 __le32 dup_non_aggr; 1043 1044 /* MPDUs dropped due to processed before */ 1045 __le32 dup_past; 1046 1047 /* MPDUs dropped due to duplicate in reorder queue */ 1048 __le32 dup_in_reorder; 1049 1050 /* Reorder timeout happened */ 1051 __le32 reorder_timeout; 1052 1053 /* invalid bar ssn */ 1054 __le32 invalid_bar_ssn; 1055 1056 /* reorder reset due to bar ssn */ 1057 __le32 ssn_reset; 1058 }; 1059 1060 struct htt_dbg_stats_wal_tx_stats { 1061 /* Num HTT cookies queued to dispatch list */ 1062 __le32 comp_queued; 1063 1064 /* Num HTT cookies dispatched */ 1065 __le32 comp_delivered; 1066 1067 /* Num MSDU queued to WAL */ 1068 __le32 msdu_enqued; 1069 1070 /* Num MPDU queue to WAL */ 1071 __le32 mpdu_enqued; 1072 1073 /* Num MSDUs dropped by WMM limit */ 1074 __le32 wmm_drop; 1075 1076 /* Num Local frames queued */ 1077 __le32 local_enqued; 1078 1079 /* Num Local frames done */ 1080 __le32 local_freed; 1081 1082 /* Num queued to HW */ 1083 __le32 hw_queued; 1084 1085 /* Num PPDU reaped from HW */ 1086 __le32 hw_reaped; 1087 1088 /* Num underruns */ 1089 __le32 underrun; 1090 1091 /* Num PPDUs cleaned up in TX abort */ 1092 __le32 tx_abort; 1093 1094 /* Num MPDUs requed by SW */ 1095 __le32 mpdus_requed; 1096 1097 /* excessive retries */ 1098 __le32 tx_ko; 1099 1100 /* data hw rate code */ 1101 __le32 data_rc; 1102 1103 /* Scheduler self triggers */ 1104 __le32 self_triggers; 1105 1106 /* frames dropped due to excessive sw retries */ 1107 __le32 sw_retry_failure; 1108 1109 /* illegal rate phy errors */ 1110 __le32 illgl_rate_phy_err; 1111 1112 /* wal pdev continuous xretry */ 1113 __le32 pdev_cont_xretry; 1114 1115 /* wal pdev continuous xretry */ 1116 __le32 pdev_tx_timeout; 1117 1118 /* wal pdev resets */ 1119 __le32 pdev_resets; 1120 1121 __le32 phy_underrun; 1122 1123 /* MPDU is more than txop limit */ 1124 __le32 txop_ovf; 1125 } __packed; 1126 1127 struct htt_dbg_stats_wal_rx_stats { 1128 /* Cnts any change in ring routing mid-ppdu */ 1129 __le32 mid_ppdu_route_change; 1130 1131 /* Total number of statuses processed */ 1132 __le32 status_rcvd; 1133 1134 /* Extra frags on rings 0-3 */ 1135 __le32 r0_frags; 1136 __le32 r1_frags; 1137 __le32 r2_frags; 1138 __le32 r3_frags; 1139 1140 /* MSDUs / MPDUs delivered to HTT */ 1141 __le32 htt_msdus; 1142 __le32 htt_mpdus; 1143 1144 /* MSDUs / MPDUs delivered to local stack */ 1145 __le32 loc_msdus; 1146 __le32 loc_mpdus; 1147 1148 /* AMSDUs that have more MSDUs than the status ring size */ 1149 __le32 oversize_amsdu; 1150 1151 /* Number of PHY errors */ 1152 __le32 phy_errs; 1153 1154 /* Number of PHY errors drops */ 1155 __le32 phy_err_drop; 1156 1157 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1158 __le32 mpdu_errs; 1159 } __packed; 1160 1161 struct htt_dbg_stats_wal_peer_stats { 1162 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 1163 } __packed; 1164 1165 struct htt_dbg_stats_wal_pdev_txrx { 1166 struct htt_dbg_stats_wal_tx_stats tx_stats; 1167 struct htt_dbg_stats_wal_rx_stats rx_stats; 1168 struct htt_dbg_stats_wal_peer_stats peer_stats; 1169 } __packed; 1170 1171 struct htt_dbg_stats_rx_rate_info { 1172 __le32 mcs[10]; 1173 __le32 sgi[10]; 1174 __le32 nss[4]; 1175 __le32 stbc[10]; 1176 __le32 bw[3]; 1177 __le32 pream[6]; 1178 __le32 ldpc; 1179 __le32 txbf; 1180 }; 1181 1182 /* 1183 * htt_dbg_stats_status - 1184 * present - The requested stats have been delivered in full. 1185 * This indicates that either the stats information was contained 1186 * in its entirety within this message, or else this message 1187 * completes the delivery of the requested stats info that was 1188 * partially delivered through earlier STATS_CONF messages. 1189 * partial - The requested stats have been delivered in part. 1190 * One or more subsequent STATS_CONF messages with the same 1191 * cookie value will be sent to deliver the remainder of the 1192 * information. 1193 * error - The requested stats could not be delivered, for example due 1194 * to a shortage of memory to construct a message holding the 1195 * requested stats. 1196 * invalid - The requested stat type is either not recognized, or the 1197 * target is configured to not gather the stats type in question. 1198 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1199 * series_done - This special value indicates that no further stats info 1200 * elements are present within a series of stats info elems 1201 * (within a stats upload confirmation message). 1202 */ 1203 enum htt_dbg_stats_status { 1204 HTT_DBG_STATS_STATUS_PRESENT = 0, 1205 HTT_DBG_STATS_STATUS_PARTIAL = 1, 1206 HTT_DBG_STATS_STATUS_ERROR = 2, 1207 HTT_DBG_STATS_STATUS_INVALID = 3, 1208 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 1209 }; 1210 1211 /* 1212 * target -> host statistics upload 1213 * 1214 * The following field definitions describe the format of the HTT target 1215 * to host stats upload confirmation message. 1216 * The message contains a cookie echoed from the HTT host->target stats 1217 * upload request, which identifies which request the confirmation is 1218 * for, and a series of tag-length-value stats information elements. 1219 * The tag-length header for each stats info element also includes a 1220 * status field, to indicate whether the request for the stat type in 1221 * question was fully met, partially met, unable to be met, or invalid 1222 * (if the stat type in question is disabled in the target). 1223 * A special value of all 1's in this status field is used to indicate 1224 * the end of the series of stats info elements. 1225 * 1226 * 1227 * |31 16|15 8|7 5|4 0| 1228 * |------------------------------------------------------------| 1229 * | reserved | msg type | 1230 * |------------------------------------------------------------| 1231 * | cookie LSBs | 1232 * |------------------------------------------------------------| 1233 * | cookie MSBs | 1234 * |------------------------------------------------------------| 1235 * | stats entry length | reserved | S |stat type| 1236 * |------------------------------------------------------------| 1237 * | | 1238 * | type-specific stats info | 1239 * | | 1240 * |------------------------------------------------------------| 1241 * | stats entry length | reserved | S |stat type| 1242 * |------------------------------------------------------------| 1243 * | | 1244 * | type-specific stats info | 1245 * | | 1246 * |------------------------------------------------------------| 1247 * | n/a | reserved | 111 | n/a | 1248 * |------------------------------------------------------------| 1249 * Header fields: 1250 * - MSG_TYPE 1251 * Bits 7:0 1252 * Purpose: identifies this is a statistics upload confirmation message 1253 * Value: 0x9 1254 * - COOKIE_LSBS 1255 * Bits 31:0 1256 * Purpose: Provide a mechanism to match a target->host stats confirmation 1257 * message with its preceding host->target stats request message. 1258 * Value: LSBs of the opaque cookie specified by the host-side requestor 1259 * - COOKIE_MSBS 1260 * Bits 31:0 1261 * Purpose: Provide a mechanism to match a target->host stats confirmation 1262 * message with its preceding host->target stats request message. 1263 * Value: MSBs of the opaque cookie specified by the host-side requestor 1264 * 1265 * Stats Information Element tag-length header fields: 1266 * - STAT_TYPE 1267 * Bits 4:0 1268 * Purpose: identifies the type of statistics info held in the 1269 * following information element 1270 * Value: htt_dbg_stats_type 1271 * - STATUS 1272 * Bits 7:5 1273 * Purpose: indicate whether the requested stats are present 1274 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 1275 * the completion of the stats entry series 1276 * - LENGTH 1277 * Bits 31:16 1278 * Purpose: indicate the stats information size 1279 * Value: This field specifies the number of bytes of stats information 1280 * that follows the element tag-length header. 1281 * It is expected but not required that this length is a multiple of 1282 * 4 bytes. Even if the length is not an integer multiple of 4, the 1283 * subsequent stats entry header will begin on a 4-byte aligned 1284 * boundary. 1285 */ 1286 1287 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1288 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1289 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1290 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1291 1292 struct htt_stats_conf_item { 1293 union { 1294 u8 info; 1295 struct { 1296 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1297 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1298 } __packed; 1299 } __packed; 1300 u8 pad; 1301 __le16 length; 1302 u8 payload[0]; /* roundup(length, 4) long */ 1303 } __packed; 1304 1305 struct htt_stats_conf { 1306 u8 pad[3]; 1307 __le32 cookie_lsb; 1308 __le32 cookie_msb; 1309 1310 /* each item has variable length! */ 1311 struct htt_stats_conf_item items[0]; 1312 } __packed; 1313 1314 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1315 const struct htt_stats_conf_item *item) 1316 { 1317 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1318 } 1319 1320 /* 1321 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1322 * 1323 * The following field definitions describe the format of the HTT host 1324 * to target frag_desc/msdu_ext bank configuration message. 1325 * The message contains the based address and the min and max id of the 1326 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1327 * MSDU_EXT/FRAG_DESC. 1328 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1329 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1330 * the hardware does the mapping/translation. 1331 * 1332 * Total banks that can be configured is configured to 16. 1333 * 1334 * This should be called before any TX has be initiated by the HTT 1335 * 1336 * |31 16|15 8|7 5|4 0| 1337 * |------------------------------------------------------------| 1338 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1339 * |------------------------------------------------------------| 1340 * | BANK0_BASE_ADDRESS | 1341 * |------------------------------------------------------------| 1342 * | ... | 1343 * |------------------------------------------------------------| 1344 * | BANK15_BASE_ADDRESS | 1345 * |------------------------------------------------------------| 1346 * | BANK0_MAX_ID | BANK0_MIN_ID | 1347 * |------------------------------------------------------------| 1348 * | ... | 1349 * |------------------------------------------------------------| 1350 * | BANK15_MAX_ID | BANK15_MIN_ID | 1351 * |------------------------------------------------------------| 1352 * Header fields: 1353 * - MSG_TYPE 1354 * Bits 7:0 1355 * Value: 0x6 1356 * - BANKx_BASE_ADDRESS 1357 * Bits 31:0 1358 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1359 * bank physical/bus address. 1360 * - BANKx_MIN_ID 1361 * Bits 15:0 1362 * Purpose: Provide a mechanism to specify the min index that needs to 1363 * mapped. 1364 * - BANKx_MAX_ID 1365 * Bits 31:16 1366 * Purpose: Provide a mechanism to specify the max index that needs to 1367 * 1368 */ 1369 struct htt_frag_desc_bank_id { 1370 __le16 bank_min_id; 1371 __le16 bank_max_id; 1372 } __packed; 1373 1374 /* real is 16 but it wouldn't fit in the max htt message size 1375 * so we use a conservatively safe value for now 1376 */ 1377 #define HTT_FRAG_DESC_BANK_MAX 4 1378 1379 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1380 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1381 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2) 1382 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3) 1383 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4) 1384 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4 1385 1386 enum htt_q_depth_type { 1387 HTT_Q_DEPTH_TYPE_BYTES = 0, 1388 HTT_Q_DEPTH_TYPE_MSDUS = 1, 1389 }; 1390 1391 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \ 1392 TARGET_10_4_NUM_VDEVS) 1393 #define HTT_TX_Q_STATE_NUM_TIDS 8 1394 #define HTT_TX_Q_STATE_ENTRY_SIZE 1 1395 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0 1396 1397 /** 1398 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config 1399 * 1400 * Defines host q state format and behavior. See htt_q_state. 1401 * 1402 * @record_size: Defines the size of each host q entry in bytes. In practice 1403 * however firmware (at least 10.4.3-00191) ignores this host 1404 * configuration value and uses hardcoded value of 1. 1405 * @record_multiplier: This is valid only when q depth type is MSDUs. It 1406 * defines the exponent for the power of 2 multiplication. 1407 */ 1408 struct htt_q_state_conf { 1409 __le32 paddr; 1410 __le16 num_peers; 1411 __le16 num_tids; 1412 u8 record_size; 1413 u8 record_multiplier; 1414 u8 pad[2]; 1415 } __packed; 1416 1417 struct htt_frag_desc_bank_cfg32 { 1418 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1419 u8 num_banks; 1420 u8 desc_size; 1421 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1422 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1423 struct htt_q_state_conf q_state; 1424 } __packed; 1425 1426 struct htt_frag_desc_bank_cfg64 { 1427 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1428 u8 num_banks; 1429 u8 desc_size; 1430 __le64 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1431 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1432 struct htt_q_state_conf q_state; 1433 } __packed; 1434 1435 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128 1436 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f 1437 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0 1438 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0 1439 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6 1440 1441 /** 1442 * htt_q_state - shared between host and firmware via DMA 1443 * 1444 * This structure is used for the host to expose it's software queue state to 1445 * firmware so that its rate control can schedule fetch requests for optimized 1446 * performance. This is most notably used for MU-MIMO aggregation when multiple 1447 * MU clients are connected. 1448 * 1449 * @count: Each element defines the host queue depth. When q depth type was 1450 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as: 1451 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and 1452 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as 1453 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 ** 1454 * record_multiplier (see htt_q_state_conf). 1455 * @map: Used by firmware to quickly check which host queues are not empty. It 1456 * is a bitmap simply saying. 1457 * @seq: Used by firmware to quickly check if the host queues were updated 1458 * since it last checked. 1459 * 1460 * FIXME: Is the q_state map[] size calculation really correct? 1461 */ 1462 struct htt_q_state { 1463 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS]; 1464 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32]; 1465 __le32 seq; 1466 } __packed; 1467 1468 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff 1469 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0 1470 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000 1471 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12 1472 1473 struct htt_tx_fetch_record { 1474 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */ 1475 __le16 num_msdus; 1476 __le32 num_bytes; 1477 } __packed; 1478 1479 struct htt_tx_fetch_ind { 1480 u8 pad0; 1481 __le16 fetch_seq_num; 1482 __le32 token; 1483 __le16 num_resp_ids; 1484 __le16 num_records; 1485 struct htt_tx_fetch_record records[0]; 1486 __le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */ 1487 } __packed; 1488 1489 static inline void * 1490 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind) 1491 { 1492 return (void *)&ind->records[le16_to_cpu(ind->num_records)]; 1493 } 1494 1495 struct htt_tx_fetch_resp { 1496 u8 pad0; 1497 __le16 resp_id; 1498 __le16 fetch_seq_num; 1499 __le16 num_records; 1500 __le32 token; 1501 struct htt_tx_fetch_record records[0]; 1502 } __packed; 1503 1504 struct htt_tx_fetch_confirm { 1505 u8 pad0; 1506 __le16 num_resp_ids; 1507 __le32 resp_ids[0]; 1508 } __packed; 1509 1510 enum htt_tx_mode_switch_mode { 1511 HTT_TX_MODE_SWITCH_PUSH = 0, 1512 HTT_TX_MODE_SWITCH_PUSH_PULL = 1, 1513 }; 1514 1515 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0) 1516 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe 1517 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1 1518 1519 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003 1520 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0 1521 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc 1522 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2 1523 1524 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff 1525 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0 1526 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000 1527 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12 1528 1529 struct htt_tx_mode_switch_record { 1530 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */ 1531 __le16 num_max_msdus; 1532 } __packed; 1533 1534 struct htt_tx_mode_switch_ind { 1535 u8 pad0; 1536 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */ 1537 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */ 1538 u8 pad1[2]; 1539 struct htt_tx_mode_switch_record records[0]; 1540 } __packed; 1541 1542 struct htt_channel_change { 1543 u8 pad[3]; 1544 __le32 freq; 1545 __le32 center_freq1; 1546 __le32 center_freq2; 1547 __le32 phymode; 1548 } __packed; 1549 1550 struct htt_per_peer_tx_stats_ind { 1551 __le32 succ_bytes; 1552 __le32 retry_bytes; 1553 __le32 failed_bytes; 1554 u8 ratecode; 1555 u8 flags; 1556 __le16 peer_id; 1557 __le16 succ_pkts; 1558 __le16 retry_pkts; 1559 __le16 failed_pkts; 1560 __le16 tx_duration; 1561 __le32 reserved1; 1562 __le32 reserved2; 1563 } __packed; 1564 1565 struct htt_peer_tx_stats { 1566 u8 num_ppdu; 1567 u8 ppdu_len; 1568 u8 version; 1569 u8 payload[0]; 1570 } __packed; 1571 1572 #define ATH10K_10_2_TX_STATS_OFFSET 136 1573 #define PEER_STATS_FOR_NO_OF_PPDUS 4 1574 1575 struct ath10k_10_2_peer_tx_stats { 1576 u8 ratecode[PEER_STATS_FOR_NO_OF_PPDUS]; 1577 u8 success_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1578 __le16 success_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1579 u8 retry_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1580 __le16 retry_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1581 u8 failed_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1582 __le16 failed_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1583 u8 flags[PEER_STATS_FOR_NO_OF_PPDUS]; 1584 __le32 tx_duration; 1585 u8 tx_ppdu_cnt; 1586 u8 peer_id; 1587 } __packed; 1588 1589 union htt_rx_pn_t { 1590 /* WEP: 24-bit PN */ 1591 u32 pn24; 1592 1593 /* TKIP or CCMP: 48-bit PN */ 1594 u64 pn48; 1595 1596 /* WAPI: 128-bit PN */ 1597 u64 pn128[2]; 1598 }; 1599 1600 struct htt_cmd { 1601 struct htt_cmd_hdr hdr; 1602 union { 1603 struct htt_ver_req ver_req; 1604 struct htt_mgmt_tx_desc mgmt_tx; 1605 struct htt_data_tx_desc data_tx; 1606 struct htt_rx_ring_setup_32 rx_setup_32; 1607 struct htt_rx_ring_setup_64 rx_setup_64; 1608 struct htt_stats_req stats_req; 1609 struct htt_oob_sync_req oob_sync_req; 1610 struct htt_aggr_conf aggr_conf; 1611 struct htt_frag_desc_bank_cfg32 frag_desc_bank_cfg32; 1612 struct htt_frag_desc_bank_cfg64 frag_desc_bank_cfg64; 1613 struct htt_tx_fetch_resp tx_fetch_resp; 1614 }; 1615 } __packed; 1616 1617 struct htt_resp { 1618 struct htt_resp_hdr hdr; 1619 union { 1620 struct htt_ver_resp ver_resp; 1621 struct htt_mgmt_tx_completion mgmt_tx_completion; 1622 struct htt_data_tx_completion data_tx_completion; 1623 struct htt_rx_indication rx_ind; 1624 struct htt_rx_fragment_indication rx_frag_ind; 1625 struct htt_rx_peer_map peer_map; 1626 struct htt_rx_peer_unmap peer_unmap; 1627 struct htt_rx_flush rx_flush; 1628 struct htt_rx_addba rx_addba; 1629 struct htt_rx_delba rx_delba; 1630 struct htt_security_indication security_indication; 1631 struct htt_rc_update rc_update; 1632 struct htt_rx_test rx_test; 1633 struct htt_pktlog_msg pktlog_msg; 1634 struct htt_stats_conf stats_conf; 1635 struct htt_rx_pn_ind rx_pn_ind; 1636 struct htt_rx_offload_ind rx_offload_ind; 1637 struct htt_rx_in_ord_ind rx_in_ord_ind; 1638 struct htt_tx_fetch_ind tx_fetch_ind; 1639 struct htt_tx_fetch_confirm tx_fetch_confirm; 1640 struct htt_tx_mode_switch_ind tx_mode_switch_ind; 1641 struct htt_channel_change chan_change; 1642 struct htt_peer_tx_stats peer_tx_stats; 1643 }; 1644 } __packed; 1645 1646 /*** host side structures follow ***/ 1647 1648 struct htt_tx_done { 1649 u16 msdu_id; 1650 u16 status; 1651 }; 1652 1653 enum htt_tx_compl_state { 1654 HTT_TX_COMPL_STATE_NONE, 1655 HTT_TX_COMPL_STATE_ACK, 1656 HTT_TX_COMPL_STATE_NOACK, 1657 HTT_TX_COMPL_STATE_DISCARD, 1658 }; 1659 1660 struct htt_peer_map_event { 1661 u8 vdev_id; 1662 u16 peer_id; 1663 u8 addr[ETH_ALEN]; 1664 }; 1665 1666 struct htt_peer_unmap_event { 1667 u16 peer_id; 1668 }; 1669 1670 struct ath10k_htt_txbuf_32 { 1671 struct htt_data_tx_desc_frag frags[2]; 1672 struct ath10k_htc_hdr htc_hdr; 1673 struct htt_cmd_hdr cmd_hdr; 1674 struct htt_data_tx_desc cmd_tx; 1675 } __packed; 1676 1677 struct ath10k_htt_txbuf_64 { 1678 struct htt_data_tx_desc_frag frags[2]; 1679 struct ath10k_htc_hdr htc_hdr; 1680 struct htt_cmd_hdr cmd_hdr; 1681 struct htt_data_tx_desc_64 cmd_tx; 1682 } __packed; 1683 1684 struct ath10k_htt { 1685 struct ath10k *ar; 1686 enum ath10k_htc_ep_id eid; 1687 1688 u8 target_version_major; 1689 u8 target_version_minor; 1690 struct completion target_version_received; 1691 u8 max_num_amsdu; 1692 u8 max_num_ampdu; 1693 1694 const enum htt_t2h_msg_type *t2h_msg_types; 1695 u32 t2h_msg_types_max; 1696 1697 struct { 1698 /* 1699 * Ring of network buffer objects - This ring is 1700 * used exclusively by the host SW. This ring 1701 * mirrors the dev_addrs_ring that is shared 1702 * between the host SW and the MAC HW. The host SW 1703 * uses this netbufs ring to locate the network 1704 * buffer objects whose data buffers the HW has 1705 * filled. 1706 */ 1707 struct sk_buff **netbufs_ring; 1708 1709 /* This is used only with firmware supporting IN_ORD_IND. 1710 * 1711 * With Full Rx Reorder the HTT Rx Ring is more of a temporary 1712 * buffer ring from which buffer addresses are copied by the 1713 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND 1714 * pointing to specific (re-ordered) buffers. 1715 * 1716 * FIXME: With kernel generic hashing functions there's a lot 1717 * of hash collisions for sk_buffs. 1718 */ 1719 bool in_ord_rx; 1720 DECLARE_HASHTABLE(skb_table, 4); 1721 1722 /* 1723 * Ring of buffer addresses - 1724 * This ring holds the "physical" device address of the 1725 * rx buffers the host SW provides for the MAC HW to 1726 * fill. 1727 */ 1728 union { 1729 __le64 *paddrs_ring_64; 1730 __le32 *paddrs_ring_32; 1731 }; 1732 1733 /* 1734 * Base address of ring, as a "physical" device address 1735 * rather than a CPU address. 1736 */ 1737 dma_addr_t base_paddr; 1738 1739 /* how many elems in the ring (power of 2) */ 1740 int size; 1741 1742 /* size - 1 */ 1743 unsigned int size_mask; 1744 1745 /* how many rx buffers to keep in the ring */ 1746 int fill_level; 1747 1748 /* how many rx buffers (full+empty) are in the ring */ 1749 int fill_cnt; 1750 1751 /* 1752 * alloc_idx - where HTT SW has deposited empty buffers 1753 * This is allocated in consistent mem, so that the FW can 1754 * read this variable, and program the HW's FW_IDX reg with 1755 * the value of this shadow register. 1756 */ 1757 struct { 1758 __le32 *vaddr; 1759 dma_addr_t paddr; 1760 } alloc_idx; 1761 1762 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1763 struct { 1764 unsigned int msdu_payld; 1765 } sw_rd_idx; 1766 1767 /* 1768 * refill_retry_timer - timer triggered when the ring is 1769 * not refilled to the level expected 1770 */ 1771 struct timer_list refill_retry_timer; 1772 1773 /* Protects access to all rx ring buffer state variables */ 1774 spinlock_t lock; 1775 } rx_ring; 1776 1777 unsigned int prefetch_len; 1778 1779 /* Protects access to pending_tx, num_pending_tx */ 1780 spinlock_t tx_lock; 1781 int max_num_pending_tx; 1782 int num_pending_tx; 1783 int num_pending_mgmt_tx; 1784 struct idr pending_tx; 1785 wait_queue_head_t empty_tx_wq; 1786 1787 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */ 1788 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done); 1789 1790 /* set if host-fw communication goes haywire 1791 * used to avoid further failures 1792 */ 1793 bool rx_confused; 1794 atomic_t num_mpdus_ready; 1795 1796 /* This is used to group tx/rx completions separately and process them 1797 * in batches to reduce cache stalls 1798 */ 1799 struct sk_buff_head rx_msdus_q; 1800 struct sk_buff_head rx_in_ord_compl_q; 1801 struct sk_buff_head tx_fetch_ind_q; 1802 1803 /* rx_status template */ 1804 struct ieee80211_rx_status rx_status; 1805 1806 struct { 1807 dma_addr_t paddr; 1808 union { 1809 struct htt_msdu_ext_desc *vaddr_desc_32; 1810 struct htt_msdu_ext_desc_64 *vaddr_desc_64; 1811 }; 1812 size_t size; 1813 } frag_desc; 1814 1815 struct { 1816 dma_addr_t paddr; 1817 union { 1818 struct ath10k_htt_txbuf_32 *vaddr_txbuff_32; 1819 struct ath10k_htt_txbuf_64 *vaddr_txbuff_64; 1820 }; 1821 size_t size; 1822 } txbuf; 1823 1824 struct { 1825 bool enabled; 1826 struct htt_q_state *vaddr; 1827 dma_addr_t paddr; 1828 u16 num_push_allowed; 1829 u16 num_peers; 1830 u16 num_tids; 1831 enum htt_tx_mode_switch_mode mode; 1832 enum htt_q_depth_type type; 1833 } tx_q_state; 1834 1835 bool tx_mem_allocated; 1836 const struct ath10k_htt_tx_ops *tx_ops; 1837 const struct ath10k_htt_rx_ops *rx_ops; 1838 }; 1839 1840 struct ath10k_htt_tx_ops { 1841 int (*htt_send_rx_ring_cfg)(struct ath10k_htt *htt); 1842 int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt); 1843 int (*htt_alloc_frag_desc)(struct ath10k_htt *htt); 1844 void (*htt_free_frag_desc)(struct ath10k_htt *htt); 1845 int (*htt_tx)(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 1846 struct sk_buff *msdu); 1847 int (*htt_alloc_txbuff)(struct ath10k_htt *htt); 1848 void (*htt_free_txbuff)(struct ath10k_htt *htt); 1849 }; 1850 1851 struct ath10k_htt_rx_ops { 1852 size_t (*htt_get_rx_ring_size)(struct ath10k_htt *htt); 1853 void (*htt_config_paddrs_ring)(struct ath10k_htt *htt, void *vaddr); 1854 void (*htt_set_paddrs_ring)(struct ath10k_htt *htt, dma_addr_t paddr, 1855 int idx); 1856 void* (*htt_get_vaddr_ring)(struct ath10k_htt *htt); 1857 void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx); 1858 }; 1859 1860 #define RX_HTT_HDR_STATUS_LEN 64 1861 1862 /* This structure layout is programmed via rx ring setup 1863 * so that FW knows how to transfer the rx descriptor to the host. 1864 * Buffers like this are placed on the rx ring. 1865 */ 1866 struct htt_rx_desc { 1867 union { 1868 /* This field is filled on the host using the msdu buffer 1869 * from htt_rx_indication 1870 */ 1871 struct fw_rx_desc_base fw_desc; 1872 u32 pad; 1873 } __packed; 1874 struct { 1875 struct rx_attention attention; 1876 struct rx_frag_info frag_info; 1877 struct rx_mpdu_start mpdu_start; 1878 struct rx_msdu_start msdu_start; 1879 struct rx_msdu_end msdu_end; 1880 struct rx_mpdu_end mpdu_end; 1881 struct rx_ppdu_start ppdu_start; 1882 struct rx_ppdu_end ppdu_end; 1883 } __packed; 1884 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1885 u8 msdu_payload[0]; 1886 }; 1887 1888 #define HTT_RX_DESC_ALIGN 8 1889 1890 #define HTT_MAC_ADDR_LEN 6 1891 1892 /* 1893 * FIX THIS 1894 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 1895 * rounded up to a cache line size. 1896 */ 1897 #define HTT_RX_BUF_SIZE 1920 1898 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 1899 1900 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 1901 * aggregated traffic more nicely. 1902 */ 1903 #define ATH10K_HTT_MAX_NUM_REFILL 100 1904 1905 /* 1906 * DMA_MAP expects the buffer to be an integral number of cache lines. 1907 * Rather than checking the actual cache line size, this code makes a 1908 * conservative estimate of what the cache line size could be. 1909 */ 1910 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 1911 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 1912 1913 /* These values are default in most firmware revisions and apparently are a 1914 * sweet spot performance wise. 1915 */ 1916 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3 1917 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64 1918 1919 int ath10k_htt_connect(struct ath10k_htt *htt); 1920 int ath10k_htt_init(struct ath10k *ar); 1921 int ath10k_htt_setup(struct ath10k_htt *htt); 1922 1923 int ath10k_htt_tx_start(struct ath10k_htt *htt); 1924 void ath10k_htt_tx_stop(struct ath10k_htt *htt); 1925 void ath10k_htt_tx_destroy(struct ath10k_htt *htt); 1926 void ath10k_htt_tx_free(struct ath10k_htt *htt); 1927 1928 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 1929 int ath10k_htt_rx_ring_refill(struct ath10k *ar); 1930 void ath10k_htt_rx_free(struct ath10k_htt *htt); 1931 1932 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1933 void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1934 bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1935 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 1936 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 1937 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 1938 u8 max_subfrms_ampdu, 1939 u8 max_subfrms_amsdu); 1940 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1941 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 1942 __le32 token, 1943 __le16 fetch_seq_num, 1944 struct htt_tx_fetch_record *records, 1945 size_t num_records); 1946 1947 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 1948 struct ieee80211_txq *txq); 1949 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 1950 struct ieee80211_txq *txq); 1951 void ath10k_htt_tx_txq_sync(struct ath10k *ar); 1952 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 1953 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt); 1954 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt); 1955 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 1956 bool is_presp); 1957 1958 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); 1959 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 1960 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu); 1961 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar, 1962 struct sk_buff *skb); 1963 int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget); 1964 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt); 1965 void ath10k_htt_set_rx_ops(struct ath10k_htt *htt); 1966 #endif 1967