1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HTT_H_ 19 #define _HTT_H_ 20 21 #include <linux/bug.h> 22 #include <linux/interrupt.h> 23 #include <linux/dmapool.h> 24 #include <net/mac80211.h> 25 26 #include "htc.h" 27 #include "rx_desc.h" 28 29 enum htt_dbg_stats_type { 30 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 31 HTT_DBG_STATS_RX_REORDER = 1 << 1, 32 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 33 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 34 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 35 /* bits 5-23 currently reserved */ 36 37 HTT_DBG_NUM_STATS /* keep this last */ 38 }; 39 40 enum htt_h2t_msg_type { /* host-to-target */ 41 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 42 HTT_H2T_MSG_TYPE_TX_FRM = 1, 43 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 44 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 45 HTT_H2T_MSG_TYPE_SYNC = 4, 46 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 47 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 48 49 /* This command is used for sending management frames in HTT < 3.0. 50 * HTT >= 3.0 uses TX_FRM for everything. */ 51 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 52 53 HTT_H2T_NUM_MSGS /* keep this last */ 54 }; 55 56 struct htt_cmd_hdr { 57 u8 msg_type; 58 } __packed; 59 60 struct htt_ver_req { 61 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 62 } __packed; 63 64 /* 65 * HTT tx MSDU descriptor 66 * 67 * The HTT tx MSDU descriptor is created by the host HTT SW for each 68 * tx MSDU. The HTT tx MSDU descriptor contains the information that 69 * the target firmware needs for the FW's tx processing, particularly 70 * for creating the HW msdu descriptor. 71 * The same HTT tx descriptor is used for HL and LL systems, though 72 * a few fields within the tx descriptor are used only by LL or 73 * only by HL. 74 * The HTT tx descriptor is defined in two manners: by a struct with 75 * bitfields, and by a series of [dword offset, bit mask, bit shift] 76 * definitions. 77 * The target should use the struct def, for simplicitly and clarity, 78 * but the host shall use the bit-mast + bit-shift defs, to be endian- 79 * neutral. Specifically, the host shall use the get/set macros built 80 * around the mask + shift defs. 81 */ 82 struct htt_data_tx_desc_frag { 83 __le32 paddr; 84 __le32 len; 85 } __packed; 86 87 enum htt_data_tx_desc_flags0 { 88 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 89 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 90 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 91 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 92 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 93 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 94 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 95 }; 96 97 enum htt_data_tx_desc_flags1 { 98 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 99 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 100 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 101 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 102 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 103 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 104 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 105 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 106 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 107 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 108 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 109 }; 110 111 enum htt_data_tx_ext_tid { 112 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 113 HTT_DATA_TX_EXT_TID_MGMT = 17, 114 HTT_DATA_TX_EXT_TID_INVALID = 31 115 }; 116 117 #define HTT_INVALID_PEERID 0xFFFF 118 119 /* 120 * htt_data_tx_desc - used for data tx path 121 * 122 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 123 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 124 * for special kinds of tids 125 * postponed: only for HL hosts. indicates if this is a resend 126 * (HL hosts manage queues on the host ) 127 * more_in_batch: only for HL hosts. indicates if more packets are 128 * pending. this allows target to wait and aggregate 129 */ 130 struct htt_data_tx_desc { 131 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 132 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 133 __le16 len; 134 __le16 id; 135 __le32 frags_paddr; 136 __le32 peerid; 137 u8 prefetch[0]; /* start of frame, for FW classification engine */ 138 } __packed; 139 140 enum htt_rx_ring_flags { 141 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 142 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 143 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 144 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 145 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 146 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 147 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 148 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 149 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 150 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 151 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 152 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 153 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 154 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 155 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 156 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 157 }; 158 159 struct htt_rx_ring_setup_ring { 160 __le32 fw_idx_shadow_reg_paddr; 161 __le32 rx_ring_base_paddr; 162 __le16 rx_ring_len; /* in 4-byte words */ 163 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 164 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 165 __le16 fw_idx_init_val; 166 167 /* the following offsets are in 4-byte units */ 168 __le16 mac80211_hdr_offset; 169 __le16 msdu_payload_offset; 170 __le16 ppdu_start_offset; 171 __le16 ppdu_end_offset; 172 __le16 mpdu_start_offset; 173 __le16 mpdu_end_offset; 174 __le16 msdu_start_offset; 175 __le16 msdu_end_offset; 176 __le16 rx_attention_offset; 177 __le16 frag_info_offset; 178 } __packed; 179 180 struct htt_rx_ring_setup_hdr { 181 u8 num_rings; /* supported values: 1, 2 */ 182 __le16 rsvd0; 183 } __packed; 184 185 struct htt_rx_ring_setup { 186 struct htt_rx_ring_setup_hdr hdr; 187 struct htt_rx_ring_setup_ring rings[0]; 188 } __packed; 189 190 /* 191 * htt_stats_req - request target to send specified statistics 192 * 193 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 194 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 195 * so make sure its little-endian. 196 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 197 * so make sure its little-endian. 198 * @cfg_val: stat_type specific configuration 199 * @stat_type: see %htt_dbg_stats_type 200 * @cookie_lsb: used for confirmation message from target->host 201 * @cookie_msb: ditto as %cookie 202 */ 203 struct htt_stats_req { 204 u8 upload_types[3]; 205 u8 rsvd0; 206 u8 reset_types[3]; 207 struct { 208 u8 mpdu_bytes; 209 u8 mpdu_num_msdus; 210 u8 msdu_bytes; 211 } __packed; 212 u8 stat_type; 213 __le32 cookie_lsb; 214 __le32 cookie_msb; 215 } __packed; 216 217 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 218 219 /* 220 * htt_oob_sync_req - request out-of-band sync 221 * 222 * The HTT SYNC tells the target to suspend processing of subsequent 223 * HTT host-to-target messages until some other target agent locally 224 * informs the target HTT FW that the current sync counter is equal to 225 * or greater than (in a modulo sense) the sync counter specified in 226 * the SYNC message. 227 * 228 * This allows other host-target components to synchronize their operation 229 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 230 * security key has been downloaded to and activated by the target. 231 * In the absence of any explicit synchronization counter value 232 * specification, the target HTT FW will use zero as the default current 233 * sync value. 234 * 235 * The HTT target FW will suspend its host->target message processing as long 236 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 237 */ 238 struct htt_oob_sync_req { 239 u8 sync_count; 240 __le16 rsvd0; 241 } __packed; 242 243 struct htt_aggr_conf { 244 u8 max_num_ampdu_subframes; 245 /* amsdu_subframes is limited by 0x1F mask */ 246 u8 max_num_amsdu_subframes; 247 } __packed; 248 249 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 250 251 struct htt_mgmt_tx_desc { 252 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 253 __le32 msdu_paddr; 254 __le32 desc_id; 255 __le32 len; 256 __le32 vdev_id; 257 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 258 } __packed; 259 260 enum htt_mgmt_tx_status { 261 HTT_MGMT_TX_STATUS_OK = 0, 262 HTT_MGMT_TX_STATUS_RETRY = 1, 263 HTT_MGMT_TX_STATUS_DROP = 2 264 }; 265 266 /*=== target -> host messages ===============================================*/ 267 268 269 enum htt_t2h_msg_type { 270 HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0, 271 HTT_T2H_MSG_TYPE_RX_IND = 0x1, 272 HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2, 273 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 274 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 275 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 276 HTT_T2H_MSG_TYPE_RX_DELBA = 0x6, 277 HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 278 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 279 HTT_T2H_MSG_TYPE_STATS_CONF = 0x9, 280 HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 281 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 282 HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 283 HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 284 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION = 0xe, 285 HTT_T2H_MSG_TYPE_TEST, 286 /* keep this last */ 287 HTT_T2H_NUM_MSGS 288 }; 289 290 /* 291 * htt_resp_hdr - header for target-to-host messages 292 * 293 * msg_type: see htt_t2h_msg_type 294 */ 295 struct htt_resp_hdr { 296 u8 msg_type; 297 } __packed; 298 299 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 300 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 301 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 302 303 /* htt_ver_resp - response sent for htt_ver_req */ 304 struct htt_ver_resp { 305 u8 minor; 306 u8 major; 307 u8 rsvd0; 308 } __packed; 309 310 struct htt_mgmt_tx_completion { 311 u8 rsvd0; 312 u8 rsvd1; 313 u8 rsvd2; 314 __le32 desc_id; 315 __le32 status; 316 } __packed; 317 318 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x3F) 319 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 320 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 6) 321 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 7) 322 323 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 324 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 325 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 326 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 327 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 328 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 329 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 330 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 331 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 332 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 333 334 struct htt_rx_indication_hdr { 335 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 336 __le16 peer_id; 337 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 338 } __packed; 339 340 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 341 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 342 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 343 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 344 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 345 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 346 347 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 348 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 349 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 350 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 351 352 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 353 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 354 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 355 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 356 357 enum htt_rx_legacy_rate { 358 HTT_RX_OFDM_48 = 0, 359 HTT_RX_OFDM_24 = 1, 360 HTT_RX_OFDM_12, 361 HTT_RX_OFDM_6, 362 HTT_RX_OFDM_54, 363 HTT_RX_OFDM_36, 364 HTT_RX_OFDM_18, 365 HTT_RX_OFDM_9, 366 367 /* long preamble */ 368 HTT_RX_CCK_11_LP = 0, 369 HTT_RX_CCK_5_5_LP = 1, 370 HTT_RX_CCK_2_LP, 371 HTT_RX_CCK_1_LP, 372 /* short preamble */ 373 HTT_RX_CCK_11_SP, 374 HTT_RX_CCK_5_5_SP, 375 HTT_RX_CCK_2_SP 376 }; 377 378 enum htt_rx_legacy_rate_type { 379 HTT_RX_LEGACY_RATE_OFDM = 0, 380 HTT_RX_LEGACY_RATE_CCK 381 }; 382 383 enum htt_rx_preamble_type { 384 HTT_RX_LEGACY = 0x4, 385 HTT_RX_HT = 0x8, 386 HTT_RX_HT_WITH_TXBF = 0x9, 387 HTT_RX_VHT = 0xC, 388 HTT_RX_VHT_WITH_TXBF = 0xD, 389 }; 390 391 /* 392 * Fields: phy_err_valid, phy_err_code, tsf, 393 * usec_timestamp, sub_usec_timestamp 394 * ..are valid only if end_valid == 1. 395 * 396 * Fields: rssi_chains, legacy_rate_type, 397 * legacy_rate_cck, preamble_type, service, 398 * vht_sig_* 399 * ..are valid only if start_valid == 1; 400 */ 401 struct htt_rx_indication_ppdu { 402 u8 combined_rssi; 403 u8 sub_usec_timestamp; 404 u8 phy_err_code; 405 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 406 struct { 407 u8 pri20_db; 408 u8 ext20_db; 409 u8 ext40_db; 410 u8 ext80_db; 411 } __packed rssi_chains[4]; 412 __le32 tsf; 413 __le32 usec_timestamp; 414 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 415 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 416 } __packed; 417 418 enum htt_rx_mpdu_status { 419 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 420 HTT_RX_IND_MPDU_STATUS_OK, 421 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 422 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 423 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 424 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 425 /* only accept EAPOL frames */ 426 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 427 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 428 /* Non-data in promiscous mode */ 429 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 430 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 431 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 432 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 433 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 434 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 435 436 /* 437 * MISC: discard for unspecified reasons. 438 * Leave this enum value last. 439 */ 440 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 441 }; 442 443 struct htt_rx_indication_mpdu_range { 444 u8 mpdu_count; 445 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 446 u8 pad0; 447 u8 pad1; 448 } __packed; 449 450 struct htt_rx_indication_prefix { 451 __le16 fw_rx_desc_bytes; 452 u8 pad0; 453 u8 pad1; 454 }; 455 456 struct htt_rx_indication { 457 struct htt_rx_indication_hdr hdr; 458 struct htt_rx_indication_ppdu ppdu; 459 struct htt_rx_indication_prefix prefix; 460 461 /* 462 * the following fields are both dynamically sized, so 463 * take care addressing them 464 */ 465 466 /* the size of this is %fw_rx_desc_bytes */ 467 struct fw_rx_desc_base fw_desc; 468 469 /* 470 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 471 * and has %num_mpdu_ranges elements. 472 */ 473 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 474 } __packed; 475 476 static inline struct htt_rx_indication_mpdu_range * 477 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 478 { 479 void *ptr = rx_ind; 480 481 ptr += sizeof(rx_ind->hdr) 482 + sizeof(rx_ind->ppdu) 483 + sizeof(rx_ind->prefix) 484 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 485 return ptr; 486 } 487 488 enum htt_rx_flush_mpdu_status { 489 HTT_RX_FLUSH_MPDU_DISCARD = 0, 490 HTT_RX_FLUSH_MPDU_REORDER = 1, 491 }; 492 493 /* 494 * htt_rx_flush - discard or reorder given range of mpdus 495 * 496 * Note: host must check if all sequence numbers between 497 * [seq_num_start, seq_num_end-1] are valid. 498 */ 499 struct htt_rx_flush { 500 __le16 peer_id; 501 u8 tid; 502 u8 rsvd0; 503 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 504 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 505 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 506 }; 507 508 struct htt_rx_peer_map { 509 u8 vdev_id; 510 __le16 peer_id; 511 u8 addr[6]; 512 u8 rsvd0; 513 u8 rsvd1; 514 } __packed; 515 516 struct htt_rx_peer_unmap { 517 u8 rsvd0; 518 __le16 peer_id; 519 } __packed; 520 521 enum htt_security_types { 522 HTT_SECURITY_NONE, 523 HTT_SECURITY_WEP128, 524 HTT_SECURITY_WEP104, 525 HTT_SECURITY_WEP40, 526 HTT_SECURITY_TKIP, 527 HTT_SECURITY_TKIP_NOMIC, 528 HTT_SECURITY_AES_CCMP, 529 HTT_SECURITY_WAPI, 530 531 HTT_NUM_SECURITY_TYPES /* keep this last! */ 532 }; 533 534 enum htt_security_flags { 535 #define HTT_SECURITY_TYPE_MASK 0x7F 536 #define HTT_SECURITY_TYPE_LSB 0 537 HTT_SECURITY_IS_UNICAST = 1 << 7 538 }; 539 540 struct htt_security_indication { 541 union { 542 /* dont use bitfields; undefined behaviour */ 543 u8 flags; /* %htt_security_flags */ 544 struct { 545 u8 security_type:7, /* %htt_security_types */ 546 is_unicast:1; 547 } __packed; 548 } __packed; 549 __le16 peer_id; 550 u8 michael_key[8]; 551 u8 wapi_rsc[16]; 552 } __packed; 553 554 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 555 #define HTT_RX_BA_INFO0_TID_LSB 0 556 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 557 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 558 559 struct htt_rx_addba { 560 u8 window_size; 561 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 562 } __packed; 563 564 struct htt_rx_delba { 565 u8 rsvd0; 566 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 567 } __packed; 568 569 enum htt_data_tx_status { 570 HTT_DATA_TX_STATUS_OK = 0, 571 HTT_DATA_TX_STATUS_DISCARD = 1, 572 HTT_DATA_TX_STATUS_NO_ACK = 2, 573 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 574 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 575 }; 576 577 enum htt_data_tx_flags { 578 #define HTT_DATA_TX_STATUS_MASK 0x07 579 #define HTT_DATA_TX_STATUS_LSB 0 580 #define HTT_DATA_TX_TID_MASK 0x78 581 #define HTT_DATA_TX_TID_LSB 3 582 HTT_DATA_TX_TID_INVALID = 1 << 7 583 }; 584 585 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 586 587 struct htt_data_tx_completion { 588 union { 589 u8 flags; 590 struct { 591 u8 status:3, 592 tid:4, 593 tid_invalid:1; 594 } __packed; 595 } __packed; 596 u8 num_msdus; 597 u8 rsvd0; 598 __le16 msdus[0]; /* variable length based on %num_msdus */ 599 } __packed; 600 601 struct htt_tx_compl_ind_base { 602 u32 hdr; 603 u16 payload[1/*or more*/]; 604 } __packed; 605 606 struct htt_rc_tx_done_params { 607 u32 rate_code; 608 u32 rate_code_flags; 609 u32 flags; 610 u32 num_enqued; /* 1 for non-AMPDU */ 611 u32 num_retries; 612 u32 num_failed; /* for AMPDU */ 613 u32 ack_rssi; 614 u32 time_stamp; 615 u32 is_probe; 616 }; 617 618 struct htt_rc_update { 619 u8 vdev_id; 620 __le16 peer_id; 621 u8 addr[6]; 622 u8 num_elems; 623 u8 rsvd0; 624 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 625 } __packed; 626 627 /* see htt_rx_indication for similar fields and descriptions */ 628 struct htt_rx_fragment_indication { 629 union { 630 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 631 struct { 632 u8 ext_tid:5, 633 flush_valid:1; 634 } __packed; 635 } __packed; 636 __le16 peer_id; 637 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 638 __le16 fw_rx_desc_bytes; 639 __le16 rsvd0; 640 641 u8 fw_msdu_rx_desc[0]; 642 } __packed; 643 644 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 645 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 646 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 647 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 648 649 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 650 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 651 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 652 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 653 654 /* 655 * target -> host test message definition 656 * 657 * The following field definitions describe the format of the test 658 * message sent from the target to the host. 659 * The message consists of a 4-octet header, followed by a variable 660 * number of 32-bit integer values, followed by a variable number 661 * of 8-bit character values. 662 * 663 * |31 16|15 8|7 0| 664 * |-----------------------------------------------------------| 665 * | num chars | num ints | msg type | 666 * |-----------------------------------------------------------| 667 * | int 0 | 668 * |-----------------------------------------------------------| 669 * | int 1 | 670 * |-----------------------------------------------------------| 671 * | ... | 672 * |-----------------------------------------------------------| 673 * | char 3 | char 2 | char 1 | char 0 | 674 * |-----------------------------------------------------------| 675 * | | | ... | char 4 | 676 * |-----------------------------------------------------------| 677 * - MSG_TYPE 678 * Bits 7:0 679 * Purpose: identifies this as a test message 680 * Value: HTT_MSG_TYPE_TEST 681 * - NUM_INTS 682 * Bits 15:8 683 * Purpose: indicate how many 32-bit integers follow the message header 684 * - NUM_CHARS 685 * Bits 31:16 686 * Purpose: indicate how many 8-bit charaters follow the series of integers 687 */ 688 struct htt_rx_test { 689 u8 num_ints; 690 __le16 num_chars; 691 692 /* payload consists of 2 lists: 693 * a) num_ints * sizeof(__le32) 694 * b) num_chars * sizeof(u8) aligned to 4bytes */ 695 u8 payload[0]; 696 } __packed; 697 698 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 699 { 700 return (__le32 *)rx_test->payload; 701 } 702 703 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 704 { 705 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 706 } 707 708 /* 709 * target -> host packet log message 710 * 711 * The following field definitions describe the format of the packet log 712 * message sent from the target to the host. 713 * The message consists of a 4-octet header,followed by a variable number 714 * of 32-bit character values. 715 * 716 * |31 24|23 16|15 8|7 0| 717 * |-----------------------------------------------------------| 718 * | | | | msg type | 719 * |-----------------------------------------------------------| 720 * | payload | 721 * |-----------------------------------------------------------| 722 * - MSG_TYPE 723 * Bits 7:0 724 * Purpose: identifies this as a test message 725 * Value: HTT_MSG_TYPE_PACKETLOG 726 */ 727 struct htt_pktlog_msg { 728 u8 pad[3]; 729 __le32 payload[1 /* or more */]; 730 } __packed; 731 732 struct htt_dbg_stats_rx_reorder_stats { 733 /* Non QoS MPDUs received */ 734 __le32 deliver_non_qos; 735 736 /* MPDUs received in-order */ 737 __le32 deliver_in_order; 738 739 /* Flush due to reorder timer expired */ 740 __le32 deliver_flush_timeout; 741 742 /* Flush due to move out of window */ 743 __le32 deliver_flush_oow; 744 745 /* Flush due to DELBA */ 746 __le32 deliver_flush_delba; 747 748 /* MPDUs dropped due to FCS error */ 749 __le32 fcs_error; 750 751 /* MPDUs dropped due to monitor mode non-data packet */ 752 __le32 mgmt_ctrl; 753 754 /* MPDUs dropped due to invalid peer */ 755 __le32 invalid_peer; 756 757 /* MPDUs dropped due to duplication (non aggregation) */ 758 __le32 dup_non_aggr; 759 760 /* MPDUs dropped due to processed before */ 761 __le32 dup_past; 762 763 /* MPDUs dropped due to duplicate in reorder queue */ 764 __le32 dup_in_reorder; 765 766 /* Reorder timeout happened */ 767 __le32 reorder_timeout; 768 769 /* invalid bar ssn */ 770 __le32 invalid_bar_ssn; 771 772 /* reorder reset due to bar ssn */ 773 __le32 ssn_reset; 774 }; 775 776 struct htt_dbg_stats_wal_tx_stats { 777 /* Num HTT cookies queued to dispatch list */ 778 __le32 comp_queued; 779 780 /* Num HTT cookies dispatched */ 781 __le32 comp_delivered; 782 783 /* Num MSDU queued to WAL */ 784 __le32 msdu_enqued; 785 786 /* Num MPDU queue to WAL */ 787 __le32 mpdu_enqued; 788 789 /* Num MSDUs dropped by WMM limit */ 790 __le32 wmm_drop; 791 792 /* Num Local frames queued */ 793 __le32 local_enqued; 794 795 /* Num Local frames done */ 796 __le32 local_freed; 797 798 /* Num queued to HW */ 799 __le32 hw_queued; 800 801 /* Num PPDU reaped from HW */ 802 __le32 hw_reaped; 803 804 /* Num underruns */ 805 __le32 underrun; 806 807 /* Num PPDUs cleaned up in TX abort */ 808 __le32 tx_abort; 809 810 /* Num MPDUs requed by SW */ 811 __le32 mpdus_requed; 812 813 /* excessive retries */ 814 __le32 tx_ko; 815 816 /* data hw rate code */ 817 __le32 data_rc; 818 819 /* Scheduler self triggers */ 820 __le32 self_triggers; 821 822 /* frames dropped due to excessive sw retries */ 823 __le32 sw_retry_failure; 824 825 /* illegal rate phy errors */ 826 __le32 illgl_rate_phy_err; 827 828 /* wal pdev continous xretry */ 829 __le32 pdev_cont_xretry; 830 831 /* wal pdev continous xretry */ 832 __le32 pdev_tx_timeout; 833 834 /* wal pdev resets */ 835 __le32 pdev_resets; 836 837 __le32 phy_underrun; 838 839 /* MPDU is more than txop limit */ 840 __le32 txop_ovf; 841 } __packed; 842 843 struct htt_dbg_stats_wal_rx_stats { 844 /* Cnts any change in ring routing mid-ppdu */ 845 __le32 mid_ppdu_route_change; 846 847 /* Total number of statuses processed */ 848 __le32 status_rcvd; 849 850 /* Extra frags on rings 0-3 */ 851 __le32 r0_frags; 852 __le32 r1_frags; 853 __le32 r2_frags; 854 __le32 r3_frags; 855 856 /* MSDUs / MPDUs delivered to HTT */ 857 __le32 htt_msdus; 858 __le32 htt_mpdus; 859 860 /* MSDUs / MPDUs delivered to local stack */ 861 __le32 loc_msdus; 862 __le32 loc_mpdus; 863 864 /* AMSDUs that have more MSDUs than the status ring size */ 865 __le32 oversize_amsdu; 866 867 /* Number of PHY errors */ 868 __le32 phy_errs; 869 870 /* Number of PHY errors drops */ 871 __le32 phy_err_drop; 872 873 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 874 __le32 mpdu_errs; 875 } __packed; 876 877 struct htt_dbg_stats_wal_peer_stats { 878 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 879 } __packed; 880 881 struct htt_dbg_stats_wal_pdev_txrx { 882 struct htt_dbg_stats_wal_tx_stats tx_stats; 883 struct htt_dbg_stats_wal_rx_stats rx_stats; 884 struct htt_dbg_stats_wal_peer_stats peer_stats; 885 } __packed; 886 887 struct htt_dbg_stats_rx_rate_info { 888 __le32 mcs[10]; 889 __le32 sgi[10]; 890 __le32 nss[4]; 891 __le32 stbc[10]; 892 __le32 bw[3]; 893 __le32 pream[6]; 894 __le32 ldpc; 895 __le32 txbf; 896 }; 897 898 /* 899 * htt_dbg_stats_status - 900 * present - The requested stats have been delivered in full. 901 * This indicates that either the stats information was contained 902 * in its entirety within this message, or else this message 903 * completes the delivery of the requested stats info that was 904 * partially delivered through earlier STATS_CONF messages. 905 * partial - The requested stats have been delivered in part. 906 * One or more subsequent STATS_CONF messages with the same 907 * cookie value will be sent to deliver the remainder of the 908 * information. 909 * error - The requested stats could not be delivered, for example due 910 * to a shortage of memory to construct a message holding the 911 * requested stats. 912 * invalid - The requested stat type is either not recognized, or the 913 * target is configured to not gather the stats type in question. 914 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 915 * series_done - This special value indicates that no further stats info 916 * elements are present within a series of stats info elems 917 * (within a stats upload confirmation message). 918 */ 919 enum htt_dbg_stats_status { 920 HTT_DBG_STATS_STATUS_PRESENT = 0, 921 HTT_DBG_STATS_STATUS_PARTIAL = 1, 922 HTT_DBG_STATS_STATUS_ERROR = 2, 923 HTT_DBG_STATS_STATUS_INVALID = 3, 924 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 925 }; 926 927 /* 928 * target -> host statistics upload 929 * 930 * The following field definitions describe the format of the HTT target 931 * to host stats upload confirmation message. 932 * The message contains a cookie echoed from the HTT host->target stats 933 * upload request, which identifies which request the confirmation is 934 * for, and a series of tag-length-value stats information elements. 935 * The tag-length header for each stats info element also includes a 936 * status field, to indicate whether the request for the stat type in 937 * question was fully met, partially met, unable to be met, or invalid 938 * (if the stat type in question is disabled in the target). 939 * A special value of all 1's in this status field is used to indicate 940 * the end of the series of stats info elements. 941 * 942 * 943 * |31 16|15 8|7 5|4 0| 944 * |------------------------------------------------------------| 945 * | reserved | msg type | 946 * |------------------------------------------------------------| 947 * | cookie LSBs | 948 * |------------------------------------------------------------| 949 * | cookie MSBs | 950 * |------------------------------------------------------------| 951 * | stats entry length | reserved | S |stat type| 952 * |------------------------------------------------------------| 953 * | | 954 * | type-specific stats info | 955 * | | 956 * |------------------------------------------------------------| 957 * | stats entry length | reserved | S |stat type| 958 * |------------------------------------------------------------| 959 * | | 960 * | type-specific stats info | 961 * | | 962 * |------------------------------------------------------------| 963 * | n/a | reserved | 111 | n/a | 964 * |------------------------------------------------------------| 965 * Header fields: 966 * - MSG_TYPE 967 * Bits 7:0 968 * Purpose: identifies this is a statistics upload confirmation message 969 * Value: 0x9 970 * - COOKIE_LSBS 971 * Bits 31:0 972 * Purpose: Provide a mechanism to match a target->host stats confirmation 973 * message with its preceding host->target stats request message. 974 * Value: LSBs of the opaque cookie specified by the host-side requestor 975 * - COOKIE_MSBS 976 * Bits 31:0 977 * Purpose: Provide a mechanism to match a target->host stats confirmation 978 * message with its preceding host->target stats request message. 979 * Value: MSBs of the opaque cookie specified by the host-side requestor 980 * 981 * Stats Information Element tag-length header fields: 982 * - STAT_TYPE 983 * Bits 4:0 984 * Purpose: identifies the type of statistics info held in the 985 * following information element 986 * Value: htt_dbg_stats_type 987 * - STATUS 988 * Bits 7:5 989 * Purpose: indicate whether the requested stats are present 990 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 991 * the completion of the stats entry series 992 * - LENGTH 993 * Bits 31:16 994 * Purpose: indicate the stats information size 995 * Value: This field specifies the number of bytes of stats information 996 * that follows the element tag-length header. 997 * It is expected but not required that this length is a multiple of 998 * 4 bytes. Even if the length is not an integer multiple of 4, the 999 * subsequent stats entry header will begin on a 4-byte aligned 1000 * boundary. 1001 */ 1002 1003 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1004 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1005 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1006 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1007 1008 struct htt_stats_conf_item { 1009 union { 1010 u8 info; 1011 struct { 1012 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1013 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1014 } __packed; 1015 } __packed; 1016 u8 pad; 1017 __le16 length; 1018 u8 payload[0]; /* roundup(length, 4) long */ 1019 } __packed; 1020 1021 struct htt_stats_conf { 1022 u8 pad[3]; 1023 __le32 cookie_lsb; 1024 __le32 cookie_msb; 1025 1026 /* each item has variable length! */ 1027 struct htt_stats_conf_item items[0]; 1028 } __packed; 1029 1030 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1031 const struct htt_stats_conf_item *item) 1032 { 1033 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1034 } 1035 /* 1036 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1037 * 1038 * The following field definitions describe the format of the HTT host 1039 * to target frag_desc/msdu_ext bank configuration message. 1040 * The message contains the based address and the min and max id of the 1041 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1042 * MSDU_EXT/FRAG_DESC. 1043 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1044 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1045 * the hardware does the mapping/translation. 1046 * 1047 * Total banks that can be configured is configured to 16. 1048 * 1049 * This should be called before any TX has be initiated by the HTT 1050 * 1051 * |31 16|15 8|7 5|4 0| 1052 * |------------------------------------------------------------| 1053 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1054 * |------------------------------------------------------------| 1055 * | BANK0_BASE_ADDRESS | 1056 * |------------------------------------------------------------| 1057 * | ... | 1058 * |------------------------------------------------------------| 1059 * | BANK15_BASE_ADDRESS | 1060 * |------------------------------------------------------------| 1061 * | BANK0_MAX_ID | BANK0_MIN_ID | 1062 * |------------------------------------------------------------| 1063 * | ... | 1064 * |------------------------------------------------------------| 1065 * | BANK15_MAX_ID | BANK15_MIN_ID | 1066 * |------------------------------------------------------------| 1067 * Header fields: 1068 * - MSG_TYPE 1069 * Bits 7:0 1070 * Value: 0x6 1071 * - BANKx_BASE_ADDRESS 1072 * Bits 31:0 1073 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1074 * bank physical/bus address. 1075 * - BANKx_MIN_ID 1076 * Bits 15:0 1077 * Purpose: Provide a mechanism to specify the min index that needs to 1078 * mapped. 1079 * - BANKx_MAX_ID 1080 * Bits 31:16 1081 * Purpose: Provide a mechanism to specify the max index that needs to 1082 * 1083 */ 1084 struct htt_frag_desc_bank_id { 1085 __le16 bank_min_id; 1086 __le16 bank_max_id; 1087 } __packed; 1088 1089 /* real is 16 but it wouldn't fit in the max htt message size 1090 * so we use a conservatively safe value for now */ 1091 #define HTT_FRAG_DESC_BANK_MAX 4 1092 1093 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1094 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1095 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP (1 << 2) 1096 1097 struct htt_frag_desc_bank_cfg { 1098 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1099 u8 num_banks; 1100 u8 desc_size; 1101 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1102 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1103 } __packed; 1104 1105 union htt_rx_pn_t { 1106 /* WEP: 24-bit PN */ 1107 u32 pn24; 1108 1109 /* TKIP or CCMP: 48-bit PN */ 1110 u_int64_t pn48; 1111 1112 /* WAPI: 128-bit PN */ 1113 u_int64_t pn128[2]; 1114 }; 1115 1116 struct htt_cmd { 1117 struct htt_cmd_hdr hdr; 1118 union { 1119 struct htt_ver_req ver_req; 1120 struct htt_mgmt_tx_desc mgmt_tx; 1121 struct htt_data_tx_desc data_tx; 1122 struct htt_rx_ring_setup rx_setup; 1123 struct htt_stats_req stats_req; 1124 struct htt_oob_sync_req oob_sync_req; 1125 struct htt_aggr_conf aggr_conf; 1126 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg; 1127 }; 1128 } __packed; 1129 1130 struct htt_resp { 1131 struct htt_resp_hdr hdr; 1132 union { 1133 struct htt_ver_resp ver_resp; 1134 struct htt_mgmt_tx_completion mgmt_tx_completion; 1135 struct htt_data_tx_completion data_tx_completion; 1136 struct htt_rx_indication rx_ind; 1137 struct htt_rx_fragment_indication rx_frag_ind; 1138 struct htt_rx_peer_map peer_map; 1139 struct htt_rx_peer_unmap peer_unmap; 1140 struct htt_rx_flush rx_flush; 1141 struct htt_rx_addba rx_addba; 1142 struct htt_rx_delba rx_delba; 1143 struct htt_security_indication security_indication; 1144 struct htt_rc_update rc_update; 1145 struct htt_rx_test rx_test; 1146 struct htt_pktlog_msg pktlog_msg; 1147 struct htt_stats_conf stats_conf; 1148 }; 1149 } __packed; 1150 1151 1152 /*** host side structures follow ***/ 1153 1154 struct htt_tx_done { 1155 u32 msdu_id; 1156 bool discard; 1157 bool no_ack; 1158 }; 1159 1160 struct htt_peer_map_event { 1161 u8 vdev_id; 1162 u16 peer_id; 1163 u8 addr[ETH_ALEN]; 1164 }; 1165 1166 struct htt_peer_unmap_event { 1167 u16 peer_id; 1168 }; 1169 1170 struct ath10k_htt_txbuf { 1171 struct htt_data_tx_desc_frag frags[2]; 1172 struct ath10k_htc_hdr htc_hdr; 1173 struct htt_cmd_hdr cmd_hdr; 1174 struct htt_data_tx_desc cmd_tx; 1175 } __packed; 1176 1177 struct ath10k_htt { 1178 struct ath10k *ar; 1179 enum ath10k_htc_ep_id eid; 1180 1181 int max_throughput_mbps; 1182 u8 target_version_major; 1183 u8 target_version_minor; 1184 struct completion target_version_received; 1185 1186 struct { 1187 /* 1188 * Ring of network buffer objects - This ring is 1189 * used exclusively by the host SW. This ring 1190 * mirrors the dev_addrs_ring that is shared 1191 * between the host SW and the MAC HW. The host SW 1192 * uses this netbufs ring to locate the network 1193 * buffer objects whose data buffers the HW has 1194 * filled. 1195 */ 1196 struct sk_buff **netbufs_ring; 1197 /* 1198 * Ring of buffer addresses - 1199 * This ring holds the "physical" device address of the 1200 * rx buffers the host SW provides for the MAC HW to 1201 * fill. 1202 */ 1203 __le32 *paddrs_ring; 1204 1205 /* 1206 * Base address of ring, as a "physical" device address 1207 * rather than a CPU address. 1208 */ 1209 dma_addr_t base_paddr; 1210 1211 /* how many elems in the ring (power of 2) */ 1212 int size; 1213 1214 /* size - 1 */ 1215 unsigned size_mask; 1216 1217 /* how many rx buffers to keep in the ring */ 1218 int fill_level; 1219 1220 /* how many rx buffers (full+empty) are in the ring */ 1221 int fill_cnt; 1222 1223 /* 1224 * alloc_idx - where HTT SW has deposited empty buffers 1225 * This is allocated in consistent mem, so that the FW can 1226 * read this variable, and program the HW's FW_IDX reg with 1227 * the value of this shadow register. 1228 */ 1229 struct { 1230 __le32 *vaddr; 1231 dma_addr_t paddr; 1232 } alloc_idx; 1233 1234 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1235 struct { 1236 unsigned msdu_payld; 1237 } sw_rd_idx; 1238 1239 /* 1240 * refill_retry_timer - timer triggered when the ring is 1241 * not refilled to the level expected 1242 */ 1243 struct timer_list refill_retry_timer; 1244 1245 /* Protects access to all rx ring buffer state variables */ 1246 spinlock_t lock; 1247 } rx_ring; 1248 1249 unsigned int prefetch_len; 1250 1251 /* Protects access to %pending_tx, %used_msdu_ids */ 1252 spinlock_t tx_lock; 1253 int max_num_pending_tx; 1254 int num_pending_tx; 1255 struct sk_buff **pending_tx; 1256 unsigned long *used_msdu_ids; /* bitmap */ 1257 wait_queue_head_t empty_tx_wq; 1258 struct dma_pool *tx_pool; 1259 1260 /* set if host-fw communication goes haywire 1261 * used to avoid further failures */ 1262 bool rx_confused; 1263 struct tasklet_struct rx_replenish_task; 1264 1265 /* This is used to group tx/rx completions separately and process them 1266 * in batches to reduce cache stalls */ 1267 struct tasklet_struct txrx_compl_task; 1268 struct sk_buff_head tx_compl_q; 1269 struct sk_buff_head rx_compl_q; 1270 1271 /* rx_status template */ 1272 struct ieee80211_rx_status rx_status; 1273 }; 1274 1275 #define RX_HTT_HDR_STATUS_LEN 64 1276 1277 /* This structure layout is programmed via rx ring setup 1278 * so that FW knows how to transfer the rx descriptor to the host. 1279 * Buffers like this are placed on the rx ring. */ 1280 struct htt_rx_desc { 1281 union { 1282 /* This field is filled on the host using the msdu buffer 1283 * from htt_rx_indication */ 1284 struct fw_rx_desc_base fw_desc; 1285 u32 pad; 1286 } __packed; 1287 struct { 1288 struct rx_attention attention; 1289 struct rx_frag_info frag_info; 1290 struct rx_mpdu_start mpdu_start; 1291 struct rx_msdu_start msdu_start; 1292 struct rx_msdu_end msdu_end; 1293 struct rx_mpdu_end mpdu_end; 1294 struct rx_ppdu_start ppdu_start; 1295 struct rx_ppdu_end ppdu_end; 1296 } __packed; 1297 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1298 u8 msdu_payload[0]; 1299 }; 1300 1301 #define HTT_RX_DESC_ALIGN 8 1302 1303 #define HTT_MAC_ADDR_LEN 6 1304 1305 /* 1306 * FIX THIS 1307 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 1308 * rounded up to a cache line size. 1309 */ 1310 #define HTT_RX_BUF_SIZE 1920 1311 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 1312 1313 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 1314 * aggregated traffic more nicely. */ 1315 #define ATH10K_HTT_MAX_NUM_REFILL 16 1316 1317 /* 1318 * DMA_MAP expects the buffer to be an integral number of cache lines. 1319 * Rather than checking the actual cache line size, this code makes a 1320 * conservative estimate of what the cache line size could be. 1321 */ 1322 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 1323 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 1324 1325 int ath10k_htt_connect(struct ath10k_htt *htt); 1326 int ath10k_htt_init(struct ath10k *ar); 1327 int ath10k_htt_setup(struct ath10k_htt *htt); 1328 1329 int ath10k_htt_tx_alloc(struct ath10k_htt *htt); 1330 void ath10k_htt_tx_free(struct ath10k_htt *htt); 1331 1332 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 1333 void ath10k_htt_rx_free(struct ath10k_htt *htt); 1334 1335 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1336 void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1337 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 1338 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 1339 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt); 1340 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 1341 u8 max_subfrms_ampdu, 1342 u8 max_subfrms_amsdu); 1343 1344 void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 1345 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt); 1346 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 1347 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *); 1348 int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *); 1349 1350 #endif 1351