1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _HTT_H_ 9 #define _HTT_H_ 10 11 #include <linux/bug.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmapool.h> 14 #include <linux/hashtable.h> 15 #include <linux/kfifo.h> 16 #include <net/mac80211.h> 17 18 #include "htc.h" 19 #include "hw.h" 20 #include "rx_desc.h" 21 22 enum htt_dbg_stats_type { 23 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 24 HTT_DBG_STATS_RX_REORDER = 1 << 1, 25 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 26 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 27 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 28 /* bits 5-23 currently reserved */ 29 30 HTT_DBG_NUM_STATS /* keep this last */ 31 }; 32 33 enum htt_h2t_msg_type { /* host-to-target */ 34 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 35 HTT_H2T_MSG_TYPE_TX_FRM = 1, 36 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 37 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 38 HTT_H2T_MSG_TYPE_SYNC = 4, 39 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 40 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 41 42 /* This command is used for sending management frames in HTT < 3.0. 43 * HTT >= 3.0 uses TX_FRM for everything. 44 */ 45 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 46 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11, 47 48 HTT_H2T_NUM_MSGS /* keep this last */ 49 }; 50 51 struct htt_cmd_hdr { 52 u8 msg_type; 53 } __packed; 54 55 struct htt_ver_req { 56 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 57 } __packed; 58 59 /* 60 * HTT tx MSDU descriptor 61 * 62 * The HTT tx MSDU descriptor is created by the host HTT SW for each 63 * tx MSDU. The HTT tx MSDU descriptor contains the information that 64 * the target firmware needs for the FW's tx processing, particularly 65 * for creating the HW msdu descriptor. 66 * The same HTT tx descriptor is used for HL and LL systems, though 67 * a few fields within the tx descriptor are used only by LL or 68 * only by HL. 69 * The HTT tx descriptor is defined in two manners: by a struct with 70 * bitfields, and by a series of [dword offset, bit mask, bit shift] 71 * definitions. 72 * The target should use the struct def, for simplicitly and clarity, 73 * but the host shall use the bit-mast + bit-shift defs, to be endian- 74 * neutral. Specifically, the host shall use the get/set macros built 75 * around the mask + shift defs. 76 */ 77 struct htt_data_tx_desc_frag { 78 union { 79 struct double_word_addr { 80 __le32 paddr; 81 __le32 len; 82 } __packed dword_addr; 83 struct triple_word_addr { 84 __le32 paddr_lo; 85 __le16 paddr_hi; 86 __le16 len_16; 87 } __packed tword_addr; 88 } __packed; 89 } __packed; 90 91 struct htt_msdu_ext_desc { 92 __le32 tso_flag[3]; 93 __le16 ip_identification; 94 u8 flags; 95 u8 reserved; 96 struct htt_data_tx_desc_frag frags[6]; 97 }; 98 99 struct htt_msdu_ext_desc_64 { 100 __le32 tso_flag[5]; 101 __le16 ip_identification; 102 u8 flags; 103 u8 reserved; 104 struct htt_data_tx_desc_frag frags[6]; 105 }; 106 107 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0) 108 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1) 109 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2) 110 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3) 111 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4) 112 113 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \ 114 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \ 115 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \ 116 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \ 117 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE) 118 119 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16) 120 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17) 121 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18) 122 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19) 123 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20) 124 #define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21) 125 126 #define HTT_MSDU_CHECKSUM_ENABLE_64 (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 \ 127 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 \ 128 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 \ 129 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 \ 130 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64) 131 132 enum htt_data_tx_desc_flags0 { 133 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 134 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 135 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 136 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 137 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 138 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 139 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 140 }; 141 142 enum htt_data_tx_desc_flags1 { 143 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 144 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 145 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 146 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 147 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 148 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 149 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 150 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 151 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 152 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 153 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 154 }; 155 156 enum htt_data_tx_ext_tid { 157 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 158 HTT_DATA_TX_EXT_TID_MGMT = 17, 159 HTT_DATA_TX_EXT_TID_INVALID = 31 160 }; 161 162 #define HTT_INVALID_PEERID 0xFFFF 163 164 /* 165 * htt_data_tx_desc - used for data tx path 166 * 167 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 168 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 169 * for special kinds of tids 170 * postponed: only for HL hosts. indicates if this is a resend 171 * (HL hosts manage queues on the host ) 172 * more_in_batch: only for HL hosts. indicates if more packets are 173 * pending. this allows target to wait and aggregate 174 * freq: 0 means home channel of given vdev. intended for offchannel 175 */ 176 struct htt_data_tx_desc { 177 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 178 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 179 __le16 len; 180 __le16 id; 181 __le32 frags_paddr; 182 union { 183 __le32 peerid; 184 struct { 185 __le16 peerid; 186 __le16 freq; 187 } __packed offchan_tx; 188 } __packed; 189 u8 prefetch[0]; /* start of frame, for FW classification engine */ 190 } __packed; 191 192 struct htt_data_tx_desc_64 { 193 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 194 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 195 __le16 len; 196 __le16 id; 197 __le64 frags_paddr; 198 union { 199 __le32 peerid; 200 struct { 201 __le16 peerid; 202 __le16 freq; 203 } __packed offchan_tx; 204 } __packed; 205 u8 prefetch[0]; /* start of frame, for FW classification engine */ 206 } __packed; 207 208 enum htt_rx_ring_flags { 209 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 210 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 211 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 212 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 213 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 214 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 215 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 216 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 217 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 218 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 219 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 220 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 221 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 222 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 223 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 224 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 225 }; 226 227 #define HTT_RX_RING_SIZE_MIN 128 228 #define HTT_RX_RING_SIZE_MAX 2048 229 #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX 230 #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1) 231 #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1) 232 233 struct htt_rx_ring_setup_ring32 { 234 __le32 fw_idx_shadow_reg_paddr; 235 __le32 rx_ring_base_paddr; 236 __le16 rx_ring_len; /* in 4-byte words */ 237 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 238 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 239 __le16 fw_idx_init_val; 240 241 /* the following offsets are in 4-byte units */ 242 __le16 mac80211_hdr_offset; 243 __le16 msdu_payload_offset; 244 __le16 ppdu_start_offset; 245 __le16 ppdu_end_offset; 246 __le16 mpdu_start_offset; 247 __le16 mpdu_end_offset; 248 __le16 msdu_start_offset; 249 __le16 msdu_end_offset; 250 __le16 rx_attention_offset; 251 __le16 frag_info_offset; 252 } __packed; 253 254 struct htt_rx_ring_setup_ring64 { 255 __le64 fw_idx_shadow_reg_paddr; 256 __le64 rx_ring_base_paddr; 257 __le16 rx_ring_len; /* in 4-byte words */ 258 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 259 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 260 __le16 fw_idx_init_val; 261 262 /* the following offsets are in 4-byte units */ 263 __le16 mac80211_hdr_offset; 264 __le16 msdu_payload_offset; 265 __le16 ppdu_start_offset; 266 __le16 ppdu_end_offset; 267 __le16 mpdu_start_offset; 268 __le16 mpdu_end_offset; 269 __le16 msdu_start_offset; 270 __le16 msdu_end_offset; 271 __le16 rx_attention_offset; 272 __le16 frag_info_offset; 273 } __packed; 274 275 struct htt_rx_ring_setup_hdr { 276 u8 num_rings; /* supported values: 1, 2 */ 277 __le16 rsvd0; 278 } __packed; 279 280 struct htt_rx_ring_setup_32 { 281 struct htt_rx_ring_setup_hdr hdr; 282 struct htt_rx_ring_setup_ring32 rings[0]; 283 } __packed; 284 285 struct htt_rx_ring_setup_64 { 286 struct htt_rx_ring_setup_hdr hdr; 287 struct htt_rx_ring_setup_ring64 rings[0]; 288 } __packed; 289 290 /* 291 * htt_stats_req - request target to send specified statistics 292 * 293 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 294 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 295 * so make sure its little-endian. 296 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 297 * so make sure its little-endian. 298 * @cfg_val: stat_type specific configuration 299 * @stat_type: see %htt_dbg_stats_type 300 * @cookie_lsb: used for confirmation message from target->host 301 * @cookie_msb: ditto as %cookie 302 */ 303 struct htt_stats_req { 304 u8 upload_types[3]; 305 u8 rsvd0; 306 u8 reset_types[3]; 307 struct { 308 u8 mpdu_bytes; 309 u8 mpdu_num_msdus; 310 u8 msdu_bytes; 311 } __packed; 312 u8 stat_type; 313 __le32 cookie_lsb; 314 __le32 cookie_msb; 315 } __packed; 316 317 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 318 319 /* 320 * htt_oob_sync_req - request out-of-band sync 321 * 322 * The HTT SYNC tells the target to suspend processing of subsequent 323 * HTT host-to-target messages until some other target agent locally 324 * informs the target HTT FW that the current sync counter is equal to 325 * or greater than (in a modulo sense) the sync counter specified in 326 * the SYNC message. 327 * 328 * This allows other host-target components to synchronize their operation 329 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 330 * security key has been downloaded to and activated by the target. 331 * In the absence of any explicit synchronization counter value 332 * specification, the target HTT FW will use zero as the default current 333 * sync value. 334 * 335 * The HTT target FW will suspend its host->target message processing as long 336 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 337 */ 338 struct htt_oob_sync_req { 339 u8 sync_count; 340 __le16 rsvd0; 341 } __packed; 342 343 struct htt_aggr_conf { 344 u8 max_num_ampdu_subframes; 345 /* amsdu_subframes is limited by 0x1F mask */ 346 u8 max_num_amsdu_subframes; 347 } __packed; 348 349 struct htt_aggr_conf_v2 { 350 u8 max_num_ampdu_subframes; 351 /* amsdu_subframes is limited by 0x1F mask */ 352 u8 max_num_amsdu_subframes; 353 u8 reserved; 354 } __packed; 355 356 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 357 struct htt_mgmt_tx_desc_qca99x0 { 358 __le32 rate; 359 } __packed; 360 361 struct htt_mgmt_tx_desc { 362 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 363 __le32 msdu_paddr; 364 __le32 desc_id; 365 __le32 len; 366 __le32 vdev_id; 367 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 368 union { 369 struct htt_mgmt_tx_desc_qca99x0 qca99x0; 370 } __packed; 371 } __packed; 372 373 enum htt_mgmt_tx_status { 374 HTT_MGMT_TX_STATUS_OK = 0, 375 HTT_MGMT_TX_STATUS_RETRY = 1, 376 HTT_MGMT_TX_STATUS_DROP = 2 377 }; 378 379 /*=== target -> host messages ===============================================*/ 380 381 enum htt_main_t2h_msg_type { 382 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0, 383 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1, 384 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2, 385 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3, 386 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 387 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5, 388 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6, 389 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 390 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8, 391 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9, 392 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 393 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb, 394 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 395 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 396 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 397 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10, 398 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 399 HTT_MAIN_T2H_MSG_TYPE_TEST, 400 /* keep this last */ 401 HTT_MAIN_T2H_NUM_MSGS 402 }; 403 404 enum htt_10x_t2h_msg_type { 405 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0, 406 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1, 407 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2, 408 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3, 409 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 410 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5, 411 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6, 412 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 413 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8, 414 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9, 415 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 416 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb, 417 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 418 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 419 HTT_10X_T2H_MSG_TYPE_TEST = 0xe, 420 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 421 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11, 422 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12, 423 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13, 424 /* keep this last */ 425 HTT_10X_T2H_NUM_MSGS 426 }; 427 428 enum htt_tlv_t2h_msg_type { 429 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0, 430 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1, 431 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2, 432 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3, 433 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 434 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5, 435 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6, 436 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 437 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8, 438 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9, 439 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 440 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb, 441 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */ 442 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 443 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 444 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 445 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10, 446 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 447 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 448 /* 0x13 reservd */ 449 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 450 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 451 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 452 HTT_TLV_T2H_MSG_TYPE_TEST, 453 /* keep this last */ 454 HTT_TLV_T2H_NUM_MSGS 455 }; 456 457 enum htt_10_4_t2h_msg_type { 458 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0, 459 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1, 460 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2, 461 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3, 462 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 463 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5, 464 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6, 465 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 466 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8, 467 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9, 468 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 469 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb, 470 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 471 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 472 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 473 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 474 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10, 475 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11, 476 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12, 477 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13, 478 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14, 479 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15, 480 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16, 481 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17, 482 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18, 483 /* 0x19 to 0x2f are reserved */ 484 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30, 485 HTT_10_4_T2H_MSG_TYPE_PEER_STATS = 0x31, 486 /* keep this last */ 487 HTT_10_4_T2H_NUM_MSGS 488 }; 489 490 enum htt_t2h_msg_type { 491 HTT_T2H_MSG_TYPE_VERSION_CONF, 492 HTT_T2H_MSG_TYPE_RX_IND, 493 HTT_T2H_MSG_TYPE_RX_FLUSH, 494 HTT_T2H_MSG_TYPE_PEER_MAP, 495 HTT_T2H_MSG_TYPE_PEER_UNMAP, 496 HTT_T2H_MSG_TYPE_RX_ADDBA, 497 HTT_T2H_MSG_TYPE_RX_DELBA, 498 HTT_T2H_MSG_TYPE_TX_COMPL_IND, 499 HTT_T2H_MSG_TYPE_PKTLOG, 500 HTT_T2H_MSG_TYPE_STATS_CONF, 501 HTT_T2H_MSG_TYPE_RX_FRAG_IND, 502 HTT_T2H_MSG_TYPE_SEC_IND, 503 HTT_T2H_MSG_TYPE_RC_UPDATE_IND, 504 HTT_T2H_MSG_TYPE_TX_INSPECT_IND, 505 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION, 506 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, 507 HTT_T2H_MSG_TYPE_RX_PN_IND, 508 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND, 509 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND, 510 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE, 511 HTT_T2H_MSG_TYPE_CHAN_CHANGE, 512 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR, 513 HTT_T2H_MSG_TYPE_AGGR_CONF, 514 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, 515 HTT_T2H_MSG_TYPE_TEST, 516 HTT_T2H_MSG_TYPE_EN_STATS, 517 HTT_T2H_MSG_TYPE_TX_FETCH_IND, 518 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM, 519 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND, 520 HTT_T2H_MSG_TYPE_PEER_STATS, 521 /* keep this last */ 522 HTT_T2H_NUM_MSGS 523 }; 524 525 /* 526 * htt_resp_hdr - header for target-to-host messages 527 * 528 * msg_type: see htt_t2h_msg_type 529 */ 530 struct htt_resp_hdr { 531 u8 msg_type; 532 } __packed; 533 534 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 535 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 536 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 537 538 /* htt_ver_resp - response sent for htt_ver_req */ 539 struct htt_ver_resp { 540 u8 minor; 541 u8 major; 542 u8 rsvd0; 543 } __packed; 544 545 #define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI BIT(0) 546 547 #define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK GENMASK(7, 0) 548 549 struct htt_mgmt_tx_completion { 550 u8 rsvd0; 551 u8 rsvd1; 552 u8 flags; 553 __le32 desc_id; 554 __le32 status; 555 __le32 ppdu_id; 556 __le32 info; 557 } __packed; 558 559 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F) 560 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 561 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5) 562 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6) 563 #define HTT_RX_INDICATION_INFO0_PPDU_DURATION BIT(7) 564 565 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 566 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 567 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 568 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 569 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 570 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 571 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 572 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 573 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 574 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 575 576 #define HTT_TX_CMPL_FLAG_DATA_RSSI BIT(0) 577 #define HTT_TX_CMPL_FLAG_PPID_PRESENT BIT(1) 578 #define HTT_TX_CMPL_FLAG_PA_PRESENT BIT(2) 579 #define HTT_TX_CMPL_FLAG_PPDU_DURATION_PRESENT BIT(3) 580 581 #define HTT_TX_DATA_RSSI_ENABLE_WCN3990 BIT(3) 582 #define HTT_TX_DATA_APPEND_RETRIES BIT(0) 583 #define HTT_TX_DATA_APPEND_TIMESTAMP BIT(1) 584 585 struct htt_rx_indication_hdr { 586 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 587 __le16 peer_id; 588 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 589 } __packed; 590 591 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 592 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 593 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 594 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 595 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 596 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 597 598 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 599 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 600 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 601 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 602 603 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 604 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 605 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 606 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 607 608 enum htt_rx_legacy_rate { 609 HTT_RX_OFDM_48 = 0, 610 HTT_RX_OFDM_24 = 1, 611 HTT_RX_OFDM_12, 612 HTT_RX_OFDM_6, 613 HTT_RX_OFDM_54, 614 HTT_RX_OFDM_36, 615 HTT_RX_OFDM_18, 616 HTT_RX_OFDM_9, 617 618 /* long preamble */ 619 HTT_RX_CCK_11_LP = 0, 620 HTT_RX_CCK_5_5_LP = 1, 621 HTT_RX_CCK_2_LP, 622 HTT_RX_CCK_1_LP, 623 /* short preamble */ 624 HTT_RX_CCK_11_SP, 625 HTT_RX_CCK_5_5_SP, 626 HTT_RX_CCK_2_SP 627 }; 628 629 enum htt_rx_legacy_rate_type { 630 HTT_RX_LEGACY_RATE_OFDM = 0, 631 HTT_RX_LEGACY_RATE_CCK 632 }; 633 634 enum htt_rx_preamble_type { 635 HTT_RX_LEGACY = 0x4, 636 HTT_RX_HT = 0x8, 637 HTT_RX_HT_WITH_TXBF = 0x9, 638 HTT_RX_VHT = 0xC, 639 HTT_RX_VHT_WITH_TXBF = 0xD, 640 }; 641 642 /* 643 * Fields: phy_err_valid, phy_err_code, tsf, 644 * usec_timestamp, sub_usec_timestamp 645 * ..are valid only if end_valid == 1. 646 * 647 * Fields: rssi_chains, legacy_rate_type, 648 * legacy_rate_cck, preamble_type, service, 649 * vht_sig_* 650 * ..are valid only if start_valid == 1; 651 */ 652 struct htt_rx_indication_ppdu { 653 u8 combined_rssi; 654 u8 sub_usec_timestamp; 655 u8 phy_err_code; 656 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 657 struct { 658 u8 pri20_db; 659 u8 ext20_db; 660 u8 ext40_db; 661 u8 ext80_db; 662 } __packed rssi_chains[4]; 663 __le32 tsf; 664 __le32 usec_timestamp; 665 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 666 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 667 } __packed; 668 669 enum htt_rx_mpdu_status { 670 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 671 HTT_RX_IND_MPDU_STATUS_OK, 672 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 673 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 674 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 675 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 676 /* only accept EAPOL frames */ 677 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 678 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 679 /* Non-data in promiscuous mode */ 680 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 681 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 682 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 683 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 684 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 685 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 686 687 /* 688 * MISC: discard for unspecified reasons. 689 * Leave this enum value last. 690 */ 691 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 692 }; 693 694 struct htt_rx_indication_mpdu_range { 695 u8 mpdu_count; 696 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 697 u8 pad0; 698 u8 pad1; 699 } __packed; 700 701 struct htt_rx_indication_prefix { 702 __le16 fw_rx_desc_bytes; 703 u8 pad0; 704 u8 pad1; 705 }; 706 707 struct htt_rx_indication { 708 struct htt_rx_indication_hdr hdr; 709 struct htt_rx_indication_ppdu ppdu; 710 struct htt_rx_indication_prefix prefix; 711 712 /* 713 * the following fields are both dynamically sized, so 714 * take care addressing them 715 */ 716 717 /* the size of this is %fw_rx_desc_bytes */ 718 struct fw_rx_desc_base fw_desc; 719 720 /* 721 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 722 * and has %num_mpdu_ranges elements. 723 */ 724 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 725 } __packed; 726 727 /* High latency version of the RX indication */ 728 struct htt_rx_indication_hl { 729 struct htt_rx_indication_hdr hdr; 730 struct htt_rx_indication_ppdu ppdu; 731 struct htt_rx_indication_prefix prefix; 732 struct fw_rx_desc_hl fw_desc; 733 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 734 } __packed; 735 736 static inline struct htt_rx_indication_mpdu_range * 737 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 738 { 739 void *ptr = rx_ind; 740 741 ptr += sizeof(rx_ind->hdr) 742 + sizeof(rx_ind->ppdu) 743 + sizeof(rx_ind->prefix) 744 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 745 return ptr; 746 } 747 748 static inline struct htt_rx_indication_mpdu_range * 749 htt_rx_ind_get_mpdu_ranges_hl(struct htt_rx_indication_hl *rx_ind) 750 { 751 void *ptr = rx_ind; 752 753 ptr += sizeof(rx_ind->hdr) 754 + sizeof(rx_ind->ppdu) 755 + sizeof(rx_ind->prefix) 756 + sizeof(rx_ind->fw_desc); 757 return ptr; 758 } 759 760 enum htt_rx_flush_mpdu_status { 761 HTT_RX_FLUSH_MPDU_DISCARD = 0, 762 HTT_RX_FLUSH_MPDU_REORDER = 1, 763 }; 764 765 /* 766 * htt_rx_flush - discard or reorder given range of mpdus 767 * 768 * Note: host must check if all sequence numbers between 769 * [seq_num_start, seq_num_end-1] are valid. 770 */ 771 struct htt_rx_flush { 772 __le16 peer_id; 773 u8 tid; 774 u8 rsvd0; 775 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 776 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 777 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 778 }; 779 780 struct htt_rx_peer_map { 781 u8 vdev_id; 782 __le16 peer_id; 783 u8 addr[6]; 784 u8 rsvd0; 785 u8 rsvd1; 786 } __packed; 787 788 struct htt_rx_peer_unmap { 789 u8 rsvd0; 790 __le16 peer_id; 791 } __packed; 792 793 enum htt_security_types { 794 HTT_SECURITY_NONE, 795 HTT_SECURITY_WEP128, 796 HTT_SECURITY_WEP104, 797 HTT_SECURITY_WEP40, 798 HTT_SECURITY_TKIP, 799 HTT_SECURITY_TKIP_NOMIC, 800 HTT_SECURITY_AES_CCMP, 801 HTT_SECURITY_WAPI, 802 803 HTT_NUM_SECURITY_TYPES /* keep this last! */ 804 }; 805 806 enum htt_security_flags { 807 #define HTT_SECURITY_TYPE_MASK 0x7F 808 #define HTT_SECURITY_TYPE_LSB 0 809 HTT_SECURITY_IS_UNICAST = 1 << 7 810 }; 811 812 struct htt_security_indication { 813 union { 814 /* dont use bitfields; undefined behaviour */ 815 u8 flags; /* %htt_security_flags */ 816 struct { 817 u8 security_type:7, /* %htt_security_types */ 818 is_unicast:1; 819 } __packed; 820 } __packed; 821 __le16 peer_id; 822 u8 michael_key[8]; 823 u8 wapi_rsc[16]; 824 } __packed; 825 826 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 827 #define HTT_RX_BA_INFO0_TID_LSB 0 828 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 829 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 830 831 struct htt_rx_addba { 832 u8 window_size; 833 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 834 } __packed; 835 836 struct htt_rx_delba { 837 u8 rsvd0; 838 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 839 } __packed; 840 841 enum htt_data_tx_status { 842 HTT_DATA_TX_STATUS_OK = 0, 843 HTT_DATA_TX_STATUS_DISCARD = 1, 844 HTT_DATA_TX_STATUS_NO_ACK = 2, 845 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 846 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 847 }; 848 849 enum htt_data_tx_flags { 850 #define HTT_DATA_TX_STATUS_MASK 0x07 851 #define HTT_DATA_TX_STATUS_LSB 0 852 #define HTT_DATA_TX_TID_MASK 0x78 853 #define HTT_DATA_TX_TID_LSB 3 854 HTT_DATA_TX_TID_INVALID = 1 << 7 855 }; 856 857 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 858 859 struct htt_append_retries { 860 __le16 msdu_id; 861 u8 tx_retries; 862 u8 flag; 863 } __packed; 864 865 struct htt_data_tx_completion_ext { 866 struct htt_append_retries a_retries; 867 __le32 t_stamp; 868 __le16 msdus_rssi[0]; 869 } __packed; 870 871 /** 872 * @brief target -> host TX completion indication message definition 873 * 874 * @details 875 * The following diagram shows the format of the TX completion indication sent 876 * from the target to the host 877 * 878 * |31 28|27|26|25|24|23 16| 15 |14 11|10 8|7 0| 879 * |-------------------------------------------------------------| 880 * header: |rsvd |A2|TP|A1|A0| num | t_i| tid |status| msg_type | 881 * |-------------------------------------------------------------| 882 * payload: | MSDU1 ID | MSDU0 ID | 883 * |-------------------------------------------------------------| 884 * : MSDU3 ID : MSDU2 ID : 885 * |-------------------------------------------------------------| 886 * | struct htt_tx_compl_ind_append_retries | 887 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 888 * | struct htt_tx_compl_ind_append_tx_tstamp | 889 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 890 * | MSDU1 ACK RSSI | MSDU0 ACK RSSI | 891 * |-------------------------------------------------------------| 892 * : MSDU3 ACK RSSI : MSDU2 ACK RSSI : 893 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 894 * -msg_type 895 * Bits 7:0 896 * Purpose: identifies this as HTT TX completion indication 897 * -status 898 * Bits 10:8 899 * Purpose: the TX completion status of payload fragmentations descriptors 900 * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD 901 * -tid 902 * Bits 14:11 903 * Purpose: the tid associated with those fragmentation descriptors. It is 904 * valid or not, depending on the tid_invalid bit. 905 * Value: 0 to 15 906 * -tid_invalid 907 * Bits 15:15 908 * Purpose: this bit indicates whether the tid field is valid or not 909 * Value: 0 indicates valid, 1 indicates invalid 910 * -num 911 * Bits 23:16 912 * Purpose: the number of payload in this indication 913 * Value: 1 to 255 914 * -A0 = append 915 * Bits 24:24 916 * Purpose: append the struct htt_tx_compl_ind_append_retries which contains 917 * the number of tx retries for one MSDU at the end of this message 918 * Value: 0 indicates no appending, 1 indicates appending 919 * -A1 = append1 920 * Bits 25:25 921 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tstamp which 922 * contains the timestamp info for each TX msdu id in payload. 923 * Value: 0 indicates no appending, 1 indicates appending 924 * -TP = MSDU tx power presence 925 * Bits 26:26 926 * Purpose: Indicate whether the TX_COMPL_IND includes a tx power report 927 * for each MSDU referenced by the TX_COMPL_IND message. 928 * The order of the per-MSDU tx power reports matches the order 929 * of the MSDU IDs. 930 * Value: 0 indicates not appending, 1 indicates appending 931 * -A2 = append2 932 * Bits 27:27 933 * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in 934 * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report 935 * matches the order of the MSDU IDs. 936 * The ACK RSSI values are valid when status is COMPLETE_OK (and 937 * this append2 bit is set). 938 * Value: 0 indicates not appending, 1 indicates appending 939 */ 940 941 struct htt_data_tx_completion { 942 union { 943 u8 flags; 944 struct { 945 u8 status:3, 946 tid:4, 947 tid_invalid:1; 948 } __packed; 949 } __packed; 950 u8 num_msdus; 951 u8 flags2; /* HTT_TX_CMPL_FLAG_DATA_RSSI */ 952 __le16 msdus[0]; /* variable length based on %num_msdus */ 953 } __packed; 954 955 #define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK GENMASK(15, 0) 956 #define HTT_TX_PPDU_DUR_INFO0_TID_MASK GENMASK(20, 16) 957 958 struct htt_data_tx_ppdu_dur { 959 __le32 info0; /* HTT_TX_PPDU_DUR_INFO0_ */ 960 __le32 tx_duration; /* in usecs */ 961 } __packed; 962 963 #define HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK GENMASK(7, 0) 964 965 struct htt_data_tx_compl_ppdu_dur { 966 __le32 info0; /* HTT_TX_COMPL_PPDU_DUR_INFO0_ */ 967 struct htt_data_tx_ppdu_dur ppdu_dur[0]; 968 } __packed; 969 970 struct htt_tx_compl_ind_base { 971 u32 hdr; 972 u16 payload[1/*or more*/]; 973 } __packed; 974 975 struct htt_rc_tx_done_params { 976 u32 rate_code; 977 u32 rate_code_flags; 978 u32 flags; 979 u32 num_enqued; /* 1 for non-AMPDU */ 980 u32 num_retries; 981 u32 num_failed; /* for AMPDU */ 982 u32 ack_rssi; 983 u32 time_stamp; 984 u32 is_probe; 985 }; 986 987 struct htt_rc_update { 988 u8 vdev_id; 989 __le16 peer_id; 990 u8 addr[6]; 991 u8 num_elems; 992 u8 rsvd0; 993 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 994 } __packed; 995 996 /* see htt_rx_indication for similar fields and descriptions */ 997 struct htt_rx_fragment_indication { 998 union { 999 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 1000 struct { 1001 u8 ext_tid:5, 1002 flush_valid:1; 1003 } __packed; 1004 } __packed; 1005 __le16 peer_id; 1006 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 1007 __le16 fw_rx_desc_bytes; 1008 __le16 rsvd0; 1009 1010 u8 fw_msdu_rx_desc[0]; 1011 } __packed; 1012 1013 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 1014 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 1015 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 1016 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 1017 1018 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 1019 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 1020 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 1021 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 1022 1023 struct htt_rx_pn_ind { 1024 __le16 peer_id; 1025 u8 tid; 1026 u8 seqno_start; 1027 u8 seqno_end; 1028 u8 pn_ie_count; 1029 u8 reserved; 1030 u8 pn_ies[0]; 1031 } __packed; 1032 1033 struct htt_rx_offload_msdu { 1034 __le16 msdu_len; 1035 __le16 peer_id; 1036 u8 vdev_id; 1037 u8 tid; 1038 u8 fw_desc; 1039 u8 payload[0]; 1040 } __packed; 1041 1042 struct htt_rx_offload_ind { 1043 u8 reserved; 1044 __le16 msdu_count; 1045 } __packed; 1046 1047 struct htt_rx_in_ord_msdu_desc { 1048 __le32 msdu_paddr; 1049 __le16 msdu_len; 1050 u8 fw_desc; 1051 u8 reserved; 1052 } __packed; 1053 1054 struct htt_rx_in_ord_msdu_desc_ext { 1055 __le64 msdu_paddr; 1056 __le16 msdu_len; 1057 u8 fw_desc; 1058 u8 reserved; 1059 } __packed; 1060 1061 struct htt_rx_in_ord_ind { 1062 u8 info; 1063 __le16 peer_id; 1064 u8 vdev_id; 1065 u8 reserved; 1066 __le16 msdu_count; 1067 union { 1068 struct htt_rx_in_ord_msdu_desc msdu_descs32[0]; 1069 struct htt_rx_in_ord_msdu_desc_ext msdu_descs64[0]; 1070 } __packed; 1071 } __packed; 1072 1073 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f 1074 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 1075 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020 1076 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 1077 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040 1078 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 1079 1080 /* 1081 * target -> host test message definition 1082 * 1083 * The following field definitions describe the format of the test 1084 * message sent from the target to the host. 1085 * The message consists of a 4-octet header, followed by a variable 1086 * number of 32-bit integer values, followed by a variable number 1087 * of 8-bit character values. 1088 * 1089 * |31 16|15 8|7 0| 1090 * |-----------------------------------------------------------| 1091 * | num chars | num ints | msg type | 1092 * |-----------------------------------------------------------| 1093 * | int 0 | 1094 * |-----------------------------------------------------------| 1095 * | int 1 | 1096 * |-----------------------------------------------------------| 1097 * | ... | 1098 * |-----------------------------------------------------------| 1099 * | char 3 | char 2 | char 1 | char 0 | 1100 * |-----------------------------------------------------------| 1101 * | | | ... | char 4 | 1102 * |-----------------------------------------------------------| 1103 * - MSG_TYPE 1104 * Bits 7:0 1105 * Purpose: identifies this as a test message 1106 * Value: HTT_MSG_TYPE_TEST 1107 * - NUM_INTS 1108 * Bits 15:8 1109 * Purpose: indicate how many 32-bit integers follow the message header 1110 * - NUM_CHARS 1111 * Bits 31:16 1112 * Purpose: indicate how many 8-bit characters follow the series of integers 1113 */ 1114 struct htt_rx_test { 1115 u8 num_ints; 1116 __le16 num_chars; 1117 1118 /* payload consists of 2 lists: 1119 * a) num_ints * sizeof(__le32) 1120 * b) num_chars * sizeof(u8) aligned to 4bytes 1121 */ 1122 u8 payload[0]; 1123 } __packed; 1124 1125 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 1126 { 1127 return (__le32 *)rx_test->payload; 1128 } 1129 1130 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 1131 { 1132 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 1133 } 1134 1135 /* 1136 * target -> host packet log message 1137 * 1138 * The following field definitions describe the format of the packet log 1139 * message sent from the target to the host. 1140 * The message consists of a 4-octet header,followed by a variable number 1141 * of 32-bit character values. 1142 * 1143 * |31 24|23 16|15 8|7 0| 1144 * |-----------------------------------------------------------| 1145 * | | | | msg type | 1146 * |-----------------------------------------------------------| 1147 * | payload | 1148 * |-----------------------------------------------------------| 1149 * - MSG_TYPE 1150 * Bits 7:0 1151 * Purpose: identifies this as a test message 1152 * Value: HTT_MSG_TYPE_PACKETLOG 1153 */ 1154 struct htt_pktlog_msg { 1155 u8 pad[3]; 1156 u8 payload[0]; 1157 } __packed; 1158 1159 struct htt_dbg_stats_rx_reorder_stats { 1160 /* Non QoS MPDUs received */ 1161 __le32 deliver_non_qos; 1162 1163 /* MPDUs received in-order */ 1164 __le32 deliver_in_order; 1165 1166 /* Flush due to reorder timer expired */ 1167 __le32 deliver_flush_timeout; 1168 1169 /* Flush due to move out of window */ 1170 __le32 deliver_flush_oow; 1171 1172 /* Flush due to DELBA */ 1173 __le32 deliver_flush_delba; 1174 1175 /* MPDUs dropped due to FCS error */ 1176 __le32 fcs_error; 1177 1178 /* MPDUs dropped due to monitor mode non-data packet */ 1179 __le32 mgmt_ctrl; 1180 1181 /* MPDUs dropped due to invalid peer */ 1182 __le32 invalid_peer; 1183 1184 /* MPDUs dropped due to duplication (non aggregation) */ 1185 __le32 dup_non_aggr; 1186 1187 /* MPDUs dropped due to processed before */ 1188 __le32 dup_past; 1189 1190 /* MPDUs dropped due to duplicate in reorder queue */ 1191 __le32 dup_in_reorder; 1192 1193 /* Reorder timeout happened */ 1194 __le32 reorder_timeout; 1195 1196 /* invalid bar ssn */ 1197 __le32 invalid_bar_ssn; 1198 1199 /* reorder reset due to bar ssn */ 1200 __le32 ssn_reset; 1201 }; 1202 1203 struct htt_dbg_stats_wal_tx_stats { 1204 /* Num HTT cookies queued to dispatch list */ 1205 __le32 comp_queued; 1206 1207 /* Num HTT cookies dispatched */ 1208 __le32 comp_delivered; 1209 1210 /* Num MSDU queued to WAL */ 1211 __le32 msdu_enqued; 1212 1213 /* Num MPDU queue to WAL */ 1214 __le32 mpdu_enqued; 1215 1216 /* Num MSDUs dropped by WMM limit */ 1217 __le32 wmm_drop; 1218 1219 /* Num Local frames queued */ 1220 __le32 local_enqued; 1221 1222 /* Num Local frames done */ 1223 __le32 local_freed; 1224 1225 /* Num queued to HW */ 1226 __le32 hw_queued; 1227 1228 /* Num PPDU reaped from HW */ 1229 __le32 hw_reaped; 1230 1231 /* Num underruns */ 1232 __le32 underrun; 1233 1234 /* Num PPDUs cleaned up in TX abort */ 1235 __le32 tx_abort; 1236 1237 /* Num MPDUs requed by SW */ 1238 __le32 mpdus_requed; 1239 1240 /* excessive retries */ 1241 __le32 tx_ko; 1242 1243 /* data hw rate code */ 1244 __le32 data_rc; 1245 1246 /* Scheduler self triggers */ 1247 __le32 self_triggers; 1248 1249 /* frames dropped due to excessive sw retries */ 1250 __le32 sw_retry_failure; 1251 1252 /* illegal rate phy errors */ 1253 __le32 illgl_rate_phy_err; 1254 1255 /* wal pdev continuous xretry */ 1256 __le32 pdev_cont_xretry; 1257 1258 /* wal pdev continuous xretry */ 1259 __le32 pdev_tx_timeout; 1260 1261 /* wal pdev resets */ 1262 __le32 pdev_resets; 1263 1264 __le32 phy_underrun; 1265 1266 /* MPDU is more than txop limit */ 1267 __le32 txop_ovf; 1268 } __packed; 1269 1270 struct htt_dbg_stats_wal_rx_stats { 1271 /* Cnts any change in ring routing mid-ppdu */ 1272 __le32 mid_ppdu_route_change; 1273 1274 /* Total number of statuses processed */ 1275 __le32 status_rcvd; 1276 1277 /* Extra frags on rings 0-3 */ 1278 __le32 r0_frags; 1279 __le32 r1_frags; 1280 __le32 r2_frags; 1281 __le32 r3_frags; 1282 1283 /* MSDUs / MPDUs delivered to HTT */ 1284 __le32 htt_msdus; 1285 __le32 htt_mpdus; 1286 1287 /* MSDUs / MPDUs delivered to local stack */ 1288 __le32 loc_msdus; 1289 __le32 loc_mpdus; 1290 1291 /* AMSDUs that have more MSDUs than the status ring size */ 1292 __le32 oversize_amsdu; 1293 1294 /* Number of PHY errors */ 1295 __le32 phy_errs; 1296 1297 /* Number of PHY errors drops */ 1298 __le32 phy_err_drop; 1299 1300 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1301 __le32 mpdu_errs; 1302 } __packed; 1303 1304 struct htt_dbg_stats_wal_peer_stats { 1305 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 1306 } __packed; 1307 1308 struct htt_dbg_stats_wal_pdev_txrx { 1309 struct htt_dbg_stats_wal_tx_stats tx_stats; 1310 struct htt_dbg_stats_wal_rx_stats rx_stats; 1311 struct htt_dbg_stats_wal_peer_stats peer_stats; 1312 } __packed; 1313 1314 struct htt_dbg_stats_rx_rate_info { 1315 __le32 mcs[10]; 1316 __le32 sgi[10]; 1317 __le32 nss[4]; 1318 __le32 stbc[10]; 1319 __le32 bw[3]; 1320 __le32 pream[6]; 1321 __le32 ldpc; 1322 __le32 txbf; 1323 }; 1324 1325 /* 1326 * htt_dbg_stats_status - 1327 * present - The requested stats have been delivered in full. 1328 * This indicates that either the stats information was contained 1329 * in its entirety within this message, or else this message 1330 * completes the delivery of the requested stats info that was 1331 * partially delivered through earlier STATS_CONF messages. 1332 * partial - The requested stats have been delivered in part. 1333 * One or more subsequent STATS_CONF messages with the same 1334 * cookie value will be sent to deliver the remainder of the 1335 * information. 1336 * error - The requested stats could not be delivered, for example due 1337 * to a shortage of memory to construct a message holding the 1338 * requested stats. 1339 * invalid - The requested stat type is either not recognized, or the 1340 * target is configured to not gather the stats type in question. 1341 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1342 * series_done - This special value indicates that no further stats info 1343 * elements are present within a series of stats info elems 1344 * (within a stats upload confirmation message). 1345 */ 1346 enum htt_dbg_stats_status { 1347 HTT_DBG_STATS_STATUS_PRESENT = 0, 1348 HTT_DBG_STATS_STATUS_PARTIAL = 1, 1349 HTT_DBG_STATS_STATUS_ERROR = 2, 1350 HTT_DBG_STATS_STATUS_INVALID = 3, 1351 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 1352 }; 1353 1354 /* 1355 * target -> host statistics upload 1356 * 1357 * The following field definitions describe the format of the HTT target 1358 * to host stats upload confirmation message. 1359 * The message contains a cookie echoed from the HTT host->target stats 1360 * upload request, which identifies which request the confirmation is 1361 * for, and a series of tag-length-value stats information elements. 1362 * The tag-length header for each stats info element also includes a 1363 * status field, to indicate whether the request for the stat type in 1364 * question was fully met, partially met, unable to be met, or invalid 1365 * (if the stat type in question is disabled in the target). 1366 * A special value of all 1's in this status field is used to indicate 1367 * the end of the series of stats info elements. 1368 * 1369 * 1370 * |31 16|15 8|7 5|4 0| 1371 * |------------------------------------------------------------| 1372 * | reserved | msg type | 1373 * |------------------------------------------------------------| 1374 * | cookie LSBs | 1375 * |------------------------------------------------------------| 1376 * | cookie MSBs | 1377 * |------------------------------------------------------------| 1378 * | stats entry length | reserved | S |stat type| 1379 * |------------------------------------------------------------| 1380 * | | 1381 * | type-specific stats info | 1382 * | | 1383 * |------------------------------------------------------------| 1384 * | stats entry length | reserved | S |stat type| 1385 * |------------------------------------------------------------| 1386 * | | 1387 * | type-specific stats info | 1388 * | | 1389 * |------------------------------------------------------------| 1390 * | n/a | reserved | 111 | n/a | 1391 * |------------------------------------------------------------| 1392 * Header fields: 1393 * - MSG_TYPE 1394 * Bits 7:0 1395 * Purpose: identifies this is a statistics upload confirmation message 1396 * Value: 0x9 1397 * - COOKIE_LSBS 1398 * Bits 31:0 1399 * Purpose: Provide a mechanism to match a target->host stats confirmation 1400 * message with its preceding host->target stats request message. 1401 * Value: LSBs of the opaque cookie specified by the host-side requestor 1402 * - COOKIE_MSBS 1403 * Bits 31:0 1404 * Purpose: Provide a mechanism to match a target->host stats confirmation 1405 * message with its preceding host->target stats request message. 1406 * Value: MSBs of the opaque cookie specified by the host-side requestor 1407 * 1408 * Stats Information Element tag-length header fields: 1409 * - STAT_TYPE 1410 * Bits 4:0 1411 * Purpose: identifies the type of statistics info held in the 1412 * following information element 1413 * Value: htt_dbg_stats_type 1414 * - STATUS 1415 * Bits 7:5 1416 * Purpose: indicate whether the requested stats are present 1417 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 1418 * the completion of the stats entry series 1419 * - LENGTH 1420 * Bits 31:16 1421 * Purpose: indicate the stats information size 1422 * Value: This field specifies the number of bytes of stats information 1423 * that follows the element tag-length header. 1424 * It is expected but not required that this length is a multiple of 1425 * 4 bytes. Even if the length is not an integer multiple of 4, the 1426 * subsequent stats entry header will begin on a 4-byte aligned 1427 * boundary. 1428 */ 1429 1430 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1431 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1432 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1433 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1434 1435 struct htt_stats_conf_item { 1436 union { 1437 u8 info; 1438 struct { 1439 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1440 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1441 } __packed; 1442 } __packed; 1443 u8 pad; 1444 __le16 length; 1445 u8 payload[0]; /* roundup(length, 4) long */ 1446 } __packed; 1447 1448 struct htt_stats_conf { 1449 u8 pad[3]; 1450 __le32 cookie_lsb; 1451 __le32 cookie_msb; 1452 1453 /* each item has variable length! */ 1454 struct htt_stats_conf_item items[0]; 1455 } __packed; 1456 1457 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1458 const struct htt_stats_conf_item *item) 1459 { 1460 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1461 } 1462 1463 /* 1464 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1465 * 1466 * The following field definitions describe the format of the HTT host 1467 * to target frag_desc/msdu_ext bank configuration message. 1468 * The message contains the based address and the min and max id of the 1469 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1470 * MSDU_EXT/FRAG_DESC. 1471 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1472 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1473 * the hardware does the mapping/translation. 1474 * 1475 * Total banks that can be configured is configured to 16. 1476 * 1477 * This should be called before any TX has be initiated by the HTT 1478 * 1479 * |31 16|15 8|7 5|4 0| 1480 * |------------------------------------------------------------| 1481 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1482 * |------------------------------------------------------------| 1483 * | BANK0_BASE_ADDRESS | 1484 * |------------------------------------------------------------| 1485 * | ... | 1486 * |------------------------------------------------------------| 1487 * | BANK15_BASE_ADDRESS | 1488 * |------------------------------------------------------------| 1489 * | BANK0_MAX_ID | BANK0_MIN_ID | 1490 * |------------------------------------------------------------| 1491 * | ... | 1492 * |------------------------------------------------------------| 1493 * | BANK15_MAX_ID | BANK15_MIN_ID | 1494 * |------------------------------------------------------------| 1495 * Header fields: 1496 * - MSG_TYPE 1497 * Bits 7:0 1498 * Value: 0x6 1499 * - BANKx_BASE_ADDRESS 1500 * Bits 31:0 1501 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1502 * bank physical/bus address. 1503 * - BANKx_MIN_ID 1504 * Bits 15:0 1505 * Purpose: Provide a mechanism to specify the min index that needs to 1506 * mapped. 1507 * - BANKx_MAX_ID 1508 * Bits 31:16 1509 * Purpose: Provide a mechanism to specify the max index that needs to 1510 * 1511 */ 1512 struct htt_frag_desc_bank_id { 1513 __le16 bank_min_id; 1514 __le16 bank_max_id; 1515 } __packed; 1516 1517 /* real is 16 but it wouldn't fit in the max htt message size 1518 * so we use a conservatively safe value for now 1519 */ 1520 #define HTT_FRAG_DESC_BANK_MAX 4 1521 1522 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1523 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1524 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2) 1525 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3) 1526 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4) 1527 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4 1528 1529 enum htt_q_depth_type { 1530 HTT_Q_DEPTH_TYPE_BYTES = 0, 1531 HTT_Q_DEPTH_TYPE_MSDUS = 1, 1532 }; 1533 1534 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \ 1535 TARGET_10_4_NUM_VDEVS) 1536 #define HTT_TX_Q_STATE_NUM_TIDS 8 1537 #define HTT_TX_Q_STATE_ENTRY_SIZE 1 1538 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0 1539 1540 /** 1541 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config 1542 * 1543 * Defines host q state format and behavior. See htt_q_state. 1544 * 1545 * @record_size: Defines the size of each host q entry in bytes. In practice 1546 * however firmware (at least 10.4.3-00191) ignores this host 1547 * configuration value and uses hardcoded value of 1. 1548 * @record_multiplier: This is valid only when q depth type is MSDUs. It 1549 * defines the exponent for the power of 2 multiplication. 1550 */ 1551 struct htt_q_state_conf { 1552 __le32 paddr; 1553 __le16 num_peers; 1554 __le16 num_tids; 1555 u8 record_size; 1556 u8 record_multiplier; 1557 u8 pad[2]; 1558 } __packed; 1559 1560 struct htt_frag_desc_bank_cfg32 { 1561 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1562 u8 num_banks; 1563 u8 desc_size; 1564 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1565 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1566 struct htt_q_state_conf q_state; 1567 } __packed; 1568 1569 struct htt_frag_desc_bank_cfg64 { 1570 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1571 u8 num_banks; 1572 u8 desc_size; 1573 __le64 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1574 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1575 struct htt_q_state_conf q_state; 1576 } __packed; 1577 1578 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128 1579 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f 1580 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0 1581 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0 1582 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6 1583 1584 /** 1585 * htt_q_state - shared between host and firmware via DMA 1586 * 1587 * This structure is used for the host to expose it's software queue state to 1588 * firmware so that its rate control can schedule fetch requests for optimized 1589 * performance. This is most notably used for MU-MIMO aggregation when multiple 1590 * MU clients are connected. 1591 * 1592 * @count: Each element defines the host queue depth. When q depth type was 1593 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as: 1594 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and 1595 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as 1596 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 ** 1597 * record_multiplier (see htt_q_state_conf). 1598 * @map: Used by firmware to quickly check which host queues are not empty. It 1599 * is a bitmap simply saying. 1600 * @seq: Used by firmware to quickly check if the host queues were updated 1601 * since it last checked. 1602 * 1603 * FIXME: Is the q_state map[] size calculation really correct? 1604 */ 1605 struct htt_q_state { 1606 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS]; 1607 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32]; 1608 __le32 seq; 1609 } __packed; 1610 1611 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff 1612 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0 1613 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000 1614 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12 1615 1616 struct htt_tx_fetch_record { 1617 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */ 1618 __le16 num_msdus; 1619 __le32 num_bytes; 1620 } __packed; 1621 1622 struct htt_tx_fetch_ind { 1623 u8 pad0; 1624 __le16 fetch_seq_num; 1625 __le32 token; 1626 __le16 num_resp_ids; 1627 __le16 num_records; 1628 struct htt_tx_fetch_record records[0]; 1629 __le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */ 1630 } __packed; 1631 1632 static inline void * 1633 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind) 1634 { 1635 return (void *)&ind->records[le16_to_cpu(ind->num_records)]; 1636 } 1637 1638 struct htt_tx_fetch_resp { 1639 u8 pad0; 1640 __le16 resp_id; 1641 __le16 fetch_seq_num; 1642 __le16 num_records; 1643 __le32 token; 1644 struct htt_tx_fetch_record records[0]; 1645 } __packed; 1646 1647 struct htt_tx_fetch_confirm { 1648 u8 pad0; 1649 __le16 num_resp_ids; 1650 __le32 resp_ids[0]; 1651 } __packed; 1652 1653 enum htt_tx_mode_switch_mode { 1654 HTT_TX_MODE_SWITCH_PUSH = 0, 1655 HTT_TX_MODE_SWITCH_PUSH_PULL = 1, 1656 }; 1657 1658 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0) 1659 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe 1660 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1 1661 1662 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003 1663 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0 1664 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc 1665 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2 1666 1667 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff 1668 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0 1669 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000 1670 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12 1671 1672 struct htt_tx_mode_switch_record { 1673 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */ 1674 __le16 num_max_msdus; 1675 } __packed; 1676 1677 struct htt_tx_mode_switch_ind { 1678 u8 pad0; 1679 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */ 1680 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */ 1681 u8 pad1[2]; 1682 struct htt_tx_mode_switch_record records[0]; 1683 } __packed; 1684 1685 struct htt_channel_change { 1686 u8 pad[3]; 1687 __le32 freq; 1688 __le32 center_freq1; 1689 __le32 center_freq2; 1690 __le32 phymode; 1691 } __packed; 1692 1693 struct htt_per_peer_tx_stats_ind { 1694 __le32 succ_bytes; 1695 __le32 retry_bytes; 1696 __le32 failed_bytes; 1697 u8 ratecode; 1698 u8 flags; 1699 __le16 peer_id; 1700 __le16 succ_pkts; 1701 __le16 retry_pkts; 1702 __le16 failed_pkts; 1703 __le16 tx_duration; 1704 __le32 reserved1; 1705 __le32 reserved2; 1706 } __packed; 1707 1708 struct htt_peer_tx_stats { 1709 u8 num_ppdu; 1710 u8 ppdu_len; 1711 u8 version; 1712 u8 payload[0]; 1713 } __packed; 1714 1715 #define ATH10K_10_2_TX_STATS_OFFSET 136 1716 #define PEER_STATS_FOR_NO_OF_PPDUS 4 1717 1718 struct ath10k_10_2_peer_tx_stats { 1719 u8 ratecode[PEER_STATS_FOR_NO_OF_PPDUS]; 1720 u8 success_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1721 __le16 success_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1722 u8 retry_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1723 __le16 retry_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1724 u8 failed_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1725 __le16 failed_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1726 u8 flags[PEER_STATS_FOR_NO_OF_PPDUS]; 1727 __le32 tx_duration; 1728 u8 tx_ppdu_cnt; 1729 u8 peer_id; 1730 } __packed; 1731 1732 union htt_rx_pn_t { 1733 /* WEP: 24-bit PN */ 1734 u32 pn24; 1735 1736 /* TKIP or CCMP: 48-bit PN */ 1737 u64 pn48; 1738 1739 /* WAPI: 128-bit PN */ 1740 u64 pn128[2]; 1741 }; 1742 1743 struct htt_cmd { 1744 struct htt_cmd_hdr hdr; 1745 union { 1746 struct htt_ver_req ver_req; 1747 struct htt_mgmt_tx_desc mgmt_tx; 1748 struct htt_data_tx_desc data_tx; 1749 struct htt_rx_ring_setup_32 rx_setup_32; 1750 struct htt_rx_ring_setup_64 rx_setup_64; 1751 struct htt_stats_req stats_req; 1752 struct htt_oob_sync_req oob_sync_req; 1753 struct htt_aggr_conf aggr_conf; 1754 struct htt_aggr_conf_v2 aggr_conf_v2; 1755 struct htt_frag_desc_bank_cfg32 frag_desc_bank_cfg32; 1756 struct htt_frag_desc_bank_cfg64 frag_desc_bank_cfg64; 1757 struct htt_tx_fetch_resp tx_fetch_resp; 1758 }; 1759 } __packed; 1760 1761 struct htt_resp { 1762 struct htt_resp_hdr hdr; 1763 union { 1764 struct htt_ver_resp ver_resp; 1765 struct htt_mgmt_tx_completion mgmt_tx_completion; 1766 struct htt_data_tx_completion data_tx_completion; 1767 struct htt_rx_indication rx_ind; 1768 struct htt_rx_indication_hl rx_ind_hl; 1769 struct htt_rx_fragment_indication rx_frag_ind; 1770 struct htt_rx_peer_map peer_map; 1771 struct htt_rx_peer_unmap peer_unmap; 1772 struct htt_rx_flush rx_flush; 1773 struct htt_rx_addba rx_addba; 1774 struct htt_rx_delba rx_delba; 1775 struct htt_security_indication security_indication; 1776 struct htt_rc_update rc_update; 1777 struct htt_rx_test rx_test; 1778 struct htt_pktlog_msg pktlog_msg; 1779 struct htt_stats_conf stats_conf; 1780 struct htt_rx_pn_ind rx_pn_ind; 1781 struct htt_rx_offload_ind rx_offload_ind; 1782 struct htt_rx_in_ord_ind rx_in_ord_ind; 1783 struct htt_tx_fetch_ind tx_fetch_ind; 1784 struct htt_tx_fetch_confirm tx_fetch_confirm; 1785 struct htt_tx_mode_switch_ind tx_mode_switch_ind; 1786 struct htt_channel_change chan_change; 1787 struct htt_peer_tx_stats peer_tx_stats; 1788 }; 1789 } __packed; 1790 1791 /*** host side structures follow ***/ 1792 1793 struct htt_tx_done { 1794 u16 msdu_id; 1795 u16 status; 1796 u8 ack_rssi; 1797 }; 1798 1799 enum htt_tx_compl_state { 1800 HTT_TX_COMPL_STATE_NONE, 1801 HTT_TX_COMPL_STATE_ACK, 1802 HTT_TX_COMPL_STATE_NOACK, 1803 HTT_TX_COMPL_STATE_DISCARD, 1804 }; 1805 1806 struct htt_peer_map_event { 1807 u8 vdev_id; 1808 u16 peer_id; 1809 u8 addr[ETH_ALEN]; 1810 }; 1811 1812 struct htt_peer_unmap_event { 1813 u16 peer_id; 1814 }; 1815 1816 struct ath10k_htt_txbuf_32 { 1817 struct htt_data_tx_desc_frag frags[2]; 1818 struct ath10k_htc_hdr htc_hdr; 1819 struct htt_cmd_hdr cmd_hdr; 1820 struct htt_data_tx_desc cmd_tx; 1821 } __packed __aligned(4); 1822 1823 struct ath10k_htt_txbuf_64 { 1824 struct htt_data_tx_desc_frag frags[2]; 1825 struct ath10k_htc_hdr htc_hdr; 1826 struct htt_cmd_hdr cmd_hdr; 1827 struct htt_data_tx_desc_64 cmd_tx; 1828 } __packed __aligned(4); 1829 1830 struct ath10k_htt { 1831 struct ath10k *ar; 1832 enum ath10k_htc_ep_id eid; 1833 1834 u8 target_version_major; 1835 u8 target_version_minor; 1836 struct completion target_version_received; 1837 u8 max_num_amsdu; 1838 u8 max_num_ampdu; 1839 1840 const enum htt_t2h_msg_type *t2h_msg_types; 1841 u32 t2h_msg_types_max; 1842 1843 struct { 1844 /* 1845 * Ring of network buffer objects - This ring is 1846 * used exclusively by the host SW. This ring 1847 * mirrors the dev_addrs_ring that is shared 1848 * between the host SW and the MAC HW. The host SW 1849 * uses this netbufs ring to locate the network 1850 * buffer objects whose data buffers the HW has 1851 * filled. 1852 */ 1853 struct sk_buff **netbufs_ring; 1854 1855 /* This is used only with firmware supporting IN_ORD_IND. 1856 * 1857 * With Full Rx Reorder the HTT Rx Ring is more of a temporary 1858 * buffer ring from which buffer addresses are copied by the 1859 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND 1860 * pointing to specific (re-ordered) buffers. 1861 * 1862 * FIXME: With kernel generic hashing functions there's a lot 1863 * of hash collisions for sk_buffs. 1864 */ 1865 bool in_ord_rx; 1866 DECLARE_HASHTABLE(skb_table, 4); 1867 1868 /* 1869 * Ring of buffer addresses - 1870 * This ring holds the "physical" device address of the 1871 * rx buffers the host SW provides for the MAC HW to 1872 * fill. 1873 */ 1874 union { 1875 __le64 *paddrs_ring_64; 1876 __le32 *paddrs_ring_32; 1877 }; 1878 1879 /* 1880 * Base address of ring, as a "physical" device address 1881 * rather than a CPU address. 1882 */ 1883 dma_addr_t base_paddr; 1884 1885 /* how many elems in the ring (power of 2) */ 1886 int size; 1887 1888 /* size - 1 */ 1889 unsigned int size_mask; 1890 1891 /* how many rx buffers to keep in the ring */ 1892 int fill_level; 1893 1894 /* how many rx buffers (full+empty) are in the ring */ 1895 int fill_cnt; 1896 1897 /* 1898 * alloc_idx - where HTT SW has deposited empty buffers 1899 * This is allocated in consistent mem, so that the FW can 1900 * read this variable, and program the HW's FW_IDX reg with 1901 * the value of this shadow register. 1902 */ 1903 struct { 1904 __le32 *vaddr; 1905 dma_addr_t paddr; 1906 } alloc_idx; 1907 1908 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1909 struct { 1910 unsigned int msdu_payld; 1911 } sw_rd_idx; 1912 1913 /* 1914 * refill_retry_timer - timer triggered when the ring is 1915 * not refilled to the level expected 1916 */ 1917 struct timer_list refill_retry_timer; 1918 1919 /* Protects access to all rx ring buffer state variables */ 1920 spinlock_t lock; 1921 } rx_ring; 1922 1923 unsigned int prefetch_len; 1924 1925 /* Protects access to pending_tx, num_pending_tx */ 1926 spinlock_t tx_lock; 1927 int max_num_pending_tx; 1928 int num_pending_tx; 1929 int num_pending_mgmt_tx; 1930 struct idr pending_tx; 1931 wait_queue_head_t empty_tx_wq; 1932 1933 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */ 1934 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done); 1935 1936 /* set if host-fw communication goes haywire 1937 * used to avoid further failures 1938 */ 1939 bool rx_confused; 1940 atomic_t num_mpdus_ready; 1941 1942 /* This is used to group tx/rx completions separately and process them 1943 * in batches to reduce cache stalls 1944 */ 1945 struct sk_buff_head rx_msdus_q; 1946 struct sk_buff_head rx_in_ord_compl_q; 1947 struct sk_buff_head tx_fetch_ind_q; 1948 1949 /* rx_status template */ 1950 struct ieee80211_rx_status rx_status; 1951 1952 struct { 1953 dma_addr_t paddr; 1954 union { 1955 struct htt_msdu_ext_desc *vaddr_desc_32; 1956 struct htt_msdu_ext_desc_64 *vaddr_desc_64; 1957 }; 1958 size_t size; 1959 } frag_desc; 1960 1961 struct { 1962 dma_addr_t paddr; 1963 union { 1964 struct ath10k_htt_txbuf_32 *vaddr_txbuff_32; 1965 struct ath10k_htt_txbuf_64 *vaddr_txbuff_64; 1966 }; 1967 size_t size; 1968 } txbuf; 1969 1970 struct { 1971 bool enabled; 1972 struct htt_q_state *vaddr; 1973 dma_addr_t paddr; 1974 u16 num_push_allowed; 1975 u16 num_peers; 1976 u16 num_tids; 1977 enum htt_tx_mode_switch_mode mode; 1978 enum htt_q_depth_type type; 1979 } tx_q_state; 1980 1981 bool tx_mem_allocated; 1982 const struct ath10k_htt_tx_ops *tx_ops; 1983 const struct ath10k_htt_rx_ops *rx_ops; 1984 }; 1985 1986 struct ath10k_htt_tx_ops { 1987 int (*htt_send_rx_ring_cfg)(struct ath10k_htt *htt); 1988 int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt); 1989 int (*htt_alloc_frag_desc)(struct ath10k_htt *htt); 1990 void (*htt_free_frag_desc)(struct ath10k_htt *htt); 1991 int (*htt_tx)(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 1992 struct sk_buff *msdu); 1993 int (*htt_alloc_txbuff)(struct ath10k_htt *htt); 1994 void (*htt_free_txbuff)(struct ath10k_htt *htt); 1995 int (*htt_h2t_aggr_cfg_msg)(struct ath10k_htt *htt, 1996 u8 max_subfrms_ampdu, 1997 u8 max_subfrms_amsdu); 1998 }; 1999 2000 static inline int ath10k_htt_send_rx_ring_cfg(struct ath10k_htt *htt) 2001 { 2002 if (!htt->tx_ops->htt_send_rx_ring_cfg) 2003 return -EOPNOTSUPP; 2004 2005 return htt->tx_ops->htt_send_rx_ring_cfg(htt); 2006 } 2007 2008 static inline int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) 2009 { 2010 if (!htt->tx_ops->htt_send_frag_desc_bank_cfg) 2011 return -EOPNOTSUPP; 2012 2013 return htt->tx_ops->htt_send_frag_desc_bank_cfg(htt); 2014 } 2015 2016 static inline int ath10k_htt_alloc_frag_desc(struct ath10k_htt *htt) 2017 { 2018 if (!htt->tx_ops->htt_alloc_frag_desc) 2019 return -EOPNOTSUPP; 2020 2021 return htt->tx_ops->htt_alloc_frag_desc(htt); 2022 } 2023 2024 static inline void ath10k_htt_free_frag_desc(struct ath10k_htt *htt) 2025 { 2026 if (htt->tx_ops->htt_free_frag_desc) 2027 htt->tx_ops->htt_free_frag_desc(htt); 2028 } 2029 2030 static inline int ath10k_htt_tx(struct ath10k_htt *htt, 2031 enum ath10k_hw_txrx_mode txmode, 2032 struct sk_buff *msdu) 2033 { 2034 return htt->tx_ops->htt_tx(htt, txmode, msdu); 2035 } 2036 2037 static inline int ath10k_htt_alloc_txbuff(struct ath10k_htt *htt) 2038 { 2039 if (!htt->tx_ops->htt_alloc_txbuff) 2040 return -EOPNOTSUPP; 2041 2042 return htt->tx_ops->htt_alloc_txbuff(htt); 2043 } 2044 2045 static inline void ath10k_htt_free_txbuff(struct ath10k_htt *htt) 2046 { 2047 if (htt->tx_ops->htt_free_txbuff) 2048 htt->tx_ops->htt_free_txbuff(htt); 2049 } 2050 2051 struct ath10k_htt_rx_ops { 2052 size_t (*htt_get_rx_ring_size)(struct ath10k_htt *htt); 2053 void (*htt_config_paddrs_ring)(struct ath10k_htt *htt, void *vaddr); 2054 void (*htt_set_paddrs_ring)(struct ath10k_htt *htt, dma_addr_t paddr, 2055 int idx); 2056 void* (*htt_get_vaddr_ring)(struct ath10k_htt *htt); 2057 void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx); 2058 }; 2059 2060 static inline size_t ath10k_htt_get_rx_ring_size(struct ath10k_htt *htt) 2061 { 2062 if (!htt->rx_ops->htt_get_rx_ring_size) 2063 return 0; 2064 2065 return htt->rx_ops->htt_get_rx_ring_size(htt); 2066 } 2067 2068 static inline void ath10k_htt_config_paddrs_ring(struct ath10k_htt *htt, 2069 void *vaddr) 2070 { 2071 if (htt->rx_ops->htt_config_paddrs_ring) 2072 htt->rx_ops->htt_config_paddrs_ring(htt, vaddr); 2073 } 2074 2075 static inline void ath10k_htt_set_paddrs_ring(struct ath10k_htt *htt, 2076 dma_addr_t paddr, 2077 int idx) 2078 { 2079 if (htt->rx_ops->htt_set_paddrs_ring) 2080 htt->rx_ops->htt_set_paddrs_ring(htt, paddr, idx); 2081 } 2082 2083 static inline void *ath10k_htt_get_vaddr_ring(struct ath10k_htt *htt) 2084 { 2085 if (!htt->rx_ops->htt_get_vaddr_ring) 2086 return NULL; 2087 2088 return htt->rx_ops->htt_get_vaddr_ring(htt); 2089 } 2090 2091 static inline void ath10k_htt_reset_paddrs_ring(struct ath10k_htt *htt, int idx) 2092 { 2093 if (htt->rx_ops->htt_reset_paddrs_ring) 2094 htt->rx_ops->htt_reset_paddrs_ring(htt, idx); 2095 } 2096 2097 #define RX_HTT_HDR_STATUS_LEN 64 2098 2099 /* This structure layout is programmed via rx ring setup 2100 * so that FW knows how to transfer the rx descriptor to the host. 2101 * Buffers like this are placed on the rx ring. 2102 */ 2103 struct htt_rx_desc { 2104 union { 2105 /* This field is filled on the host using the msdu buffer 2106 * from htt_rx_indication 2107 */ 2108 struct fw_rx_desc_base fw_desc; 2109 u32 pad; 2110 } __packed; 2111 struct { 2112 struct rx_attention attention; 2113 struct rx_frag_info frag_info; 2114 struct rx_mpdu_start mpdu_start; 2115 struct rx_msdu_start msdu_start; 2116 struct rx_msdu_end msdu_end; 2117 struct rx_mpdu_end mpdu_end; 2118 struct rx_ppdu_start ppdu_start; 2119 struct rx_ppdu_end ppdu_end; 2120 } __packed; 2121 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 2122 u8 msdu_payload[0]; 2123 }; 2124 2125 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_MASK 0x00000fff 2126 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_LSB 0 2127 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_MASK 0x00001000 2128 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_LSB 12 2129 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_MASK 0x00002000 2130 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_LSB 13 2131 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_MASK 0x00008000 2132 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_LSB 15 2133 #define HTT_RX_DESC_HL_INFO_FRAGMENT_MASK 0x00010000 2134 #define HTT_RX_DESC_HL_INFO_FRAGMENT_LSB 16 2135 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_MASK 0x01fe0000 2136 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_LSB 17 2137 2138 struct htt_rx_desc_base_hl { 2139 __le32 info; /* HTT_RX_DESC_HL_INFO_ */ 2140 }; 2141 2142 struct htt_rx_chan_info { 2143 __le16 primary_chan_center_freq_mhz; 2144 __le16 contig_chan1_center_freq_mhz; 2145 __le16 contig_chan2_center_freq_mhz; 2146 u8 phy_mode; 2147 u8 reserved; 2148 } __packed; 2149 2150 #define HTT_RX_DESC_ALIGN 8 2151 2152 #define HTT_MAC_ADDR_LEN 6 2153 2154 /* 2155 * FIX THIS 2156 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 2157 * rounded up to a cache line size. 2158 */ 2159 #define HTT_RX_BUF_SIZE 1920 2160 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 2161 2162 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 2163 * aggregated traffic more nicely. 2164 */ 2165 #define ATH10K_HTT_MAX_NUM_REFILL 100 2166 2167 /* 2168 * DMA_MAP expects the buffer to be an integral number of cache lines. 2169 * Rather than checking the actual cache line size, this code makes a 2170 * conservative estimate of what the cache line size could be. 2171 */ 2172 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 2173 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 2174 2175 /* These values are default in most firmware revisions and apparently are a 2176 * sweet spot performance wise. 2177 */ 2178 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3 2179 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64 2180 2181 int ath10k_htt_connect(struct ath10k_htt *htt); 2182 int ath10k_htt_init(struct ath10k *ar); 2183 int ath10k_htt_setup(struct ath10k_htt *htt); 2184 2185 int ath10k_htt_tx_start(struct ath10k_htt *htt); 2186 void ath10k_htt_tx_stop(struct ath10k_htt *htt); 2187 void ath10k_htt_tx_destroy(struct ath10k_htt *htt); 2188 void ath10k_htt_tx_free(struct ath10k_htt *htt); 2189 2190 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 2191 int ath10k_htt_rx_ring_refill(struct ath10k *ar); 2192 void ath10k_htt_rx_free(struct ath10k_htt *htt); 2193 2194 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 2195 void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 2196 bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 2197 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 2198 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 2199 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 2200 u8 max_subfrms_ampdu, 2201 u8 max_subfrms_amsdu); 2202 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb); 2203 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 2204 __le32 token, 2205 __le16 fetch_seq_num, 2206 struct htt_tx_fetch_record *records, 2207 size_t num_records); 2208 2209 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 2210 struct ieee80211_txq *txq); 2211 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 2212 struct ieee80211_txq *txq); 2213 void ath10k_htt_tx_txq_sync(struct ath10k *ar); 2214 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 2215 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt); 2216 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt); 2217 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 2218 bool is_presp); 2219 2220 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); 2221 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 2222 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu); 2223 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar, 2224 struct sk_buff *skb); 2225 int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget); 2226 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt); 2227 void ath10k_htt_set_rx_ops(struct ath10k_htt *htt); 2228 #endif 2229