1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _HTT_H_ 9 #define _HTT_H_ 10 11 #include <linux/bug.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmapool.h> 14 #include <linux/hashtable.h> 15 #include <linux/kfifo.h> 16 #include <net/mac80211.h> 17 18 #include "htc.h" 19 #include "hw.h" 20 #include "rx_desc.h" 21 22 enum htt_dbg_stats_type { 23 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 24 HTT_DBG_STATS_RX_REORDER = 1 << 1, 25 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 26 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 27 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 28 /* bits 5-23 currently reserved */ 29 30 HTT_DBG_NUM_STATS /* keep this last */ 31 }; 32 33 enum htt_h2t_msg_type { /* host-to-target */ 34 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 35 HTT_H2T_MSG_TYPE_TX_FRM = 1, 36 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 37 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 38 HTT_H2T_MSG_TYPE_SYNC = 4, 39 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 40 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 41 42 /* This command is used for sending management frames in HTT < 3.0. 43 * HTT >= 3.0 uses TX_FRM for everything. 44 */ 45 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 46 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11, 47 48 HTT_H2T_NUM_MSGS /* keep this last */ 49 }; 50 51 struct htt_cmd_hdr { 52 u8 msg_type; 53 } __packed; 54 55 struct htt_ver_req { 56 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 57 } __packed; 58 59 /* 60 * HTT tx MSDU descriptor 61 * 62 * The HTT tx MSDU descriptor is created by the host HTT SW for each 63 * tx MSDU. The HTT tx MSDU descriptor contains the information that 64 * the target firmware needs for the FW's tx processing, particularly 65 * for creating the HW msdu descriptor. 66 * The same HTT tx descriptor is used for HL and LL systems, though 67 * a few fields within the tx descriptor are used only by LL or 68 * only by HL. 69 * The HTT tx descriptor is defined in two manners: by a struct with 70 * bitfields, and by a series of [dword offset, bit mask, bit shift] 71 * definitions. 72 * The target should use the struct def, for simplicitly and clarity, 73 * but the host shall use the bit-mast + bit-shift defs, to be endian- 74 * neutral. Specifically, the host shall use the get/set macros built 75 * around the mask + shift defs. 76 */ 77 struct htt_data_tx_desc_frag { 78 union { 79 struct double_word_addr { 80 __le32 paddr; 81 __le32 len; 82 } __packed dword_addr; 83 struct triple_word_addr { 84 __le32 paddr_lo; 85 __le16 paddr_hi; 86 __le16 len_16; 87 } __packed tword_addr; 88 } __packed; 89 } __packed; 90 91 struct htt_msdu_ext_desc { 92 __le32 tso_flag[3]; 93 __le16 ip_identification; 94 u8 flags; 95 u8 reserved; 96 struct htt_data_tx_desc_frag frags[6]; 97 }; 98 99 struct htt_msdu_ext_desc_64 { 100 __le32 tso_flag[5]; 101 __le16 ip_identification; 102 u8 flags; 103 u8 reserved; 104 struct htt_data_tx_desc_frag frags[6]; 105 }; 106 107 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0) 108 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1) 109 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2) 110 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3) 111 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4) 112 113 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \ 114 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \ 115 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \ 116 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \ 117 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE) 118 119 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16) 120 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17) 121 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18) 122 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19) 123 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20) 124 #define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21) 125 126 #define HTT_MSDU_CHECKSUM_ENABLE_64 (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 \ 127 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 \ 128 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 \ 129 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 \ 130 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64) 131 132 enum htt_data_tx_desc_flags0 { 133 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 134 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 135 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 136 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 137 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 138 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 139 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 140 }; 141 142 enum htt_data_tx_desc_flags1 { 143 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 144 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 145 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 146 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 147 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 148 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 149 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 150 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 151 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 152 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 153 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 154 }; 155 156 enum htt_data_tx_ext_tid { 157 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 158 HTT_DATA_TX_EXT_TID_MGMT = 17, 159 HTT_DATA_TX_EXT_TID_INVALID = 31 160 }; 161 162 #define HTT_INVALID_PEERID 0xFFFF 163 164 /* 165 * htt_data_tx_desc - used for data tx path 166 * 167 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 168 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 169 * for special kinds of tids 170 * postponed: only for HL hosts. indicates if this is a resend 171 * (HL hosts manage queues on the host ) 172 * more_in_batch: only for HL hosts. indicates if more packets are 173 * pending. this allows target to wait and aggregate 174 * freq: 0 means home channel of given vdev. intended for offchannel 175 */ 176 struct htt_data_tx_desc { 177 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 178 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 179 __le16 len; 180 __le16 id; 181 __le32 frags_paddr; 182 union { 183 __le32 peerid; 184 struct { 185 __le16 peerid; 186 __le16 freq; 187 } __packed offchan_tx; 188 } __packed; 189 u8 prefetch[0]; /* start of frame, for FW classification engine */ 190 } __packed; 191 192 struct htt_data_tx_desc_64 { 193 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 194 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 195 __le16 len; 196 __le16 id; 197 __le64 frags_paddr; 198 union { 199 __le32 peerid; 200 struct { 201 __le16 peerid; 202 __le16 freq; 203 } __packed offchan_tx; 204 } __packed; 205 u8 prefetch[0]; /* start of frame, for FW classification engine */ 206 } __packed; 207 208 enum htt_rx_ring_flags { 209 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 210 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 211 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 212 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 213 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 214 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 215 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 216 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 217 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 218 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 219 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 220 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 221 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 222 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 223 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 224 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 225 }; 226 227 #define HTT_RX_RING_SIZE_MIN 128 228 #define HTT_RX_RING_SIZE_MAX 2048 229 #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX 230 #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1) 231 #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1) 232 233 struct htt_rx_ring_setup_ring32 { 234 __le32 fw_idx_shadow_reg_paddr; 235 __le32 rx_ring_base_paddr; 236 __le16 rx_ring_len; /* in 4-byte words */ 237 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 238 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 239 __le16 fw_idx_init_val; 240 241 /* the following offsets are in 4-byte units */ 242 __le16 mac80211_hdr_offset; 243 __le16 msdu_payload_offset; 244 __le16 ppdu_start_offset; 245 __le16 ppdu_end_offset; 246 __le16 mpdu_start_offset; 247 __le16 mpdu_end_offset; 248 __le16 msdu_start_offset; 249 __le16 msdu_end_offset; 250 __le16 rx_attention_offset; 251 __le16 frag_info_offset; 252 } __packed; 253 254 struct htt_rx_ring_setup_ring64 { 255 __le64 fw_idx_shadow_reg_paddr; 256 __le64 rx_ring_base_paddr; 257 __le16 rx_ring_len; /* in 4-byte words */ 258 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 259 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 260 __le16 fw_idx_init_val; 261 262 /* the following offsets are in 4-byte units */ 263 __le16 mac80211_hdr_offset; 264 __le16 msdu_payload_offset; 265 __le16 ppdu_start_offset; 266 __le16 ppdu_end_offset; 267 __le16 mpdu_start_offset; 268 __le16 mpdu_end_offset; 269 __le16 msdu_start_offset; 270 __le16 msdu_end_offset; 271 __le16 rx_attention_offset; 272 __le16 frag_info_offset; 273 } __packed; 274 275 struct htt_rx_ring_setup_hdr { 276 u8 num_rings; /* supported values: 1, 2 */ 277 __le16 rsvd0; 278 } __packed; 279 280 struct htt_rx_ring_setup_32 { 281 struct htt_rx_ring_setup_hdr hdr; 282 struct htt_rx_ring_setup_ring32 rings[0]; 283 } __packed; 284 285 struct htt_rx_ring_setup_64 { 286 struct htt_rx_ring_setup_hdr hdr; 287 struct htt_rx_ring_setup_ring64 rings[0]; 288 } __packed; 289 290 /* 291 * htt_stats_req - request target to send specified statistics 292 * 293 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 294 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 295 * so make sure its little-endian. 296 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 297 * so make sure its little-endian. 298 * @cfg_val: stat_type specific configuration 299 * @stat_type: see %htt_dbg_stats_type 300 * @cookie_lsb: used for confirmation message from target->host 301 * @cookie_msb: ditto as %cookie 302 */ 303 struct htt_stats_req { 304 u8 upload_types[3]; 305 u8 rsvd0; 306 u8 reset_types[3]; 307 struct { 308 u8 mpdu_bytes; 309 u8 mpdu_num_msdus; 310 u8 msdu_bytes; 311 } __packed; 312 u8 stat_type; 313 __le32 cookie_lsb; 314 __le32 cookie_msb; 315 } __packed; 316 317 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 318 #define HTT_STATS_BIT_MASK GENMASK(16, 0) 319 320 /* 321 * htt_oob_sync_req - request out-of-band sync 322 * 323 * The HTT SYNC tells the target to suspend processing of subsequent 324 * HTT host-to-target messages until some other target agent locally 325 * informs the target HTT FW that the current sync counter is equal to 326 * or greater than (in a modulo sense) the sync counter specified in 327 * the SYNC message. 328 * 329 * This allows other host-target components to synchronize their operation 330 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 331 * security key has been downloaded to and activated by the target. 332 * In the absence of any explicit synchronization counter value 333 * specification, the target HTT FW will use zero as the default current 334 * sync value. 335 * 336 * The HTT target FW will suspend its host->target message processing as long 337 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 338 */ 339 struct htt_oob_sync_req { 340 u8 sync_count; 341 __le16 rsvd0; 342 } __packed; 343 344 struct htt_aggr_conf { 345 u8 max_num_ampdu_subframes; 346 /* amsdu_subframes is limited by 0x1F mask */ 347 u8 max_num_amsdu_subframes; 348 } __packed; 349 350 struct htt_aggr_conf_v2 { 351 u8 max_num_ampdu_subframes; 352 /* amsdu_subframes is limited by 0x1F mask */ 353 u8 max_num_amsdu_subframes; 354 u8 reserved; 355 } __packed; 356 357 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 358 struct htt_mgmt_tx_desc_qca99x0 { 359 __le32 rate; 360 } __packed; 361 362 struct htt_mgmt_tx_desc { 363 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 364 __le32 msdu_paddr; 365 __le32 desc_id; 366 __le32 len; 367 __le32 vdev_id; 368 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 369 union { 370 struct htt_mgmt_tx_desc_qca99x0 qca99x0; 371 } __packed; 372 } __packed; 373 374 enum htt_mgmt_tx_status { 375 HTT_MGMT_TX_STATUS_OK = 0, 376 HTT_MGMT_TX_STATUS_RETRY = 1, 377 HTT_MGMT_TX_STATUS_DROP = 2 378 }; 379 380 /*=== target -> host messages ===============================================*/ 381 382 enum htt_main_t2h_msg_type { 383 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0, 384 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1, 385 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2, 386 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3, 387 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 388 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5, 389 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6, 390 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 391 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8, 392 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9, 393 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 394 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb, 395 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 396 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 397 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 398 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10, 399 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 400 HTT_MAIN_T2H_MSG_TYPE_TEST, 401 /* keep this last */ 402 HTT_MAIN_T2H_NUM_MSGS 403 }; 404 405 enum htt_10x_t2h_msg_type { 406 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0, 407 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1, 408 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2, 409 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3, 410 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 411 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5, 412 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6, 413 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 414 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8, 415 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9, 416 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 417 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb, 418 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 419 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 420 HTT_10X_T2H_MSG_TYPE_TEST = 0xe, 421 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 422 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11, 423 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12, 424 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13, 425 /* keep this last */ 426 HTT_10X_T2H_NUM_MSGS 427 }; 428 429 enum htt_tlv_t2h_msg_type { 430 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0, 431 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1, 432 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2, 433 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3, 434 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 435 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5, 436 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6, 437 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 438 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8, 439 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9, 440 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 441 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb, 442 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */ 443 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 444 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 445 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 446 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10, 447 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 448 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 449 /* 0x13 reservd */ 450 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 451 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 452 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 453 HTT_TLV_T2H_MSG_TYPE_TEST, 454 /* keep this last */ 455 HTT_TLV_T2H_NUM_MSGS 456 }; 457 458 enum htt_10_4_t2h_msg_type { 459 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0, 460 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1, 461 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2, 462 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3, 463 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 464 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5, 465 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6, 466 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 467 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8, 468 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9, 469 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 470 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb, 471 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 472 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 473 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 474 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 475 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10, 476 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11, 477 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12, 478 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13, 479 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14, 480 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15, 481 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16, 482 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17, 483 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18, 484 /* 0x19 to 0x2f are reserved */ 485 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30, 486 HTT_10_4_T2H_MSG_TYPE_PEER_STATS = 0x31, 487 /* keep this last */ 488 HTT_10_4_T2H_NUM_MSGS 489 }; 490 491 enum htt_t2h_msg_type { 492 HTT_T2H_MSG_TYPE_VERSION_CONF, 493 HTT_T2H_MSG_TYPE_RX_IND, 494 HTT_T2H_MSG_TYPE_RX_FLUSH, 495 HTT_T2H_MSG_TYPE_PEER_MAP, 496 HTT_T2H_MSG_TYPE_PEER_UNMAP, 497 HTT_T2H_MSG_TYPE_RX_ADDBA, 498 HTT_T2H_MSG_TYPE_RX_DELBA, 499 HTT_T2H_MSG_TYPE_TX_COMPL_IND, 500 HTT_T2H_MSG_TYPE_PKTLOG, 501 HTT_T2H_MSG_TYPE_STATS_CONF, 502 HTT_T2H_MSG_TYPE_RX_FRAG_IND, 503 HTT_T2H_MSG_TYPE_SEC_IND, 504 HTT_T2H_MSG_TYPE_RC_UPDATE_IND, 505 HTT_T2H_MSG_TYPE_TX_INSPECT_IND, 506 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION, 507 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, 508 HTT_T2H_MSG_TYPE_RX_PN_IND, 509 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND, 510 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND, 511 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE, 512 HTT_T2H_MSG_TYPE_CHAN_CHANGE, 513 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR, 514 HTT_T2H_MSG_TYPE_AGGR_CONF, 515 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, 516 HTT_T2H_MSG_TYPE_TEST, 517 HTT_T2H_MSG_TYPE_EN_STATS, 518 HTT_T2H_MSG_TYPE_TX_FETCH_IND, 519 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM, 520 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND, 521 HTT_T2H_MSG_TYPE_PEER_STATS, 522 /* keep this last */ 523 HTT_T2H_NUM_MSGS 524 }; 525 526 /* 527 * htt_resp_hdr - header for target-to-host messages 528 * 529 * msg_type: see htt_t2h_msg_type 530 */ 531 struct htt_resp_hdr { 532 u8 msg_type; 533 } __packed; 534 535 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 536 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 537 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 538 539 /* htt_ver_resp - response sent for htt_ver_req */ 540 struct htt_ver_resp { 541 u8 minor; 542 u8 major; 543 u8 rsvd0; 544 } __packed; 545 546 #define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI BIT(0) 547 548 #define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK GENMASK(7, 0) 549 550 struct htt_mgmt_tx_completion { 551 u8 rsvd0; 552 u8 rsvd1; 553 u8 flags; 554 __le32 desc_id; 555 __le32 status; 556 __le32 ppdu_id; 557 __le32 info; 558 } __packed; 559 560 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F) 561 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 562 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5) 563 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6) 564 #define HTT_RX_INDICATION_INFO0_PPDU_DURATION BIT(7) 565 566 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 567 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 568 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 569 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 570 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 571 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 572 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 573 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 574 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 575 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 576 577 #define HTT_TX_CMPL_FLAG_DATA_RSSI BIT(0) 578 #define HTT_TX_CMPL_FLAG_PPID_PRESENT BIT(1) 579 #define HTT_TX_CMPL_FLAG_PA_PRESENT BIT(2) 580 #define HTT_TX_CMPL_FLAG_PPDU_DURATION_PRESENT BIT(3) 581 582 #define HTT_TX_DATA_RSSI_ENABLE_WCN3990 BIT(3) 583 #define HTT_TX_DATA_APPEND_RETRIES BIT(0) 584 #define HTT_TX_DATA_APPEND_TIMESTAMP BIT(1) 585 586 struct htt_rx_indication_hdr { 587 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 588 __le16 peer_id; 589 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 590 } __packed; 591 592 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 593 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 594 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 595 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 596 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 597 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 598 599 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 600 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 601 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 602 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 603 604 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 605 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 606 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 607 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 608 609 enum htt_rx_legacy_rate { 610 HTT_RX_OFDM_48 = 0, 611 HTT_RX_OFDM_24 = 1, 612 HTT_RX_OFDM_12, 613 HTT_RX_OFDM_6, 614 HTT_RX_OFDM_54, 615 HTT_RX_OFDM_36, 616 HTT_RX_OFDM_18, 617 HTT_RX_OFDM_9, 618 619 /* long preamble */ 620 HTT_RX_CCK_11_LP = 0, 621 HTT_RX_CCK_5_5_LP = 1, 622 HTT_RX_CCK_2_LP, 623 HTT_RX_CCK_1_LP, 624 /* short preamble */ 625 HTT_RX_CCK_11_SP, 626 HTT_RX_CCK_5_5_SP, 627 HTT_RX_CCK_2_SP 628 }; 629 630 enum htt_rx_legacy_rate_type { 631 HTT_RX_LEGACY_RATE_OFDM = 0, 632 HTT_RX_LEGACY_RATE_CCK 633 }; 634 635 enum htt_rx_preamble_type { 636 HTT_RX_LEGACY = 0x4, 637 HTT_RX_HT = 0x8, 638 HTT_RX_HT_WITH_TXBF = 0x9, 639 HTT_RX_VHT = 0xC, 640 HTT_RX_VHT_WITH_TXBF = 0xD, 641 }; 642 643 /* 644 * Fields: phy_err_valid, phy_err_code, tsf, 645 * usec_timestamp, sub_usec_timestamp 646 * ..are valid only if end_valid == 1. 647 * 648 * Fields: rssi_chains, legacy_rate_type, 649 * legacy_rate_cck, preamble_type, service, 650 * vht_sig_* 651 * ..are valid only if start_valid == 1; 652 */ 653 struct htt_rx_indication_ppdu { 654 u8 combined_rssi; 655 u8 sub_usec_timestamp; 656 u8 phy_err_code; 657 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 658 struct { 659 u8 pri20_db; 660 u8 ext20_db; 661 u8 ext40_db; 662 u8 ext80_db; 663 } __packed rssi_chains[4]; 664 __le32 tsf; 665 __le32 usec_timestamp; 666 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 667 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 668 } __packed; 669 670 enum htt_rx_mpdu_status { 671 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 672 HTT_RX_IND_MPDU_STATUS_OK, 673 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 674 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 675 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 676 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 677 /* only accept EAPOL frames */ 678 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 679 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 680 /* Non-data in promiscuous mode */ 681 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 682 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 683 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 684 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 685 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 686 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 687 688 /* 689 * MISC: discard for unspecified reasons. 690 * Leave this enum value last. 691 */ 692 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 693 }; 694 695 struct htt_rx_indication_mpdu_range { 696 u8 mpdu_count; 697 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 698 u8 pad0; 699 u8 pad1; 700 } __packed; 701 702 struct htt_rx_indication_prefix { 703 __le16 fw_rx_desc_bytes; 704 u8 pad0; 705 u8 pad1; 706 }; 707 708 struct htt_rx_indication { 709 struct htt_rx_indication_hdr hdr; 710 struct htt_rx_indication_ppdu ppdu; 711 struct htt_rx_indication_prefix prefix; 712 713 /* 714 * the following fields are both dynamically sized, so 715 * take care addressing them 716 */ 717 718 /* the size of this is %fw_rx_desc_bytes */ 719 struct fw_rx_desc_base fw_desc; 720 721 /* 722 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 723 * and has %num_mpdu_ranges elements. 724 */ 725 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 726 } __packed; 727 728 /* High latency version of the RX indication */ 729 struct htt_rx_indication_hl { 730 struct htt_rx_indication_hdr hdr; 731 struct htt_rx_indication_ppdu ppdu; 732 struct htt_rx_indication_prefix prefix; 733 struct fw_rx_desc_hl fw_desc; 734 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 735 } __packed; 736 737 struct htt_hl_rx_desc { 738 __le32 info; 739 __le32 pn_31_0; 740 union { 741 struct { 742 __le16 pn_47_32; 743 __le16 pn_63_48; 744 } pn16; 745 __le32 pn_63_32; 746 } u0; 747 __le32 pn_95_64; 748 __le32 pn_127_96; 749 } __packed; 750 751 static inline struct htt_rx_indication_mpdu_range * 752 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 753 { 754 void *ptr = rx_ind; 755 756 ptr += sizeof(rx_ind->hdr) 757 + sizeof(rx_ind->ppdu) 758 + sizeof(rx_ind->prefix) 759 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 760 return ptr; 761 } 762 763 static inline struct htt_rx_indication_mpdu_range * 764 htt_rx_ind_get_mpdu_ranges_hl(struct htt_rx_indication_hl *rx_ind) 765 { 766 void *ptr = rx_ind; 767 768 ptr += sizeof(rx_ind->hdr) 769 + sizeof(rx_ind->ppdu) 770 + sizeof(rx_ind->prefix) 771 + sizeof(rx_ind->fw_desc); 772 return ptr; 773 } 774 775 enum htt_rx_flush_mpdu_status { 776 HTT_RX_FLUSH_MPDU_DISCARD = 0, 777 HTT_RX_FLUSH_MPDU_REORDER = 1, 778 }; 779 780 /* 781 * htt_rx_flush - discard or reorder given range of mpdus 782 * 783 * Note: host must check if all sequence numbers between 784 * [seq_num_start, seq_num_end-1] are valid. 785 */ 786 struct htt_rx_flush { 787 __le16 peer_id; 788 u8 tid; 789 u8 rsvd0; 790 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 791 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 792 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 793 }; 794 795 struct htt_rx_peer_map { 796 u8 vdev_id; 797 __le16 peer_id; 798 u8 addr[6]; 799 u8 rsvd0; 800 u8 rsvd1; 801 } __packed; 802 803 struct htt_rx_peer_unmap { 804 u8 rsvd0; 805 __le16 peer_id; 806 } __packed; 807 808 enum htt_txrx_sec_cast_type { 809 HTT_TXRX_SEC_MCAST = 0, 810 HTT_TXRX_SEC_UCAST 811 }; 812 813 enum htt_rx_pn_check_type { 814 HTT_RX_NON_PN_CHECK = 0, 815 HTT_RX_PN_CHECK 816 }; 817 818 enum htt_rx_tkip_demic_type { 819 HTT_RX_NON_TKIP_MIC = 0, 820 HTT_RX_TKIP_MIC 821 }; 822 823 enum htt_security_types { 824 HTT_SECURITY_NONE, 825 HTT_SECURITY_WEP128, 826 HTT_SECURITY_WEP104, 827 HTT_SECURITY_WEP40, 828 HTT_SECURITY_TKIP, 829 HTT_SECURITY_TKIP_NOMIC, 830 HTT_SECURITY_AES_CCMP, 831 HTT_SECURITY_WAPI, 832 833 HTT_NUM_SECURITY_TYPES /* keep this last! */ 834 }; 835 836 #define ATH10K_HTT_TXRX_PEER_SECURITY_MAX 2 837 #define ATH10K_TXRX_NUM_EXT_TIDS 19 838 839 enum htt_security_flags { 840 #define HTT_SECURITY_TYPE_MASK 0x7F 841 #define HTT_SECURITY_TYPE_LSB 0 842 HTT_SECURITY_IS_UNICAST = 1 << 7 843 }; 844 845 struct htt_security_indication { 846 union { 847 /* dont use bitfields; undefined behaviour */ 848 u8 flags; /* %htt_security_flags */ 849 struct { 850 u8 security_type:7, /* %htt_security_types */ 851 is_unicast:1; 852 } __packed; 853 } __packed; 854 __le16 peer_id; 855 u8 michael_key[8]; 856 u8 wapi_rsc[16]; 857 } __packed; 858 859 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 860 #define HTT_RX_BA_INFO0_TID_LSB 0 861 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 862 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 863 864 struct htt_rx_addba { 865 u8 window_size; 866 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 867 } __packed; 868 869 struct htt_rx_delba { 870 u8 rsvd0; 871 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 872 } __packed; 873 874 enum htt_data_tx_status { 875 HTT_DATA_TX_STATUS_OK = 0, 876 HTT_DATA_TX_STATUS_DISCARD = 1, 877 HTT_DATA_TX_STATUS_NO_ACK = 2, 878 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 879 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 880 }; 881 882 enum htt_data_tx_flags { 883 #define HTT_DATA_TX_STATUS_MASK 0x07 884 #define HTT_DATA_TX_STATUS_LSB 0 885 #define HTT_DATA_TX_TID_MASK 0x78 886 #define HTT_DATA_TX_TID_LSB 3 887 HTT_DATA_TX_TID_INVALID = 1 << 7 888 }; 889 890 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 891 892 struct htt_append_retries { 893 __le16 msdu_id; 894 u8 tx_retries; 895 u8 flag; 896 } __packed; 897 898 struct htt_data_tx_completion_ext { 899 struct htt_append_retries a_retries; 900 __le32 t_stamp; 901 __le16 msdus_rssi[0]; 902 } __packed; 903 904 /** 905 * @brief target -> host TX completion indication message definition 906 * 907 * @details 908 * The following diagram shows the format of the TX completion indication sent 909 * from the target to the host 910 * 911 * |31 28|27|26|25|24|23 16| 15 |14 11|10 8|7 0| 912 * |-------------------------------------------------------------| 913 * header: |rsvd |A2|TP|A1|A0| num | t_i| tid |status| msg_type | 914 * |-------------------------------------------------------------| 915 * payload: | MSDU1 ID | MSDU0 ID | 916 * |-------------------------------------------------------------| 917 * : MSDU3 ID : MSDU2 ID : 918 * |-------------------------------------------------------------| 919 * | struct htt_tx_compl_ind_append_retries | 920 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 921 * | struct htt_tx_compl_ind_append_tx_tstamp | 922 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 923 * | MSDU1 ACK RSSI | MSDU0 ACK RSSI | 924 * |-------------------------------------------------------------| 925 * : MSDU3 ACK RSSI : MSDU2 ACK RSSI : 926 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 927 * -msg_type 928 * Bits 7:0 929 * Purpose: identifies this as HTT TX completion indication 930 * -status 931 * Bits 10:8 932 * Purpose: the TX completion status of payload fragmentations descriptors 933 * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD 934 * -tid 935 * Bits 14:11 936 * Purpose: the tid associated with those fragmentation descriptors. It is 937 * valid or not, depending on the tid_invalid bit. 938 * Value: 0 to 15 939 * -tid_invalid 940 * Bits 15:15 941 * Purpose: this bit indicates whether the tid field is valid or not 942 * Value: 0 indicates valid, 1 indicates invalid 943 * -num 944 * Bits 23:16 945 * Purpose: the number of payload in this indication 946 * Value: 1 to 255 947 * -A0 = append 948 * Bits 24:24 949 * Purpose: append the struct htt_tx_compl_ind_append_retries which contains 950 * the number of tx retries for one MSDU at the end of this message 951 * Value: 0 indicates no appending, 1 indicates appending 952 * -A1 = append1 953 * Bits 25:25 954 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tstamp which 955 * contains the timestamp info for each TX msdu id in payload. 956 * Value: 0 indicates no appending, 1 indicates appending 957 * -TP = MSDU tx power presence 958 * Bits 26:26 959 * Purpose: Indicate whether the TX_COMPL_IND includes a tx power report 960 * for each MSDU referenced by the TX_COMPL_IND message. 961 * The order of the per-MSDU tx power reports matches the order 962 * of the MSDU IDs. 963 * Value: 0 indicates not appending, 1 indicates appending 964 * -A2 = append2 965 * Bits 27:27 966 * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in 967 * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report 968 * matches the order of the MSDU IDs. 969 * The ACK RSSI values are valid when status is COMPLETE_OK (and 970 * this append2 bit is set). 971 * Value: 0 indicates not appending, 1 indicates appending 972 */ 973 974 struct htt_data_tx_completion { 975 union { 976 u8 flags; 977 struct { 978 u8 status:3, 979 tid:4, 980 tid_invalid:1; 981 } __packed; 982 } __packed; 983 u8 num_msdus; 984 u8 flags2; /* HTT_TX_CMPL_FLAG_DATA_RSSI */ 985 __le16 msdus[0]; /* variable length based on %num_msdus */ 986 } __packed; 987 988 #define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK GENMASK(15, 0) 989 #define HTT_TX_PPDU_DUR_INFO0_TID_MASK GENMASK(20, 16) 990 991 struct htt_data_tx_ppdu_dur { 992 __le32 info0; /* HTT_TX_PPDU_DUR_INFO0_ */ 993 __le32 tx_duration; /* in usecs */ 994 } __packed; 995 996 #define HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK GENMASK(7, 0) 997 998 struct htt_data_tx_compl_ppdu_dur { 999 __le32 info0; /* HTT_TX_COMPL_PPDU_DUR_INFO0_ */ 1000 struct htt_data_tx_ppdu_dur ppdu_dur[0]; 1001 } __packed; 1002 1003 struct htt_tx_compl_ind_base { 1004 u32 hdr; 1005 u16 payload[1/*or more*/]; 1006 } __packed; 1007 1008 struct htt_rc_tx_done_params { 1009 u32 rate_code; 1010 u32 rate_code_flags; 1011 u32 flags; 1012 u32 num_enqued; /* 1 for non-AMPDU */ 1013 u32 num_retries; 1014 u32 num_failed; /* for AMPDU */ 1015 u32 ack_rssi; 1016 u32 time_stamp; 1017 u32 is_probe; 1018 }; 1019 1020 struct htt_rc_update { 1021 u8 vdev_id; 1022 __le16 peer_id; 1023 u8 addr[6]; 1024 u8 num_elems; 1025 u8 rsvd0; 1026 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 1027 } __packed; 1028 1029 /* see htt_rx_indication for similar fields and descriptions */ 1030 struct htt_rx_fragment_indication { 1031 union { 1032 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 1033 struct { 1034 u8 ext_tid:5, 1035 flush_valid:1; 1036 } __packed; 1037 } __packed; 1038 __le16 peer_id; 1039 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 1040 __le16 fw_rx_desc_bytes; 1041 __le16 rsvd0; 1042 1043 u8 fw_msdu_rx_desc[0]; 1044 } __packed; 1045 1046 #define ATH10K_IEEE80211_EXTIV BIT(5) 1047 #define ATH10K_IEEE80211_TKIP_MICLEN 8 /* trailing MIC */ 1048 1049 #define HTT_RX_FRAG_IND_INFO0_HEADER_LEN 16 1050 1051 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 1052 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 1053 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 1054 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 1055 1056 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 1057 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 1058 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 1059 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 1060 1061 struct htt_rx_pn_ind { 1062 __le16 peer_id; 1063 u8 tid; 1064 u8 seqno_start; 1065 u8 seqno_end; 1066 u8 pn_ie_count; 1067 u8 reserved; 1068 u8 pn_ies[0]; 1069 } __packed; 1070 1071 struct htt_rx_offload_msdu { 1072 __le16 msdu_len; 1073 __le16 peer_id; 1074 u8 vdev_id; 1075 u8 tid; 1076 u8 fw_desc; 1077 u8 payload[0]; 1078 } __packed; 1079 1080 struct htt_rx_offload_ind { 1081 u8 reserved; 1082 __le16 msdu_count; 1083 } __packed; 1084 1085 struct htt_rx_in_ord_msdu_desc { 1086 __le32 msdu_paddr; 1087 __le16 msdu_len; 1088 u8 fw_desc; 1089 u8 reserved; 1090 } __packed; 1091 1092 struct htt_rx_in_ord_msdu_desc_ext { 1093 __le64 msdu_paddr; 1094 __le16 msdu_len; 1095 u8 fw_desc; 1096 u8 reserved; 1097 } __packed; 1098 1099 struct htt_rx_in_ord_ind { 1100 u8 info; 1101 __le16 peer_id; 1102 u8 vdev_id; 1103 u8 reserved; 1104 __le16 msdu_count; 1105 union { 1106 struct htt_rx_in_ord_msdu_desc msdu_descs32[0]; 1107 struct htt_rx_in_ord_msdu_desc_ext msdu_descs64[0]; 1108 } __packed; 1109 } __packed; 1110 1111 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f 1112 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 1113 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020 1114 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 1115 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040 1116 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 1117 1118 /* 1119 * target -> host test message definition 1120 * 1121 * The following field definitions describe the format of the test 1122 * message sent from the target to the host. 1123 * The message consists of a 4-octet header, followed by a variable 1124 * number of 32-bit integer values, followed by a variable number 1125 * of 8-bit character values. 1126 * 1127 * |31 16|15 8|7 0| 1128 * |-----------------------------------------------------------| 1129 * | num chars | num ints | msg type | 1130 * |-----------------------------------------------------------| 1131 * | int 0 | 1132 * |-----------------------------------------------------------| 1133 * | int 1 | 1134 * |-----------------------------------------------------------| 1135 * | ... | 1136 * |-----------------------------------------------------------| 1137 * | char 3 | char 2 | char 1 | char 0 | 1138 * |-----------------------------------------------------------| 1139 * | | | ... | char 4 | 1140 * |-----------------------------------------------------------| 1141 * - MSG_TYPE 1142 * Bits 7:0 1143 * Purpose: identifies this as a test message 1144 * Value: HTT_MSG_TYPE_TEST 1145 * - NUM_INTS 1146 * Bits 15:8 1147 * Purpose: indicate how many 32-bit integers follow the message header 1148 * - NUM_CHARS 1149 * Bits 31:16 1150 * Purpose: indicate how many 8-bit characters follow the series of integers 1151 */ 1152 struct htt_rx_test { 1153 u8 num_ints; 1154 __le16 num_chars; 1155 1156 /* payload consists of 2 lists: 1157 * a) num_ints * sizeof(__le32) 1158 * b) num_chars * sizeof(u8) aligned to 4bytes 1159 */ 1160 u8 payload[0]; 1161 } __packed; 1162 1163 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 1164 { 1165 return (__le32 *)rx_test->payload; 1166 } 1167 1168 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 1169 { 1170 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 1171 } 1172 1173 /* 1174 * target -> host packet log message 1175 * 1176 * The following field definitions describe the format of the packet log 1177 * message sent from the target to the host. 1178 * The message consists of a 4-octet header,followed by a variable number 1179 * of 32-bit character values. 1180 * 1181 * |31 24|23 16|15 8|7 0| 1182 * |-----------------------------------------------------------| 1183 * | | | | msg type | 1184 * |-----------------------------------------------------------| 1185 * | payload | 1186 * |-----------------------------------------------------------| 1187 * - MSG_TYPE 1188 * Bits 7:0 1189 * Purpose: identifies this as a test message 1190 * Value: HTT_MSG_TYPE_PACKETLOG 1191 */ 1192 struct htt_pktlog_msg { 1193 u8 pad[3]; 1194 u8 payload[0]; 1195 } __packed; 1196 1197 struct htt_dbg_stats_rx_reorder_stats { 1198 /* Non QoS MPDUs received */ 1199 __le32 deliver_non_qos; 1200 1201 /* MPDUs received in-order */ 1202 __le32 deliver_in_order; 1203 1204 /* Flush due to reorder timer expired */ 1205 __le32 deliver_flush_timeout; 1206 1207 /* Flush due to move out of window */ 1208 __le32 deliver_flush_oow; 1209 1210 /* Flush due to DELBA */ 1211 __le32 deliver_flush_delba; 1212 1213 /* MPDUs dropped due to FCS error */ 1214 __le32 fcs_error; 1215 1216 /* MPDUs dropped due to monitor mode non-data packet */ 1217 __le32 mgmt_ctrl; 1218 1219 /* MPDUs dropped due to invalid peer */ 1220 __le32 invalid_peer; 1221 1222 /* MPDUs dropped due to duplication (non aggregation) */ 1223 __le32 dup_non_aggr; 1224 1225 /* MPDUs dropped due to processed before */ 1226 __le32 dup_past; 1227 1228 /* MPDUs dropped due to duplicate in reorder queue */ 1229 __le32 dup_in_reorder; 1230 1231 /* Reorder timeout happened */ 1232 __le32 reorder_timeout; 1233 1234 /* invalid bar ssn */ 1235 __le32 invalid_bar_ssn; 1236 1237 /* reorder reset due to bar ssn */ 1238 __le32 ssn_reset; 1239 }; 1240 1241 struct htt_dbg_stats_wal_tx_stats { 1242 /* Num HTT cookies queued to dispatch list */ 1243 __le32 comp_queued; 1244 1245 /* Num HTT cookies dispatched */ 1246 __le32 comp_delivered; 1247 1248 /* Num MSDU queued to WAL */ 1249 __le32 msdu_enqued; 1250 1251 /* Num MPDU queue to WAL */ 1252 __le32 mpdu_enqued; 1253 1254 /* Num MSDUs dropped by WMM limit */ 1255 __le32 wmm_drop; 1256 1257 /* Num Local frames queued */ 1258 __le32 local_enqued; 1259 1260 /* Num Local frames done */ 1261 __le32 local_freed; 1262 1263 /* Num queued to HW */ 1264 __le32 hw_queued; 1265 1266 /* Num PPDU reaped from HW */ 1267 __le32 hw_reaped; 1268 1269 /* Num underruns */ 1270 __le32 underrun; 1271 1272 /* Num PPDUs cleaned up in TX abort */ 1273 __le32 tx_abort; 1274 1275 /* Num MPDUs requed by SW */ 1276 __le32 mpdus_requed; 1277 1278 /* excessive retries */ 1279 __le32 tx_ko; 1280 1281 /* data hw rate code */ 1282 __le32 data_rc; 1283 1284 /* Scheduler self triggers */ 1285 __le32 self_triggers; 1286 1287 /* frames dropped due to excessive sw retries */ 1288 __le32 sw_retry_failure; 1289 1290 /* illegal rate phy errors */ 1291 __le32 illgl_rate_phy_err; 1292 1293 /* wal pdev continuous xretry */ 1294 __le32 pdev_cont_xretry; 1295 1296 /* wal pdev continuous xretry */ 1297 __le32 pdev_tx_timeout; 1298 1299 /* wal pdev resets */ 1300 __le32 pdev_resets; 1301 1302 __le32 phy_underrun; 1303 1304 /* MPDU is more than txop limit */ 1305 __le32 txop_ovf; 1306 } __packed; 1307 1308 struct htt_dbg_stats_wal_rx_stats { 1309 /* Cnts any change in ring routing mid-ppdu */ 1310 __le32 mid_ppdu_route_change; 1311 1312 /* Total number of statuses processed */ 1313 __le32 status_rcvd; 1314 1315 /* Extra frags on rings 0-3 */ 1316 __le32 r0_frags; 1317 __le32 r1_frags; 1318 __le32 r2_frags; 1319 __le32 r3_frags; 1320 1321 /* MSDUs / MPDUs delivered to HTT */ 1322 __le32 htt_msdus; 1323 __le32 htt_mpdus; 1324 1325 /* MSDUs / MPDUs delivered to local stack */ 1326 __le32 loc_msdus; 1327 __le32 loc_mpdus; 1328 1329 /* AMSDUs that have more MSDUs than the status ring size */ 1330 __le32 oversize_amsdu; 1331 1332 /* Number of PHY errors */ 1333 __le32 phy_errs; 1334 1335 /* Number of PHY errors drops */ 1336 __le32 phy_err_drop; 1337 1338 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1339 __le32 mpdu_errs; 1340 } __packed; 1341 1342 struct htt_dbg_stats_wal_peer_stats { 1343 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 1344 } __packed; 1345 1346 struct htt_dbg_stats_wal_pdev_txrx { 1347 struct htt_dbg_stats_wal_tx_stats tx_stats; 1348 struct htt_dbg_stats_wal_rx_stats rx_stats; 1349 struct htt_dbg_stats_wal_peer_stats peer_stats; 1350 } __packed; 1351 1352 struct htt_dbg_stats_rx_rate_info { 1353 __le32 mcs[10]; 1354 __le32 sgi[10]; 1355 __le32 nss[4]; 1356 __le32 stbc[10]; 1357 __le32 bw[3]; 1358 __le32 pream[6]; 1359 __le32 ldpc; 1360 __le32 txbf; 1361 }; 1362 1363 /* 1364 * htt_dbg_stats_status - 1365 * present - The requested stats have been delivered in full. 1366 * This indicates that either the stats information was contained 1367 * in its entirety within this message, or else this message 1368 * completes the delivery of the requested stats info that was 1369 * partially delivered through earlier STATS_CONF messages. 1370 * partial - The requested stats have been delivered in part. 1371 * One or more subsequent STATS_CONF messages with the same 1372 * cookie value will be sent to deliver the remainder of the 1373 * information. 1374 * error - The requested stats could not be delivered, for example due 1375 * to a shortage of memory to construct a message holding the 1376 * requested stats. 1377 * invalid - The requested stat type is either not recognized, or the 1378 * target is configured to not gather the stats type in question. 1379 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1380 * series_done - This special value indicates that no further stats info 1381 * elements are present within a series of stats info elems 1382 * (within a stats upload confirmation message). 1383 */ 1384 enum htt_dbg_stats_status { 1385 HTT_DBG_STATS_STATUS_PRESENT = 0, 1386 HTT_DBG_STATS_STATUS_PARTIAL = 1, 1387 HTT_DBG_STATS_STATUS_ERROR = 2, 1388 HTT_DBG_STATS_STATUS_INVALID = 3, 1389 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 1390 }; 1391 1392 /* 1393 * target -> host statistics upload 1394 * 1395 * The following field definitions describe the format of the HTT target 1396 * to host stats upload confirmation message. 1397 * The message contains a cookie echoed from the HTT host->target stats 1398 * upload request, which identifies which request the confirmation is 1399 * for, and a series of tag-length-value stats information elements. 1400 * The tag-length header for each stats info element also includes a 1401 * status field, to indicate whether the request for the stat type in 1402 * question was fully met, partially met, unable to be met, or invalid 1403 * (if the stat type in question is disabled in the target). 1404 * A special value of all 1's in this status field is used to indicate 1405 * the end of the series of stats info elements. 1406 * 1407 * 1408 * |31 16|15 8|7 5|4 0| 1409 * |------------------------------------------------------------| 1410 * | reserved | msg type | 1411 * |------------------------------------------------------------| 1412 * | cookie LSBs | 1413 * |------------------------------------------------------------| 1414 * | cookie MSBs | 1415 * |------------------------------------------------------------| 1416 * | stats entry length | reserved | S |stat type| 1417 * |------------------------------------------------------------| 1418 * | | 1419 * | type-specific stats info | 1420 * | | 1421 * |------------------------------------------------------------| 1422 * | stats entry length | reserved | S |stat type| 1423 * |------------------------------------------------------------| 1424 * | | 1425 * | type-specific stats info | 1426 * | | 1427 * |------------------------------------------------------------| 1428 * | n/a | reserved | 111 | n/a | 1429 * |------------------------------------------------------------| 1430 * Header fields: 1431 * - MSG_TYPE 1432 * Bits 7:0 1433 * Purpose: identifies this is a statistics upload confirmation message 1434 * Value: 0x9 1435 * - COOKIE_LSBS 1436 * Bits 31:0 1437 * Purpose: Provide a mechanism to match a target->host stats confirmation 1438 * message with its preceding host->target stats request message. 1439 * Value: LSBs of the opaque cookie specified by the host-side requestor 1440 * - COOKIE_MSBS 1441 * Bits 31:0 1442 * Purpose: Provide a mechanism to match a target->host stats confirmation 1443 * message with its preceding host->target stats request message. 1444 * Value: MSBs of the opaque cookie specified by the host-side requestor 1445 * 1446 * Stats Information Element tag-length header fields: 1447 * - STAT_TYPE 1448 * Bits 4:0 1449 * Purpose: identifies the type of statistics info held in the 1450 * following information element 1451 * Value: htt_dbg_stats_type 1452 * - STATUS 1453 * Bits 7:5 1454 * Purpose: indicate whether the requested stats are present 1455 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 1456 * the completion of the stats entry series 1457 * - LENGTH 1458 * Bits 31:16 1459 * Purpose: indicate the stats information size 1460 * Value: This field specifies the number of bytes of stats information 1461 * that follows the element tag-length header. 1462 * It is expected but not required that this length is a multiple of 1463 * 4 bytes. Even if the length is not an integer multiple of 4, the 1464 * subsequent stats entry header will begin on a 4-byte aligned 1465 * boundary. 1466 */ 1467 1468 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1469 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1470 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1471 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1472 1473 struct htt_stats_conf_item { 1474 union { 1475 u8 info; 1476 struct { 1477 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1478 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1479 } __packed; 1480 } __packed; 1481 u8 pad; 1482 __le16 length; 1483 u8 payload[0]; /* roundup(length, 4) long */ 1484 } __packed; 1485 1486 struct htt_stats_conf { 1487 u8 pad[3]; 1488 __le32 cookie_lsb; 1489 __le32 cookie_msb; 1490 1491 /* each item has variable length! */ 1492 struct htt_stats_conf_item items[0]; 1493 } __packed; 1494 1495 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1496 const struct htt_stats_conf_item *item) 1497 { 1498 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1499 } 1500 1501 /* 1502 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1503 * 1504 * The following field definitions describe the format of the HTT host 1505 * to target frag_desc/msdu_ext bank configuration message. 1506 * The message contains the based address and the min and max id of the 1507 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1508 * MSDU_EXT/FRAG_DESC. 1509 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1510 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1511 * the hardware does the mapping/translation. 1512 * 1513 * Total banks that can be configured is configured to 16. 1514 * 1515 * This should be called before any TX has be initiated by the HTT 1516 * 1517 * |31 16|15 8|7 5|4 0| 1518 * |------------------------------------------------------------| 1519 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1520 * |------------------------------------------------------------| 1521 * | BANK0_BASE_ADDRESS | 1522 * |------------------------------------------------------------| 1523 * | ... | 1524 * |------------------------------------------------------------| 1525 * | BANK15_BASE_ADDRESS | 1526 * |------------------------------------------------------------| 1527 * | BANK0_MAX_ID | BANK0_MIN_ID | 1528 * |------------------------------------------------------------| 1529 * | ... | 1530 * |------------------------------------------------------------| 1531 * | BANK15_MAX_ID | BANK15_MIN_ID | 1532 * |------------------------------------------------------------| 1533 * Header fields: 1534 * - MSG_TYPE 1535 * Bits 7:0 1536 * Value: 0x6 1537 * - BANKx_BASE_ADDRESS 1538 * Bits 31:0 1539 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1540 * bank physical/bus address. 1541 * - BANKx_MIN_ID 1542 * Bits 15:0 1543 * Purpose: Provide a mechanism to specify the min index that needs to 1544 * mapped. 1545 * - BANKx_MAX_ID 1546 * Bits 31:16 1547 * Purpose: Provide a mechanism to specify the max index that needs to 1548 * 1549 */ 1550 struct htt_frag_desc_bank_id { 1551 __le16 bank_min_id; 1552 __le16 bank_max_id; 1553 } __packed; 1554 1555 /* real is 16 but it wouldn't fit in the max htt message size 1556 * so we use a conservatively safe value for now 1557 */ 1558 #define HTT_FRAG_DESC_BANK_MAX 4 1559 1560 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1561 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1562 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2) 1563 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3) 1564 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4) 1565 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4 1566 1567 enum htt_q_depth_type { 1568 HTT_Q_DEPTH_TYPE_BYTES = 0, 1569 HTT_Q_DEPTH_TYPE_MSDUS = 1, 1570 }; 1571 1572 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \ 1573 TARGET_10_4_NUM_VDEVS) 1574 #define HTT_TX_Q_STATE_NUM_TIDS 8 1575 #define HTT_TX_Q_STATE_ENTRY_SIZE 1 1576 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0 1577 1578 /** 1579 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config 1580 * 1581 * Defines host q state format and behavior. See htt_q_state. 1582 * 1583 * @record_size: Defines the size of each host q entry in bytes. In practice 1584 * however firmware (at least 10.4.3-00191) ignores this host 1585 * configuration value and uses hardcoded value of 1. 1586 * @record_multiplier: This is valid only when q depth type is MSDUs. It 1587 * defines the exponent for the power of 2 multiplication. 1588 */ 1589 struct htt_q_state_conf { 1590 __le32 paddr; 1591 __le16 num_peers; 1592 __le16 num_tids; 1593 u8 record_size; 1594 u8 record_multiplier; 1595 u8 pad[2]; 1596 } __packed; 1597 1598 struct htt_frag_desc_bank_cfg32 { 1599 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1600 u8 num_banks; 1601 u8 desc_size; 1602 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1603 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1604 struct htt_q_state_conf q_state; 1605 } __packed; 1606 1607 struct htt_frag_desc_bank_cfg64 { 1608 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1609 u8 num_banks; 1610 u8 desc_size; 1611 __le64 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1612 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1613 struct htt_q_state_conf q_state; 1614 } __packed; 1615 1616 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128 1617 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f 1618 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0 1619 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0 1620 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6 1621 1622 /** 1623 * htt_q_state - shared between host and firmware via DMA 1624 * 1625 * This structure is used for the host to expose it's software queue state to 1626 * firmware so that its rate control can schedule fetch requests for optimized 1627 * performance. This is most notably used for MU-MIMO aggregation when multiple 1628 * MU clients are connected. 1629 * 1630 * @count: Each element defines the host queue depth. When q depth type was 1631 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as: 1632 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and 1633 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as 1634 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 ** 1635 * record_multiplier (see htt_q_state_conf). 1636 * @map: Used by firmware to quickly check which host queues are not empty. It 1637 * is a bitmap simply saying. 1638 * @seq: Used by firmware to quickly check if the host queues were updated 1639 * since it last checked. 1640 * 1641 * FIXME: Is the q_state map[] size calculation really correct? 1642 */ 1643 struct htt_q_state { 1644 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS]; 1645 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32]; 1646 __le32 seq; 1647 } __packed; 1648 1649 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff 1650 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0 1651 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000 1652 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12 1653 1654 struct htt_tx_fetch_record { 1655 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */ 1656 __le16 num_msdus; 1657 __le32 num_bytes; 1658 } __packed; 1659 1660 struct htt_tx_fetch_ind { 1661 u8 pad0; 1662 __le16 fetch_seq_num; 1663 __le32 token; 1664 __le16 num_resp_ids; 1665 __le16 num_records; 1666 struct htt_tx_fetch_record records[0]; 1667 __le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */ 1668 } __packed; 1669 1670 static inline void * 1671 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind) 1672 { 1673 return (void *)&ind->records[le16_to_cpu(ind->num_records)]; 1674 } 1675 1676 struct htt_tx_fetch_resp { 1677 u8 pad0; 1678 __le16 resp_id; 1679 __le16 fetch_seq_num; 1680 __le16 num_records; 1681 __le32 token; 1682 struct htt_tx_fetch_record records[0]; 1683 } __packed; 1684 1685 struct htt_tx_fetch_confirm { 1686 u8 pad0; 1687 __le16 num_resp_ids; 1688 __le32 resp_ids[0]; 1689 } __packed; 1690 1691 enum htt_tx_mode_switch_mode { 1692 HTT_TX_MODE_SWITCH_PUSH = 0, 1693 HTT_TX_MODE_SWITCH_PUSH_PULL = 1, 1694 }; 1695 1696 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0) 1697 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe 1698 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1 1699 1700 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003 1701 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0 1702 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc 1703 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2 1704 1705 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff 1706 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0 1707 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000 1708 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12 1709 1710 struct htt_tx_mode_switch_record { 1711 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */ 1712 __le16 num_max_msdus; 1713 } __packed; 1714 1715 struct htt_tx_mode_switch_ind { 1716 u8 pad0; 1717 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */ 1718 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */ 1719 u8 pad1[2]; 1720 struct htt_tx_mode_switch_record records[0]; 1721 } __packed; 1722 1723 struct htt_channel_change { 1724 u8 pad[3]; 1725 __le32 freq; 1726 __le32 center_freq1; 1727 __le32 center_freq2; 1728 __le32 phymode; 1729 } __packed; 1730 1731 struct htt_per_peer_tx_stats_ind { 1732 __le32 succ_bytes; 1733 __le32 retry_bytes; 1734 __le32 failed_bytes; 1735 u8 ratecode; 1736 u8 flags; 1737 __le16 peer_id; 1738 __le16 succ_pkts; 1739 __le16 retry_pkts; 1740 __le16 failed_pkts; 1741 __le16 tx_duration; 1742 __le32 reserved1; 1743 __le32 reserved2; 1744 } __packed; 1745 1746 struct htt_peer_tx_stats { 1747 u8 num_ppdu; 1748 u8 ppdu_len; 1749 u8 version; 1750 u8 payload[0]; 1751 } __packed; 1752 1753 #define ATH10K_10_2_TX_STATS_OFFSET 136 1754 #define PEER_STATS_FOR_NO_OF_PPDUS 4 1755 1756 struct ath10k_10_2_peer_tx_stats { 1757 u8 ratecode[PEER_STATS_FOR_NO_OF_PPDUS]; 1758 u8 success_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1759 __le16 success_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1760 u8 retry_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1761 __le16 retry_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1762 u8 failed_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1763 __le16 failed_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1764 u8 flags[PEER_STATS_FOR_NO_OF_PPDUS]; 1765 __le32 tx_duration; 1766 u8 tx_ppdu_cnt; 1767 u8 peer_id; 1768 } __packed; 1769 1770 union htt_rx_pn_t { 1771 /* WEP: 24-bit PN */ 1772 u32 pn24; 1773 1774 /* TKIP or CCMP: 48-bit PN */ 1775 u64 pn48; 1776 1777 /* WAPI: 128-bit PN */ 1778 u64 pn128[2]; 1779 }; 1780 1781 struct htt_cmd { 1782 struct htt_cmd_hdr hdr; 1783 union { 1784 struct htt_ver_req ver_req; 1785 struct htt_mgmt_tx_desc mgmt_tx; 1786 struct htt_data_tx_desc data_tx; 1787 struct htt_rx_ring_setup_32 rx_setup_32; 1788 struct htt_rx_ring_setup_64 rx_setup_64; 1789 struct htt_stats_req stats_req; 1790 struct htt_oob_sync_req oob_sync_req; 1791 struct htt_aggr_conf aggr_conf; 1792 struct htt_aggr_conf_v2 aggr_conf_v2; 1793 struct htt_frag_desc_bank_cfg32 frag_desc_bank_cfg32; 1794 struct htt_frag_desc_bank_cfg64 frag_desc_bank_cfg64; 1795 struct htt_tx_fetch_resp tx_fetch_resp; 1796 }; 1797 } __packed; 1798 1799 struct htt_resp { 1800 struct htt_resp_hdr hdr; 1801 union { 1802 struct htt_ver_resp ver_resp; 1803 struct htt_mgmt_tx_completion mgmt_tx_completion; 1804 struct htt_data_tx_completion data_tx_completion; 1805 struct htt_rx_indication rx_ind; 1806 struct htt_rx_indication_hl rx_ind_hl; 1807 struct htt_rx_fragment_indication rx_frag_ind; 1808 struct htt_rx_peer_map peer_map; 1809 struct htt_rx_peer_unmap peer_unmap; 1810 struct htt_rx_flush rx_flush; 1811 struct htt_rx_addba rx_addba; 1812 struct htt_rx_delba rx_delba; 1813 struct htt_security_indication security_indication; 1814 struct htt_rc_update rc_update; 1815 struct htt_rx_test rx_test; 1816 struct htt_pktlog_msg pktlog_msg; 1817 struct htt_stats_conf stats_conf; 1818 struct htt_rx_pn_ind rx_pn_ind; 1819 struct htt_rx_offload_ind rx_offload_ind; 1820 struct htt_rx_in_ord_ind rx_in_ord_ind; 1821 struct htt_tx_fetch_ind tx_fetch_ind; 1822 struct htt_tx_fetch_confirm tx_fetch_confirm; 1823 struct htt_tx_mode_switch_ind tx_mode_switch_ind; 1824 struct htt_channel_change chan_change; 1825 struct htt_peer_tx_stats peer_tx_stats; 1826 }; 1827 } __packed; 1828 1829 /*** host side structures follow ***/ 1830 1831 struct htt_tx_done { 1832 u16 msdu_id; 1833 u16 status; 1834 u8 ack_rssi; 1835 }; 1836 1837 enum htt_tx_compl_state { 1838 HTT_TX_COMPL_STATE_NONE, 1839 HTT_TX_COMPL_STATE_ACK, 1840 HTT_TX_COMPL_STATE_NOACK, 1841 HTT_TX_COMPL_STATE_DISCARD, 1842 }; 1843 1844 struct htt_peer_map_event { 1845 u8 vdev_id; 1846 u16 peer_id; 1847 u8 addr[ETH_ALEN]; 1848 }; 1849 1850 struct htt_peer_unmap_event { 1851 u16 peer_id; 1852 }; 1853 1854 struct ath10k_htt_txbuf_32 { 1855 struct htt_data_tx_desc_frag frags[2]; 1856 struct ath10k_htc_hdr htc_hdr; 1857 struct htt_cmd_hdr cmd_hdr; 1858 struct htt_data_tx_desc cmd_tx; 1859 } __packed __aligned(4); 1860 1861 struct ath10k_htt_txbuf_64 { 1862 struct htt_data_tx_desc_frag frags[2]; 1863 struct ath10k_htc_hdr htc_hdr; 1864 struct htt_cmd_hdr cmd_hdr; 1865 struct htt_data_tx_desc_64 cmd_tx; 1866 } __packed __aligned(4); 1867 1868 struct ath10k_htt { 1869 struct ath10k *ar; 1870 enum ath10k_htc_ep_id eid; 1871 1872 u8 target_version_major; 1873 u8 target_version_minor; 1874 struct completion target_version_received; 1875 u8 max_num_amsdu; 1876 u8 max_num_ampdu; 1877 1878 const enum htt_t2h_msg_type *t2h_msg_types; 1879 u32 t2h_msg_types_max; 1880 1881 struct { 1882 /* 1883 * Ring of network buffer objects - This ring is 1884 * used exclusively by the host SW. This ring 1885 * mirrors the dev_addrs_ring that is shared 1886 * between the host SW and the MAC HW. The host SW 1887 * uses this netbufs ring to locate the network 1888 * buffer objects whose data buffers the HW has 1889 * filled. 1890 */ 1891 struct sk_buff **netbufs_ring; 1892 1893 /* This is used only with firmware supporting IN_ORD_IND. 1894 * 1895 * With Full Rx Reorder the HTT Rx Ring is more of a temporary 1896 * buffer ring from which buffer addresses are copied by the 1897 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND 1898 * pointing to specific (re-ordered) buffers. 1899 * 1900 * FIXME: With kernel generic hashing functions there's a lot 1901 * of hash collisions for sk_buffs. 1902 */ 1903 bool in_ord_rx; 1904 DECLARE_HASHTABLE(skb_table, 4); 1905 1906 /* 1907 * Ring of buffer addresses - 1908 * This ring holds the "physical" device address of the 1909 * rx buffers the host SW provides for the MAC HW to 1910 * fill. 1911 */ 1912 union { 1913 __le64 *paddrs_ring_64; 1914 __le32 *paddrs_ring_32; 1915 }; 1916 1917 /* 1918 * Base address of ring, as a "physical" device address 1919 * rather than a CPU address. 1920 */ 1921 dma_addr_t base_paddr; 1922 1923 /* how many elems in the ring (power of 2) */ 1924 int size; 1925 1926 /* size - 1 */ 1927 unsigned int size_mask; 1928 1929 /* how many rx buffers to keep in the ring */ 1930 int fill_level; 1931 1932 /* how many rx buffers (full+empty) are in the ring */ 1933 int fill_cnt; 1934 1935 /* 1936 * alloc_idx - where HTT SW has deposited empty buffers 1937 * This is allocated in consistent mem, so that the FW can 1938 * read this variable, and program the HW's FW_IDX reg with 1939 * the value of this shadow register. 1940 */ 1941 struct { 1942 __le32 *vaddr; 1943 dma_addr_t paddr; 1944 } alloc_idx; 1945 1946 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1947 struct { 1948 unsigned int msdu_payld; 1949 } sw_rd_idx; 1950 1951 /* 1952 * refill_retry_timer - timer triggered when the ring is 1953 * not refilled to the level expected 1954 */ 1955 struct timer_list refill_retry_timer; 1956 1957 /* Protects access to all rx ring buffer state variables */ 1958 spinlock_t lock; 1959 } rx_ring; 1960 1961 unsigned int prefetch_len; 1962 1963 /* Protects access to pending_tx, num_pending_tx */ 1964 spinlock_t tx_lock; 1965 int max_num_pending_tx; 1966 int num_pending_tx; 1967 int num_pending_mgmt_tx; 1968 struct idr pending_tx; 1969 wait_queue_head_t empty_tx_wq; 1970 1971 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */ 1972 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done); 1973 1974 /* set if host-fw communication goes haywire 1975 * used to avoid further failures 1976 */ 1977 bool rx_confused; 1978 atomic_t num_mpdus_ready; 1979 1980 /* This is used to group tx/rx completions separately and process them 1981 * in batches to reduce cache stalls 1982 */ 1983 struct sk_buff_head rx_msdus_q; 1984 struct sk_buff_head rx_in_ord_compl_q; 1985 struct sk_buff_head tx_fetch_ind_q; 1986 1987 /* rx_status template */ 1988 struct ieee80211_rx_status rx_status; 1989 1990 struct { 1991 dma_addr_t paddr; 1992 union { 1993 struct htt_msdu_ext_desc *vaddr_desc_32; 1994 struct htt_msdu_ext_desc_64 *vaddr_desc_64; 1995 }; 1996 size_t size; 1997 } frag_desc; 1998 1999 struct { 2000 dma_addr_t paddr; 2001 union { 2002 struct ath10k_htt_txbuf_32 *vaddr_txbuff_32; 2003 struct ath10k_htt_txbuf_64 *vaddr_txbuff_64; 2004 }; 2005 size_t size; 2006 } txbuf; 2007 2008 struct { 2009 bool enabled; 2010 struct htt_q_state *vaddr; 2011 dma_addr_t paddr; 2012 u16 num_push_allowed; 2013 u16 num_peers; 2014 u16 num_tids; 2015 enum htt_tx_mode_switch_mode mode; 2016 enum htt_q_depth_type type; 2017 } tx_q_state; 2018 2019 bool tx_mem_allocated; 2020 const struct ath10k_htt_tx_ops *tx_ops; 2021 const struct ath10k_htt_rx_ops *rx_ops; 2022 }; 2023 2024 struct ath10k_htt_tx_ops { 2025 int (*htt_send_rx_ring_cfg)(struct ath10k_htt *htt); 2026 int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt); 2027 int (*htt_alloc_frag_desc)(struct ath10k_htt *htt); 2028 void (*htt_free_frag_desc)(struct ath10k_htt *htt); 2029 int (*htt_tx)(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 2030 struct sk_buff *msdu); 2031 int (*htt_alloc_txbuff)(struct ath10k_htt *htt); 2032 void (*htt_free_txbuff)(struct ath10k_htt *htt); 2033 int (*htt_h2t_aggr_cfg_msg)(struct ath10k_htt *htt, 2034 u8 max_subfrms_ampdu, 2035 u8 max_subfrms_amsdu); 2036 }; 2037 2038 static inline int ath10k_htt_send_rx_ring_cfg(struct ath10k_htt *htt) 2039 { 2040 if (!htt->tx_ops->htt_send_rx_ring_cfg) 2041 return -EOPNOTSUPP; 2042 2043 return htt->tx_ops->htt_send_rx_ring_cfg(htt); 2044 } 2045 2046 static inline int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) 2047 { 2048 if (!htt->tx_ops->htt_send_frag_desc_bank_cfg) 2049 return -EOPNOTSUPP; 2050 2051 return htt->tx_ops->htt_send_frag_desc_bank_cfg(htt); 2052 } 2053 2054 static inline int ath10k_htt_alloc_frag_desc(struct ath10k_htt *htt) 2055 { 2056 if (!htt->tx_ops->htt_alloc_frag_desc) 2057 return -EOPNOTSUPP; 2058 2059 return htt->tx_ops->htt_alloc_frag_desc(htt); 2060 } 2061 2062 static inline void ath10k_htt_free_frag_desc(struct ath10k_htt *htt) 2063 { 2064 if (htt->tx_ops->htt_free_frag_desc) 2065 htt->tx_ops->htt_free_frag_desc(htt); 2066 } 2067 2068 static inline int ath10k_htt_tx(struct ath10k_htt *htt, 2069 enum ath10k_hw_txrx_mode txmode, 2070 struct sk_buff *msdu) 2071 { 2072 return htt->tx_ops->htt_tx(htt, txmode, msdu); 2073 } 2074 2075 static inline int ath10k_htt_alloc_txbuff(struct ath10k_htt *htt) 2076 { 2077 if (!htt->tx_ops->htt_alloc_txbuff) 2078 return -EOPNOTSUPP; 2079 2080 return htt->tx_ops->htt_alloc_txbuff(htt); 2081 } 2082 2083 static inline void ath10k_htt_free_txbuff(struct ath10k_htt *htt) 2084 { 2085 if (htt->tx_ops->htt_free_txbuff) 2086 htt->tx_ops->htt_free_txbuff(htt); 2087 } 2088 2089 static inline int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 2090 u8 max_subfrms_ampdu, 2091 u8 max_subfrms_amsdu) 2092 2093 { 2094 if (!htt->tx_ops->htt_h2t_aggr_cfg_msg) 2095 return -EOPNOTSUPP; 2096 2097 return htt->tx_ops->htt_h2t_aggr_cfg_msg(htt, 2098 max_subfrms_ampdu, 2099 max_subfrms_amsdu); 2100 } 2101 2102 struct ath10k_htt_rx_ops { 2103 size_t (*htt_get_rx_ring_size)(struct ath10k_htt *htt); 2104 void (*htt_config_paddrs_ring)(struct ath10k_htt *htt, void *vaddr); 2105 void (*htt_set_paddrs_ring)(struct ath10k_htt *htt, dma_addr_t paddr, 2106 int idx); 2107 void* (*htt_get_vaddr_ring)(struct ath10k_htt *htt); 2108 void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx); 2109 bool (*htt_rx_proc_rx_frag_ind)(struct ath10k_htt *htt, 2110 struct htt_rx_fragment_indication *rx, 2111 struct sk_buff *skb); 2112 }; 2113 2114 static inline size_t ath10k_htt_get_rx_ring_size(struct ath10k_htt *htt) 2115 { 2116 if (!htt->rx_ops->htt_get_rx_ring_size) 2117 return 0; 2118 2119 return htt->rx_ops->htt_get_rx_ring_size(htt); 2120 } 2121 2122 static inline void ath10k_htt_config_paddrs_ring(struct ath10k_htt *htt, 2123 void *vaddr) 2124 { 2125 if (htt->rx_ops->htt_config_paddrs_ring) 2126 htt->rx_ops->htt_config_paddrs_ring(htt, vaddr); 2127 } 2128 2129 static inline void ath10k_htt_set_paddrs_ring(struct ath10k_htt *htt, 2130 dma_addr_t paddr, 2131 int idx) 2132 { 2133 if (htt->rx_ops->htt_set_paddrs_ring) 2134 htt->rx_ops->htt_set_paddrs_ring(htt, paddr, idx); 2135 } 2136 2137 static inline void *ath10k_htt_get_vaddr_ring(struct ath10k_htt *htt) 2138 { 2139 if (!htt->rx_ops->htt_get_vaddr_ring) 2140 return NULL; 2141 2142 return htt->rx_ops->htt_get_vaddr_ring(htt); 2143 } 2144 2145 static inline void ath10k_htt_reset_paddrs_ring(struct ath10k_htt *htt, int idx) 2146 { 2147 if (htt->rx_ops->htt_reset_paddrs_ring) 2148 htt->rx_ops->htt_reset_paddrs_ring(htt, idx); 2149 } 2150 2151 static inline bool ath10k_htt_rx_proc_rx_frag_ind(struct ath10k_htt *htt, 2152 struct htt_rx_fragment_indication *rx, 2153 struct sk_buff *skb) 2154 { 2155 if (!htt->rx_ops->htt_rx_proc_rx_frag_ind) 2156 return true; 2157 2158 return htt->rx_ops->htt_rx_proc_rx_frag_ind(htt, rx, skb); 2159 } 2160 2161 #define RX_HTT_HDR_STATUS_LEN 64 2162 2163 /* This structure layout is programmed via rx ring setup 2164 * so that FW knows how to transfer the rx descriptor to the host. 2165 * Buffers like this are placed on the rx ring. 2166 */ 2167 struct htt_rx_desc { 2168 union { 2169 /* This field is filled on the host using the msdu buffer 2170 * from htt_rx_indication 2171 */ 2172 struct fw_rx_desc_base fw_desc; 2173 u32 pad; 2174 } __packed; 2175 struct { 2176 struct rx_attention attention; 2177 struct rx_frag_info frag_info; 2178 struct rx_mpdu_start mpdu_start; 2179 struct rx_msdu_start msdu_start; 2180 struct rx_msdu_end msdu_end; 2181 struct rx_mpdu_end mpdu_end; 2182 struct rx_ppdu_start ppdu_start; 2183 struct rx_ppdu_end ppdu_end; 2184 } __packed; 2185 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 2186 u8 msdu_payload[0]; 2187 }; 2188 2189 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_MASK 0x00000fff 2190 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_LSB 0 2191 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_MASK 0x00001000 2192 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_LSB 12 2193 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_MASK 0x00002000 2194 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_LSB 13 2195 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_MASK 0x00010000 2196 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_LSB 16 2197 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_MASK 0x01fe0000 2198 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_LSB 17 2199 2200 struct htt_rx_desc_base_hl { 2201 __le32 info; /* HTT_RX_DESC_HL_INFO_ */ 2202 }; 2203 2204 struct htt_rx_chan_info { 2205 __le16 primary_chan_center_freq_mhz; 2206 __le16 contig_chan1_center_freq_mhz; 2207 __le16 contig_chan2_center_freq_mhz; 2208 u8 phy_mode; 2209 u8 reserved; 2210 } __packed; 2211 2212 #define HTT_RX_DESC_ALIGN 8 2213 2214 #define HTT_MAC_ADDR_LEN 6 2215 2216 /* 2217 * FIX THIS 2218 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 2219 * rounded up to a cache line size. 2220 */ 2221 #define HTT_RX_BUF_SIZE 1920 2222 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 2223 2224 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 2225 * aggregated traffic more nicely. 2226 */ 2227 #define ATH10K_HTT_MAX_NUM_REFILL 100 2228 2229 /* 2230 * DMA_MAP expects the buffer to be an integral number of cache lines. 2231 * Rather than checking the actual cache line size, this code makes a 2232 * conservative estimate of what the cache line size could be. 2233 */ 2234 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 2235 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 2236 2237 /* These values are default in most firmware revisions and apparently are a 2238 * sweet spot performance wise. 2239 */ 2240 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3 2241 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64 2242 2243 int ath10k_htt_connect(struct ath10k_htt *htt); 2244 int ath10k_htt_init(struct ath10k *ar); 2245 int ath10k_htt_setup(struct ath10k_htt *htt); 2246 2247 int ath10k_htt_tx_start(struct ath10k_htt *htt); 2248 void ath10k_htt_tx_stop(struct ath10k_htt *htt); 2249 void ath10k_htt_tx_destroy(struct ath10k_htt *htt); 2250 void ath10k_htt_tx_free(struct ath10k_htt *htt); 2251 2252 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 2253 int ath10k_htt_rx_ring_refill(struct ath10k *ar); 2254 void ath10k_htt_rx_free(struct ath10k_htt *htt); 2255 2256 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 2257 void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 2258 bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 2259 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 2260 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, 2261 u64 cookie); 2262 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb); 2263 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 2264 __le32 token, 2265 __le16 fetch_seq_num, 2266 struct htt_tx_fetch_record *records, 2267 size_t num_records); 2268 2269 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 2270 struct ieee80211_txq *txq); 2271 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 2272 struct ieee80211_txq *txq); 2273 void ath10k_htt_tx_txq_sync(struct ath10k *ar); 2274 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 2275 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt); 2276 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt); 2277 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 2278 bool is_presp); 2279 2280 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); 2281 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 2282 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu); 2283 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar, 2284 struct sk_buff *skb); 2285 int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget); 2286 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt); 2287 void ath10k_htt_set_rx_ops(struct ath10k_htt *htt); 2288 #endif 2289