1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HTT_H_ 19 #define _HTT_H_ 20 21 #include <linux/bug.h> 22 #include <linux/interrupt.h> 23 #include <linux/dmapool.h> 24 #include <net/mac80211.h> 25 26 #include "htc.h" 27 #include "rx_desc.h" 28 29 enum htt_dbg_stats_type { 30 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 31 HTT_DBG_STATS_RX_REORDER = 1 << 1, 32 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 33 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 34 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 35 /* bits 5-23 currently reserved */ 36 37 HTT_DBG_NUM_STATS /* keep this last */ 38 }; 39 40 enum htt_h2t_msg_type { /* host-to-target */ 41 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 42 HTT_H2T_MSG_TYPE_TX_FRM = 1, 43 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 44 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 45 HTT_H2T_MSG_TYPE_SYNC = 4, 46 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 47 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 48 49 /* This command is used for sending management frames in HTT < 3.0. 50 * HTT >= 3.0 uses TX_FRM for everything. */ 51 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 52 53 HTT_H2T_NUM_MSGS /* keep this last */ 54 }; 55 56 struct htt_cmd_hdr { 57 u8 msg_type; 58 } __packed; 59 60 struct htt_ver_req { 61 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 62 } __packed; 63 64 /* 65 * HTT tx MSDU descriptor 66 * 67 * The HTT tx MSDU descriptor is created by the host HTT SW for each 68 * tx MSDU. The HTT tx MSDU descriptor contains the information that 69 * the target firmware needs for the FW's tx processing, particularly 70 * for creating the HW msdu descriptor. 71 * The same HTT tx descriptor is used for HL and LL systems, though 72 * a few fields within the tx descriptor are used only by LL or 73 * only by HL. 74 * The HTT tx descriptor is defined in two manners: by a struct with 75 * bitfields, and by a series of [dword offset, bit mask, bit shift] 76 * definitions. 77 * The target should use the struct def, for simplicitly and clarity, 78 * but the host shall use the bit-mast + bit-shift defs, to be endian- 79 * neutral. Specifically, the host shall use the get/set macros built 80 * around the mask + shift defs. 81 */ 82 struct htt_data_tx_desc_frag { 83 __le32 paddr; 84 __le32 len; 85 } __packed; 86 87 enum htt_data_tx_desc_flags0 { 88 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 89 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 90 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 91 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 92 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 93 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 94 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 95 }; 96 97 enum htt_data_tx_desc_flags1 { 98 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 99 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 100 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 101 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 102 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 103 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 104 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 105 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 106 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 107 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 108 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 109 }; 110 111 enum htt_data_tx_ext_tid { 112 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 113 HTT_DATA_TX_EXT_TID_MGMT = 17, 114 HTT_DATA_TX_EXT_TID_INVALID = 31 115 }; 116 117 #define HTT_INVALID_PEERID 0xFFFF 118 119 /* 120 * htt_data_tx_desc - used for data tx path 121 * 122 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 123 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 124 * for special kinds of tids 125 * postponed: only for HL hosts. indicates if this is a resend 126 * (HL hosts manage queues on the host ) 127 * more_in_batch: only for HL hosts. indicates if more packets are 128 * pending. this allows target to wait and aggregate 129 */ 130 struct htt_data_tx_desc { 131 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 132 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 133 __le16 len; 134 __le16 id; 135 __le32 frags_paddr; 136 __le32 peerid; 137 u8 prefetch[0]; /* start of frame, for FW classification engine */ 138 } __packed; 139 140 enum htt_rx_ring_flags { 141 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 142 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 143 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 144 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 145 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 146 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 147 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 148 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 149 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 150 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 151 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 152 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 153 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 154 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 155 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 156 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 157 }; 158 159 struct htt_rx_ring_setup_ring { 160 __le32 fw_idx_shadow_reg_paddr; 161 __le32 rx_ring_base_paddr; 162 __le16 rx_ring_len; /* in 4-byte words */ 163 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 164 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 165 __le16 fw_idx_init_val; 166 167 /* the following offsets are in 4-byte units */ 168 __le16 mac80211_hdr_offset; 169 __le16 msdu_payload_offset; 170 __le16 ppdu_start_offset; 171 __le16 ppdu_end_offset; 172 __le16 mpdu_start_offset; 173 __le16 mpdu_end_offset; 174 __le16 msdu_start_offset; 175 __le16 msdu_end_offset; 176 __le16 rx_attention_offset; 177 __le16 frag_info_offset; 178 } __packed; 179 180 struct htt_rx_ring_setup_hdr { 181 u8 num_rings; /* supported values: 1, 2 */ 182 __le16 rsvd0; 183 } __packed; 184 185 struct htt_rx_ring_setup { 186 struct htt_rx_ring_setup_hdr hdr; 187 struct htt_rx_ring_setup_ring rings[0]; 188 } __packed; 189 190 /* 191 * htt_stats_req - request target to send specified statistics 192 * 193 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 194 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 195 * so make sure its little-endian. 196 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 197 * so make sure its little-endian. 198 * @cfg_val: stat_type specific configuration 199 * @stat_type: see %htt_dbg_stats_type 200 * @cookie_lsb: used for confirmation message from target->host 201 * @cookie_msb: ditto as %cookie 202 */ 203 struct htt_stats_req { 204 u8 upload_types[3]; 205 u8 rsvd0; 206 u8 reset_types[3]; 207 struct { 208 u8 mpdu_bytes; 209 u8 mpdu_num_msdus; 210 u8 msdu_bytes; 211 } __packed; 212 u8 stat_type; 213 __le32 cookie_lsb; 214 __le32 cookie_msb; 215 } __packed; 216 217 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 218 219 /* 220 * htt_oob_sync_req - request out-of-band sync 221 * 222 * The HTT SYNC tells the target to suspend processing of subsequent 223 * HTT host-to-target messages until some other target agent locally 224 * informs the target HTT FW that the current sync counter is equal to 225 * or greater than (in a modulo sense) the sync counter specified in 226 * the SYNC message. 227 * 228 * This allows other host-target components to synchronize their operation 229 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 230 * security key has been downloaded to and activated by the target. 231 * In the absence of any explicit synchronization counter value 232 * specification, the target HTT FW will use zero as the default current 233 * sync value. 234 * 235 * The HTT target FW will suspend its host->target message processing as long 236 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 237 */ 238 struct htt_oob_sync_req { 239 u8 sync_count; 240 __le16 rsvd0; 241 } __packed; 242 243 #define HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_MASK 0x1F 244 #define HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_LSB 0 245 246 struct htt_aggr_conf { 247 u8 max_num_ampdu_subframes; 248 union { 249 /* dont use bitfields; undefined behaviour */ 250 u8 flags; /* see %HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_ */ 251 u8 max_num_amsdu_subframes:5; 252 } __packed; 253 } __packed; 254 255 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 256 257 struct htt_mgmt_tx_desc { 258 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 259 __le32 msdu_paddr; 260 __le32 desc_id; 261 __le32 len; 262 __le32 vdev_id; 263 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 264 } __packed; 265 266 enum htt_mgmt_tx_status { 267 HTT_MGMT_TX_STATUS_OK = 0, 268 HTT_MGMT_TX_STATUS_RETRY = 1, 269 HTT_MGMT_TX_STATUS_DROP = 2 270 }; 271 272 /*=== target -> host messages ===============================================*/ 273 274 275 enum htt_t2h_msg_type { 276 HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0, 277 HTT_T2H_MSG_TYPE_RX_IND = 0x1, 278 HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2, 279 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 280 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 281 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 282 HTT_T2H_MSG_TYPE_RX_DELBA = 0x6, 283 HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 284 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 285 HTT_T2H_MSG_TYPE_STATS_CONF = 0x9, 286 HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 287 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 288 HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 289 HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 290 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION = 0xe, 291 HTT_T2H_MSG_TYPE_TEST, 292 /* keep this last */ 293 HTT_T2H_NUM_MSGS 294 }; 295 296 /* 297 * htt_resp_hdr - header for target-to-host messages 298 * 299 * msg_type: see htt_t2h_msg_type 300 */ 301 struct htt_resp_hdr { 302 u8 msg_type; 303 } __packed; 304 305 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 306 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 307 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 308 309 /* htt_ver_resp - response sent for htt_ver_req */ 310 struct htt_ver_resp { 311 u8 minor; 312 u8 major; 313 u8 rsvd0; 314 } __packed; 315 316 struct htt_mgmt_tx_completion { 317 u8 rsvd0; 318 u8 rsvd1; 319 u8 rsvd2; 320 __le32 desc_id; 321 __le32 status; 322 } __packed; 323 324 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x3F) 325 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 326 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 6) 327 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 7) 328 329 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 330 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 331 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 332 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 333 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 334 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 335 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 336 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 337 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 338 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 339 340 struct htt_rx_indication_hdr { 341 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 342 __le16 peer_id; 343 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 344 } __packed; 345 346 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 347 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 348 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 349 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 350 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 351 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 352 353 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 354 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 355 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 356 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 357 358 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 359 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 360 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 361 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 362 363 enum htt_rx_legacy_rate { 364 HTT_RX_OFDM_48 = 0, 365 HTT_RX_OFDM_24 = 1, 366 HTT_RX_OFDM_12, 367 HTT_RX_OFDM_6, 368 HTT_RX_OFDM_54, 369 HTT_RX_OFDM_36, 370 HTT_RX_OFDM_18, 371 HTT_RX_OFDM_9, 372 373 /* long preamble */ 374 HTT_RX_CCK_11_LP = 0, 375 HTT_RX_CCK_5_5_LP = 1, 376 HTT_RX_CCK_2_LP, 377 HTT_RX_CCK_1_LP, 378 /* short preamble */ 379 HTT_RX_CCK_11_SP, 380 HTT_RX_CCK_5_5_SP, 381 HTT_RX_CCK_2_SP 382 }; 383 384 enum htt_rx_legacy_rate_type { 385 HTT_RX_LEGACY_RATE_OFDM = 0, 386 HTT_RX_LEGACY_RATE_CCK 387 }; 388 389 enum htt_rx_preamble_type { 390 HTT_RX_LEGACY = 0x4, 391 HTT_RX_HT = 0x8, 392 HTT_RX_HT_WITH_TXBF = 0x9, 393 HTT_RX_VHT = 0xC, 394 HTT_RX_VHT_WITH_TXBF = 0xD, 395 }; 396 397 /* 398 * Fields: phy_err_valid, phy_err_code, tsf, 399 * usec_timestamp, sub_usec_timestamp 400 * ..are valid only if end_valid == 1. 401 * 402 * Fields: rssi_chains, legacy_rate_type, 403 * legacy_rate_cck, preamble_type, service, 404 * vht_sig_* 405 * ..are valid only if start_valid == 1; 406 */ 407 struct htt_rx_indication_ppdu { 408 u8 combined_rssi; 409 u8 sub_usec_timestamp; 410 u8 phy_err_code; 411 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 412 struct { 413 u8 pri20_db; 414 u8 ext20_db; 415 u8 ext40_db; 416 u8 ext80_db; 417 } __packed rssi_chains[4]; 418 __le32 tsf; 419 __le32 usec_timestamp; 420 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 421 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 422 } __packed; 423 424 enum htt_rx_mpdu_status { 425 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 426 HTT_RX_IND_MPDU_STATUS_OK, 427 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 428 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 429 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 430 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 431 /* only accept EAPOL frames */ 432 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 433 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 434 /* Non-data in promiscous mode */ 435 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 436 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 437 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 438 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 439 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 440 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 441 442 /* 443 * MISC: discard for unspecified reasons. 444 * Leave this enum value last. 445 */ 446 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 447 }; 448 449 struct htt_rx_indication_mpdu_range { 450 u8 mpdu_count; 451 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 452 u8 pad0; 453 u8 pad1; 454 } __packed; 455 456 struct htt_rx_indication_prefix { 457 __le16 fw_rx_desc_bytes; 458 u8 pad0; 459 u8 pad1; 460 }; 461 462 struct htt_rx_indication { 463 struct htt_rx_indication_hdr hdr; 464 struct htt_rx_indication_ppdu ppdu; 465 struct htt_rx_indication_prefix prefix; 466 467 /* 468 * the following fields are both dynamically sized, so 469 * take care addressing them 470 */ 471 472 /* the size of this is %fw_rx_desc_bytes */ 473 struct fw_rx_desc_base fw_desc; 474 475 /* 476 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 477 * and has %num_mpdu_ranges elements. 478 */ 479 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 480 } __packed; 481 482 static inline struct htt_rx_indication_mpdu_range * 483 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 484 { 485 void *ptr = rx_ind; 486 487 ptr += sizeof(rx_ind->hdr) 488 + sizeof(rx_ind->ppdu) 489 + sizeof(rx_ind->prefix) 490 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 491 return ptr; 492 } 493 494 enum htt_rx_flush_mpdu_status { 495 HTT_RX_FLUSH_MPDU_DISCARD = 0, 496 HTT_RX_FLUSH_MPDU_REORDER = 1, 497 }; 498 499 /* 500 * htt_rx_flush - discard or reorder given range of mpdus 501 * 502 * Note: host must check if all sequence numbers between 503 * [seq_num_start, seq_num_end-1] are valid. 504 */ 505 struct htt_rx_flush { 506 __le16 peer_id; 507 u8 tid; 508 u8 rsvd0; 509 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 510 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 511 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 512 }; 513 514 struct htt_rx_peer_map { 515 u8 vdev_id; 516 __le16 peer_id; 517 u8 addr[6]; 518 u8 rsvd0; 519 u8 rsvd1; 520 } __packed; 521 522 struct htt_rx_peer_unmap { 523 u8 rsvd0; 524 __le16 peer_id; 525 } __packed; 526 527 enum htt_security_types { 528 HTT_SECURITY_NONE, 529 HTT_SECURITY_WEP128, 530 HTT_SECURITY_WEP104, 531 HTT_SECURITY_WEP40, 532 HTT_SECURITY_TKIP, 533 HTT_SECURITY_TKIP_NOMIC, 534 HTT_SECURITY_AES_CCMP, 535 HTT_SECURITY_WAPI, 536 537 HTT_NUM_SECURITY_TYPES /* keep this last! */ 538 }; 539 540 enum htt_security_flags { 541 #define HTT_SECURITY_TYPE_MASK 0x7F 542 #define HTT_SECURITY_TYPE_LSB 0 543 HTT_SECURITY_IS_UNICAST = 1 << 7 544 }; 545 546 struct htt_security_indication { 547 union { 548 /* dont use bitfields; undefined behaviour */ 549 u8 flags; /* %htt_security_flags */ 550 struct { 551 u8 security_type:7, /* %htt_security_types */ 552 is_unicast:1; 553 } __packed; 554 } __packed; 555 __le16 peer_id; 556 u8 michael_key[8]; 557 u8 wapi_rsc[16]; 558 } __packed; 559 560 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 561 #define HTT_RX_BA_INFO0_TID_LSB 0 562 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 563 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 564 565 struct htt_rx_addba { 566 u8 window_size; 567 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 568 } __packed; 569 570 struct htt_rx_delba { 571 u8 rsvd0; 572 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 573 } __packed; 574 575 enum htt_data_tx_status { 576 HTT_DATA_TX_STATUS_OK = 0, 577 HTT_DATA_TX_STATUS_DISCARD = 1, 578 HTT_DATA_TX_STATUS_NO_ACK = 2, 579 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 580 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 581 }; 582 583 enum htt_data_tx_flags { 584 #define HTT_DATA_TX_STATUS_MASK 0x07 585 #define HTT_DATA_TX_STATUS_LSB 0 586 #define HTT_DATA_TX_TID_MASK 0x78 587 #define HTT_DATA_TX_TID_LSB 3 588 HTT_DATA_TX_TID_INVALID = 1 << 7 589 }; 590 591 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 592 593 struct htt_data_tx_completion { 594 union { 595 u8 flags; 596 struct { 597 u8 status:3, 598 tid:4, 599 tid_invalid:1; 600 } __packed; 601 } __packed; 602 u8 num_msdus; 603 u8 rsvd0; 604 __le16 msdus[0]; /* variable length based on %num_msdus */ 605 } __packed; 606 607 struct htt_tx_compl_ind_base { 608 u32 hdr; 609 u16 payload[1/*or more*/]; 610 } __packed; 611 612 struct htt_rc_tx_done_params { 613 u32 rate_code; 614 u32 rate_code_flags; 615 u32 flags; 616 u32 num_enqued; /* 1 for non-AMPDU */ 617 u32 num_retries; 618 u32 num_failed; /* for AMPDU */ 619 u32 ack_rssi; 620 u32 time_stamp; 621 u32 is_probe; 622 }; 623 624 struct htt_rc_update { 625 u8 vdev_id; 626 __le16 peer_id; 627 u8 addr[6]; 628 u8 num_elems; 629 u8 rsvd0; 630 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 631 } __packed; 632 633 /* see htt_rx_indication for similar fields and descriptions */ 634 struct htt_rx_fragment_indication { 635 union { 636 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 637 struct { 638 u8 ext_tid:5, 639 flush_valid:1; 640 } __packed; 641 } __packed; 642 __le16 peer_id; 643 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 644 __le16 fw_rx_desc_bytes; 645 __le16 rsvd0; 646 647 u8 fw_msdu_rx_desc[0]; 648 } __packed; 649 650 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 651 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 652 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 653 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 654 655 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 656 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 657 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 658 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 659 660 /* 661 * target -> host test message definition 662 * 663 * The following field definitions describe the format of the test 664 * message sent from the target to the host. 665 * The message consists of a 4-octet header, followed by a variable 666 * number of 32-bit integer values, followed by a variable number 667 * of 8-bit character values. 668 * 669 * |31 16|15 8|7 0| 670 * |-----------------------------------------------------------| 671 * | num chars | num ints | msg type | 672 * |-----------------------------------------------------------| 673 * | int 0 | 674 * |-----------------------------------------------------------| 675 * | int 1 | 676 * |-----------------------------------------------------------| 677 * | ... | 678 * |-----------------------------------------------------------| 679 * | char 3 | char 2 | char 1 | char 0 | 680 * |-----------------------------------------------------------| 681 * | | | ... | char 4 | 682 * |-----------------------------------------------------------| 683 * - MSG_TYPE 684 * Bits 7:0 685 * Purpose: identifies this as a test message 686 * Value: HTT_MSG_TYPE_TEST 687 * - NUM_INTS 688 * Bits 15:8 689 * Purpose: indicate how many 32-bit integers follow the message header 690 * - NUM_CHARS 691 * Bits 31:16 692 * Purpose: indicate how many 8-bit charaters follow the series of integers 693 */ 694 struct htt_rx_test { 695 u8 num_ints; 696 __le16 num_chars; 697 698 /* payload consists of 2 lists: 699 * a) num_ints * sizeof(__le32) 700 * b) num_chars * sizeof(u8) aligned to 4bytes */ 701 u8 payload[0]; 702 } __packed; 703 704 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 705 { 706 return (__le32 *)rx_test->payload; 707 } 708 709 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 710 { 711 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 712 } 713 714 /* 715 * target -> host packet log message 716 * 717 * The following field definitions describe the format of the packet log 718 * message sent from the target to the host. 719 * The message consists of a 4-octet header,followed by a variable number 720 * of 32-bit character values. 721 * 722 * |31 24|23 16|15 8|7 0| 723 * |-----------------------------------------------------------| 724 * | | | | msg type | 725 * |-----------------------------------------------------------| 726 * | payload | 727 * |-----------------------------------------------------------| 728 * - MSG_TYPE 729 * Bits 7:0 730 * Purpose: identifies this as a test message 731 * Value: HTT_MSG_TYPE_PACKETLOG 732 */ 733 struct htt_pktlog_msg { 734 u8 pad[3]; 735 __le32 payload[1 /* or more */]; 736 } __packed; 737 738 struct htt_dbg_stats_rx_reorder_stats { 739 /* Non QoS MPDUs received */ 740 __le32 deliver_non_qos; 741 742 /* MPDUs received in-order */ 743 __le32 deliver_in_order; 744 745 /* Flush due to reorder timer expired */ 746 __le32 deliver_flush_timeout; 747 748 /* Flush due to move out of window */ 749 __le32 deliver_flush_oow; 750 751 /* Flush due to DELBA */ 752 __le32 deliver_flush_delba; 753 754 /* MPDUs dropped due to FCS error */ 755 __le32 fcs_error; 756 757 /* MPDUs dropped due to monitor mode non-data packet */ 758 __le32 mgmt_ctrl; 759 760 /* MPDUs dropped due to invalid peer */ 761 __le32 invalid_peer; 762 763 /* MPDUs dropped due to duplication (non aggregation) */ 764 __le32 dup_non_aggr; 765 766 /* MPDUs dropped due to processed before */ 767 __le32 dup_past; 768 769 /* MPDUs dropped due to duplicate in reorder queue */ 770 __le32 dup_in_reorder; 771 772 /* Reorder timeout happened */ 773 __le32 reorder_timeout; 774 775 /* invalid bar ssn */ 776 __le32 invalid_bar_ssn; 777 778 /* reorder reset due to bar ssn */ 779 __le32 ssn_reset; 780 }; 781 782 struct htt_dbg_stats_wal_tx_stats { 783 /* Num HTT cookies queued to dispatch list */ 784 __le32 comp_queued; 785 786 /* Num HTT cookies dispatched */ 787 __le32 comp_delivered; 788 789 /* Num MSDU queued to WAL */ 790 __le32 msdu_enqued; 791 792 /* Num MPDU queue to WAL */ 793 __le32 mpdu_enqued; 794 795 /* Num MSDUs dropped by WMM limit */ 796 __le32 wmm_drop; 797 798 /* Num Local frames queued */ 799 __le32 local_enqued; 800 801 /* Num Local frames done */ 802 __le32 local_freed; 803 804 /* Num queued to HW */ 805 __le32 hw_queued; 806 807 /* Num PPDU reaped from HW */ 808 __le32 hw_reaped; 809 810 /* Num underruns */ 811 __le32 underrun; 812 813 /* Num PPDUs cleaned up in TX abort */ 814 __le32 tx_abort; 815 816 /* Num MPDUs requed by SW */ 817 __le32 mpdus_requed; 818 819 /* excessive retries */ 820 __le32 tx_ko; 821 822 /* data hw rate code */ 823 __le32 data_rc; 824 825 /* Scheduler self triggers */ 826 __le32 self_triggers; 827 828 /* frames dropped due to excessive sw retries */ 829 __le32 sw_retry_failure; 830 831 /* illegal rate phy errors */ 832 __le32 illgl_rate_phy_err; 833 834 /* wal pdev continous xretry */ 835 __le32 pdev_cont_xretry; 836 837 /* wal pdev continous xretry */ 838 __le32 pdev_tx_timeout; 839 840 /* wal pdev resets */ 841 __le32 pdev_resets; 842 843 __le32 phy_underrun; 844 845 /* MPDU is more than txop limit */ 846 __le32 txop_ovf; 847 } __packed; 848 849 struct htt_dbg_stats_wal_rx_stats { 850 /* Cnts any change in ring routing mid-ppdu */ 851 __le32 mid_ppdu_route_change; 852 853 /* Total number of statuses processed */ 854 __le32 status_rcvd; 855 856 /* Extra frags on rings 0-3 */ 857 __le32 r0_frags; 858 __le32 r1_frags; 859 __le32 r2_frags; 860 __le32 r3_frags; 861 862 /* MSDUs / MPDUs delivered to HTT */ 863 __le32 htt_msdus; 864 __le32 htt_mpdus; 865 866 /* MSDUs / MPDUs delivered to local stack */ 867 __le32 loc_msdus; 868 __le32 loc_mpdus; 869 870 /* AMSDUs that have more MSDUs than the status ring size */ 871 __le32 oversize_amsdu; 872 873 /* Number of PHY errors */ 874 __le32 phy_errs; 875 876 /* Number of PHY errors drops */ 877 __le32 phy_err_drop; 878 879 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 880 __le32 mpdu_errs; 881 } __packed; 882 883 struct htt_dbg_stats_wal_peer_stats { 884 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 885 } __packed; 886 887 struct htt_dbg_stats_wal_pdev_txrx { 888 struct htt_dbg_stats_wal_tx_stats tx_stats; 889 struct htt_dbg_stats_wal_rx_stats rx_stats; 890 struct htt_dbg_stats_wal_peer_stats peer_stats; 891 } __packed; 892 893 struct htt_dbg_stats_rx_rate_info { 894 __le32 mcs[10]; 895 __le32 sgi[10]; 896 __le32 nss[4]; 897 __le32 stbc[10]; 898 __le32 bw[3]; 899 __le32 pream[6]; 900 __le32 ldpc; 901 __le32 txbf; 902 }; 903 904 /* 905 * htt_dbg_stats_status - 906 * present - The requested stats have been delivered in full. 907 * This indicates that either the stats information was contained 908 * in its entirety within this message, or else this message 909 * completes the delivery of the requested stats info that was 910 * partially delivered through earlier STATS_CONF messages. 911 * partial - The requested stats have been delivered in part. 912 * One or more subsequent STATS_CONF messages with the same 913 * cookie value will be sent to deliver the remainder of the 914 * information. 915 * error - The requested stats could not be delivered, for example due 916 * to a shortage of memory to construct a message holding the 917 * requested stats. 918 * invalid - The requested stat type is either not recognized, or the 919 * target is configured to not gather the stats type in question. 920 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 921 * series_done - This special value indicates that no further stats info 922 * elements are present within a series of stats info elems 923 * (within a stats upload confirmation message). 924 */ 925 enum htt_dbg_stats_status { 926 HTT_DBG_STATS_STATUS_PRESENT = 0, 927 HTT_DBG_STATS_STATUS_PARTIAL = 1, 928 HTT_DBG_STATS_STATUS_ERROR = 2, 929 HTT_DBG_STATS_STATUS_INVALID = 3, 930 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 931 }; 932 933 /* 934 * target -> host statistics upload 935 * 936 * The following field definitions describe the format of the HTT target 937 * to host stats upload confirmation message. 938 * The message contains a cookie echoed from the HTT host->target stats 939 * upload request, which identifies which request the confirmation is 940 * for, and a series of tag-length-value stats information elements. 941 * The tag-length header for each stats info element also includes a 942 * status field, to indicate whether the request for the stat type in 943 * question was fully met, partially met, unable to be met, or invalid 944 * (if the stat type in question is disabled in the target). 945 * A special value of all 1's in this status field is used to indicate 946 * the end of the series of stats info elements. 947 * 948 * 949 * |31 16|15 8|7 5|4 0| 950 * |------------------------------------------------------------| 951 * | reserved | msg type | 952 * |------------------------------------------------------------| 953 * | cookie LSBs | 954 * |------------------------------------------------------------| 955 * | cookie MSBs | 956 * |------------------------------------------------------------| 957 * | stats entry length | reserved | S |stat type| 958 * |------------------------------------------------------------| 959 * | | 960 * | type-specific stats info | 961 * | | 962 * |------------------------------------------------------------| 963 * | stats entry length | reserved | S |stat type| 964 * |------------------------------------------------------------| 965 * | | 966 * | type-specific stats info | 967 * | | 968 * |------------------------------------------------------------| 969 * | n/a | reserved | 111 | n/a | 970 * |------------------------------------------------------------| 971 * Header fields: 972 * - MSG_TYPE 973 * Bits 7:0 974 * Purpose: identifies this is a statistics upload confirmation message 975 * Value: 0x9 976 * - COOKIE_LSBS 977 * Bits 31:0 978 * Purpose: Provide a mechanism to match a target->host stats confirmation 979 * message with its preceding host->target stats request message. 980 * Value: LSBs of the opaque cookie specified by the host-side requestor 981 * - COOKIE_MSBS 982 * Bits 31:0 983 * Purpose: Provide a mechanism to match a target->host stats confirmation 984 * message with its preceding host->target stats request message. 985 * Value: MSBs of the opaque cookie specified by the host-side requestor 986 * 987 * Stats Information Element tag-length header fields: 988 * - STAT_TYPE 989 * Bits 4:0 990 * Purpose: identifies the type of statistics info held in the 991 * following information element 992 * Value: htt_dbg_stats_type 993 * - STATUS 994 * Bits 7:5 995 * Purpose: indicate whether the requested stats are present 996 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 997 * the completion of the stats entry series 998 * - LENGTH 999 * Bits 31:16 1000 * Purpose: indicate the stats information size 1001 * Value: This field specifies the number of bytes of stats information 1002 * that follows the element tag-length header. 1003 * It is expected but not required that this length is a multiple of 1004 * 4 bytes. Even if the length is not an integer multiple of 4, the 1005 * subsequent stats entry header will begin on a 4-byte aligned 1006 * boundary. 1007 */ 1008 1009 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1010 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1011 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1012 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1013 1014 struct htt_stats_conf_item { 1015 union { 1016 u8 info; 1017 struct { 1018 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1019 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1020 } __packed; 1021 } __packed; 1022 u8 pad; 1023 __le16 length; 1024 u8 payload[0]; /* roundup(length, 4) long */ 1025 } __packed; 1026 1027 struct htt_stats_conf { 1028 u8 pad[3]; 1029 __le32 cookie_lsb; 1030 __le32 cookie_msb; 1031 1032 /* each item has variable length! */ 1033 struct htt_stats_conf_item items[0]; 1034 } __packed; 1035 1036 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1037 const struct htt_stats_conf_item *item) 1038 { 1039 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1040 } 1041 /* 1042 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1043 * 1044 * The following field definitions describe the format of the HTT host 1045 * to target frag_desc/msdu_ext bank configuration message. 1046 * The message contains the based address and the min and max id of the 1047 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1048 * MSDU_EXT/FRAG_DESC. 1049 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1050 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1051 * the hardware does the mapping/translation. 1052 * 1053 * Total banks that can be configured is configured to 16. 1054 * 1055 * This should be called before any TX has be initiated by the HTT 1056 * 1057 * |31 16|15 8|7 5|4 0| 1058 * |------------------------------------------------------------| 1059 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1060 * |------------------------------------------------------------| 1061 * | BANK0_BASE_ADDRESS | 1062 * |------------------------------------------------------------| 1063 * | ... | 1064 * |------------------------------------------------------------| 1065 * | BANK15_BASE_ADDRESS | 1066 * |------------------------------------------------------------| 1067 * | BANK0_MAX_ID | BANK0_MIN_ID | 1068 * |------------------------------------------------------------| 1069 * | ... | 1070 * |------------------------------------------------------------| 1071 * | BANK15_MAX_ID | BANK15_MIN_ID | 1072 * |------------------------------------------------------------| 1073 * Header fields: 1074 * - MSG_TYPE 1075 * Bits 7:0 1076 * Value: 0x6 1077 * - BANKx_BASE_ADDRESS 1078 * Bits 31:0 1079 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1080 * bank physical/bus address. 1081 * - BANKx_MIN_ID 1082 * Bits 15:0 1083 * Purpose: Provide a mechanism to specify the min index that needs to 1084 * mapped. 1085 * - BANKx_MAX_ID 1086 * Bits 31:16 1087 * Purpose: Provide a mechanism to specify the max index that needs to 1088 * 1089 */ 1090 struct htt_frag_desc_bank_id { 1091 __le16 bank_min_id; 1092 __le16 bank_max_id; 1093 } __packed; 1094 1095 /* real is 16 but it wouldn't fit in the max htt message size 1096 * so we use a conservatively safe value for now */ 1097 #define HTT_FRAG_DESC_BANK_MAX 4 1098 1099 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1100 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1101 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP (1 << 2) 1102 1103 struct htt_frag_desc_bank_cfg { 1104 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1105 u8 num_banks; 1106 u8 desc_size; 1107 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1108 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1109 } __packed; 1110 1111 union htt_rx_pn_t { 1112 /* WEP: 24-bit PN */ 1113 u32 pn24; 1114 1115 /* TKIP or CCMP: 48-bit PN */ 1116 u_int64_t pn48; 1117 1118 /* WAPI: 128-bit PN */ 1119 u_int64_t pn128[2]; 1120 }; 1121 1122 struct htt_cmd { 1123 struct htt_cmd_hdr hdr; 1124 union { 1125 struct htt_ver_req ver_req; 1126 struct htt_mgmt_tx_desc mgmt_tx; 1127 struct htt_data_tx_desc data_tx; 1128 struct htt_rx_ring_setup rx_setup; 1129 struct htt_stats_req stats_req; 1130 struct htt_oob_sync_req oob_sync_req; 1131 struct htt_aggr_conf aggr_conf; 1132 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg; 1133 }; 1134 } __packed; 1135 1136 struct htt_resp { 1137 struct htt_resp_hdr hdr; 1138 union { 1139 struct htt_ver_resp ver_resp; 1140 struct htt_mgmt_tx_completion mgmt_tx_completion; 1141 struct htt_data_tx_completion data_tx_completion; 1142 struct htt_rx_indication rx_ind; 1143 struct htt_rx_fragment_indication rx_frag_ind; 1144 struct htt_rx_peer_map peer_map; 1145 struct htt_rx_peer_unmap peer_unmap; 1146 struct htt_rx_flush rx_flush; 1147 struct htt_rx_addba rx_addba; 1148 struct htt_rx_delba rx_delba; 1149 struct htt_security_indication security_indication; 1150 struct htt_rc_update rc_update; 1151 struct htt_rx_test rx_test; 1152 struct htt_pktlog_msg pktlog_msg; 1153 struct htt_stats_conf stats_conf; 1154 }; 1155 } __packed; 1156 1157 1158 /*** host side structures follow ***/ 1159 1160 struct htt_tx_done { 1161 u32 msdu_id; 1162 bool discard; 1163 bool no_ack; 1164 }; 1165 1166 struct htt_peer_map_event { 1167 u8 vdev_id; 1168 u16 peer_id; 1169 u8 addr[ETH_ALEN]; 1170 }; 1171 1172 struct htt_peer_unmap_event { 1173 u16 peer_id; 1174 }; 1175 1176 struct ath10k_htt_txbuf { 1177 struct htt_data_tx_desc_frag frags[2]; 1178 struct ath10k_htc_hdr htc_hdr; 1179 struct htt_cmd_hdr cmd_hdr; 1180 struct htt_data_tx_desc cmd_tx; 1181 } __packed; 1182 1183 struct ath10k_htt { 1184 struct ath10k *ar; 1185 enum ath10k_htc_ep_id eid; 1186 1187 int max_throughput_mbps; 1188 u8 target_version_major; 1189 u8 target_version_minor; 1190 struct completion target_version_received; 1191 1192 struct { 1193 /* 1194 * Ring of network buffer objects - This ring is 1195 * used exclusively by the host SW. This ring 1196 * mirrors the dev_addrs_ring that is shared 1197 * between the host SW and the MAC HW. The host SW 1198 * uses this netbufs ring to locate the network 1199 * buffer objects whose data buffers the HW has 1200 * filled. 1201 */ 1202 struct sk_buff **netbufs_ring; 1203 /* 1204 * Ring of buffer addresses - 1205 * This ring holds the "physical" device address of the 1206 * rx buffers the host SW provides for the MAC HW to 1207 * fill. 1208 */ 1209 __le32 *paddrs_ring; 1210 1211 /* 1212 * Base address of ring, as a "physical" device address 1213 * rather than a CPU address. 1214 */ 1215 dma_addr_t base_paddr; 1216 1217 /* how many elems in the ring (power of 2) */ 1218 int size; 1219 1220 /* size - 1 */ 1221 unsigned size_mask; 1222 1223 /* how many rx buffers to keep in the ring */ 1224 int fill_level; 1225 1226 /* how many rx buffers (full+empty) are in the ring */ 1227 int fill_cnt; 1228 1229 /* 1230 * alloc_idx - where HTT SW has deposited empty buffers 1231 * This is allocated in consistent mem, so that the FW can 1232 * read this variable, and program the HW's FW_IDX reg with 1233 * the value of this shadow register. 1234 */ 1235 struct { 1236 __le32 *vaddr; 1237 dma_addr_t paddr; 1238 } alloc_idx; 1239 1240 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1241 struct { 1242 unsigned msdu_payld; 1243 } sw_rd_idx; 1244 1245 /* 1246 * refill_retry_timer - timer triggered when the ring is 1247 * not refilled to the level expected 1248 */ 1249 struct timer_list refill_retry_timer; 1250 1251 /* Protects access to all rx ring buffer state variables */ 1252 spinlock_t lock; 1253 } rx_ring; 1254 1255 unsigned int prefetch_len; 1256 1257 /* Protects access to %pending_tx, %used_msdu_ids */ 1258 spinlock_t tx_lock; 1259 int max_num_pending_tx; 1260 int num_pending_tx; 1261 struct sk_buff **pending_tx; 1262 unsigned long *used_msdu_ids; /* bitmap */ 1263 wait_queue_head_t empty_tx_wq; 1264 struct dma_pool *tx_pool; 1265 1266 /* set if host-fw communication goes haywire 1267 * used to avoid further failures */ 1268 bool rx_confused; 1269 struct tasklet_struct rx_replenish_task; 1270 1271 /* This is used to group tx/rx completions separately and process them 1272 * in batches to reduce cache stalls */ 1273 struct tasklet_struct txrx_compl_task; 1274 struct sk_buff_head tx_compl_q; 1275 struct sk_buff_head rx_compl_q; 1276 1277 /* rx_status template */ 1278 struct ieee80211_rx_status rx_status; 1279 }; 1280 1281 #define RX_HTT_HDR_STATUS_LEN 64 1282 1283 /* This structure layout is programmed via rx ring setup 1284 * so that FW knows how to transfer the rx descriptor to the host. 1285 * Buffers like this are placed on the rx ring. */ 1286 struct htt_rx_desc { 1287 union { 1288 /* This field is filled on the host using the msdu buffer 1289 * from htt_rx_indication */ 1290 struct fw_rx_desc_base fw_desc; 1291 u32 pad; 1292 } __packed; 1293 struct { 1294 struct rx_attention attention; 1295 struct rx_frag_info frag_info; 1296 struct rx_mpdu_start mpdu_start; 1297 struct rx_msdu_start msdu_start; 1298 struct rx_msdu_end msdu_end; 1299 struct rx_mpdu_end mpdu_end; 1300 struct rx_ppdu_start ppdu_start; 1301 struct rx_ppdu_end ppdu_end; 1302 } __packed; 1303 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1304 u8 msdu_payload[0]; 1305 }; 1306 1307 #define HTT_RX_DESC_ALIGN 8 1308 1309 #define HTT_MAC_ADDR_LEN 6 1310 1311 /* 1312 * FIX THIS 1313 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 1314 * rounded up to a cache line size. 1315 */ 1316 #define HTT_RX_BUF_SIZE 1920 1317 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 1318 1319 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 1320 * aggregated traffic more nicely. */ 1321 #define ATH10K_HTT_MAX_NUM_REFILL 16 1322 1323 /* 1324 * DMA_MAP expects the buffer to be an integral number of cache lines. 1325 * Rather than checking the actual cache line size, this code makes a 1326 * conservative estimate of what the cache line size could be. 1327 */ 1328 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 1329 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 1330 1331 int ath10k_htt_connect(struct ath10k_htt *htt); 1332 int ath10k_htt_init(struct ath10k *ar); 1333 int ath10k_htt_setup(struct ath10k_htt *htt); 1334 1335 int ath10k_htt_tx_alloc(struct ath10k_htt *htt); 1336 void ath10k_htt_tx_free(struct ath10k_htt *htt); 1337 1338 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 1339 void ath10k_htt_rx_free(struct ath10k_htt *htt); 1340 1341 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1342 void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1343 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 1344 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 1345 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt); 1346 1347 void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 1348 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt); 1349 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 1350 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *); 1351 int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *); 1352 1353 #endif 1354