1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HTT_H_ 19 #define _HTT_H_ 20 21 #include <linux/bug.h> 22 #include <linux/interrupt.h> 23 24 #include "htc.h" 25 #include "rx_desc.h" 26 27 enum htt_dbg_stats_type { 28 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 29 HTT_DBG_STATS_RX_REORDER = 1 << 1, 30 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 31 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 32 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 33 /* bits 5-23 currently reserved */ 34 35 HTT_DBG_NUM_STATS /* keep this last */ 36 }; 37 38 enum htt_h2t_msg_type { /* host-to-target */ 39 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 40 HTT_H2T_MSG_TYPE_TX_FRM = 1, 41 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 42 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 43 HTT_H2T_MSG_TYPE_SYNC = 4, 44 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 45 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 46 47 /* This command is used for sending management frames in HTT < 3.0. 48 * HTT >= 3.0 uses TX_FRM for everything. */ 49 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 50 51 HTT_H2T_NUM_MSGS /* keep this last */ 52 }; 53 54 struct htt_cmd_hdr { 55 u8 msg_type; 56 } __packed; 57 58 struct htt_ver_req { 59 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 60 } __packed; 61 62 /* 63 * HTT tx MSDU descriptor 64 * 65 * The HTT tx MSDU descriptor is created by the host HTT SW for each 66 * tx MSDU. The HTT tx MSDU descriptor contains the information that 67 * the target firmware needs for the FW's tx processing, particularly 68 * for creating the HW msdu descriptor. 69 * The same HTT tx descriptor is used for HL and LL systems, though 70 * a few fields within the tx descriptor are used only by LL or 71 * only by HL. 72 * The HTT tx descriptor is defined in two manners: by a struct with 73 * bitfields, and by a series of [dword offset, bit mask, bit shift] 74 * definitions. 75 * The target should use the struct def, for simplicitly and clarity, 76 * but the host shall use the bit-mast + bit-shift defs, to be endian- 77 * neutral. Specifically, the host shall use the get/set macros built 78 * around the mask + shift defs. 79 */ 80 struct htt_data_tx_desc_frag { 81 __le32 paddr; 82 __le32 len; 83 } __packed; 84 85 enum htt_data_tx_desc_flags0 { 86 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 87 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 88 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 89 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 90 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 91 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 92 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 93 }; 94 95 enum htt_data_tx_desc_flags1 { 96 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 97 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 98 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 99 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 100 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 101 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 102 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 103 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 104 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 105 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 106 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 107 }; 108 109 enum htt_data_tx_ext_tid { 110 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 111 HTT_DATA_TX_EXT_TID_MGMT = 17, 112 HTT_DATA_TX_EXT_TID_INVALID = 31 113 }; 114 115 #define HTT_INVALID_PEERID 0xFFFF 116 117 /* 118 * htt_data_tx_desc - used for data tx path 119 * 120 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 121 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 122 * for special kinds of tids 123 * postponed: only for HL hosts. indicates if this is a resend 124 * (HL hosts manage queues on the host ) 125 * more_in_batch: only for HL hosts. indicates if more packets are 126 * pending. this allows target to wait and aggregate 127 */ 128 struct htt_data_tx_desc { 129 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 130 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 131 __le16 len; 132 __le16 id; 133 __le32 frags_paddr; 134 __le32 peerid; 135 u8 prefetch[0]; /* start of frame, for FW classification engine */ 136 } __packed; 137 138 enum htt_rx_ring_flags { 139 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 140 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 141 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 142 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 143 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 144 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 145 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 146 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 147 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 148 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 149 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 150 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 151 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 152 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 153 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 154 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 155 }; 156 157 struct htt_rx_ring_setup_ring { 158 __le32 fw_idx_shadow_reg_paddr; 159 __le32 rx_ring_base_paddr; 160 __le16 rx_ring_len; /* in 4-byte words */ 161 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 162 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 163 __le16 fw_idx_init_val; 164 165 /* the following offsets are in 4-byte units */ 166 __le16 mac80211_hdr_offset; 167 __le16 msdu_payload_offset; 168 __le16 ppdu_start_offset; 169 __le16 ppdu_end_offset; 170 __le16 mpdu_start_offset; 171 __le16 mpdu_end_offset; 172 __le16 msdu_start_offset; 173 __le16 msdu_end_offset; 174 __le16 rx_attention_offset; 175 __le16 frag_info_offset; 176 } __packed; 177 178 struct htt_rx_ring_setup_hdr { 179 u8 num_rings; /* supported values: 1, 2 */ 180 __le16 rsvd0; 181 } __packed; 182 183 struct htt_rx_ring_setup { 184 struct htt_rx_ring_setup_hdr hdr; 185 struct htt_rx_ring_setup_ring rings[0]; 186 } __packed; 187 188 /* 189 * htt_stats_req - request target to send specified statistics 190 * 191 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 192 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 193 * so make sure its little-endian. 194 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 195 * so make sure its little-endian. 196 * @cfg_val: stat_type specific configuration 197 * @stat_type: see %htt_dbg_stats_type 198 * @cookie_lsb: used for confirmation message from target->host 199 * @cookie_msb: ditto as %cookie 200 */ 201 struct htt_stats_req { 202 u8 upload_types[3]; 203 u8 rsvd0; 204 u8 reset_types[3]; 205 struct { 206 u8 mpdu_bytes; 207 u8 mpdu_num_msdus; 208 u8 msdu_bytes; 209 } __packed; 210 u8 stat_type; 211 __le32 cookie_lsb; 212 __le32 cookie_msb; 213 } __packed; 214 215 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 216 217 /* 218 * htt_oob_sync_req - request out-of-band sync 219 * 220 * The HTT SYNC tells the target to suspend processing of subsequent 221 * HTT host-to-target messages until some other target agent locally 222 * informs the target HTT FW that the current sync counter is equal to 223 * or greater than (in a modulo sense) the sync counter specified in 224 * the SYNC message. 225 * 226 * This allows other host-target components to synchronize their operation 227 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 228 * security key has been downloaded to and activated by the target. 229 * In the absence of any explicit synchronization counter value 230 * specification, the target HTT FW will use zero as the default current 231 * sync value. 232 * 233 * The HTT target FW will suspend its host->target message processing as long 234 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 235 */ 236 struct htt_oob_sync_req { 237 u8 sync_count; 238 __le16 rsvd0; 239 } __packed; 240 241 #define HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_MASK 0x1F 242 #define HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_LSB 0 243 244 struct htt_aggr_conf { 245 u8 max_num_ampdu_subframes; 246 union { 247 /* dont use bitfields; undefined behaviour */ 248 u8 flags; /* see %HTT_AGGR_CONF_MAX_NUM_AMSDU_SUBFRAMES_ */ 249 u8 max_num_amsdu_subframes:5; 250 } __packed; 251 } __packed; 252 253 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 254 255 struct htt_mgmt_tx_desc { 256 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 257 __le32 msdu_paddr; 258 __le32 desc_id; 259 __le32 len; 260 __le32 vdev_id; 261 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 262 } __packed; 263 264 enum htt_mgmt_tx_status { 265 HTT_MGMT_TX_STATUS_OK = 0, 266 HTT_MGMT_TX_STATUS_RETRY = 1, 267 HTT_MGMT_TX_STATUS_DROP = 2 268 }; 269 270 /*=== target -> host messages ===============================================*/ 271 272 273 enum htt_t2h_msg_type { 274 HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0, 275 HTT_T2H_MSG_TYPE_RX_IND = 0x1, 276 HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2, 277 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 278 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 279 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 280 HTT_T2H_MSG_TYPE_RX_DELBA = 0x6, 281 HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 282 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 283 HTT_T2H_MSG_TYPE_STATS_CONF = 0x9, 284 HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 285 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 286 HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 287 HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 288 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION = 0xe, 289 HTT_T2H_MSG_TYPE_TEST, 290 /* keep this last */ 291 HTT_T2H_NUM_MSGS 292 }; 293 294 /* 295 * htt_resp_hdr - header for target-to-host messages 296 * 297 * msg_type: see htt_t2h_msg_type 298 */ 299 struct htt_resp_hdr { 300 u8 msg_type; 301 } __packed; 302 303 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 304 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 305 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 306 307 /* htt_ver_resp - response sent for htt_ver_req */ 308 struct htt_ver_resp { 309 u8 minor; 310 u8 major; 311 u8 rsvd0; 312 } __packed; 313 314 struct htt_mgmt_tx_completion { 315 u8 rsvd0; 316 u8 rsvd1; 317 u8 rsvd2; 318 __le32 desc_id; 319 __le32 status; 320 } __packed; 321 322 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x3F) 323 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 324 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 6) 325 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 7) 326 327 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 328 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 329 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 330 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 331 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 332 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 333 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 334 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 335 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 336 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 337 338 struct htt_rx_indication_hdr { 339 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 340 __le16 peer_id; 341 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 342 } __packed; 343 344 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 345 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 346 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 347 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 348 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 349 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 350 351 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 352 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 353 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 354 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 355 356 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 357 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 358 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 359 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 360 361 enum htt_rx_legacy_rate { 362 HTT_RX_OFDM_48 = 0, 363 HTT_RX_OFDM_24 = 1, 364 HTT_RX_OFDM_12, 365 HTT_RX_OFDM_6, 366 HTT_RX_OFDM_54, 367 HTT_RX_OFDM_36, 368 HTT_RX_OFDM_18, 369 HTT_RX_OFDM_9, 370 371 /* long preamble */ 372 HTT_RX_CCK_11_LP = 0, 373 HTT_RX_CCK_5_5_LP = 1, 374 HTT_RX_CCK_2_LP, 375 HTT_RX_CCK_1_LP, 376 /* short preamble */ 377 HTT_RX_CCK_11_SP, 378 HTT_RX_CCK_5_5_SP, 379 HTT_RX_CCK_2_SP 380 }; 381 382 enum htt_rx_legacy_rate_type { 383 HTT_RX_LEGACY_RATE_OFDM = 0, 384 HTT_RX_LEGACY_RATE_CCK 385 }; 386 387 enum htt_rx_preamble_type { 388 HTT_RX_LEGACY = 0x4, 389 HTT_RX_HT = 0x8, 390 HTT_RX_HT_WITH_TXBF = 0x9, 391 HTT_RX_VHT = 0xC, 392 HTT_RX_VHT_WITH_TXBF = 0xD, 393 }; 394 395 /* 396 * Fields: phy_err_valid, phy_err_code, tsf, 397 * usec_timestamp, sub_usec_timestamp 398 * ..are valid only if end_valid == 1. 399 * 400 * Fields: rssi_chains, legacy_rate_type, 401 * legacy_rate_cck, preamble_type, service, 402 * vht_sig_* 403 * ..are valid only if start_valid == 1; 404 */ 405 struct htt_rx_indication_ppdu { 406 u8 combined_rssi; 407 u8 sub_usec_timestamp; 408 u8 phy_err_code; 409 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 410 struct { 411 u8 pri20_db; 412 u8 ext20_db; 413 u8 ext40_db; 414 u8 ext80_db; 415 } __packed rssi_chains[4]; 416 __le32 tsf; 417 __le32 usec_timestamp; 418 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 419 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 420 } __packed; 421 422 enum htt_rx_mpdu_status { 423 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 424 HTT_RX_IND_MPDU_STATUS_OK, 425 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 426 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 427 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 428 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 429 /* only accept EAPOL frames */ 430 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 431 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 432 /* Non-data in promiscous mode */ 433 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 434 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 435 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 436 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 437 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 438 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 439 440 /* 441 * MISC: discard for unspecified reasons. 442 * Leave this enum value last. 443 */ 444 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 445 }; 446 447 struct htt_rx_indication_mpdu_range { 448 u8 mpdu_count; 449 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 450 u8 pad0; 451 u8 pad1; 452 } __packed; 453 454 struct htt_rx_indication_prefix { 455 __le16 fw_rx_desc_bytes; 456 u8 pad0; 457 u8 pad1; 458 }; 459 460 struct htt_rx_indication { 461 struct htt_rx_indication_hdr hdr; 462 struct htt_rx_indication_ppdu ppdu; 463 struct htt_rx_indication_prefix prefix; 464 465 /* 466 * the following fields are both dynamically sized, so 467 * take care addressing them 468 */ 469 470 /* the size of this is %fw_rx_desc_bytes */ 471 struct fw_rx_desc_base fw_desc; 472 473 /* 474 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 475 * and has %num_mpdu_ranges elements. 476 */ 477 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 478 } __packed; 479 480 static inline struct htt_rx_indication_mpdu_range * 481 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 482 { 483 void *ptr = rx_ind; 484 485 ptr += sizeof(rx_ind->hdr) 486 + sizeof(rx_ind->ppdu) 487 + sizeof(rx_ind->prefix) 488 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 489 return ptr; 490 } 491 492 enum htt_rx_flush_mpdu_status { 493 HTT_RX_FLUSH_MPDU_DISCARD = 0, 494 HTT_RX_FLUSH_MPDU_REORDER = 1, 495 }; 496 497 /* 498 * htt_rx_flush - discard or reorder given range of mpdus 499 * 500 * Note: host must check if all sequence numbers between 501 * [seq_num_start, seq_num_end-1] are valid. 502 */ 503 struct htt_rx_flush { 504 __le16 peer_id; 505 u8 tid; 506 u8 rsvd0; 507 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 508 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 509 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 510 }; 511 512 struct htt_rx_peer_map { 513 u8 vdev_id; 514 __le16 peer_id; 515 u8 addr[6]; 516 u8 rsvd0; 517 u8 rsvd1; 518 } __packed; 519 520 struct htt_rx_peer_unmap { 521 u8 rsvd0; 522 __le16 peer_id; 523 } __packed; 524 525 enum htt_security_types { 526 HTT_SECURITY_NONE, 527 HTT_SECURITY_WEP128, 528 HTT_SECURITY_WEP104, 529 HTT_SECURITY_WEP40, 530 HTT_SECURITY_TKIP, 531 HTT_SECURITY_TKIP_NOMIC, 532 HTT_SECURITY_AES_CCMP, 533 HTT_SECURITY_WAPI, 534 535 HTT_NUM_SECURITY_TYPES /* keep this last! */ 536 }; 537 538 enum htt_security_flags { 539 #define HTT_SECURITY_TYPE_MASK 0x7F 540 #define HTT_SECURITY_TYPE_LSB 0 541 HTT_SECURITY_IS_UNICAST = 1 << 7 542 }; 543 544 struct htt_security_indication { 545 union { 546 /* dont use bitfields; undefined behaviour */ 547 u8 flags; /* %htt_security_flags */ 548 struct { 549 u8 security_type:7, /* %htt_security_types */ 550 is_unicast:1; 551 } __packed; 552 } __packed; 553 __le16 peer_id; 554 u8 michael_key[8]; 555 u8 wapi_rsc[16]; 556 } __packed; 557 558 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 559 #define HTT_RX_BA_INFO0_TID_LSB 0 560 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 561 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 562 563 struct htt_rx_addba { 564 u8 window_size; 565 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 566 } __packed; 567 568 struct htt_rx_delba { 569 u8 rsvd0; 570 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 571 } __packed; 572 573 enum htt_data_tx_status { 574 HTT_DATA_TX_STATUS_OK = 0, 575 HTT_DATA_TX_STATUS_DISCARD = 1, 576 HTT_DATA_TX_STATUS_NO_ACK = 2, 577 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 578 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 579 }; 580 581 enum htt_data_tx_flags { 582 #define HTT_DATA_TX_STATUS_MASK 0x07 583 #define HTT_DATA_TX_STATUS_LSB 0 584 #define HTT_DATA_TX_TID_MASK 0x78 585 #define HTT_DATA_TX_TID_LSB 3 586 HTT_DATA_TX_TID_INVALID = 1 << 7 587 }; 588 589 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 590 591 struct htt_data_tx_completion { 592 union { 593 u8 flags; 594 struct { 595 u8 status:3, 596 tid:4, 597 tid_invalid:1; 598 } __packed; 599 } __packed; 600 u8 num_msdus; 601 u8 rsvd0; 602 __le16 msdus[0]; /* variable length based on %num_msdus */ 603 } __packed; 604 605 struct htt_tx_compl_ind_base { 606 u32 hdr; 607 u16 payload[1/*or more*/]; 608 } __packed; 609 610 struct htt_rc_tx_done_params { 611 u32 rate_code; 612 u32 rate_code_flags; 613 u32 flags; 614 u32 num_enqued; /* 1 for non-AMPDU */ 615 u32 num_retries; 616 u32 num_failed; /* for AMPDU */ 617 u32 ack_rssi; 618 u32 time_stamp; 619 u32 is_probe; 620 }; 621 622 struct htt_rc_update { 623 u8 vdev_id; 624 __le16 peer_id; 625 u8 addr[6]; 626 u8 num_elems; 627 u8 rsvd0; 628 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 629 } __packed; 630 631 /* see htt_rx_indication for similar fields and descriptions */ 632 struct htt_rx_fragment_indication { 633 union { 634 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 635 struct { 636 u8 ext_tid:5, 637 flush_valid:1; 638 } __packed; 639 } __packed; 640 __le16 peer_id; 641 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 642 __le16 fw_rx_desc_bytes; 643 __le16 rsvd0; 644 645 u8 fw_msdu_rx_desc[0]; 646 } __packed; 647 648 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 649 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 650 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 651 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 652 653 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 654 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 655 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 656 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 657 658 /* 659 * target -> host test message definition 660 * 661 * The following field definitions describe the format of the test 662 * message sent from the target to the host. 663 * The message consists of a 4-octet header, followed by a variable 664 * number of 32-bit integer values, followed by a variable number 665 * of 8-bit character values. 666 * 667 * |31 16|15 8|7 0| 668 * |-----------------------------------------------------------| 669 * | num chars | num ints | msg type | 670 * |-----------------------------------------------------------| 671 * | int 0 | 672 * |-----------------------------------------------------------| 673 * | int 1 | 674 * |-----------------------------------------------------------| 675 * | ... | 676 * |-----------------------------------------------------------| 677 * | char 3 | char 2 | char 1 | char 0 | 678 * |-----------------------------------------------------------| 679 * | | | ... | char 4 | 680 * |-----------------------------------------------------------| 681 * - MSG_TYPE 682 * Bits 7:0 683 * Purpose: identifies this as a test message 684 * Value: HTT_MSG_TYPE_TEST 685 * - NUM_INTS 686 * Bits 15:8 687 * Purpose: indicate how many 32-bit integers follow the message header 688 * - NUM_CHARS 689 * Bits 31:16 690 * Purpose: indicate how many 8-bit charaters follow the series of integers 691 */ 692 struct htt_rx_test { 693 u8 num_ints; 694 __le16 num_chars; 695 696 /* payload consists of 2 lists: 697 * a) num_ints * sizeof(__le32) 698 * b) num_chars * sizeof(u8) aligned to 4bytes */ 699 u8 payload[0]; 700 } __packed; 701 702 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 703 { 704 return (__le32 *)rx_test->payload; 705 } 706 707 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 708 { 709 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 710 } 711 712 /* 713 * target -> host packet log message 714 * 715 * The following field definitions describe the format of the packet log 716 * message sent from the target to the host. 717 * The message consists of a 4-octet header,followed by a variable number 718 * of 32-bit character values. 719 * 720 * |31 24|23 16|15 8|7 0| 721 * |-----------------------------------------------------------| 722 * | | | | msg type | 723 * |-----------------------------------------------------------| 724 * | payload | 725 * |-----------------------------------------------------------| 726 * - MSG_TYPE 727 * Bits 7:0 728 * Purpose: identifies this as a test message 729 * Value: HTT_MSG_TYPE_PACKETLOG 730 */ 731 struct htt_pktlog_msg { 732 u8 pad[3]; 733 __le32 payload[1 /* or more */]; 734 } __packed; 735 736 struct htt_dbg_stats_rx_reorder_stats { 737 /* Non QoS MPDUs received */ 738 __le32 deliver_non_qos; 739 740 /* MPDUs received in-order */ 741 __le32 deliver_in_order; 742 743 /* Flush due to reorder timer expired */ 744 __le32 deliver_flush_timeout; 745 746 /* Flush due to move out of window */ 747 __le32 deliver_flush_oow; 748 749 /* Flush due to DELBA */ 750 __le32 deliver_flush_delba; 751 752 /* MPDUs dropped due to FCS error */ 753 __le32 fcs_error; 754 755 /* MPDUs dropped due to monitor mode non-data packet */ 756 __le32 mgmt_ctrl; 757 758 /* MPDUs dropped due to invalid peer */ 759 __le32 invalid_peer; 760 761 /* MPDUs dropped due to duplication (non aggregation) */ 762 __le32 dup_non_aggr; 763 764 /* MPDUs dropped due to processed before */ 765 __le32 dup_past; 766 767 /* MPDUs dropped due to duplicate in reorder queue */ 768 __le32 dup_in_reorder; 769 770 /* Reorder timeout happened */ 771 __le32 reorder_timeout; 772 773 /* invalid bar ssn */ 774 __le32 invalid_bar_ssn; 775 776 /* reorder reset due to bar ssn */ 777 __le32 ssn_reset; 778 }; 779 780 struct htt_dbg_stats_wal_tx_stats { 781 /* Num HTT cookies queued to dispatch list */ 782 __le32 comp_queued; 783 784 /* Num HTT cookies dispatched */ 785 __le32 comp_delivered; 786 787 /* Num MSDU queued to WAL */ 788 __le32 msdu_enqued; 789 790 /* Num MPDU queue to WAL */ 791 __le32 mpdu_enqued; 792 793 /* Num MSDUs dropped by WMM limit */ 794 __le32 wmm_drop; 795 796 /* Num Local frames queued */ 797 __le32 local_enqued; 798 799 /* Num Local frames done */ 800 __le32 local_freed; 801 802 /* Num queued to HW */ 803 __le32 hw_queued; 804 805 /* Num PPDU reaped from HW */ 806 __le32 hw_reaped; 807 808 /* Num underruns */ 809 __le32 underrun; 810 811 /* Num PPDUs cleaned up in TX abort */ 812 __le32 tx_abort; 813 814 /* Num MPDUs requed by SW */ 815 __le32 mpdus_requed; 816 817 /* excessive retries */ 818 __le32 tx_ko; 819 820 /* data hw rate code */ 821 __le32 data_rc; 822 823 /* Scheduler self triggers */ 824 __le32 self_triggers; 825 826 /* frames dropped due to excessive sw retries */ 827 __le32 sw_retry_failure; 828 829 /* illegal rate phy errors */ 830 __le32 illgl_rate_phy_err; 831 832 /* wal pdev continous xretry */ 833 __le32 pdev_cont_xretry; 834 835 /* wal pdev continous xretry */ 836 __le32 pdev_tx_timeout; 837 838 /* wal pdev resets */ 839 __le32 pdev_resets; 840 841 __le32 phy_underrun; 842 843 /* MPDU is more than txop limit */ 844 __le32 txop_ovf; 845 } __packed; 846 847 struct htt_dbg_stats_wal_rx_stats { 848 /* Cnts any change in ring routing mid-ppdu */ 849 __le32 mid_ppdu_route_change; 850 851 /* Total number of statuses processed */ 852 __le32 status_rcvd; 853 854 /* Extra frags on rings 0-3 */ 855 __le32 r0_frags; 856 __le32 r1_frags; 857 __le32 r2_frags; 858 __le32 r3_frags; 859 860 /* MSDUs / MPDUs delivered to HTT */ 861 __le32 htt_msdus; 862 __le32 htt_mpdus; 863 864 /* MSDUs / MPDUs delivered to local stack */ 865 __le32 loc_msdus; 866 __le32 loc_mpdus; 867 868 /* AMSDUs that have more MSDUs than the status ring size */ 869 __le32 oversize_amsdu; 870 871 /* Number of PHY errors */ 872 __le32 phy_errs; 873 874 /* Number of PHY errors drops */ 875 __le32 phy_err_drop; 876 877 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 878 __le32 mpdu_errs; 879 } __packed; 880 881 struct htt_dbg_stats_wal_peer_stats { 882 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 883 } __packed; 884 885 struct htt_dbg_stats_wal_pdev_txrx { 886 struct htt_dbg_stats_wal_tx_stats tx_stats; 887 struct htt_dbg_stats_wal_rx_stats rx_stats; 888 struct htt_dbg_stats_wal_peer_stats peer_stats; 889 } __packed; 890 891 struct htt_dbg_stats_rx_rate_info { 892 __le32 mcs[10]; 893 __le32 sgi[10]; 894 __le32 nss[4]; 895 __le32 stbc[10]; 896 __le32 bw[3]; 897 __le32 pream[6]; 898 __le32 ldpc; 899 __le32 txbf; 900 }; 901 902 /* 903 * htt_dbg_stats_status - 904 * present - The requested stats have been delivered in full. 905 * This indicates that either the stats information was contained 906 * in its entirety within this message, or else this message 907 * completes the delivery of the requested stats info that was 908 * partially delivered through earlier STATS_CONF messages. 909 * partial - The requested stats have been delivered in part. 910 * One or more subsequent STATS_CONF messages with the same 911 * cookie value will be sent to deliver the remainder of the 912 * information. 913 * error - The requested stats could not be delivered, for example due 914 * to a shortage of memory to construct a message holding the 915 * requested stats. 916 * invalid - The requested stat type is either not recognized, or the 917 * target is configured to not gather the stats type in question. 918 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 919 * series_done - This special value indicates that no further stats info 920 * elements are present within a series of stats info elems 921 * (within a stats upload confirmation message). 922 */ 923 enum htt_dbg_stats_status { 924 HTT_DBG_STATS_STATUS_PRESENT = 0, 925 HTT_DBG_STATS_STATUS_PARTIAL = 1, 926 HTT_DBG_STATS_STATUS_ERROR = 2, 927 HTT_DBG_STATS_STATUS_INVALID = 3, 928 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 929 }; 930 931 /* 932 * target -> host statistics upload 933 * 934 * The following field definitions describe the format of the HTT target 935 * to host stats upload confirmation message. 936 * The message contains a cookie echoed from the HTT host->target stats 937 * upload request, which identifies which request the confirmation is 938 * for, and a series of tag-length-value stats information elements. 939 * The tag-length header for each stats info element also includes a 940 * status field, to indicate whether the request for the stat type in 941 * question was fully met, partially met, unable to be met, or invalid 942 * (if the stat type in question is disabled in the target). 943 * A special value of all 1's in this status field is used to indicate 944 * the end of the series of stats info elements. 945 * 946 * 947 * |31 16|15 8|7 5|4 0| 948 * |------------------------------------------------------------| 949 * | reserved | msg type | 950 * |------------------------------------------------------------| 951 * | cookie LSBs | 952 * |------------------------------------------------------------| 953 * | cookie MSBs | 954 * |------------------------------------------------------------| 955 * | stats entry length | reserved | S |stat type| 956 * |------------------------------------------------------------| 957 * | | 958 * | type-specific stats info | 959 * | | 960 * |------------------------------------------------------------| 961 * | stats entry length | reserved | S |stat type| 962 * |------------------------------------------------------------| 963 * | | 964 * | type-specific stats info | 965 * | | 966 * |------------------------------------------------------------| 967 * | n/a | reserved | 111 | n/a | 968 * |------------------------------------------------------------| 969 * Header fields: 970 * - MSG_TYPE 971 * Bits 7:0 972 * Purpose: identifies this is a statistics upload confirmation message 973 * Value: 0x9 974 * - COOKIE_LSBS 975 * Bits 31:0 976 * Purpose: Provide a mechanism to match a target->host stats confirmation 977 * message with its preceding host->target stats request message. 978 * Value: LSBs of the opaque cookie specified by the host-side requestor 979 * - COOKIE_MSBS 980 * Bits 31:0 981 * Purpose: Provide a mechanism to match a target->host stats confirmation 982 * message with its preceding host->target stats request message. 983 * Value: MSBs of the opaque cookie specified by the host-side requestor 984 * 985 * Stats Information Element tag-length header fields: 986 * - STAT_TYPE 987 * Bits 4:0 988 * Purpose: identifies the type of statistics info held in the 989 * following information element 990 * Value: htt_dbg_stats_type 991 * - STATUS 992 * Bits 7:5 993 * Purpose: indicate whether the requested stats are present 994 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 995 * the completion of the stats entry series 996 * - LENGTH 997 * Bits 31:16 998 * Purpose: indicate the stats information size 999 * Value: This field specifies the number of bytes of stats information 1000 * that follows the element tag-length header. 1001 * It is expected but not required that this length is a multiple of 1002 * 4 bytes. Even if the length is not an integer multiple of 4, the 1003 * subsequent stats entry header will begin on a 4-byte aligned 1004 * boundary. 1005 */ 1006 1007 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1008 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1009 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1010 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1011 1012 struct htt_stats_conf_item { 1013 union { 1014 u8 info; 1015 struct { 1016 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1017 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1018 } __packed; 1019 } __packed; 1020 u8 pad; 1021 __le16 length; 1022 u8 payload[0]; /* roundup(length, 4) long */ 1023 } __packed; 1024 1025 struct htt_stats_conf { 1026 u8 pad[3]; 1027 __le32 cookie_lsb; 1028 __le32 cookie_msb; 1029 1030 /* each item has variable length! */ 1031 struct htt_stats_conf_item items[0]; 1032 } __packed; 1033 1034 static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1035 const struct htt_stats_conf_item *item) 1036 { 1037 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1038 } 1039 /* 1040 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1041 * 1042 * The following field definitions describe the format of the HTT host 1043 * to target frag_desc/msdu_ext bank configuration message. 1044 * The message contains the based address and the min and max id of the 1045 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1046 * MSDU_EXT/FRAG_DESC. 1047 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1048 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1049 * the hardware does the mapping/translation. 1050 * 1051 * Total banks that can be configured is configured to 16. 1052 * 1053 * This should be called before any TX has be initiated by the HTT 1054 * 1055 * |31 16|15 8|7 5|4 0| 1056 * |------------------------------------------------------------| 1057 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1058 * |------------------------------------------------------------| 1059 * | BANK0_BASE_ADDRESS | 1060 * |------------------------------------------------------------| 1061 * | ... | 1062 * |------------------------------------------------------------| 1063 * | BANK15_BASE_ADDRESS | 1064 * |------------------------------------------------------------| 1065 * | BANK0_MAX_ID | BANK0_MIN_ID | 1066 * |------------------------------------------------------------| 1067 * | ... | 1068 * |------------------------------------------------------------| 1069 * | BANK15_MAX_ID | BANK15_MIN_ID | 1070 * |------------------------------------------------------------| 1071 * Header fields: 1072 * - MSG_TYPE 1073 * Bits 7:0 1074 * Value: 0x6 1075 * - BANKx_BASE_ADDRESS 1076 * Bits 31:0 1077 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1078 * bank physical/bus address. 1079 * - BANKx_MIN_ID 1080 * Bits 15:0 1081 * Purpose: Provide a mechanism to specify the min index that needs to 1082 * mapped. 1083 * - BANKx_MAX_ID 1084 * Bits 31:16 1085 * Purpose: Provide a mechanism to specify the max index that needs to 1086 * 1087 */ 1088 struct htt_frag_desc_bank_id { 1089 __le16 bank_min_id; 1090 __le16 bank_max_id; 1091 } __packed; 1092 1093 /* real is 16 but it wouldn't fit in the max htt message size 1094 * so we use a conservatively safe value for now */ 1095 #define HTT_FRAG_DESC_BANK_MAX 4 1096 1097 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1098 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1099 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP (1 << 2) 1100 1101 struct htt_frag_desc_bank_cfg { 1102 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1103 u8 num_banks; 1104 u8 desc_size; 1105 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1106 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1107 } __packed; 1108 1109 union htt_rx_pn_t { 1110 /* WEP: 24-bit PN */ 1111 u32 pn24; 1112 1113 /* TKIP or CCMP: 48-bit PN */ 1114 u_int64_t pn48; 1115 1116 /* WAPI: 128-bit PN */ 1117 u_int64_t pn128[2]; 1118 }; 1119 1120 struct htt_cmd { 1121 struct htt_cmd_hdr hdr; 1122 union { 1123 struct htt_ver_req ver_req; 1124 struct htt_mgmt_tx_desc mgmt_tx; 1125 struct htt_data_tx_desc data_tx; 1126 struct htt_rx_ring_setup rx_setup; 1127 struct htt_stats_req stats_req; 1128 struct htt_oob_sync_req oob_sync_req; 1129 struct htt_aggr_conf aggr_conf; 1130 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg; 1131 }; 1132 } __packed; 1133 1134 struct htt_resp { 1135 struct htt_resp_hdr hdr; 1136 union { 1137 struct htt_ver_resp ver_resp; 1138 struct htt_mgmt_tx_completion mgmt_tx_completion; 1139 struct htt_data_tx_completion data_tx_completion; 1140 struct htt_rx_indication rx_ind; 1141 struct htt_rx_fragment_indication rx_frag_ind; 1142 struct htt_rx_peer_map peer_map; 1143 struct htt_rx_peer_unmap peer_unmap; 1144 struct htt_rx_flush rx_flush; 1145 struct htt_rx_addba rx_addba; 1146 struct htt_rx_delba rx_delba; 1147 struct htt_security_indication security_indication; 1148 struct htt_rc_update rc_update; 1149 struct htt_rx_test rx_test; 1150 struct htt_pktlog_msg pktlog_msg; 1151 struct htt_stats_conf stats_conf; 1152 }; 1153 } __packed; 1154 1155 1156 /*** host side structures follow ***/ 1157 1158 struct htt_tx_done { 1159 u32 msdu_id; 1160 bool discard; 1161 bool no_ack; 1162 }; 1163 1164 struct htt_peer_map_event { 1165 u8 vdev_id; 1166 u16 peer_id; 1167 u8 addr[ETH_ALEN]; 1168 }; 1169 1170 struct htt_peer_unmap_event { 1171 u16 peer_id; 1172 }; 1173 1174 struct htt_rx_info { 1175 struct sk_buff *skb; 1176 enum htt_rx_mpdu_status status; 1177 enum htt_rx_mpdu_encrypt_type encrypt_type; 1178 s8 signal; 1179 struct { 1180 u8 info0; 1181 u32 info1; 1182 u32 info2; 1183 } rate; 1184 bool fcs_err; 1185 }; 1186 1187 struct ath10k_htt { 1188 struct ath10k *ar; 1189 enum ath10k_htc_ep_id eid; 1190 1191 int max_throughput_mbps; 1192 u8 target_version_major; 1193 u8 target_version_minor; 1194 struct completion target_version_received; 1195 1196 struct { 1197 /* 1198 * Ring of network buffer objects - This ring is 1199 * used exclusively by the host SW. This ring 1200 * mirrors the dev_addrs_ring that is shared 1201 * between the host SW and the MAC HW. The host SW 1202 * uses this netbufs ring to locate the network 1203 * buffer objects whose data buffers the HW has 1204 * filled. 1205 */ 1206 struct sk_buff **netbufs_ring; 1207 /* 1208 * Ring of buffer addresses - 1209 * This ring holds the "physical" device address of the 1210 * rx buffers the host SW provides for the MAC HW to 1211 * fill. 1212 */ 1213 __le32 *paddrs_ring; 1214 1215 /* 1216 * Base address of ring, as a "physical" device address 1217 * rather than a CPU address. 1218 */ 1219 dma_addr_t base_paddr; 1220 1221 /* how many elems in the ring (power of 2) */ 1222 int size; 1223 1224 /* size - 1 */ 1225 unsigned size_mask; 1226 1227 /* how many rx buffers to keep in the ring */ 1228 int fill_level; 1229 1230 /* how many rx buffers (full+empty) are in the ring */ 1231 int fill_cnt; 1232 1233 /* 1234 * alloc_idx - where HTT SW has deposited empty buffers 1235 * This is allocated in consistent mem, so that the FW can 1236 * read this variable, and program the HW's FW_IDX reg with 1237 * the value of this shadow register. 1238 */ 1239 struct { 1240 __le32 *vaddr; 1241 dma_addr_t paddr; 1242 } alloc_idx; 1243 1244 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1245 struct { 1246 unsigned msdu_payld; 1247 } sw_rd_idx; 1248 1249 /* 1250 * refill_retry_timer - timer triggered when the ring is 1251 * not refilled to the level expected 1252 */ 1253 struct timer_list refill_retry_timer; 1254 1255 /* Protects access to all rx ring buffer state variables */ 1256 spinlock_t lock; 1257 } rx_ring; 1258 1259 unsigned int prefetch_len; 1260 1261 /* Protects access to %pending_tx, %used_msdu_ids */ 1262 spinlock_t tx_lock; 1263 int max_num_pending_tx; 1264 int num_pending_tx; 1265 struct sk_buff **pending_tx; 1266 unsigned long *used_msdu_ids; /* bitmap */ 1267 wait_queue_head_t empty_tx_wq; 1268 1269 /* set if host-fw communication goes haywire 1270 * used to avoid further failures */ 1271 bool rx_confused; 1272 struct tasklet_struct rx_replenish_task; 1273 }; 1274 1275 #define RX_HTT_HDR_STATUS_LEN 64 1276 1277 /* This structure layout is programmed via rx ring setup 1278 * so that FW knows how to transfer the rx descriptor to the host. 1279 * Buffers like this are placed on the rx ring. */ 1280 struct htt_rx_desc { 1281 union { 1282 /* This field is filled on the host using the msdu buffer 1283 * from htt_rx_indication */ 1284 struct fw_rx_desc_base fw_desc; 1285 u32 pad; 1286 } __packed; 1287 struct { 1288 struct rx_attention attention; 1289 struct rx_frag_info frag_info; 1290 struct rx_mpdu_start mpdu_start; 1291 struct rx_msdu_start msdu_start; 1292 struct rx_msdu_end msdu_end; 1293 struct rx_mpdu_end mpdu_end; 1294 struct rx_ppdu_start ppdu_start; 1295 struct rx_ppdu_end ppdu_end; 1296 } __packed; 1297 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1298 u8 msdu_payload[0]; 1299 }; 1300 1301 #define HTT_RX_DESC_ALIGN 8 1302 1303 #define HTT_MAC_ADDR_LEN 6 1304 1305 /* 1306 * FIX THIS 1307 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 1308 * rounded up to a cache line size. 1309 */ 1310 #define HTT_RX_BUF_SIZE 1920 1311 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 1312 1313 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 1314 * aggregated traffic more nicely. */ 1315 #define ATH10K_HTT_MAX_NUM_REFILL 16 1316 1317 /* 1318 * DMA_MAP expects the buffer to be an integral number of cache lines. 1319 * Rather than checking the actual cache line size, this code makes a 1320 * conservative estimate of what the cache line size could be. 1321 */ 1322 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 1323 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 1324 1325 int ath10k_htt_attach(struct ath10k *ar); 1326 int ath10k_htt_attach_target(struct ath10k_htt *htt); 1327 void ath10k_htt_detach(struct ath10k_htt *htt); 1328 1329 int ath10k_htt_tx_attach(struct ath10k_htt *htt); 1330 void ath10k_htt_tx_detach(struct ath10k_htt *htt); 1331 int ath10k_htt_rx_attach(struct ath10k_htt *htt); 1332 void ath10k_htt_rx_detach(struct ath10k_htt *htt); 1333 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1334 void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1335 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 1336 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 1337 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt); 1338 1339 void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 1340 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt); 1341 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 1342 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *); 1343 int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *); 1344 #endif 1345