1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _HTT_H_ 9 #define _HTT_H_ 10 11 #include <linux/bug.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmapool.h> 14 #include <linux/hashtable.h> 15 #include <linux/kfifo.h> 16 #include <net/mac80211.h> 17 18 #include "htc.h" 19 #include "hw.h" 20 #include "rx_desc.h" 21 22 enum htt_dbg_stats_type { 23 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 24 HTT_DBG_STATS_RX_REORDER = 1 << 1, 25 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 26 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 27 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 28 /* bits 5-23 currently reserved */ 29 30 HTT_DBG_NUM_STATS /* keep this last */ 31 }; 32 33 enum htt_h2t_msg_type { /* host-to-target */ 34 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 35 HTT_H2T_MSG_TYPE_TX_FRM = 1, 36 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 37 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 38 HTT_H2T_MSG_TYPE_SYNC = 4, 39 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 40 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 41 42 /* This command is used for sending management frames in HTT < 3.0. 43 * HTT >= 3.0 uses TX_FRM for everything. 44 */ 45 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 46 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11, 47 48 HTT_H2T_NUM_MSGS /* keep this last */ 49 }; 50 51 struct htt_cmd_hdr { 52 u8 msg_type; 53 } __packed; 54 55 struct htt_ver_req { 56 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 57 } __packed; 58 59 /* 60 * HTT tx MSDU descriptor 61 * 62 * The HTT tx MSDU descriptor is created by the host HTT SW for each 63 * tx MSDU. The HTT tx MSDU descriptor contains the information that 64 * the target firmware needs for the FW's tx processing, particularly 65 * for creating the HW msdu descriptor. 66 * The same HTT tx descriptor is used for HL and LL systems, though 67 * a few fields within the tx descriptor are used only by LL or 68 * only by HL. 69 * The HTT tx descriptor is defined in two manners: by a struct with 70 * bitfields, and by a series of [dword offset, bit mask, bit shift] 71 * definitions. 72 * The target should use the struct def, for simplicitly and clarity, 73 * but the host shall use the bit-mast + bit-shift defs, to be endian- 74 * neutral. Specifically, the host shall use the get/set macros built 75 * around the mask + shift defs. 76 */ 77 struct htt_data_tx_desc_frag { 78 union { 79 struct double_word_addr { 80 __le32 paddr; 81 __le32 len; 82 } __packed dword_addr; 83 struct triple_word_addr { 84 __le32 paddr_lo; 85 __le16 paddr_hi; 86 __le16 len_16; 87 } __packed tword_addr; 88 } __packed; 89 } __packed; 90 91 struct htt_msdu_ext_desc { 92 __le32 tso_flag[3]; 93 __le16 ip_identification; 94 u8 flags; 95 u8 reserved; 96 struct htt_data_tx_desc_frag frags[6]; 97 }; 98 99 struct htt_msdu_ext_desc_64 { 100 __le32 tso_flag[5]; 101 __le16 ip_identification; 102 u8 flags; 103 u8 reserved; 104 struct htt_data_tx_desc_frag frags[6]; 105 }; 106 107 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0) 108 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1) 109 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2) 110 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3) 111 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4) 112 113 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \ 114 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \ 115 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \ 116 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \ 117 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE) 118 119 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16) 120 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17) 121 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18) 122 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19) 123 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20) 124 #define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21) 125 126 #define HTT_MSDU_CHECKSUM_ENABLE_64 (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 \ 127 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 \ 128 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 \ 129 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 \ 130 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64) 131 132 enum htt_data_tx_desc_flags0 { 133 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 134 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 135 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 136 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 137 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 138 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 139 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 140 }; 141 142 enum htt_data_tx_desc_flags1 { 143 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 144 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 145 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 146 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 147 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 148 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 149 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 150 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 151 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 152 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 153 HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE = 1 << 15 154 }; 155 156 #define HTT_TX_CREDIT_DELTA_ABS_M 0xffff0000 157 #define HTT_TX_CREDIT_DELTA_ABS_S 16 158 #define HTT_TX_CREDIT_DELTA_ABS_GET(word) \ 159 (((word) & HTT_TX_CREDIT_DELTA_ABS_M) >> HTT_TX_CREDIT_DELTA_ABS_S) 160 161 #define HTT_TX_CREDIT_SIGN_BIT_M 0x00000100 162 #define HTT_TX_CREDIT_SIGN_BIT_S 8 163 #define HTT_TX_CREDIT_SIGN_BIT_GET(word) \ 164 (((word) & HTT_TX_CREDIT_SIGN_BIT_M) >> HTT_TX_CREDIT_SIGN_BIT_S) 165 166 enum htt_data_tx_ext_tid { 167 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 168 HTT_DATA_TX_EXT_TID_MGMT = 17, 169 HTT_DATA_TX_EXT_TID_INVALID = 31 170 }; 171 172 #define HTT_INVALID_PEERID 0xFFFF 173 174 /* 175 * htt_data_tx_desc - used for data tx path 176 * 177 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 178 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 179 * for special kinds of tids 180 * postponed: only for HL hosts. indicates if this is a resend 181 * (HL hosts manage queues on the host ) 182 * more_in_batch: only for HL hosts. indicates if more packets are 183 * pending. this allows target to wait and aggregate 184 * freq: 0 means home channel of given vdev. intended for offchannel 185 */ 186 struct htt_data_tx_desc { 187 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 188 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 189 __le16 len; 190 __le16 id; 191 __le32 frags_paddr; 192 union { 193 __le32 peerid; 194 struct { 195 __le16 peerid; 196 __le16 freq; 197 } __packed offchan_tx; 198 } __packed; 199 u8 prefetch[0]; /* start of frame, for FW classification engine */ 200 } __packed; 201 202 struct htt_data_tx_desc_64 { 203 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 204 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 205 __le16 len; 206 __le16 id; 207 __le64 frags_paddr; 208 union { 209 __le32 peerid; 210 struct { 211 __le16 peerid; 212 __le16 freq; 213 } __packed offchan_tx; 214 } __packed; 215 u8 prefetch[0]; /* start of frame, for FW classification engine */ 216 } __packed; 217 218 enum htt_rx_ring_flags { 219 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 220 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 221 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 222 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 223 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 224 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 225 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 226 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 227 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 228 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 229 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 230 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 231 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 232 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 233 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 234 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 235 }; 236 237 #define HTT_RX_RING_SIZE_MIN 128 238 #define HTT_RX_RING_SIZE_MAX 2048 239 #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX 240 #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1) 241 #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1) 242 243 struct htt_rx_ring_setup_ring32 { 244 __le32 fw_idx_shadow_reg_paddr; 245 __le32 rx_ring_base_paddr; 246 __le16 rx_ring_len; /* in 4-byte words */ 247 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 248 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 249 __le16 fw_idx_init_val; 250 251 /* the following offsets are in 4-byte units */ 252 __le16 mac80211_hdr_offset; 253 __le16 msdu_payload_offset; 254 __le16 ppdu_start_offset; 255 __le16 ppdu_end_offset; 256 __le16 mpdu_start_offset; 257 __le16 mpdu_end_offset; 258 __le16 msdu_start_offset; 259 __le16 msdu_end_offset; 260 __le16 rx_attention_offset; 261 __le16 frag_info_offset; 262 } __packed; 263 264 struct htt_rx_ring_setup_ring64 { 265 __le64 fw_idx_shadow_reg_paddr; 266 __le64 rx_ring_base_paddr; 267 __le16 rx_ring_len; /* in 4-byte words */ 268 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 269 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 270 __le16 fw_idx_init_val; 271 272 /* the following offsets are in 4-byte units */ 273 __le16 mac80211_hdr_offset; 274 __le16 msdu_payload_offset; 275 __le16 ppdu_start_offset; 276 __le16 ppdu_end_offset; 277 __le16 mpdu_start_offset; 278 __le16 mpdu_end_offset; 279 __le16 msdu_start_offset; 280 __le16 msdu_end_offset; 281 __le16 rx_attention_offset; 282 __le16 frag_info_offset; 283 } __packed; 284 285 struct htt_rx_ring_setup_hdr { 286 u8 num_rings; /* supported values: 1, 2 */ 287 __le16 rsvd0; 288 } __packed; 289 290 struct htt_rx_ring_setup_32 { 291 struct htt_rx_ring_setup_hdr hdr; 292 struct htt_rx_ring_setup_ring32 rings[]; 293 } __packed; 294 295 struct htt_rx_ring_setup_64 { 296 struct htt_rx_ring_setup_hdr hdr; 297 struct htt_rx_ring_setup_ring64 rings[]; 298 } __packed; 299 300 /* 301 * htt_stats_req - request target to send specified statistics 302 * 303 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 304 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 305 * so make sure its little-endian. 306 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 307 * so make sure its little-endian. 308 * @cfg_val: stat_type specific configuration 309 * @stat_type: see %htt_dbg_stats_type 310 * @cookie_lsb: used for confirmation message from target->host 311 * @cookie_msb: ditto as %cookie 312 */ 313 struct htt_stats_req { 314 u8 upload_types[3]; 315 u8 rsvd0; 316 u8 reset_types[3]; 317 struct { 318 u8 mpdu_bytes; 319 u8 mpdu_num_msdus; 320 u8 msdu_bytes; 321 } __packed; 322 u8 stat_type; 323 __le32 cookie_lsb; 324 __le32 cookie_msb; 325 } __packed; 326 327 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 328 #define HTT_STATS_BIT_MASK GENMASK(16, 0) 329 330 /* 331 * htt_oob_sync_req - request out-of-band sync 332 * 333 * The HTT SYNC tells the target to suspend processing of subsequent 334 * HTT host-to-target messages until some other target agent locally 335 * informs the target HTT FW that the current sync counter is equal to 336 * or greater than (in a modulo sense) the sync counter specified in 337 * the SYNC message. 338 * 339 * This allows other host-target components to synchronize their operation 340 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 341 * security key has been downloaded to and activated by the target. 342 * In the absence of any explicit synchronization counter value 343 * specification, the target HTT FW will use zero as the default current 344 * sync value. 345 * 346 * The HTT target FW will suspend its host->target message processing as long 347 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 348 */ 349 struct htt_oob_sync_req { 350 u8 sync_count; 351 __le16 rsvd0; 352 } __packed; 353 354 struct htt_aggr_conf { 355 u8 max_num_ampdu_subframes; 356 /* amsdu_subframes is limited by 0x1F mask */ 357 u8 max_num_amsdu_subframes; 358 } __packed; 359 360 struct htt_aggr_conf_v2 { 361 u8 max_num_ampdu_subframes; 362 /* amsdu_subframes is limited by 0x1F mask */ 363 u8 max_num_amsdu_subframes; 364 u8 reserved; 365 } __packed; 366 367 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 368 struct htt_mgmt_tx_desc_qca99x0 { 369 __le32 rate; 370 } __packed; 371 372 struct htt_mgmt_tx_desc { 373 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 374 __le32 msdu_paddr; 375 __le32 desc_id; 376 __le32 len; 377 __le32 vdev_id; 378 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 379 union { 380 struct htt_mgmt_tx_desc_qca99x0 qca99x0; 381 } __packed; 382 } __packed; 383 384 enum htt_mgmt_tx_status { 385 HTT_MGMT_TX_STATUS_OK = 0, 386 HTT_MGMT_TX_STATUS_RETRY = 1, 387 HTT_MGMT_TX_STATUS_DROP = 2 388 }; 389 390 /*=== target -> host messages ===============================================*/ 391 392 enum htt_main_t2h_msg_type { 393 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0, 394 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1, 395 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2, 396 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3, 397 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 398 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5, 399 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6, 400 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 401 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8, 402 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9, 403 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 404 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb, 405 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 406 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 407 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 408 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10, 409 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 410 HTT_MAIN_T2H_MSG_TYPE_TEST, 411 /* keep this last */ 412 HTT_MAIN_T2H_NUM_MSGS 413 }; 414 415 enum htt_10x_t2h_msg_type { 416 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0, 417 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1, 418 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2, 419 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3, 420 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 421 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5, 422 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6, 423 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 424 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8, 425 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9, 426 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 427 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb, 428 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 429 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 430 HTT_10X_T2H_MSG_TYPE_TEST = 0xe, 431 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 432 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11, 433 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12, 434 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13, 435 /* keep this last */ 436 HTT_10X_T2H_NUM_MSGS 437 }; 438 439 enum htt_tlv_t2h_msg_type { 440 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0, 441 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1, 442 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2, 443 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3, 444 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 445 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5, 446 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6, 447 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 448 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8, 449 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9, 450 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 451 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb, 452 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */ 453 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 454 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 455 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 456 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10, 457 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 458 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 459 /* 0x13 reservd */ 460 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 461 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 462 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 463 HTT_TLV_T2H_MSG_TYPE_TEST, 464 /* keep this last */ 465 HTT_TLV_T2H_NUM_MSGS 466 }; 467 468 enum htt_10_4_t2h_msg_type { 469 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0, 470 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1, 471 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2, 472 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3, 473 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 474 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5, 475 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6, 476 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 477 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8, 478 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9, 479 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 480 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb, 481 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 482 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 483 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 484 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 485 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10, 486 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11, 487 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12, 488 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13, 489 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14, 490 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15, 491 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16, 492 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17, 493 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18, 494 /* 0x19 to 0x2f are reserved */ 495 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30, 496 HTT_10_4_T2H_MSG_TYPE_PEER_STATS = 0x31, 497 /* keep this last */ 498 HTT_10_4_T2H_NUM_MSGS 499 }; 500 501 enum htt_t2h_msg_type { 502 HTT_T2H_MSG_TYPE_VERSION_CONF, 503 HTT_T2H_MSG_TYPE_RX_IND, 504 HTT_T2H_MSG_TYPE_RX_FLUSH, 505 HTT_T2H_MSG_TYPE_PEER_MAP, 506 HTT_T2H_MSG_TYPE_PEER_UNMAP, 507 HTT_T2H_MSG_TYPE_RX_ADDBA, 508 HTT_T2H_MSG_TYPE_RX_DELBA, 509 HTT_T2H_MSG_TYPE_TX_COMPL_IND, 510 HTT_T2H_MSG_TYPE_PKTLOG, 511 HTT_T2H_MSG_TYPE_STATS_CONF, 512 HTT_T2H_MSG_TYPE_RX_FRAG_IND, 513 HTT_T2H_MSG_TYPE_SEC_IND, 514 HTT_T2H_MSG_TYPE_RC_UPDATE_IND, 515 HTT_T2H_MSG_TYPE_TX_INSPECT_IND, 516 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION, 517 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, 518 HTT_T2H_MSG_TYPE_RX_PN_IND, 519 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND, 520 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND, 521 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE, 522 HTT_T2H_MSG_TYPE_CHAN_CHANGE, 523 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR, 524 HTT_T2H_MSG_TYPE_AGGR_CONF, 525 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, 526 HTT_T2H_MSG_TYPE_TEST, 527 HTT_T2H_MSG_TYPE_EN_STATS, 528 HTT_T2H_MSG_TYPE_TX_FETCH_IND, 529 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM, 530 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND, 531 HTT_T2H_MSG_TYPE_PEER_STATS, 532 /* keep this last */ 533 HTT_T2H_NUM_MSGS 534 }; 535 536 /* 537 * htt_resp_hdr - header for target-to-host messages 538 * 539 * msg_type: see htt_t2h_msg_type 540 */ 541 struct htt_resp_hdr { 542 u8 msg_type; 543 } __packed; 544 545 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 546 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 547 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 548 549 /* htt_ver_resp - response sent for htt_ver_req */ 550 struct htt_ver_resp { 551 u8 minor; 552 u8 major; 553 u8 rsvd0; 554 } __packed; 555 556 #define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI BIT(0) 557 558 #define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK GENMASK(7, 0) 559 560 struct htt_mgmt_tx_completion { 561 u8 rsvd0; 562 u8 rsvd1; 563 u8 flags; 564 __le32 desc_id; 565 __le32 status; 566 __le32 ppdu_id; 567 __le32 info; 568 } __packed; 569 570 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F) 571 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 572 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5) 573 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6) 574 #define HTT_RX_INDICATION_INFO0_PPDU_DURATION BIT(7) 575 576 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 577 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 578 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 579 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 580 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 581 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 582 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 583 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 584 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 585 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 586 587 #define HTT_TX_CMPL_FLAG_DATA_RSSI BIT(0) 588 #define HTT_TX_CMPL_FLAG_PPID_PRESENT BIT(1) 589 #define HTT_TX_CMPL_FLAG_PA_PRESENT BIT(2) 590 #define HTT_TX_CMPL_FLAG_PPDU_DURATION_PRESENT BIT(3) 591 592 #define HTT_TX_DATA_RSSI_ENABLE_WCN3990 BIT(3) 593 #define HTT_TX_DATA_APPEND_RETRIES BIT(0) 594 #define HTT_TX_DATA_APPEND_TIMESTAMP BIT(1) 595 596 struct htt_rx_indication_hdr { 597 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 598 __le16 peer_id; 599 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 600 } __packed; 601 602 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 603 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 604 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 605 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 606 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 607 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 608 609 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 610 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 611 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 612 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 613 614 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 615 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 616 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 617 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 618 619 enum htt_rx_legacy_rate { 620 HTT_RX_OFDM_48 = 0, 621 HTT_RX_OFDM_24 = 1, 622 HTT_RX_OFDM_12, 623 HTT_RX_OFDM_6, 624 HTT_RX_OFDM_54, 625 HTT_RX_OFDM_36, 626 HTT_RX_OFDM_18, 627 HTT_RX_OFDM_9, 628 629 /* long preamble */ 630 HTT_RX_CCK_11_LP = 0, 631 HTT_RX_CCK_5_5_LP = 1, 632 HTT_RX_CCK_2_LP, 633 HTT_RX_CCK_1_LP, 634 /* short preamble */ 635 HTT_RX_CCK_11_SP, 636 HTT_RX_CCK_5_5_SP, 637 HTT_RX_CCK_2_SP 638 }; 639 640 enum htt_rx_legacy_rate_type { 641 HTT_RX_LEGACY_RATE_OFDM = 0, 642 HTT_RX_LEGACY_RATE_CCK 643 }; 644 645 enum htt_rx_preamble_type { 646 HTT_RX_LEGACY = 0x4, 647 HTT_RX_HT = 0x8, 648 HTT_RX_HT_WITH_TXBF = 0x9, 649 HTT_RX_VHT = 0xC, 650 HTT_RX_VHT_WITH_TXBF = 0xD, 651 }; 652 653 /* 654 * Fields: phy_err_valid, phy_err_code, tsf, 655 * usec_timestamp, sub_usec_timestamp 656 * ..are valid only if end_valid == 1. 657 * 658 * Fields: rssi_chains, legacy_rate_type, 659 * legacy_rate_cck, preamble_type, service, 660 * vht_sig_* 661 * ..are valid only if start_valid == 1; 662 */ 663 struct htt_rx_indication_ppdu { 664 u8 combined_rssi; 665 u8 sub_usec_timestamp; 666 u8 phy_err_code; 667 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 668 struct { 669 u8 pri20_db; 670 u8 ext20_db; 671 u8 ext40_db; 672 u8 ext80_db; 673 } __packed rssi_chains[4]; 674 __le32 tsf; 675 __le32 usec_timestamp; 676 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 677 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 678 } __packed; 679 680 enum htt_rx_mpdu_status { 681 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 682 HTT_RX_IND_MPDU_STATUS_OK, 683 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 684 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 685 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 686 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 687 /* only accept EAPOL frames */ 688 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 689 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 690 /* Non-data in promiscuous mode */ 691 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 692 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 693 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 694 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 695 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 696 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 697 698 /* 699 * MISC: discard for unspecified reasons. 700 * Leave this enum value last. 701 */ 702 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 703 }; 704 705 struct htt_rx_indication_mpdu_range { 706 u8 mpdu_count; 707 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 708 u8 pad0; 709 u8 pad1; 710 } __packed; 711 712 struct htt_rx_indication_prefix { 713 __le16 fw_rx_desc_bytes; 714 u8 pad0; 715 u8 pad1; 716 }; 717 718 struct htt_rx_indication { 719 struct htt_rx_indication_hdr hdr; 720 struct htt_rx_indication_ppdu ppdu; 721 struct htt_rx_indication_prefix prefix; 722 723 /* 724 * the following fields are both dynamically sized, so 725 * take care addressing them 726 */ 727 728 /* the size of this is %fw_rx_desc_bytes */ 729 struct fw_rx_desc_base fw_desc; 730 731 /* 732 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 733 * and has %num_mpdu_ranges elements. 734 */ 735 struct htt_rx_indication_mpdu_range mpdu_ranges[]; 736 } __packed; 737 738 /* High latency version of the RX indication */ 739 struct htt_rx_indication_hl { 740 struct htt_rx_indication_hdr hdr; 741 struct htt_rx_indication_ppdu ppdu; 742 struct htt_rx_indication_prefix prefix; 743 struct fw_rx_desc_hl fw_desc; 744 struct htt_rx_indication_mpdu_range mpdu_ranges[]; 745 } __packed; 746 747 struct htt_hl_rx_desc { 748 __le32 info; 749 __le32 pn_31_0; 750 union { 751 struct { 752 __le16 pn_47_32; 753 __le16 pn_63_48; 754 } pn16; 755 __le32 pn_63_32; 756 } u0; 757 __le32 pn_95_64; 758 __le32 pn_127_96; 759 } __packed; 760 761 static inline struct htt_rx_indication_mpdu_range * 762 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 763 { 764 void *ptr = rx_ind; 765 766 ptr += sizeof(rx_ind->hdr) 767 + sizeof(rx_ind->ppdu) 768 + sizeof(rx_ind->prefix) 769 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 770 return ptr; 771 } 772 773 static inline struct htt_rx_indication_mpdu_range * 774 htt_rx_ind_get_mpdu_ranges_hl(struct htt_rx_indication_hl *rx_ind) 775 { 776 void *ptr = rx_ind; 777 778 ptr += sizeof(rx_ind->hdr) 779 + sizeof(rx_ind->ppdu) 780 + sizeof(rx_ind->prefix) 781 + sizeof(rx_ind->fw_desc); 782 return ptr; 783 } 784 785 enum htt_rx_flush_mpdu_status { 786 HTT_RX_FLUSH_MPDU_DISCARD = 0, 787 HTT_RX_FLUSH_MPDU_REORDER = 1, 788 }; 789 790 /* 791 * htt_rx_flush - discard or reorder given range of mpdus 792 * 793 * Note: host must check if all sequence numbers between 794 * [seq_num_start, seq_num_end-1] are valid. 795 */ 796 struct htt_rx_flush { 797 __le16 peer_id; 798 u8 tid; 799 u8 rsvd0; 800 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 801 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 802 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 803 }; 804 805 struct htt_rx_peer_map { 806 u8 vdev_id; 807 __le16 peer_id; 808 u8 addr[6]; 809 u8 rsvd0; 810 u8 rsvd1; 811 } __packed; 812 813 struct htt_rx_peer_unmap { 814 u8 rsvd0; 815 __le16 peer_id; 816 } __packed; 817 818 enum htt_txrx_sec_cast_type { 819 HTT_TXRX_SEC_MCAST = 0, 820 HTT_TXRX_SEC_UCAST 821 }; 822 823 enum htt_rx_pn_check_type { 824 HTT_RX_NON_PN_CHECK = 0, 825 HTT_RX_PN_CHECK 826 }; 827 828 enum htt_rx_tkip_demic_type { 829 HTT_RX_NON_TKIP_MIC = 0, 830 HTT_RX_TKIP_MIC 831 }; 832 833 enum htt_security_types { 834 HTT_SECURITY_NONE, 835 HTT_SECURITY_WEP128, 836 HTT_SECURITY_WEP104, 837 HTT_SECURITY_WEP40, 838 HTT_SECURITY_TKIP, 839 HTT_SECURITY_TKIP_NOMIC, 840 HTT_SECURITY_AES_CCMP, 841 HTT_SECURITY_WAPI, 842 843 HTT_NUM_SECURITY_TYPES /* keep this last! */ 844 }; 845 846 #define ATH10K_HTT_TXRX_PEER_SECURITY_MAX 2 847 #define ATH10K_TXRX_NUM_EXT_TIDS 19 848 #define ATH10K_TXRX_NON_QOS_TID 16 849 850 enum htt_security_flags { 851 #define HTT_SECURITY_TYPE_MASK 0x7F 852 #define HTT_SECURITY_TYPE_LSB 0 853 HTT_SECURITY_IS_UNICAST = 1 << 7 854 }; 855 856 struct htt_security_indication { 857 union { 858 /* dont use bitfields; undefined behaviour */ 859 u8 flags; /* %htt_security_flags */ 860 struct { 861 u8 security_type:7, /* %htt_security_types */ 862 is_unicast:1; 863 } __packed; 864 } __packed; 865 __le16 peer_id; 866 u8 michael_key[8]; 867 u8 wapi_rsc[16]; 868 } __packed; 869 870 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 871 #define HTT_RX_BA_INFO0_TID_LSB 0 872 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 873 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 874 875 struct htt_rx_addba { 876 u8 window_size; 877 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 878 } __packed; 879 880 struct htt_rx_delba { 881 u8 rsvd0; 882 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 883 } __packed; 884 885 enum htt_data_tx_status { 886 HTT_DATA_TX_STATUS_OK = 0, 887 HTT_DATA_TX_STATUS_DISCARD = 1, 888 HTT_DATA_TX_STATUS_NO_ACK = 2, 889 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 890 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 891 }; 892 893 enum htt_data_tx_flags { 894 #define HTT_DATA_TX_STATUS_MASK 0x07 895 #define HTT_DATA_TX_STATUS_LSB 0 896 #define HTT_DATA_TX_TID_MASK 0x78 897 #define HTT_DATA_TX_TID_LSB 3 898 HTT_DATA_TX_TID_INVALID = 1 << 7 899 }; 900 901 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 902 903 struct htt_append_retries { 904 __le16 msdu_id; 905 u8 tx_retries; 906 u8 flag; 907 } __packed; 908 909 struct htt_data_tx_completion_ext { 910 struct htt_append_retries a_retries; 911 __le32 t_stamp; 912 __le16 msdus_rssi[]; 913 } __packed; 914 915 /** 916 * @brief target -> host TX completion indication message definition 917 * 918 * @details 919 * The following diagram shows the format of the TX completion indication sent 920 * from the target to the host 921 * 922 * |31 28|27|26|25|24|23 16| 15 |14 11|10 8|7 0| 923 * |-------------------------------------------------------------| 924 * header: |rsvd |A2|TP|A1|A0| num | t_i| tid |status| msg_type | 925 * |-------------------------------------------------------------| 926 * payload: | MSDU1 ID | MSDU0 ID | 927 * |-------------------------------------------------------------| 928 * : MSDU3 ID : MSDU2 ID : 929 * |-------------------------------------------------------------| 930 * | struct htt_tx_compl_ind_append_retries | 931 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 932 * | struct htt_tx_compl_ind_append_tx_tstamp | 933 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 934 * | MSDU1 ACK RSSI | MSDU0 ACK RSSI | 935 * |-------------------------------------------------------------| 936 * : MSDU3 ACK RSSI : MSDU2 ACK RSSI : 937 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 938 * -msg_type 939 * Bits 7:0 940 * Purpose: identifies this as HTT TX completion indication 941 * -status 942 * Bits 10:8 943 * Purpose: the TX completion status of payload fragmentations descriptors 944 * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD 945 * -tid 946 * Bits 14:11 947 * Purpose: the tid associated with those fragmentation descriptors. It is 948 * valid or not, depending on the tid_invalid bit. 949 * Value: 0 to 15 950 * -tid_invalid 951 * Bits 15:15 952 * Purpose: this bit indicates whether the tid field is valid or not 953 * Value: 0 indicates valid, 1 indicates invalid 954 * -num 955 * Bits 23:16 956 * Purpose: the number of payload in this indication 957 * Value: 1 to 255 958 * -A0 = append 959 * Bits 24:24 960 * Purpose: append the struct htt_tx_compl_ind_append_retries which contains 961 * the number of tx retries for one MSDU at the end of this message 962 * Value: 0 indicates no appending, 1 indicates appending 963 * -A1 = append1 964 * Bits 25:25 965 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tstamp which 966 * contains the timestamp info for each TX msdu id in payload. 967 * Value: 0 indicates no appending, 1 indicates appending 968 * -TP = MSDU tx power presence 969 * Bits 26:26 970 * Purpose: Indicate whether the TX_COMPL_IND includes a tx power report 971 * for each MSDU referenced by the TX_COMPL_IND message. 972 * The order of the per-MSDU tx power reports matches the order 973 * of the MSDU IDs. 974 * Value: 0 indicates not appending, 1 indicates appending 975 * -A2 = append2 976 * Bits 27:27 977 * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in 978 * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report 979 * matches the order of the MSDU IDs. 980 * The ACK RSSI values are valid when status is COMPLETE_OK (and 981 * this append2 bit is set). 982 * Value: 0 indicates not appending, 1 indicates appending 983 */ 984 985 struct htt_data_tx_completion { 986 union { 987 u8 flags; 988 struct { 989 u8 status:3, 990 tid:4, 991 tid_invalid:1; 992 } __packed; 993 } __packed; 994 u8 num_msdus; 995 u8 flags2; /* HTT_TX_CMPL_FLAG_DATA_RSSI */ 996 __le16 msdus[]; /* variable length based on %num_msdus */ 997 } __packed; 998 999 #define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK GENMASK(15, 0) 1000 #define HTT_TX_PPDU_DUR_INFO0_TID_MASK GENMASK(20, 16) 1001 1002 struct htt_data_tx_ppdu_dur { 1003 __le32 info0; /* HTT_TX_PPDU_DUR_INFO0_ */ 1004 __le32 tx_duration; /* in usecs */ 1005 } __packed; 1006 1007 #define HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK GENMASK(7, 0) 1008 1009 struct htt_data_tx_compl_ppdu_dur { 1010 __le32 info0; /* HTT_TX_COMPL_PPDU_DUR_INFO0_ */ 1011 struct htt_data_tx_ppdu_dur ppdu_dur[]; 1012 } __packed; 1013 1014 struct htt_tx_compl_ind_base { 1015 u32 hdr; 1016 u16 payload[1/*or more*/]; 1017 } __packed; 1018 1019 struct htt_rc_tx_done_params { 1020 u32 rate_code; 1021 u32 rate_code_flags; 1022 u32 flags; 1023 u32 num_enqued; /* 1 for non-AMPDU */ 1024 u32 num_retries; 1025 u32 num_failed; /* for AMPDU */ 1026 u32 ack_rssi; 1027 u32 time_stamp; 1028 u32 is_probe; 1029 }; 1030 1031 struct htt_rc_update { 1032 u8 vdev_id; 1033 __le16 peer_id; 1034 u8 addr[6]; 1035 u8 num_elems; 1036 u8 rsvd0; 1037 struct htt_rc_tx_done_params params[]; /* variable length %num_elems */ 1038 } __packed; 1039 1040 /* see htt_rx_indication for similar fields and descriptions */ 1041 struct htt_rx_fragment_indication { 1042 union { 1043 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 1044 struct { 1045 u8 ext_tid:5, 1046 flush_valid:1; 1047 } __packed; 1048 } __packed; 1049 __le16 peer_id; 1050 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 1051 __le16 fw_rx_desc_bytes; 1052 __le16 rsvd0; 1053 1054 u8 fw_msdu_rx_desc[]; 1055 } __packed; 1056 1057 #define ATH10K_IEEE80211_EXTIV BIT(5) 1058 #define ATH10K_IEEE80211_TKIP_MICLEN 8 /* trailing MIC */ 1059 1060 #define HTT_RX_FRAG_IND_INFO0_HEADER_LEN 16 1061 1062 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 1063 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 1064 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 1065 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 1066 1067 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 1068 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 1069 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 1070 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 1071 1072 struct htt_rx_pn_ind { 1073 __le16 peer_id; 1074 u8 tid; 1075 u8 seqno_start; 1076 u8 seqno_end; 1077 u8 pn_ie_count; 1078 u8 reserved; 1079 u8 pn_ies[]; 1080 } __packed; 1081 1082 struct htt_rx_offload_msdu { 1083 __le16 msdu_len; 1084 __le16 peer_id; 1085 u8 vdev_id; 1086 u8 tid; 1087 u8 fw_desc; 1088 u8 payload[]; 1089 } __packed; 1090 1091 struct htt_rx_offload_ind { 1092 u8 reserved; 1093 __le16 msdu_count; 1094 } __packed; 1095 1096 struct htt_rx_in_ord_msdu_desc { 1097 __le32 msdu_paddr; 1098 __le16 msdu_len; 1099 u8 fw_desc; 1100 u8 reserved; 1101 } __packed; 1102 1103 struct htt_rx_in_ord_msdu_desc_ext { 1104 __le64 msdu_paddr; 1105 __le16 msdu_len; 1106 u8 fw_desc; 1107 u8 reserved; 1108 } __packed; 1109 1110 struct htt_rx_in_ord_ind { 1111 u8 info; 1112 __le16 peer_id; 1113 u8 vdev_id; 1114 u8 reserved; 1115 __le16 msdu_count; 1116 union { 1117 struct htt_rx_in_ord_msdu_desc msdu_descs32[0]; 1118 struct htt_rx_in_ord_msdu_desc_ext msdu_descs64[0]; 1119 } __packed; 1120 } __packed; 1121 1122 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f 1123 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 1124 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020 1125 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 1126 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040 1127 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 1128 1129 /* 1130 * target -> host test message definition 1131 * 1132 * The following field definitions describe the format of the test 1133 * message sent from the target to the host. 1134 * The message consists of a 4-octet header, followed by a variable 1135 * number of 32-bit integer values, followed by a variable number 1136 * of 8-bit character values. 1137 * 1138 * |31 16|15 8|7 0| 1139 * |-----------------------------------------------------------| 1140 * | num chars | num ints | msg type | 1141 * |-----------------------------------------------------------| 1142 * | int 0 | 1143 * |-----------------------------------------------------------| 1144 * | int 1 | 1145 * |-----------------------------------------------------------| 1146 * | ... | 1147 * |-----------------------------------------------------------| 1148 * | char 3 | char 2 | char 1 | char 0 | 1149 * |-----------------------------------------------------------| 1150 * | | | ... | char 4 | 1151 * |-----------------------------------------------------------| 1152 * - MSG_TYPE 1153 * Bits 7:0 1154 * Purpose: identifies this as a test message 1155 * Value: HTT_MSG_TYPE_TEST 1156 * - NUM_INTS 1157 * Bits 15:8 1158 * Purpose: indicate how many 32-bit integers follow the message header 1159 * - NUM_CHARS 1160 * Bits 31:16 1161 * Purpose: indicate how many 8-bit characters follow the series of integers 1162 */ 1163 struct htt_rx_test { 1164 u8 num_ints; 1165 __le16 num_chars; 1166 1167 /* payload consists of 2 lists: 1168 * a) num_ints * sizeof(__le32) 1169 * b) num_chars * sizeof(u8) aligned to 4bytes 1170 */ 1171 u8 payload[]; 1172 } __packed; 1173 1174 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 1175 { 1176 return (__le32 *)rx_test->payload; 1177 } 1178 1179 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 1180 { 1181 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 1182 } 1183 1184 /* 1185 * target -> host packet log message 1186 * 1187 * The following field definitions describe the format of the packet log 1188 * message sent from the target to the host. 1189 * The message consists of a 4-octet header,followed by a variable number 1190 * of 32-bit character values. 1191 * 1192 * |31 24|23 16|15 8|7 0| 1193 * |-----------------------------------------------------------| 1194 * | | | | msg type | 1195 * |-----------------------------------------------------------| 1196 * | payload | 1197 * |-----------------------------------------------------------| 1198 * - MSG_TYPE 1199 * Bits 7:0 1200 * Purpose: identifies this as a test message 1201 * Value: HTT_MSG_TYPE_PACKETLOG 1202 */ 1203 struct htt_pktlog_msg { 1204 u8 pad[3]; 1205 u8 payload[]; 1206 } __packed; 1207 1208 struct htt_dbg_stats_rx_reorder_stats { 1209 /* Non QoS MPDUs received */ 1210 __le32 deliver_non_qos; 1211 1212 /* MPDUs received in-order */ 1213 __le32 deliver_in_order; 1214 1215 /* Flush due to reorder timer expired */ 1216 __le32 deliver_flush_timeout; 1217 1218 /* Flush due to move out of window */ 1219 __le32 deliver_flush_oow; 1220 1221 /* Flush due to DELBA */ 1222 __le32 deliver_flush_delba; 1223 1224 /* MPDUs dropped due to FCS error */ 1225 __le32 fcs_error; 1226 1227 /* MPDUs dropped due to monitor mode non-data packet */ 1228 __le32 mgmt_ctrl; 1229 1230 /* MPDUs dropped due to invalid peer */ 1231 __le32 invalid_peer; 1232 1233 /* MPDUs dropped due to duplication (non aggregation) */ 1234 __le32 dup_non_aggr; 1235 1236 /* MPDUs dropped due to processed before */ 1237 __le32 dup_past; 1238 1239 /* MPDUs dropped due to duplicate in reorder queue */ 1240 __le32 dup_in_reorder; 1241 1242 /* Reorder timeout happened */ 1243 __le32 reorder_timeout; 1244 1245 /* invalid bar ssn */ 1246 __le32 invalid_bar_ssn; 1247 1248 /* reorder reset due to bar ssn */ 1249 __le32 ssn_reset; 1250 }; 1251 1252 struct htt_dbg_stats_wal_tx_stats { 1253 /* Num HTT cookies queued to dispatch list */ 1254 __le32 comp_queued; 1255 1256 /* Num HTT cookies dispatched */ 1257 __le32 comp_delivered; 1258 1259 /* Num MSDU queued to WAL */ 1260 __le32 msdu_enqued; 1261 1262 /* Num MPDU queue to WAL */ 1263 __le32 mpdu_enqued; 1264 1265 /* Num MSDUs dropped by WMM limit */ 1266 __le32 wmm_drop; 1267 1268 /* Num Local frames queued */ 1269 __le32 local_enqued; 1270 1271 /* Num Local frames done */ 1272 __le32 local_freed; 1273 1274 /* Num queued to HW */ 1275 __le32 hw_queued; 1276 1277 /* Num PPDU reaped from HW */ 1278 __le32 hw_reaped; 1279 1280 /* Num underruns */ 1281 __le32 underrun; 1282 1283 /* Num PPDUs cleaned up in TX abort */ 1284 __le32 tx_abort; 1285 1286 /* Num MPDUs requeued by SW */ 1287 __le32 mpdus_requeued; 1288 1289 /* excessive retries */ 1290 __le32 tx_ko; 1291 1292 /* data hw rate code */ 1293 __le32 data_rc; 1294 1295 /* Scheduler self triggers */ 1296 __le32 self_triggers; 1297 1298 /* frames dropped due to excessive sw retries */ 1299 __le32 sw_retry_failure; 1300 1301 /* illegal rate phy errors */ 1302 __le32 illgl_rate_phy_err; 1303 1304 /* wal pdev continuous xretry */ 1305 __le32 pdev_cont_xretry; 1306 1307 /* wal pdev continuous xretry */ 1308 __le32 pdev_tx_timeout; 1309 1310 /* wal pdev resets */ 1311 __le32 pdev_resets; 1312 1313 __le32 phy_underrun; 1314 1315 /* MPDU is more than txop limit */ 1316 __le32 txop_ovf; 1317 } __packed; 1318 1319 struct htt_dbg_stats_wal_rx_stats { 1320 /* Cnts any change in ring routing mid-ppdu */ 1321 __le32 mid_ppdu_route_change; 1322 1323 /* Total number of statuses processed */ 1324 __le32 status_rcvd; 1325 1326 /* Extra frags on rings 0-3 */ 1327 __le32 r0_frags; 1328 __le32 r1_frags; 1329 __le32 r2_frags; 1330 __le32 r3_frags; 1331 1332 /* MSDUs / MPDUs delivered to HTT */ 1333 __le32 htt_msdus; 1334 __le32 htt_mpdus; 1335 1336 /* MSDUs / MPDUs delivered to local stack */ 1337 __le32 loc_msdus; 1338 __le32 loc_mpdus; 1339 1340 /* AMSDUs that have more MSDUs than the status ring size */ 1341 __le32 oversize_amsdu; 1342 1343 /* Number of PHY errors */ 1344 __le32 phy_errs; 1345 1346 /* Number of PHY errors drops */ 1347 __le32 phy_err_drop; 1348 1349 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1350 __le32 mpdu_errs; 1351 } __packed; 1352 1353 struct htt_dbg_stats_wal_peer_stats { 1354 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 1355 } __packed; 1356 1357 struct htt_dbg_stats_wal_pdev_txrx { 1358 struct htt_dbg_stats_wal_tx_stats tx_stats; 1359 struct htt_dbg_stats_wal_rx_stats rx_stats; 1360 struct htt_dbg_stats_wal_peer_stats peer_stats; 1361 } __packed; 1362 1363 struct htt_dbg_stats_rx_rate_info { 1364 __le32 mcs[10]; 1365 __le32 sgi[10]; 1366 __le32 nss[4]; 1367 __le32 stbc[10]; 1368 __le32 bw[3]; 1369 __le32 pream[6]; 1370 __le32 ldpc; 1371 __le32 txbf; 1372 }; 1373 1374 /* 1375 * htt_dbg_stats_status - 1376 * present - The requested stats have been delivered in full. 1377 * This indicates that either the stats information was contained 1378 * in its entirety within this message, or else this message 1379 * completes the delivery of the requested stats info that was 1380 * partially delivered through earlier STATS_CONF messages. 1381 * partial - The requested stats have been delivered in part. 1382 * One or more subsequent STATS_CONF messages with the same 1383 * cookie value will be sent to deliver the remainder of the 1384 * information. 1385 * error - The requested stats could not be delivered, for example due 1386 * to a shortage of memory to construct a message holding the 1387 * requested stats. 1388 * invalid - The requested stat type is either not recognized, or the 1389 * target is configured to not gather the stats type in question. 1390 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1391 * series_done - This special value indicates that no further stats info 1392 * elements are present within a series of stats info elems 1393 * (within a stats upload confirmation message). 1394 */ 1395 enum htt_dbg_stats_status { 1396 HTT_DBG_STATS_STATUS_PRESENT = 0, 1397 HTT_DBG_STATS_STATUS_PARTIAL = 1, 1398 HTT_DBG_STATS_STATUS_ERROR = 2, 1399 HTT_DBG_STATS_STATUS_INVALID = 3, 1400 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 1401 }; 1402 1403 /* 1404 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1405 * 1406 * The following field definitions describe the format of the HTT host 1407 * to target frag_desc/msdu_ext bank configuration message. 1408 * The message contains the based address and the min and max id of the 1409 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1410 * MSDU_EXT/FRAG_DESC. 1411 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1412 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1413 * the hardware does the mapping/translation. 1414 * 1415 * Total banks that can be configured is configured to 16. 1416 * 1417 * This should be called before any TX has be initiated by the HTT 1418 * 1419 * |31 16|15 8|7 5|4 0| 1420 * |------------------------------------------------------------| 1421 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1422 * |------------------------------------------------------------| 1423 * | BANK0_BASE_ADDRESS | 1424 * |------------------------------------------------------------| 1425 * | ... | 1426 * |------------------------------------------------------------| 1427 * | BANK15_BASE_ADDRESS | 1428 * |------------------------------------------------------------| 1429 * | BANK0_MAX_ID | BANK0_MIN_ID | 1430 * |------------------------------------------------------------| 1431 * | ... | 1432 * |------------------------------------------------------------| 1433 * | BANK15_MAX_ID | BANK15_MIN_ID | 1434 * |------------------------------------------------------------| 1435 * Header fields: 1436 * - MSG_TYPE 1437 * Bits 7:0 1438 * Value: 0x6 1439 * - BANKx_BASE_ADDRESS 1440 * Bits 31:0 1441 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1442 * bank physical/bus address. 1443 * - BANKx_MIN_ID 1444 * Bits 15:0 1445 * Purpose: Provide a mechanism to specify the min index that needs to 1446 * mapped. 1447 * - BANKx_MAX_ID 1448 * Bits 31:16 1449 * Purpose: Provide a mechanism to specify the max index that needs to 1450 * 1451 */ 1452 struct htt_frag_desc_bank_id { 1453 __le16 bank_min_id; 1454 __le16 bank_max_id; 1455 } __packed; 1456 1457 /* real is 16 but it wouldn't fit in the max htt message size 1458 * so we use a conservatively safe value for now 1459 */ 1460 #define HTT_FRAG_DESC_BANK_MAX 4 1461 1462 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1463 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1464 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2) 1465 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3) 1466 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4) 1467 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4 1468 1469 enum htt_q_depth_type { 1470 HTT_Q_DEPTH_TYPE_BYTES = 0, 1471 HTT_Q_DEPTH_TYPE_MSDUS = 1, 1472 }; 1473 1474 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \ 1475 TARGET_10_4_NUM_VDEVS) 1476 #define HTT_TX_Q_STATE_NUM_TIDS 8 1477 #define HTT_TX_Q_STATE_ENTRY_SIZE 1 1478 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0 1479 1480 /** 1481 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config 1482 * 1483 * Defines host q state format and behavior. See htt_q_state. 1484 * 1485 * @record_size: Defines the size of each host q entry in bytes. In practice 1486 * however firmware (at least 10.4.3-00191) ignores this host 1487 * configuration value and uses hardcoded value of 1. 1488 * @record_multiplier: This is valid only when q depth type is MSDUs. It 1489 * defines the exponent for the power of 2 multiplication. 1490 */ 1491 struct htt_q_state_conf { 1492 __le32 paddr; 1493 __le16 num_peers; 1494 __le16 num_tids; 1495 u8 record_size; 1496 u8 record_multiplier; 1497 u8 pad[2]; 1498 } __packed; 1499 1500 struct htt_frag_desc_bank_cfg32 { 1501 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1502 u8 num_banks; 1503 u8 desc_size; 1504 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1505 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1506 struct htt_q_state_conf q_state; 1507 } __packed; 1508 1509 struct htt_frag_desc_bank_cfg64 { 1510 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1511 u8 num_banks; 1512 u8 desc_size; 1513 __le64 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1514 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1515 struct htt_q_state_conf q_state; 1516 } __packed; 1517 1518 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128 1519 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f 1520 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0 1521 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0 1522 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6 1523 1524 /** 1525 * htt_q_state - shared between host and firmware via DMA 1526 * 1527 * This structure is used for the host to expose it's software queue state to 1528 * firmware so that its rate control can schedule fetch requests for optimized 1529 * performance. This is most notably used for MU-MIMO aggregation when multiple 1530 * MU clients are connected. 1531 * 1532 * @count: Each element defines the host queue depth. When q depth type was 1533 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as: 1534 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and 1535 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as 1536 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 ** 1537 * record_multiplier (see htt_q_state_conf). 1538 * @map: Used by firmware to quickly check which host queues are not empty. It 1539 * is a bitmap simply saying. 1540 * @seq: Used by firmware to quickly check if the host queues were updated 1541 * since it last checked. 1542 * 1543 * FIXME: Is the q_state map[] size calculation really correct? 1544 */ 1545 struct htt_q_state { 1546 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS]; 1547 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32]; 1548 __le32 seq; 1549 } __packed; 1550 1551 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff 1552 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0 1553 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000 1554 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12 1555 1556 struct htt_tx_fetch_record { 1557 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */ 1558 __le16 num_msdus; 1559 __le32 num_bytes; 1560 } __packed; 1561 1562 struct htt_tx_fetch_ind { 1563 u8 pad0; 1564 __le16 fetch_seq_num; 1565 __le32 token; 1566 __le16 num_resp_ids; 1567 __le16 num_records; 1568 union { 1569 /* ath10k_htt_get_tx_fetch_ind_resp_ids() */ 1570 DECLARE_FLEX_ARRAY(__le32, resp_ids); 1571 DECLARE_FLEX_ARRAY(struct htt_tx_fetch_record, records); 1572 }; 1573 } __packed; 1574 1575 static inline void * 1576 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind) 1577 { 1578 return (void *)&ind->records[le16_to_cpu(ind->num_records)]; 1579 } 1580 1581 struct htt_tx_fetch_resp { 1582 u8 pad0; 1583 __le16 resp_id; 1584 __le16 fetch_seq_num; 1585 __le16 num_records; 1586 __le32 token; 1587 struct htt_tx_fetch_record records[]; 1588 } __packed; 1589 1590 struct htt_tx_fetch_confirm { 1591 u8 pad0; 1592 __le16 num_resp_ids; 1593 __le32 resp_ids[]; 1594 } __packed; 1595 1596 enum htt_tx_mode_switch_mode { 1597 HTT_TX_MODE_SWITCH_PUSH = 0, 1598 HTT_TX_MODE_SWITCH_PUSH_PULL = 1, 1599 }; 1600 1601 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0) 1602 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe 1603 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1 1604 1605 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003 1606 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0 1607 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc 1608 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2 1609 1610 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff 1611 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0 1612 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000 1613 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12 1614 1615 struct htt_tx_mode_switch_record { 1616 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */ 1617 __le16 num_max_msdus; 1618 } __packed; 1619 1620 struct htt_tx_mode_switch_ind { 1621 u8 pad0; 1622 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */ 1623 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */ 1624 u8 pad1[2]; 1625 struct htt_tx_mode_switch_record records[]; 1626 } __packed; 1627 1628 struct htt_channel_change { 1629 u8 pad[3]; 1630 __le32 freq; 1631 __le32 center_freq1; 1632 __le32 center_freq2; 1633 __le32 phymode; 1634 } __packed; 1635 1636 struct htt_per_peer_tx_stats_ind { 1637 __le32 succ_bytes; 1638 __le32 retry_bytes; 1639 __le32 failed_bytes; 1640 u8 ratecode; 1641 u8 flags; 1642 __le16 peer_id; 1643 __le16 succ_pkts; 1644 __le16 retry_pkts; 1645 __le16 failed_pkts; 1646 __le16 tx_duration; 1647 __le32 reserved1; 1648 __le32 reserved2; 1649 } __packed; 1650 1651 struct htt_peer_tx_stats { 1652 u8 num_ppdu; 1653 u8 ppdu_len; 1654 u8 version; 1655 u8 payload[]; 1656 } __packed; 1657 1658 #define ATH10K_10_2_TX_STATS_OFFSET 136 1659 #define PEER_STATS_FOR_NO_OF_PPDUS 4 1660 1661 struct ath10k_10_2_peer_tx_stats { 1662 u8 ratecode[PEER_STATS_FOR_NO_OF_PPDUS]; 1663 u8 success_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1664 __le16 success_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1665 u8 retry_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1666 __le16 retry_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1667 u8 failed_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1668 __le16 failed_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1669 u8 flags[PEER_STATS_FOR_NO_OF_PPDUS]; 1670 __le32 tx_duration; 1671 u8 tx_ppdu_cnt; 1672 u8 peer_id; 1673 } __packed; 1674 1675 union htt_rx_pn_t { 1676 /* WEP: 24-bit PN */ 1677 u32 pn24; 1678 1679 /* TKIP or CCMP: 48-bit PN */ 1680 u64 pn48; 1681 1682 /* WAPI: 128-bit PN */ 1683 u64 pn128[2]; 1684 }; 1685 1686 struct htt_cmd { 1687 struct htt_cmd_hdr hdr; 1688 union { 1689 struct htt_ver_req ver_req; 1690 struct htt_mgmt_tx_desc mgmt_tx; 1691 struct htt_data_tx_desc data_tx; 1692 struct htt_rx_ring_setup_32 rx_setup_32; 1693 struct htt_rx_ring_setup_64 rx_setup_64; 1694 struct htt_stats_req stats_req; 1695 struct htt_oob_sync_req oob_sync_req; 1696 struct htt_aggr_conf aggr_conf; 1697 struct htt_aggr_conf_v2 aggr_conf_v2; 1698 struct htt_frag_desc_bank_cfg32 frag_desc_bank_cfg32; 1699 struct htt_frag_desc_bank_cfg64 frag_desc_bank_cfg64; 1700 struct htt_tx_fetch_resp tx_fetch_resp; 1701 }; 1702 } __packed; 1703 1704 struct htt_resp { 1705 struct htt_resp_hdr hdr; 1706 union { 1707 struct htt_ver_resp ver_resp; 1708 struct htt_mgmt_tx_completion mgmt_tx_completion; 1709 struct htt_data_tx_completion data_tx_completion; 1710 struct htt_rx_indication rx_ind; 1711 struct htt_rx_indication_hl rx_ind_hl; 1712 struct htt_rx_fragment_indication rx_frag_ind; 1713 struct htt_rx_peer_map peer_map; 1714 struct htt_rx_peer_unmap peer_unmap; 1715 struct htt_rx_flush rx_flush; 1716 struct htt_rx_addba rx_addba; 1717 struct htt_rx_delba rx_delba; 1718 struct htt_security_indication security_indication; 1719 struct htt_rc_update rc_update; 1720 struct htt_rx_test rx_test; 1721 struct htt_pktlog_msg pktlog_msg; 1722 struct htt_rx_pn_ind rx_pn_ind; 1723 struct htt_rx_offload_ind rx_offload_ind; 1724 struct htt_rx_in_ord_ind rx_in_ord_ind; 1725 struct htt_tx_fetch_ind tx_fetch_ind; 1726 struct htt_tx_fetch_confirm tx_fetch_confirm; 1727 struct htt_tx_mode_switch_ind tx_mode_switch_ind; 1728 struct htt_channel_change chan_change; 1729 struct htt_peer_tx_stats peer_tx_stats; 1730 }; 1731 } __packed; 1732 1733 /*** host side structures follow ***/ 1734 1735 struct htt_tx_done { 1736 u16 msdu_id; 1737 u16 status; 1738 u8 ack_rssi; 1739 }; 1740 1741 enum htt_tx_compl_state { 1742 HTT_TX_COMPL_STATE_NONE, 1743 HTT_TX_COMPL_STATE_ACK, 1744 HTT_TX_COMPL_STATE_NOACK, 1745 HTT_TX_COMPL_STATE_DISCARD, 1746 }; 1747 1748 struct htt_peer_map_event { 1749 u8 vdev_id; 1750 u16 peer_id; 1751 u8 addr[ETH_ALEN]; 1752 }; 1753 1754 struct htt_peer_unmap_event { 1755 u16 peer_id; 1756 }; 1757 1758 struct ath10k_htt_txbuf_32 { 1759 struct htt_data_tx_desc_frag frags[2]; 1760 struct ath10k_htc_hdr htc_hdr; 1761 struct htt_cmd_hdr cmd_hdr; 1762 struct htt_data_tx_desc cmd_tx; 1763 } __packed __aligned(4); 1764 1765 struct ath10k_htt_txbuf_64 { 1766 struct htt_data_tx_desc_frag frags[2]; 1767 struct ath10k_htc_hdr htc_hdr; 1768 struct htt_cmd_hdr cmd_hdr; 1769 struct htt_data_tx_desc_64 cmd_tx; 1770 } __packed __aligned(4); 1771 1772 struct ath10k_htt { 1773 struct ath10k *ar; 1774 enum ath10k_htc_ep_id eid; 1775 1776 struct sk_buff_head rx_indication_head; 1777 1778 u8 target_version_major; 1779 u8 target_version_minor; 1780 struct completion target_version_received; 1781 u8 max_num_amsdu; 1782 u8 max_num_ampdu; 1783 1784 const enum htt_t2h_msg_type *t2h_msg_types; 1785 u32 t2h_msg_types_max; 1786 1787 struct { 1788 /* 1789 * Ring of network buffer objects - This ring is 1790 * used exclusively by the host SW. This ring 1791 * mirrors the dev_addrs_ring that is shared 1792 * between the host SW and the MAC HW. The host SW 1793 * uses this netbufs ring to locate the network 1794 * buffer objects whose data buffers the HW has 1795 * filled. 1796 */ 1797 struct sk_buff **netbufs_ring; 1798 1799 /* This is used only with firmware supporting IN_ORD_IND. 1800 * 1801 * With Full Rx Reorder the HTT Rx Ring is more of a temporary 1802 * buffer ring from which buffer addresses are copied by the 1803 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND 1804 * pointing to specific (re-ordered) buffers. 1805 * 1806 * FIXME: With kernel generic hashing functions there's a lot 1807 * of hash collisions for sk_buffs. 1808 */ 1809 bool in_ord_rx; 1810 DECLARE_HASHTABLE(skb_table, 4); 1811 1812 /* 1813 * Ring of buffer addresses - 1814 * This ring holds the "physical" device address of the 1815 * rx buffers the host SW provides for the MAC HW to 1816 * fill. 1817 */ 1818 union { 1819 __le64 *paddrs_ring_64; 1820 __le32 *paddrs_ring_32; 1821 }; 1822 1823 /* 1824 * Base address of ring, as a "physical" device address 1825 * rather than a CPU address. 1826 */ 1827 dma_addr_t base_paddr; 1828 1829 /* how many elems in the ring (power of 2) */ 1830 int size; 1831 1832 /* size - 1 */ 1833 unsigned int size_mask; 1834 1835 /* how many rx buffers to keep in the ring */ 1836 int fill_level; 1837 1838 /* how many rx buffers (full+empty) are in the ring */ 1839 int fill_cnt; 1840 1841 /* 1842 * alloc_idx - where HTT SW has deposited empty buffers 1843 * This is allocated in consistent mem, so that the FW can 1844 * read this variable, and program the HW's FW_IDX reg with 1845 * the value of this shadow register. 1846 */ 1847 struct { 1848 __le32 *vaddr; 1849 dma_addr_t paddr; 1850 } alloc_idx; 1851 1852 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1853 struct { 1854 unsigned int msdu_payld; 1855 } sw_rd_idx; 1856 1857 /* 1858 * refill_retry_timer - timer triggered when the ring is 1859 * not refilled to the level expected 1860 */ 1861 struct timer_list refill_retry_timer; 1862 1863 /* Protects access to all rx ring buffer state variables */ 1864 spinlock_t lock; 1865 } rx_ring; 1866 1867 unsigned int prefetch_len; 1868 1869 /* Protects access to pending_tx, num_pending_tx */ 1870 spinlock_t tx_lock; 1871 int max_num_pending_tx; 1872 int num_pending_tx; 1873 int num_pending_mgmt_tx; 1874 struct idr pending_tx; 1875 wait_queue_head_t empty_tx_wq; 1876 1877 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */ 1878 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done); 1879 1880 /* set if host-fw communication goes haywire 1881 * used to avoid further failures 1882 */ 1883 bool rx_confused; 1884 atomic_t num_mpdus_ready; 1885 1886 /* This is used to group tx/rx completions separately and process them 1887 * in batches to reduce cache stalls 1888 */ 1889 struct sk_buff_head rx_msdus_q; 1890 struct sk_buff_head rx_in_ord_compl_q; 1891 struct sk_buff_head tx_fetch_ind_q; 1892 1893 /* rx_status template */ 1894 struct ieee80211_rx_status rx_status; 1895 1896 struct { 1897 dma_addr_t paddr; 1898 union { 1899 struct htt_msdu_ext_desc *vaddr_desc_32; 1900 struct htt_msdu_ext_desc_64 *vaddr_desc_64; 1901 }; 1902 size_t size; 1903 } frag_desc; 1904 1905 struct { 1906 dma_addr_t paddr; 1907 union { 1908 struct ath10k_htt_txbuf_32 *vaddr_txbuff_32; 1909 struct ath10k_htt_txbuf_64 *vaddr_txbuff_64; 1910 }; 1911 size_t size; 1912 } txbuf; 1913 1914 struct { 1915 bool enabled; 1916 struct htt_q_state *vaddr; 1917 dma_addr_t paddr; 1918 u16 num_push_allowed; 1919 u16 num_peers; 1920 u16 num_tids; 1921 enum htt_tx_mode_switch_mode mode; 1922 enum htt_q_depth_type type; 1923 } tx_q_state; 1924 1925 bool tx_mem_allocated; 1926 const struct ath10k_htt_tx_ops *tx_ops; 1927 const struct ath10k_htt_rx_ops *rx_ops; 1928 bool disable_tx_comp; 1929 bool bundle_tx; 1930 struct sk_buff_head tx_req_head; 1931 struct sk_buff_head tx_complete_head; 1932 }; 1933 1934 struct ath10k_htt_tx_ops { 1935 int (*htt_send_rx_ring_cfg)(struct ath10k_htt *htt); 1936 int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt); 1937 int (*htt_alloc_frag_desc)(struct ath10k_htt *htt); 1938 void (*htt_free_frag_desc)(struct ath10k_htt *htt); 1939 int (*htt_tx)(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 1940 struct sk_buff *msdu); 1941 int (*htt_alloc_txbuff)(struct ath10k_htt *htt); 1942 void (*htt_free_txbuff)(struct ath10k_htt *htt); 1943 int (*htt_h2t_aggr_cfg_msg)(struct ath10k_htt *htt, 1944 u8 max_subfrms_ampdu, 1945 u8 max_subfrms_amsdu); 1946 void (*htt_flush_tx)(struct ath10k_htt *htt); 1947 }; 1948 1949 static inline int ath10k_htt_send_rx_ring_cfg(struct ath10k_htt *htt) 1950 { 1951 if (!htt->tx_ops->htt_send_rx_ring_cfg) 1952 return -EOPNOTSUPP; 1953 1954 return htt->tx_ops->htt_send_rx_ring_cfg(htt); 1955 } 1956 1957 static inline int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) 1958 { 1959 if (!htt->tx_ops->htt_send_frag_desc_bank_cfg) 1960 return -EOPNOTSUPP; 1961 1962 return htt->tx_ops->htt_send_frag_desc_bank_cfg(htt); 1963 } 1964 1965 static inline int ath10k_htt_alloc_frag_desc(struct ath10k_htt *htt) 1966 { 1967 if (!htt->tx_ops->htt_alloc_frag_desc) 1968 return -EOPNOTSUPP; 1969 1970 return htt->tx_ops->htt_alloc_frag_desc(htt); 1971 } 1972 1973 static inline void ath10k_htt_free_frag_desc(struct ath10k_htt *htt) 1974 { 1975 if (htt->tx_ops->htt_free_frag_desc) 1976 htt->tx_ops->htt_free_frag_desc(htt); 1977 } 1978 1979 static inline int ath10k_htt_tx(struct ath10k_htt *htt, 1980 enum ath10k_hw_txrx_mode txmode, 1981 struct sk_buff *msdu) 1982 { 1983 return htt->tx_ops->htt_tx(htt, txmode, msdu); 1984 } 1985 1986 static inline void ath10k_htt_flush_tx(struct ath10k_htt *htt) 1987 { 1988 if (htt->tx_ops->htt_flush_tx) 1989 htt->tx_ops->htt_flush_tx(htt); 1990 } 1991 1992 static inline int ath10k_htt_alloc_txbuff(struct ath10k_htt *htt) 1993 { 1994 if (!htt->tx_ops->htt_alloc_txbuff) 1995 return -EOPNOTSUPP; 1996 1997 return htt->tx_ops->htt_alloc_txbuff(htt); 1998 } 1999 2000 static inline void ath10k_htt_free_txbuff(struct ath10k_htt *htt) 2001 { 2002 if (htt->tx_ops->htt_free_txbuff) 2003 htt->tx_ops->htt_free_txbuff(htt); 2004 } 2005 2006 static inline int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 2007 u8 max_subfrms_ampdu, 2008 u8 max_subfrms_amsdu) 2009 2010 { 2011 if (!htt->tx_ops->htt_h2t_aggr_cfg_msg) 2012 return -EOPNOTSUPP; 2013 2014 return htt->tx_ops->htt_h2t_aggr_cfg_msg(htt, 2015 max_subfrms_ampdu, 2016 max_subfrms_amsdu); 2017 } 2018 2019 struct ath10k_htt_rx_ops { 2020 size_t (*htt_get_rx_ring_size)(struct ath10k_htt *htt); 2021 void (*htt_config_paddrs_ring)(struct ath10k_htt *htt, void *vaddr); 2022 void (*htt_set_paddrs_ring)(struct ath10k_htt *htt, dma_addr_t paddr, 2023 int idx); 2024 void* (*htt_get_vaddr_ring)(struct ath10k_htt *htt); 2025 void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx); 2026 bool (*htt_rx_proc_rx_frag_ind)(struct ath10k_htt *htt, 2027 struct htt_rx_fragment_indication *rx, 2028 struct sk_buff *skb); 2029 }; 2030 2031 static inline size_t ath10k_htt_get_rx_ring_size(struct ath10k_htt *htt) 2032 { 2033 if (!htt->rx_ops->htt_get_rx_ring_size) 2034 return 0; 2035 2036 return htt->rx_ops->htt_get_rx_ring_size(htt); 2037 } 2038 2039 static inline void ath10k_htt_config_paddrs_ring(struct ath10k_htt *htt, 2040 void *vaddr) 2041 { 2042 if (htt->rx_ops->htt_config_paddrs_ring) 2043 htt->rx_ops->htt_config_paddrs_ring(htt, vaddr); 2044 } 2045 2046 static inline void ath10k_htt_set_paddrs_ring(struct ath10k_htt *htt, 2047 dma_addr_t paddr, 2048 int idx) 2049 { 2050 if (htt->rx_ops->htt_set_paddrs_ring) 2051 htt->rx_ops->htt_set_paddrs_ring(htt, paddr, idx); 2052 } 2053 2054 static inline void *ath10k_htt_get_vaddr_ring(struct ath10k_htt *htt) 2055 { 2056 if (!htt->rx_ops->htt_get_vaddr_ring) 2057 return NULL; 2058 2059 return htt->rx_ops->htt_get_vaddr_ring(htt); 2060 } 2061 2062 static inline void ath10k_htt_reset_paddrs_ring(struct ath10k_htt *htt, int idx) 2063 { 2064 if (htt->rx_ops->htt_reset_paddrs_ring) 2065 htt->rx_ops->htt_reset_paddrs_ring(htt, idx); 2066 } 2067 2068 static inline bool ath10k_htt_rx_proc_rx_frag_ind(struct ath10k_htt *htt, 2069 struct htt_rx_fragment_indication *rx, 2070 struct sk_buff *skb) 2071 { 2072 if (!htt->rx_ops->htt_rx_proc_rx_frag_ind) 2073 return true; 2074 2075 return htt->rx_ops->htt_rx_proc_rx_frag_ind(htt, rx, skb); 2076 } 2077 2078 #define RX_HTT_HDR_STATUS_LEN 64 2079 2080 /* This structure layout is programmed via rx ring setup 2081 * so that FW knows how to transfer the rx descriptor to the host. 2082 * Buffers like this are placed on the rx ring. 2083 */ 2084 struct htt_rx_desc { 2085 union { 2086 /* This field is filled on the host using the msdu buffer 2087 * from htt_rx_indication 2088 */ 2089 struct fw_rx_desc_base fw_desc; 2090 u32 pad; 2091 } __packed; 2092 struct { 2093 struct rx_attention attention; 2094 struct rx_frag_info frag_info; 2095 struct rx_mpdu_start mpdu_start; 2096 struct rx_msdu_start msdu_start; 2097 struct rx_msdu_end msdu_end; 2098 struct rx_mpdu_end mpdu_end; 2099 struct rx_ppdu_start ppdu_start; 2100 struct rx_ppdu_end ppdu_end; 2101 } __packed; 2102 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 2103 u8 msdu_payload[]; 2104 }; 2105 2106 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_MASK 0x00000fff 2107 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_LSB 0 2108 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_MASK 0x00001000 2109 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_LSB 12 2110 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_MASK 0x00002000 2111 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_LSB 13 2112 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_MASK 0x00010000 2113 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_LSB 16 2114 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_MASK 0x01fe0000 2115 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_LSB 17 2116 2117 struct htt_rx_desc_base_hl { 2118 __le32 info; /* HTT_RX_DESC_HL_INFO_ */ 2119 }; 2120 2121 struct htt_rx_chan_info { 2122 __le16 primary_chan_center_freq_mhz; 2123 __le16 contig_chan1_center_freq_mhz; 2124 __le16 contig_chan2_center_freq_mhz; 2125 u8 phy_mode; 2126 u8 reserved; 2127 } __packed; 2128 2129 #define HTT_RX_DESC_ALIGN 8 2130 2131 #define HTT_MAC_ADDR_LEN 6 2132 2133 /* 2134 * FIX THIS 2135 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 2136 * rounded up to a cache line size. 2137 */ 2138 #define HTT_RX_BUF_SIZE 2048 2139 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 2140 2141 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 2142 * aggregated traffic more nicely. 2143 */ 2144 #define ATH10K_HTT_MAX_NUM_REFILL 100 2145 2146 /* 2147 * DMA_MAP expects the buffer to be an integral number of cache lines. 2148 * Rather than checking the actual cache line size, this code makes a 2149 * conservative estimate of what the cache line size could be. 2150 */ 2151 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 2152 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 2153 2154 /* These values are default in most firmware revisions and apparently are a 2155 * sweet spot performance wise. 2156 */ 2157 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3 2158 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64 2159 2160 int ath10k_htt_connect(struct ath10k_htt *htt); 2161 int ath10k_htt_init(struct ath10k *ar); 2162 int ath10k_htt_setup(struct ath10k_htt *htt); 2163 2164 int ath10k_htt_tx_start(struct ath10k_htt *htt); 2165 void ath10k_htt_tx_stop(struct ath10k_htt *htt); 2166 void ath10k_htt_tx_destroy(struct ath10k_htt *htt); 2167 void ath10k_htt_tx_free(struct ath10k_htt *htt); 2168 2169 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 2170 int ath10k_htt_rx_ring_refill(struct ath10k *ar); 2171 void ath10k_htt_rx_free(struct ath10k_htt *htt); 2172 2173 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 2174 void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 2175 bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 2176 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 2177 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, 2178 u64 cookie); 2179 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb); 2180 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 2181 __le32 token, 2182 __le16 fetch_seq_num, 2183 struct htt_tx_fetch_record *records, 2184 size_t num_records); 2185 void ath10k_htt_op_ep_tx_credits(struct ath10k *ar); 2186 2187 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 2188 struct ieee80211_txq *txq); 2189 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 2190 struct ieee80211_txq *txq); 2191 void ath10k_htt_tx_txq_sync(struct ath10k *ar); 2192 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 2193 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt); 2194 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt); 2195 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 2196 bool is_presp); 2197 2198 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); 2199 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 2200 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu); 2201 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar, 2202 struct sk_buff *skb); 2203 int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget); 2204 int ath10k_htt_rx_hl_indication(struct ath10k *ar, int budget); 2205 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt); 2206 void ath10k_htt_set_rx_ops(struct ath10k_htt *htt); 2207 #endif 2208