1f0553ca9SKalle Valo /* SPDX-License-Identifier: ISC */ 2f25b9f28SKalle Valo /* 3f25b9f28SKalle Valo * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4f25b9f28SKalle Valo */ 5f25b9f28SKalle Valo 6f25b9f28SKalle Valo #ifndef _COREDUMP_H_ 7f25b9f28SKalle Valo #define _COREDUMP_H_ 8f25b9f28SKalle Valo 9f25b9f28SKalle Valo #include "core.h" 10f25b9f28SKalle Valo 11f25b9f28SKalle Valo #define ATH10K_FW_CRASH_DUMP_VERSION 1 12f25b9f28SKalle Valo 13f25b9f28SKalle Valo /** 14f25b9f28SKalle Valo * enum ath10k_fw_crash_dump_type - types of data in the dump file 15f25b9f28SKalle Valo * @ATH10K_FW_CRASH_DUMP_REGDUMP: Register crash dump in binary format 16f25b9f28SKalle Valo */ 17f25b9f28SKalle Valo enum ath10k_fw_crash_dump_type { 18f25b9f28SKalle Valo ATH10K_FW_CRASH_DUMP_REGISTERS = 0, 19f25b9f28SKalle Valo ATH10K_FW_CRASH_DUMP_CE_DATA = 1, 20f25b9f28SKalle Valo 21703f261dSAlan Liu /* contains multiple struct ath10k_dump_ram_data_hdr */ 22703f261dSAlan Liu ATH10K_FW_CRASH_DUMP_RAM_DATA = 2, 23703f261dSAlan Liu 24f25b9f28SKalle Valo ATH10K_FW_CRASH_DUMP_MAX, 25f25b9f28SKalle Valo }; 26f25b9f28SKalle Valo 27f25b9f28SKalle Valo struct ath10k_tlv_dump_data { 28f25b9f28SKalle Valo /* see ath10k_fw_crash_dump_type above */ 29f25b9f28SKalle Valo __le32 type; 30f25b9f28SKalle Valo 31f25b9f28SKalle Valo /* in bytes */ 32f25b9f28SKalle Valo __le32 tlv_len; 33f25b9f28SKalle Valo 34f25b9f28SKalle Valo /* pad to 32-bit boundaries as needed */ 35f25b9f28SKalle Valo u8 tlv_data[]; 36f25b9f28SKalle Valo } __packed; 37f25b9f28SKalle Valo 38f25b9f28SKalle Valo struct ath10k_dump_file_data { 39f25b9f28SKalle Valo /* dump file information */ 40f25b9f28SKalle Valo 41f25b9f28SKalle Valo /* "ATH10K-FW-DUMP" */ 42f25b9f28SKalle Valo char df_magic[16]; 43f25b9f28SKalle Valo 44f25b9f28SKalle Valo __le32 len; 45f25b9f28SKalle Valo 46f25b9f28SKalle Valo /* file dump version */ 47f25b9f28SKalle Valo __le32 version; 48f25b9f28SKalle Valo 49f25b9f28SKalle Valo /* some info we can get from ath10k struct that might help */ 50f25b9f28SKalle Valo 51f25b9f28SKalle Valo guid_t guid; 52f25b9f28SKalle Valo 53f25b9f28SKalle Valo __le32 chip_id; 54f25b9f28SKalle Valo 55f25b9f28SKalle Valo /* 0 for now, in place for later hardware */ 56f25b9f28SKalle Valo __le32 bus_type; 57f25b9f28SKalle Valo 58f25b9f28SKalle Valo __le32 target_version; 59f25b9f28SKalle Valo __le32 fw_version_major; 60f25b9f28SKalle Valo __le32 fw_version_minor; 61f25b9f28SKalle Valo __le32 fw_version_release; 62f25b9f28SKalle Valo __le32 fw_version_build; 63f25b9f28SKalle Valo __le32 phy_capability; 64f25b9f28SKalle Valo __le32 hw_min_tx_power; 65f25b9f28SKalle Valo __le32 hw_max_tx_power; 66f25b9f28SKalle Valo __le32 ht_cap_info; 67f25b9f28SKalle Valo __le32 vht_cap_info; 68f25b9f28SKalle Valo __le32 num_rf_chains; 69f25b9f28SKalle Valo 70f25b9f28SKalle Valo /* firmware version string */ 71f25b9f28SKalle Valo char fw_ver[ETHTOOL_FWVERS_LEN]; 72f25b9f28SKalle Valo 73f25b9f28SKalle Valo /* Kernel related information */ 74f25b9f28SKalle Valo 75f25b9f28SKalle Valo /* time-of-day stamp */ 76f25b9f28SKalle Valo __le64 tv_sec; 77f25b9f28SKalle Valo 78f25b9f28SKalle Valo /* time-of-day stamp, nano-seconds */ 79f25b9f28SKalle Valo __le64 tv_nsec; 80f25b9f28SKalle Valo 81f25b9f28SKalle Valo /* LINUX_VERSION_CODE */ 82f25b9f28SKalle Valo __le32 kernel_ver_code; 83f25b9f28SKalle Valo 84f25b9f28SKalle Valo /* VERMAGIC_STRING */ 85f25b9f28SKalle Valo char kernel_ver[64]; 86f25b9f28SKalle Valo 87f25b9f28SKalle Valo /* room for growth w/out changing binary format */ 88f25b9f28SKalle Valo u8 unused[128]; 89f25b9f28SKalle Valo 90f25b9f28SKalle Valo /* struct ath10k_tlv_dump_data + more */ 91d3ed0cf0SGustavo A. R. Silva u8 data[]; 92f25b9f28SKalle Valo } __packed; 93f25b9f28SKalle Valo 94703f261dSAlan Liu struct ath10k_dump_ram_data_hdr { 95703f261dSAlan Liu /* enum ath10k_mem_region_type */ 96703f261dSAlan Liu __le32 region_type; 97703f261dSAlan Liu 98703f261dSAlan Liu __le32 start; 99703f261dSAlan Liu 100703f261dSAlan Liu /* length of payload data, not including this header */ 101703f261dSAlan Liu __le32 length; 102703f261dSAlan Liu 103d3ed0cf0SGustavo A. R. Silva u8 data[]; 104703f261dSAlan Liu }; 105703f261dSAlan Liu 106703f261dSAlan Liu /* magic number to fill the holes not copied due to sections in regions */ 107703f261dSAlan Liu #define ATH10K_MAGIC_NOT_COPIED 0xAA 108703f261dSAlan Liu 109703f261dSAlan Liu /* part of user space ABI */ 110703f261dSAlan Liu enum ath10k_mem_region_type { 111703f261dSAlan Liu ATH10K_MEM_REGION_TYPE_REG = 1, 112703f261dSAlan Liu ATH10K_MEM_REGION_TYPE_DRAM = 2, 113703f261dSAlan Liu ATH10K_MEM_REGION_TYPE_AXI = 3, 114703f261dSAlan Liu ATH10K_MEM_REGION_TYPE_IRAM1 = 4, 115703f261dSAlan Liu ATH10K_MEM_REGION_TYPE_IRAM2 = 5, 116219cc084SAnilkumar Kolli ATH10K_MEM_REGION_TYPE_IOSRAM = 6, 117219cc084SAnilkumar Kolli ATH10K_MEM_REGION_TYPE_IOREG = 7, 1183f14b73cSGovind Singh ATH10K_MEM_REGION_TYPE_MSA = 8, 119703f261dSAlan Liu }; 120703f261dSAlan Liu 121703f261dSAlan Liu /* Define a section of the region which should be copied. As not all parts 122703f261dSAlan Liu * of the memory is possible to copy, for example some of the registers can 123703f261dSAlan Liu * be like that, sections can be used to define what is safe to copy. 124703f261dSAlan Liu * 125703f261dSAlan Liu * To minimize the size of the array, the list must obey the format: 126703f261dSAlan Liu * '{start0,stop0},{start1,stop1},{start2,stop2}....' The values below must 127703f261dSAlan Liu * also obey to 'start0 < stop0 < start1 < stop1 < start2 < ...', otherwise 128703f261dSAlan Liu * we may encouter error in the dump processing. 129703f261dSAlan Liu */ 130703f261dSAlan Liu struct ath10k_mem_section { 131703f261dSAlan Liu u32 start; 132703f261dSAlan Liu u32 end; 133703f261dSAlan Liu }; 134703f261dSAlan Liu 135703f261dSAlan Liu /* One region of a memory layout. If the sections field is null entire 136703f261dSAlan Liu * region is copied. If sections is non-null only the areas specified in 137703f261dSAlan Liu * sections are copied and rest of the areas are filled with 138703f261dSAlan Liu * ATH10K_MAGIC_NOT_COPIED. 139703f261dSAlan Liu */ 140703f261dSAlan Liu struct ath10k_mem_region { 141703f261dSAlan Liu enum ath10k_mem_region_type type; 142703f261dSAlan Liu u32 start; 143703f261dSAlan Liu u32 len; 144703f261dSAlan Liu 145703f261dSAlan Liu const char *name; 146703f261dSAlan Liu 147703f261dSAlan Liu struct { 148703f261dSAlan Liu const struct ath10k_mem_section *sections; 149703f261dSAlan Liu u32 size; 150703f261dSAlan Liu } section_table; 151703f261dSAlan Liu }; 152703f261dSAlan Liu 153703f261dSAlan Liu /* Contains the memory layout of a hardware version identified with the 154703f261dSAlan Liu * hardware id, split into regions. 155703f261dSAlan Liu */ 156703f261dSAlan Liu struct ath10k_hw_mem_layout { 157703f261dSAlan Liu u32 hw_id; 1585f09037aSAnilkumar Kolli u32 hw_rev; 159c796d513SWen Gong enum ath10k_bus bus; 160703f261dSAlan Liu 161703f261dSAlan Liu struct { 162703f261dSAlan Liu const struct ath10k_mem_region *regions; 163703f261dSAlan Liu int size; 164703f261dSAlan Liu } region_table; 165703f261dSAlan Liu }; 166703f261dSAlan Liu 167703f261dSAlan Liu /* FIXME: where to put this? */ 168703f261dSAlan Liu extern unsigned long ath10k_coredump_mask; 169703f261dSAlan Liu 170f25b9f28SKalle Valo #ifdef CONFIG_DEV_COREDUMP 171f25b9f28SKalle Valo 172f25b9f28SKalle Valo int ath10k_coredump_submit(struct ath10k *ar); 173f25b9f28SKalle Valo struct ath10k_fw_crash_data *ath10k_coredump_new(struct ath10k *ar); 174e2fcf60cSKalle Valo int ath10k_coredump_create(struct ath10k *ar); 175703f261dSAlan Liu int ath10k_coredump_register(struct ath10k *ar); 176703f261dSAlan Liu void ath10k_coredump_unregister(struct ath10k *ar); 177e2fcf60cSKalle Valo void ath10k_coredump_destroy(struct ath10k *ar); 178f25b9f28SKalle Valo 179*6f8c8bf4SAbinaya Kalaiselvan const struct ath10k_hw_mem_layout *_ath10k_coredump_get_mem_layout(struct ath10k *ar); 180703f261dSAlan Liu const struct ath10k_hw_mem_layout *ath10k_coredump_get_mem_layout(struct ath10k *ar); 181703f261dSAlan Liu 182f25b9f28SKalle Valo #else /* CONFIG_DEV_COREDUMP */ 183f25b9f28SKalle Valo 184f25b9f28SKalle Valo static inline int ath10k_coredump_submit(struct ath10k *ar) 185f25b9f28SKalle Valo { 186f25b9f28SKalle Valo return 0; 187f25b9f28SKalle Valo } 188f25b9f28SKalle Valo 189f25b9f28SKalle Valo static inline struct ath10k_fw_crash_data *ath10k_coredump_new(struct ath10k *ar) 190f25b9f28SKalle Valo { 191f25b9f28SKalle Valo return NULL; 192f25b9f28SKalle Valo } 193f25b9f28SKalle Valo 194e2fcf60cSKalle Valo static inline int ath10k_coredump_create(struct ath10k *ar) 195e2fcf60cSKalle Valo { 196e2fcf60cSKalle Valo return 0; 197e2fcf60cSKalle Valo } 198e2fcf60cSKalle Valo 199703f261dSAlan Liu static inline int ath10k_coredump_register(struct ath10k *ar) 200703f261dSAlan Liu { 201703f261dSAlan Liu return 0; 202703f261dSAlan Liu } 203703f261dSAlan Liu 204703f261dSAlan Liu static inline void ath10k_coredump_unregister(struct ath10k *ar) 205703f261dSAlan Liu { 206703f261dSAlan Liu } 207703f261dSAlan Liu 208e2fcf60cSKalle Valo static inline void ath10k_coredump_destroy(struct ath10k *ar) 209e2fcf60cSKalle Valo { 210e2fcf60cSKalle Valo } 211e2fcf60cSKalle Valo 212703f261dSAlan Liu static inline const struct ath10k_hw_mem_layout * 213703f261dSAlan Liu ath10k_coredump_get_mem_layout(struct ath10k *ar) 214703f261dSAlan Liu { 215703f261dSAlan Liu return NULL; 216703f261dSAlan Liu } 217703f261dSAlan Liu 218*6f8c8bf4SAbinaya Kalaiselvan static inline const struct ath10k_hw_mem_layout * 219*6f8c8bf4SAbinaya Kalaiselvan _ath10k_coredump_get_mem_layout(struct ath10k *ar) 220*6f8c8bf4SAbinaya Kalaiselvan { 221*6f8c8bf4SAbinaya Kalaiselvan return NULL; 222*6f8c8bf4SAbinaya Kalaiselvan } 223*6f8c8bf4SAbinaya Kalaiselvan 224f25b9f28SKalle Valo #endif /* CONFIG_DEV_COREDUMP */ 225f25b9f28SKalle Valo 226f25b9f28SKalle Valo #endif /* _COREDUMP_H_ */ 227