1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/firmware.h> 21 #include <linux/of.h> 22 #include <linux/dmi.h> 23 #include <linux/ctype.h> 24 #include <asm/byteorder.h> 25 26 #include "core.h" 27 #include "mac.h" 28 #include "htc.h" 29 #include "hif.h" 30 #include "wmi.h" 31 #include "bmi.h" 32 #include "debug.h" 33 #include "htt.h" 34 #include "testmode.h" 35 #include "wmi-ops.h" 36 #include "coredump.h" 37 38 unsigned int ath10k_debug_mask; 39 static unsigned int ath10k_cryptmode_param; 40 static bool uart_print; 41 static bool skip_otp; 42 static bool rawmode; 43 44 /* Enable ATH10K_FW_CRASH_DUMP_REGISTERS and ATH10K_FW_CRASH_DUMP_CE_DATA 45 * by default. 46 */ 47 unsigned long ath10k_coredump_mask = 0x3; 48 49 /* FIXME: most of these should be readonly */ 50 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); 51 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644); 52 module_param(uart_print, bool, 0644); 53 module_param(skip_otp, bool, 0644); 54 module_param(rawmode, bool, 0644); 55 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444); 56 57 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 58 MODULE_PARM_DESC(uart_print, "Uart target debugging"); 59 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); 60 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software"); 61 MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath"); 62 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file"); 63 64 static const struct ath10k_hw_params ath10k_hw_params_list[] = { 65 { 66 .id = QCA988X_HW_2_0_VERSION, 67 .dev_id = QCA988X_2_0_DEVICE_ID, 68 .name = "qca988x hw2.0", 69 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 70 .uart_pin = 7, 71 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 72 .otp_exe_param = 0, 73 .channel_counters_freq_hz = 88000, 74 .max_probe_resp_desc_thres = 0, 75 .cal_data_len = 2116, 76 .fw = { 77 .dir = QCA988X_HW_2_0_FW_DIR, 78 .board = QCA988X_HW_2_0_BOARD_DATA_FILE, 79 .board_size = QCA988X_BOARD_DATA_SZ, 80 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 81 }, 82 .hw_ops = &qca988x_ops, 83 .decap_align_bytes = 4, 84 .spectral_bin_discard = 0, 85 .vht160_mcs_rx_highest = 0, 86 .vht160_mcs_tx_highest = 0, 87 .n_cipher_suites = 8, 88 .num_peers = TARGET_TLV_NUM_PEERS, 89 .ast_skid_limit = 0x10, 90 .num_wds_entries = 0x20, 91 .target_64bit = false, 92 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 93 .shadow_reg_support = false, 94 .rri_on_ddr = false, 95 }, 96 { 97 .id = QCA988X_HW_2_0_VERSION, 98 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT, 99 .name = "qca988x hw2.0 ubiquiti", 100 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 101 .uart_pin = 7, 102 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 103 .otp_exe_param = 0, 104 .channel_counters_freq_hz = 88000, 105 .max_probe_resp_desc_thres = 0, 106 .cal_data_len = 2116, 107 .fw = { 108 .dir = QCA988X_HW_2_0_FW_DIR, 109 .board = QCA988X_HW_2_0_BOARD_DATA_FILE, 110 .board_size = QCA988X_BOARD_DATA_SZ, 111 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 112 }, 113 .hw_ops = &qca988x_ops, 114 .decap_align_bytes = 4, 115 .spectral_bin_discard = 0, 116 .vht160_mcs_rx_highest = 0, 117 .vht160_mcs_tx_highest = 0, 118 .n_cipher_suites = 8, 119 .num_peers = TARGET_TLV_NUM_PEERS, 120 .ast_skid_limit = 0x10, 121 .num_wds_entries = 0x20, 122 .target_64bit = false, 123 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 124 .per_ce_irq = false, 125 .shadow_reg_support = false, 126 .rri_on_ddr = false, 127 }, 128 { 129 .id = QCA9887_HW_1_0_VERSION, 130 .dev_id = QCA9887_1_0_DEVICE_ID, 131 .name = "qca9887 hw1.0", 132 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, 133 .uart_pin = 7, 134 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 135 .otp_exe_param = 0, 136 .channel_counters_freq_hz = 88000, 137 .max_probe_resp_desc_thres = 0, 138 .cal_data_len = 2116, 139 .fw = { 140 .dir = QCA9887_HW_1_0_FW_DIR, 141 .board = QCA9887_HW_1_0_BOARD_DATA_FILE, 142 .board_size = QCA9887_BOARD_DATA_SZ, 143 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, 144 }, 145 .hw_ops = &qca988x_ops, 146 .decap_align_bytes = 4, 147 .spectral_bin_discard = 0, 148 .vht160_mcs_rx_highest = 0, 149 .vht160_mcs_tx_highest = 0, 150 .n_cipher_suites = 8, 151 .num_peers = TARGET_TLV_NUM_PEERS, 152 .ast_skid_limit = 0x10, 153 .num_wds_entries = 0x20, 154 .target_64bit = false, 155 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 156 .per_ce_irq = false, 157 .shadow_reg_support = false, 158 .rri_on_ddr = false, 159 }, 160 { 161 .id = QCA6174_HW_2_1_VERSION, 162 .dev_id = QCA6164_2_1_DEVICE_ID, 163 .name = "qca6164 hw2.1", 164 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 165 .uart_pin = 6, 166 .otp_exe_param = 0, 167 .channel_counters_freq_hz = 88000, 168 .max_probe_resp_desc_thres = 0, 169 .cal_data_len = 8124, 170 .fw = { 171 .dir = QCA6174_HW_2_1_FW_DIR, 172 .board = QCA6174_HW_2_1_BOARD_DATA_FILE, 173 .board_size = QCA6174_BOARD_DATA_SZ, 174 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 175 }, 176 .hw_ops = &qca988x_ops, 177 .decap_align_bytes = 4, 178 .spectral_bin_discard = 0, 179 .vht160_mcs_rx_highest = 0, 180 .vht160_mcs_tx_highest = 0, 181 .n_cipher_suites = 8, 182 .num_peers = TARGET_TLV_NUM_PEERS, 183 .ast_skid_limit = 0x10, 184 .num_wds_entries = 0x20, 185 .target_64bit = false, 186 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 187 .per_ce_irq = false, 188 .shadow_reg_support = false, 189 .rri_on_ddr = false, 190 }, 191 { 192 .id = QCA6174_HW_2_1_VERSION, 193 .dev_id = QCA6174_2_1_DEVICE_ID, 194 .name = "qca6174 hw2.1", 195 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 196 .uart_pin = 6, 197 .otp_exe_param = 0, 198 .channel_counters_freq_hz = 88000, 199 .max_probe_resp_desc_thres = 0, 200 .cal_data_len = 8124, 201 .fw = { 202 .dir = QCA6174_HW_2_1_FW_DIR, 203 .board = QCA6174_HW_2_1_BOARD_DATA_FILE, 204 .board_size = QCA6174_BOARD_DATA_SZ, 205 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 206 }, 207 .hw_ops = &qca988x_ops, 208 .decap_align_bytes = 4, 209 .spectral_bin_discard = 0, 210 .vht160_mcs_rx_highest = 0, 211 .vht160_mcs_tx_highest = 0, 212 .n_cipher_suites = 8, 213 .num_peers = TARGET_TLV_NUM_PEERS, 214 .ast_skid_limit = 0x10, 215 .num_wds_entries = 0x20, 216 .target_64bit = false, 217 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 218 .per_ce_irq = false, 219 .shadow_reg_support = false, 220 .rri_on_ddr = false, 221 }, 222 { 223 .id = QCA6174_HW_3_0_VERSION, 224 .dev_id = QCA6174_2_1_DEVICE_ID, 225 .name = "qca6174 hw3.0", 226 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 227 .uart_pin = 6, 228 .otp_exe_param = 0, 229 .channel_counters_freq_hz = 88000, 230 .max_probe_resp_desc_thres = 0, 231 .cal_data_len = 8124, 232 .fw = { 233 .dir = QCA6174_HW_3_0_FW_DIR, 234 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 235 .board_size = QCA6174_BOARD_DATA_SZ, 236 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 237 }, 238 .hw_ops = &qca988x_ops, 239 .decap_align_bytes = 4, 240 .spectral_bin_discard = 0, 241 .vht160_mcs_rx_highest = 0, 242 .vht160_mcs_tx_highest = 0, 243 .n_cipher_suites = 8, 244 .num_peers = TARGET_TLV_NUM_PEERS, 245 .ast_skid_limit = 0x10, 246 .num_wds_entries = 0x20, 247 .target_64bit = false, 248 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 249 .per_ce_irq = false, 250 .shadow_reg_support = false, 251 .rri_on_ddr = false, 252 }, 253 { 254 .id = QCA6174_HW_3_2_VERSION, 255 .dev_id = QCA6174_2_1_DEVICE_ID, 256 .name = "qca6174 hw3.2", 257 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 258 .uart_pin = 6, 259 .otp_exe_param = 0, 260 .channel_counters_freq_hz = 88000, 261 .max_probe_resp_desc_thres = 0, 262 .cal_data_len = 8124, 263 .fw = { 264 /* uses same binaries as hw3.0 */ 265 .dir = QCA6174_HW_3_0_FW_DIR, 266 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 267 .board_size = QCA6174_BOARD_DATA_SZ, 268 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 269 }, 270 .hw_ops = &qca6174_ops, 271 .hw_clk = qca6174_clk, 272 .target_cpu_freq = 176000000, 273 .decap_align_bytes = 4, 274 .spectral_bin_discard = 0, 275 .vht160_mcs_rx_highest = 0, 276 .vht160_mcs_tx_highest = 0, 277 .n_cipher_suites = 8, 278 .num_peers = TARGET_TLV_NUM_PEERS, 279 .ast_skid_limit = 0x10, 280 .num_wds_entries = 0x20, 281 .target_64bit = false, 282 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 283 .per_ce_irq = false, 284 .shadow_reg_support = false, 285 .rri_on_ddr = false, 286 }, 287 { 288 .id = QCA99X0_HW_2_0_DEV_VERSION, 289 .dev_id = QCA99X0_2_0_DEVICE_ID, 290 .name = "qca99x0 hw2.0", 291 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, 292 .uart_pin = 7, 293 .otp_exe_param = 0x00000700, 294 .continuous_frag_desc = true, 295 .cck_rate_map_rev2 = true, 296 .channel_counters_freq_hz = 150000, 297 .max_probe_resp_desc_thres = 24, 298 .tx_chain_mask = 0xf, 299 .rx_chain_mask = 0xf, 300 .max_spatial_stream = 4, 301 .cal_data_len = 12064, 302 .fw = { 303 .dir = QCA99X0_HW_2_0_FW_DIR, 304 .board = QCA99X0_HW_2_0_BOARD_DATA_FILE, 305 .board_size = QCA99X0_BOARD_DATA_SZ, 306 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 307 }, 308 .sw_decrypt_mcast_mgmt = true, 309 .hw_ops = &qca99x0_ops, 310 .decap_align_bytes = 1, 311 .spectral_bin_discard = 4, 312 .vht160_mcs_rx_highest = 0, 313 .vht160_mcs_tx_highest = 0, 314 .n_cipher_suites = 11, 315 .num_peers = TARGET_TLV_NUM_PEERS, 316 .ast_skid_limit = 0x10, 317 .num_wds_entries = 0x20, 318 .target_64bit = false, 319 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 320 .per_ce_irq = false, 321 .shadow_reg_support = false, 322 .rri_on_ddr = false, 323 }, 324 { 325 .id = QCA9984_HW_1_0_DEV_VERSION, 326 .dev_id = QCA9984_1_0_DEVICE_ID, 327 .name = "qca9984/qca9994 hw1.0", 328 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, 329 .uart_pin = 7, 330 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 331 .otp_exe_param = 0x00000700, 332 .continuous_frag_desc = true, 333 .cck_rate_map_rev2 = true, 334 .channel_counters_freq_hz = 150000, 335 .max_probe_resp_desc_thres = 24, 336 .tx_chain_mask = 0xf, 337 .rx_chain_mask = 0xf, 338 .max_spatial_stream = 4, 339 .cal_data_len = 12064, 340 .fw = { 341 .dir = QCA9984_HW_1_0_FW_DIR, 342 .board = QCA9984_HW_1_0_BOARD_DATA_FILE, 343 .board_size = QCA99X0_BOARD_DATA_SZ, 344 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 345 }, 346 .sw_decrypt_mcast_mgmt = true, 347 .hw_ops = &qca99x0_ops, 348 .decap_align_bytes = 1, 349 .spectral_bin_discard = 12, 350 351 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz 352 * or 2x2 160Mhz, long-guard-interval. 353 */ 354 .vht160_mcs_rx_highest = 1560, 355 .vht160_mcs_tx_highest = 1560, 356 .n_cipher_suites = 11, 357 .num_peers = TARGET_TLV_NUM_PEERS, 358 .ast_skid_limit = 0x10, 359 .num_wds_entries = 0x20, 360 .target_64bit = false, 361 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 362 .per_ce_irq = false, 363 .shadow_reg_support = false, 364 .rri_on_ddr = false, 365 }, 366 { 367 .id = QCA9888_HW_2_0_DEV_VERSION, 368 .dev_id = QCA9888_2_0_DEVICE_ID, 369 .name = "qca9888 hw2.0", 370 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, 371 .uart_pin = 7, 372 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 373 .otp_exe_param = 0x00000700, 374 .continuous_frag_desc = true, 375 .channel_counters_freq_hz = 150000, 376 .max_probe_resp_desc_thres = 24, 377 .tx_chain_mask = 3, 378 .rx_chain_mask = 3, 379 .max_spatial_stream = 2, 380 .cal_data_len = 12064, 381 .fw = { 382 .dir = QCA9888_HW_2_0_FW_DIR, 383 .board = QCA9888_HW_2_0_BOARD_DATA_FILE, 384 .board_size = QCA99X0_BOARD_DATA_SZ, 385 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 386 }, 387 .sw_decrypt_mcast_mgmt = true, 388 .hw_ops = &qca99x0_ops, 389 .decap_align_bytes = 1, 390 .spectral_bin_discard = 12, 391 392 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or 393 * 1x1 160Mhz, long-guard-interval. 394 */ 395 .vht160_mcs_rx_highest = 780, 396 .vht160_mcs_tx_highest = 780, 397 .n_cipher_suites = 11, 398 .num_peers = TARGET_TLV_NUM_PEERS, 399 .ast_skid_limit = 0x10, 400 .num_wds_entries = 0x20, 401 .target_64bit = false, 402 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 403 .per_ce_irq = false, 404 .shadow_reg_support = false, 405 .rri_on_ddr = false, 406 }, 407 { 408 .id = QCA9377_HW_1_0_DEV_VERSION, 409 .dev_id = QCA9377_1_0_DEVICE_ID, 410 .name = "qca9377 hw1.0", 411 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 412 .uart_pin = 6, 413 .otp_exe_param = 0, 414 .channel_counters_freq_hz = 88000, 415 .max_probe_resp_desc_thres = 0, 416 .cal_data_len = 8124, 417 .fw = { 418 .dir = QCA9377_HW_1_0_FW_DIR, 419 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 420 .board_size = QCA9377_BOARD_DATA_SZ, 421 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 422 }, 423 .hw_ops = &qca988x_ops, 424 .decap_align_bytes = 4, 425 .spectral_bin_discard = 0, 426 .vht160_mcs_rx_highest = 0, 427 .vht160_mcs_tx_highest = 0, 428 .n_cipher_suites = 8, 429 .num_peers = TARGET_TLV_NUM_PEERS, 430 .ast_skid_limit = 0x10, 431 .num_wds_entries = 0x20, 432 .target_64bit = false, 433 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 434 .per_ce_irq = false, 435 .shadow_reg_support = false, 436 .rri_on_ddr = false, 437 }, 438 { 439 .id = QCA9377_HW_1_1_DEV_VERSION, 440 .dev_id = QCA9377_1_0_DEVICE_ID, 441 .name = "qca9377 hw1.1", 442 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 443 .uart_pin = 6, 444 .otp_exe_param = 0, 445 .channel_counters_freq_hz = 88000, 446 .max_probe_resp_desc_thres = 0, 447 .cal_data_len = 8124, 448 .fw = { 449 .dir = QCA9377_HW_1_0_FW_DIR, 450 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 451 .board_size = QCA9377_BOARD_DATA_SZ, 452 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 453 }, 454 .hw_ops = &qca6174_ops, 455 .hw_clk = qca6174_clk, 456 .target_cpu_freq = 176000000, 457 .decap_align_bytes = 4, 458 .spectral_bin_discard = 0, 459 .vht160_mcs_rx_highest = 0, 460 .vht160_mcs_tx_highest = 0, 461 .n_cipher_suites = 8, 462 .num_peers = TARGET_TLV_NUM_PEERS, 463 .ast_skid_limit = 0x10, 464 .num_wds_entries = 0x20, 465 .target_64bit = false, 466 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 467 .per_ce_irq = false, 468 .shadow_reg_support = false, 469 .rri_on_ddr = false, 470 }, 471 { 472 .id = QCA4019_HW_1_0_DEV_VERSION, 473 .dev_id = 0, 474 .name = "qca4019 hw1.0", 475 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, 476 .uart_pin = 7, 477 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 478 .otp_exe_param = 0x0010000, 479 .continuous_frag_desc = true, 480 .cck_rate_map_rev2 = true, 481 .channel_counters_freq_hz = 125000, 482 .max_probe_resp_desc_thres = 24, 483 .tx_chain_mask = 0x3, 484 .rx_chain_mask = 0x3, 485 .max_spatial_stream = 2, 486 .cal_data_len = 12064, 487 .fw = { 488 .dir = QCA4019_HW_1_0_FW_DIR, 489 .board = QCA4019_HW_1_0_BOARD_DATA_FILE, 490 .board_size = QCA4019_BOARD_DATA_SZ, 491 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, 492 }, 493 .sw_decrypt_mcast_mgmt = true, 494 .hw_ops = &qca99x0_ops, 495 .decap_align_bytes = 1, 496 .spectral_bin_discard = 4, 497 .vht160_mcs_rx_highest = 0, 498 .vht160_mcs_tx_highest = 0, 499 .n_cipher_suites = 11, 500 .num_peers = TARGET_TLV_NUM_PEERS, 501 .ast_skid_limit = 0x10, 502 .num_wds_entries = 0x20, 503 .target_64bit = false, 504 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 505 .per_ce_irq = false, 506 .shadow_reg_support = false, 507 .rri_on_ddr = false, 508 }, 509 { 510 .id = WCN3990_HW_1_0_DEV_VERSION, 511 .dev_id = 0, 512 .name = "wcn3990 hw1.0", 513 .continuous_frag_desc = true, 514 .tx_chain_mask = 0x7, 515 .rx_chain_mask = 0x7, 516 .max_spatial_stream = 4, 517 .fw = { 518 .dir = WCN3990_HW_1_0_FW_DIR, 519 }, 520 .sw_decrypt_mcast_mgmt = true, 521 .hw_ops = &wcn3990_ops, 522 .decap_align_bytes = 1, 523 .num_peers = TARGET_HL_10_TLV_NUM_PEERS, 524 .ast_skid_limit = TARGET_HL_10_TLV_AST_SKID_LIMIT, 525 .num_wds_entries = TARGET_HL_10_TLV_NUM_WDS_ENTRIES, 526 .target_64bit = true, 527 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, 528 .per_ce_irq = true, 529 .shadow_reg_support = true, 530 .rri_on_ddr = true, 531 }, 532 }; 533 534 static const char *const ath10k_core_fw_feature_str[] = { 535 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", 536 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", 537 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", 538 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", 539 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", 540 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", 541 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", 542 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", 543 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", 544 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", 545 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode", 546 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca", 547 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp", 548 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl", 549 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param", 550 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war", 551 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast", 552 [ATH10K_FW_FEATURE_NO_PS] = "no-ps", 553 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference", 554 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi", 555 }; 556 557 static unsigned int ath10k_core_get_fw_feature_str(char *buf, 558 size_t buf_len, 559 enum ath10k_fw_features feat) 560 { 561 /* make sure that ath10k_core_fw_feature_str[] gets updated */ 562 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) != 563 ATH10K_FW_FEATURE_COUNT); 564 565 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || 566 WARN_ON(!ath10k_core_fw_feature_str[feat])) { 567 return scnprintf(buf, buf_len, "bit%d", feat); 568 } 569 570 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); 571 } 572 573 void ath10k_core_get_fw_features_str(struct ath10k *ar, 574 char *buf, 575 size_t buf_len) 576 { 577 size_t len = 0; 578 int i; 579 580 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 581 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) { 582 if (len > 0) 583 len += scnprintf(buf + len, buf_len - len, ","); 584 585 len += ath10k_core_get_fw_feature_str(buf + len, 586 buf_len - len, 587 i); 588 } 589 } 590 } 591 592 static void ath10k_send_suspend_complete(struct ath10k *ar) 593 { 594 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); 595 596 complete(&ar->target_suspend); 597 } 598 599 static void ath10k_init_sdio(struct ath10k *ar) 600 { 601 u32 param = 0; 602 603 ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256); 604 ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99); 605 ath10k_bmi_read32(ar, hi_acs_flags, ¶m); 606 607 param |= (HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET | 608 HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET | 609 HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE); 610 611 ath10k_bmi_write32(ar, hi_acs_flags, param); 612 } 613 614 static int ath10k_init_configure_target(struct ath10k *ar) 615 { 616 u32 param_host; 617 int ret; 618 619 /* tell target which HTC version it is used*/ 620 ret = ath10k_bmi_write32(ar, hi_app_host_interest, 621 HTC_PROTOCOL_VERSION); 622 if (ret) { 623 ath10k_err(ar, "settings HTC version failed\n"); 624 return ret; 625 } 626 627 /* set the firmware mode to STA/IBSS/AP */ 628 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); 629 if (ret) { 630 ath10k_err(ar, "setting firmware mode (1/2) failed\n"); 631 return ret; 632 } 633 634 /* TODO following parameters need to be re-visited. */ 635 /* num_device */ 636 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); 637 /* Firmware mode */ 638 /* FIXME: Why FW_MODE_AP ??.*/ 639 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); 640 /* mac_addr_method */ 641 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 642 /* firmware_bridge */ 643 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 644 /* fwsubmode */ 645 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); 646 647 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); 648 if (ret) { 649 ath10k_err(ar, "setting firmware mode (2/2) failed\n"); 650 return ret; 651 } 652 653 /* We do all byte-swapping on the host */ 654 ret = ath10k_bmi_write32(ar, hi_be, 0); 655 if (ret) { 656 ath10k_err(ar, "setting host CPU BE mode failed\n"); 657 return ret; 658 } 659 660 /* FW descriptor/Data swap flags */ 661 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); 662 663 if (ret) { 664 ath10k_err(ar, "setting FW data/desc swap flags failed\n"); 665 return ret; 666 } 667 668 /* Some devices have a special sanity check that verifies the PCI 669 * Device ID is written to this host interest var. It is known to be 670 * required to boot QCA6164. 671 */ 672 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext, 673 ar->dev_id); 674 if (ret) { 675 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret); 676 return ret; 677 } 678 679 return 0; 680 } 681 682 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, 683 const char *dir, 684 const char *file) 685 { 686 char filename[100]; 687 const struct firmware *fw; 688 int ret; 689 690 if (file == NULL) 691 return ERR_PTR(-ENOENT); 692 693 if (dir == NULL) 694 dir = "."; 695 696 snprintf(filename, sizeof(filename), "%s/%s", dir, file); 697 ret = firmware_request_nowarn(&fw, filename, ar->dev); 698 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 699 filename, ret); 700 701 if (ret) 702 return ERR_PTR(ret); 703 704 return fw; 705 } 706 707 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, 708 size_t data_len) 709 { 710 u32 board_data_size = ar->hw_params.fw.board_size; 711 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; 712 u32 board_ext_data_addr; 713 int ret; 714 715 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); 716 if (ret) { 717 ath10k_err(ar, "could not read board ext data addr (%d)\n", 718 ret); 719 return ret; 720 } 721 722 ath10k_dbg(ar, ATH10K_DBG_BOOT, 723 "boot push board extended data addr 0x%x\n", 724 board_ext_data_addr); 725 726 if (board_ext_data_addr == 0) 727 return 0; 728 729 if (data_len != (board_data_size + board_ext_data_size)) { 730 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", 731 data_len, board_data_size, board_ext_data_size); 732 return -EINVAL; 733 } 734 735 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, 736 data + board_data_size, 737 board_ext_data_size); 738 if (ret) { 739 ath10k_err(ar, "could not write board ext data (%d)\n", ret); 740 return ret; 741 } 742 743 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, 744 (board_ext_data_size << 16) | 1); 745 if (ret) { 746 ath10k_err(ar, "could not write board ext data bit (%d)\n", 747 ret); 748 return ret; 749 } 750 751 return 0; 752 } 753 754 static int ath10k_download_board_data(struct ath10k *ar, const void *data, 755 size_t data_len) 756 { 757 u32 board_data_size = ar->hw_params.fw.board_size; 758 u32 address; 759 int ret; 760 761 ret = ath10k_push_board_ext_data(ar, data, data_len); 762 if (ret) { 763 ath10k_err(ar, "could not push board ext data (%d)\n", ret); 764 goto exit; 765 } 766 767 ret = ath10k_bmi_read32(ar, hi_board_data, &address); 768 if (ret) { 769 ath10k_err(ar, "could not read board data addr (%d)\n", ret); 770 goto exit; 771 } 772 773 ret = ath10k_bmi_write_memory(ar, address, data, 774 min_t(u32, board_data_size, 775 data_len)); 776 if (ret) { 777 ath10k_err(ar, "could not write board data (%d)\n", ret); 778 goto exit; 779 } 780 781 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); 782 if (ret) { 783 ath10k_err(ar, "could not write board data bit (%d)\n", ret); 784 goto exit; 785 } 786 787 exit: 788 return ret; 789 } 790 791 static int ath10k_download_cal_file(struct ath10k *ar, 792 const struct firmware *file) 793 { 794 int ret; 795 796 if (!file) 797 return -ENOENT; 798 799 if (IS_ERR(file)) 800 return PTR_ERR(file); 801 802 ret = ath10k_download_board_data(ar, file->data, file->size); 803 if (ret) { 804 ath10k_err(ar, "failed to download cal_file data: %d\n", ret); 805 return ret; 806 } 807 808 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); 809 810 return 0; 811 } 812 813 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name) 814 { 815 struct device_node *node; 816 int data_len; 817 void *data; 818 int ret; 819 820 node = ar->dev->of_node; 821 if (!node) 822 /* Device Tree is optional, don't print any warnings if 823 * there's no node for ath10k. 824 */ 825 return -ENOENT; 826 827 if (!of_get_property(node, dt_name, &data_len)) { 828 /* The calibration data node is optional */ 829 return -ENOENT; 830 } 831 832 if (data_len != ar->hw_params.cal_data_len) { 833 ath10k_warn(ar, "invalid calibration data length in DT: %d\n", 834 data_len); 835 ret = -EMSGSIZE; 836 goto out; 837 } 838 839 data = kmalloc(data_len, GFP_KERNEL); 840 if (!data) { 841 ret = -ENOMEM; 842 goto out; 843 } 844 845 ret = of_property_read_u8_array(node, dt_name, data, data_len); 846 if (ret) { 847 ath10k_warn(ar, "failed to read calibration data from DT: %d\n", 848 ret); 849 goto out_free; 850 } 851 852 ret = ath10k_download_board_data(ar, data, data_len); 853 if (ret) { 854 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", 855 ret); 856 goto out_free; 857 } 858 859 ret = 0; 860 861 out_free: 862 kfree(data); 863 864 out: 865 return ret; 866 } 867 868 static int ath10k_download_cal_eeprom(struct ath10k *ar) 869 { 870 size_t data_len; 871 void *data = NULL; 872 int ret; 873 874 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len); 875 if (ret) { 876 if (ret != -EOPNOTSUPP) 877 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n", 878 ret); 879 goto out_free; 880 } 881 882 ret = ath10k_download_board_data(ar, data, data_len); 883 if (ret) { 884 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n", 885 ret); 886 goto out_free; 887 } 888 889 ret = 0; 890 891 out_free: 892 kfree(data); 893 894 return ret; 895 } 896 897 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) 898 { 899 u32 result, address; 900 u8 board_id, chip_id; 901 int ret, bmi_board_id_param; 902 903 address = ar->hw_params.patch_load_addr; 904 905 if (!ar->normal_mode_fw.fw_file.otp_data || 906 !ar->normal_mode_fw.fw_file.otp_len) { 907 ath10k_warn(ar, 908 "failed to retrieve board id because of invalid otp\n"); 909 return -ENODATA; 910 } 911 912 ath10k_dbg(ar, ATH10K_DBG_BOOT, 913 "boot upload otp to 0x%x len %zd for board id\n", 914 address, ar->normal_mode_fw.fw_file.otp_len); 915 916 ret = ath10k_bmi_fast_download(ar, address, 917 ar->normal_mode_fw.fw_file.otp_data, 918 ar->normal_mode_fw.fw_file.otp_len); 919 if (ret) { 920 ath10k_err(ar, "could not write otp for board id check: %d\n", 921 ret); 922 return ret; 923 } 924 925 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 926 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE) 927 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID; 928 else 929 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID; 930 931 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result); 932 if (ret) { 933 ath10k_err(ar, "could not execute otp for board id check: %d\n", 934 ret); 935 return ret; 936 } 937 938 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP); 939 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP); 940 941 ath10k_dbg(ar, ATH10K_DBG_BOOT, 942 "boot get otp board id result 0x%08x board_id %d chip_id %d\n", 943 result, board_id, chip_id); 944 945 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 || 946 (board_id == 0)) { 947 ath10k_dbg(ar, ATH10K_DBG_BOOT, 948 "board id does not exist in otp, ignore it\n"); 949 return -EOPNOTSUPP; 950 } 951 952 ar->id.bmi_ids_valid = true; 953 ar->id.bmi_board_id = board_id; 954 ar->id.bmi_chip_id = chip_id; 955 956 return 0; 957 } 958 959 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data) 960 { 961 struct ath10k *ar = data; 962 const char *bdf_ext; 963 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC; 964 u8 bdf_enabled; 965 int i; 966 967 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE) 968 return; 969 970 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) { 971 ath10k_dbg(ar, ATH10K_DBG_BOOT, 972 "wrong smbios bdf ext type length (%d).\n", 973 hdr->length); 974 return; 975 } 976 977 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET); 978 if (!bdf_enabled) { 979 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n"); 980 return; 981 } 982 983 /* Only one string exists (per spec) */ 984 bdf_ext = (char *)hdr + hdr->length; 985 986 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) { 987 ath10k_dbg(ar, ATH10K_DBG_BOOT, 988 "bdf variant magic does not match.\n"); 989 return; 990 } 991 992 for (i = 0; i < strlen(bdf_ext); i++) { 993 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) { 994 ath10k_dbg(ar, ATH10K_DBG_BOOT, 995 "bdf variant name contains non ascii chars.\n"); 996 return; 997 } 998 } 999 1000 /* Copy extension name without magic suffix */ 1001 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic), 1002 sizeof(ar->id.bdf_ext)) < 0) { 1003 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1004 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1005 bdf_ext); 1006 return; 1007 } 1008 1009 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1010 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1011 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext); 1012 } 1013 1014 static int ath10k_core_check_smbios(struct ath10k *ar) 1015 { 1016 ar->id.bdf_ext[0] = '\0'; 1017 dmi_walk(ath10k_core_check_bdfext, ar); 1018 1019 if (ar->id.bdf_ext[0] == '\0') 1020 return -ENODATA; 1021 1022 return 0; 1023 } 1024 1025 static int ath10k_core_check_dt(struct ath10k *ar) 1026 { 1027 struct device_node *node; 1028 const char *variant = NULL; 1029 1030 node = ar->dev->of_node; 1031 if (!node) 1032 return -ENOENT; 1033 1034 of_property_read_string(node, "qcom,ath10k-calibration-variant", 1035 &variant); 1036 if (!variant) 1037 return -ENODATA; 1038 1039 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0) 1040 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1041 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1042 variant); 1043 1044 return 0; 1045 } 1046 1047 static int ath10k_download_and_run_otp(struct ath10k *ar) 1048 { 1049 u32 result, address = ar->hw_params.patch_load_addr; 1050 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; 1051 int ret; 1052 1053 ret = ath10k_download_board_data(ar, 1054 ar->running_fw->board_data, 1055 ar->running_fw->board_len); 1056 if (ret) { 1057 ath10k_err(ar, "failed to download board data: %d\n", ret); 1058 return ret; 1059 } 1060 1061 /* OTP is optional */ 1062 1063 if (!ar->running_fw->fw_file.otp_data || 1064 !ar->running_fw->fw_file.otp_len) { 1065 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n", 1066 ar->running_fw->fw_file.otp_data, 1067 ar->running_fw->fw_file.otp_len); 1068 return 0; 1069 } 1070 1071 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", 1072 address, ar->running_fw->fw_file.otp_len); 1073 1074 ret = ath10k_bmi_fast_download(ar, address, 1075 ar->running_fw->fw_file.otp_data, 1076 ar->running_fw->fw_file.otp_len); 1077 if (ret) { 1078 ath10k_err(ar, "could not write otp (%d)\n", ret); 1079 return ret; 1080 } 1081 1082 /* As of now pre-cal is valid for 10_4 variants */ 1083 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1084 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE) 1085 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL; 1086 1087 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); 1088 if (ret) { 1089 ath10k_err(ar, "could not execute otp (%d)\n", ret); 1090 return ret; 1091 } 1092 1093 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); 1094 1095 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, 1096 ar->running_fw->fw_file.fw_features)) && 1097 result != 0) { 1098 ath10k_err(ar, "otp calibration failed: %d", result); 1099 return -EINVAL; 1100 } 1101 1102 return 0; 1103 } 1104 1105 static int ath10k_download_fw(struct ath10k *ar) 1106 { 1107 u32 address, data_len; 1108 const void *data; 1109 int ret; 1110 1111 address = ar->hw_params.patch_load_addr; 1112 1113 data = ar->running_fw->fw_file.firmware_data; 1114 data_len = ar->running_fw->fw_file.firmware_len; 1115 1116 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file); 1117 if (ret) { 1118 ath10k_err(ar, "failed to configure fw code swap: %d\n", 1119 ret); 1120 return ret; 1121 } 1122 1123 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1124 "boot uploading firmware image %pK len %d\n", 1125 data, data_len); 1126 1127 ret = ath10k_bmi_fast_download(ar, address, data, data_len); 1128 if (ret) { 1129 ath10k_err(ar, "failed to download firmware: %d\n", 1130 ret); 1131 return ret; 1132 } 1133 1134 return ret; 1135 } 1136 1137 static void ath10k_core_free_board_files(struct ath10k *ar) 1138 { 1139 if (!IS_ERR(ar->normal_mode_fw.board)) 1140 release_firmware(ar->normal_mode_fw.board); 1141 1142 ar->normal_mode_fw.board = NULL; 1143 ar->normal_mode_fw.board_data = NULL; 1144 ar->normal_mode_fw.board_len = 0; 1145 } 1146 1147 static void ath10k_core_free_firmware_files(struct ath10k *ar) 1148 { 1149 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware)) 1150 release_firmware(ar->normal_mode_fw.fw_file.firmware); 1151 1152 if (!IS_ERR(ar->cal_file)) 1153 release_firmware(ar->cal_file); 1154 1155 if (!IS_ERR(ar->pre_cal_file)) 1156 release_firmware(ar->pre_cal_file); 1157 1158 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file); 1159 1160 ar->normal_mode_fw.fw_file.otp_data = NULL; 1161 ar->normal_mode_fw.fw_file.otp_len = 0; 1162 1163 ar->normal_mode_fw.fw_file.firmware = NULL; 1164 ar->normal_mode_fw.fw_file.firmware_data = NULL; 1165 ar->normal_mode_fw.fw_file.firmware_len = 0; 1166 1167 ar->cal_file = NULL; 1168 ar->pre_cal_file = NULL; 1169 } 1170 1171 static int ath10k_fetch_cal_file(struct ath10k *ar) 1172 { 1173 char filename[100]; 1174 1175 /* pre-cal-<bus>-<id>.bin */ 1176 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", 1177 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1178 1179 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1180 if (!IS_ERR(ar->pre_cal_file)) 1181 goto success; 1182 1183 /* cal-<bus>-<id>.bin */ 1184 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", 1185 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1186 1187 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1188 if (IS_ERR(ar->cal_file)) 1189 /* calibration file is optional, don't print any warnings */ 1190 return PTR_ERR(ar->cal_file); 1191 success: 1192 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", 1193 ATH10K_FW_DIR, filename); 1194 1195 return 0; 1196 } 1197 1198 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar) 1199 { 1200 if (!ar->hw_params.fw.board) { 1201 ath10k_err(ar, "failed to find board file fw entry\n"); 1202 return -EINVAL; 1203 } 1204 1205 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1206 ar->hw_params.fw.dir, 1207 ar->hw_params.fw.board); 1208 if (IS_ERR(ar->normal_mode_fw.board)) 1209 return PTR_ERR(ar->normal_mode_fw.board); 1210 1211 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data; 1212 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size; 1213 1214 return 0; 1215 } 1216 1217 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar, 1218 const void *buf, size_t buf_len, 1219 const char *boardname) 1220 { 1221 const struct ath10k_fw_ie *hdr; 1222 bool name_match_found; 1223 int ret, board_ie_id; 1224 size_t board_ie_len; 1225 const void *board_ie_data; 1226 1227 name_match_found = false; 1228 1229 /* go through ATH10K_BD_IE_BOARD_ elements */ 1230 while (buf_len > sizeof(struct ath10k_fw_ie)) { 1231 hdr = buf; 1232 board_ie_id = le32_to_cpu(hdr->id); 1233 board_ie_len = le32_to_cpu(hdr->len); 1234 board_ie_data = hdr->data; 1235 1236 buf_len -= sizeof(*hdr); 1237 buf += sizeof(*hdr); 1238 1239 if (buf_len < ALIGN(board_ie_len, 4)) { 1240 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n", 1241 buf_len, ALIGN(board_ie_len, 4)); 1242 ret = -EINVAL; 1243 goto out; 1244 } 1245 1246 switch (board_ie_id) { 1247 case ATH10K_BD_IE_BOARD_NAME: 1248 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "", 1249 board_ie_data, board_ie_len); 1250 1251 if (board_ie_len != strlen(boardname)) 1252 break; 1253 1254 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1255 if (ret) 1256 break; 1257 1258 name_match_found = true; 1259 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1260 "boot found match for name '%s'", 1261 boardname); 1262 break; 1263 case ATH10K_BD_IE_BOARD_DATA: 1264 if (!name_match_found) 1265 /* no match found */ 1266 break; 1267 1268 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1269 "boot found board data for '%s'", 1270 boardname); 1271 1272 ar->normal_mode_fw.board_data = board_ie_data; 1273 ar->normal_mode_fw.board_len = board_ie_len; 1274 1275 ret = 0; 1276 goto out; 1277 default: 1278 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n", 1279 board_ie_id); 1280 break; 1281 } 1282 1283 /* jump over the padding */ 1284 board_ie_len = ALIGN(board_ie_len, 4); 1285 1286 buf_len -= board_ie_len; 1287 buf += board_ie_len; 1288 } 1289 1290 /* no match found */ 1291 ret = -ENOENT; 1292 1293 out: 1294 return ret; 1295 } 1296 1297 static int ath10k_core_search_bd(struct ath10k *ar, 1298 const char *boardname, 1299 const u8 *data, 1300 size_t len) 1301 { 1302 size_t ie_len; 1303 struct ath10k_fw_ie *hdr; 1304 int ret = -ENOENT, ie_id; 1305 1306 while (len > sizeof(struct ath10k_fw_ie)) { 1307 hdr = (struct ath10k_fw_ie *)data; 1308 ie_id = le32_to_cpu(hdr->id); 1309 ie_len = le32_to_cpu(hdr->len); 1310 1311 len -= sizeof(*hdr); 1312 data = hdr->data; 1313 1314 if (len < ALIGN(ie_len, 4)) { 1315 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1316 ie_id, ie_len, len); 1317 return -EINVAL; 1318 } 1319 1320 switch (ie_id) { 1321 case ATH10K_BD_IE_BOARD: 1322 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1323 boardname); 1324 if (ret == -ENOENT) 1325 /* no match found, continue */ 1326 break; 1327 1328 /* either found or error, so stop searching */ 1329 goto out; 1330 } 1331 1332 /* jump over the padding */ 1333 ie_len = ALIGN(ie_len, 4); 1334 1335 len -= ie_len; 1336 data += ie_len; 1337 } 1338 1339 out: 1340 /* return result of parse_bd_ie_board() or -ENOENT */ 1341 return ret; 1342 } 1343 1344 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar, 1345 const char *boardname, 1346 const char *fallback_boardname, 1347 const char *filename) 1348 { 1349 size_t len, magic_len; 1350 const u8 *data; 1351 int ret; 1352 1353 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1354 ar->hw_params.fw.dir, 1355 filename); 1356 if (IS_ERR(ar->normal_mode_fw.board)) 1357 return PTR_ERR(ar->normal_mode_fw.board); 1358 1359 data = ar->normal_mode_fw.board->data; 1360 len = ar->normal_mode_fw.board->size; 1361 1362 /* magic has extra null byte padded */ 1363 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1; 1364 if (len < magic_len) { 1365 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n", 1366 ar->hw_params.fw.dir, filename, len); 1367 ret = -EINVAL; 1368 goto err; 1369 } 1370 1371 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) { 1372 ath10k_err(ar, "found invalid board magic\n"); 1373 ret = -EINVAL; 1374 goto err; 1375 } 1376 1377 /* magic is padded to 4 bytes */ 1378 magic_len = ALIGN(magic_len, 4); 1379 if (len < magic_len) { 1380 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n", 1381 ar->hw_params.fw.dir, filename, len); 1382 ret = -EINVAL; 1383 goto err; 1384 } 1385 1386 data += magic_len; 1387 len -= magic_len; 1388 1389 /* attempt to find boardname in the IE list */ 1390 ret = ath10k_core_search_bd(ar, boardname, data, len); 1391 1392 /* if we didn't find it and have a fallback name, try that */ 1393 if (ret == -ENOENT && fallback_boardname) 1394 ret = ath10k_core_search_bd(ar, fallback_boardname, data, len); 1395 1396 if (ret == -ENOENT) { 1397 ath10k_err(ar, 1398 "failed to fetch board data for %s from %s/%s\n", 1399 boardname, ar->hw_params.fw.dir, filename); 1400 ret = -ENODATA; 1401 } 1402 1403 if (ret) 1404 goto err; 1405 1406 return 0; 1407 1408 err: 1409 ath10k_core_free_board_files(ar); 1410 return ret; 1411 } 1412 1413 static int ath10k_core_create_board_name(struct ath10k *ar, char *name, 1414 size_t name_len, bool with_variant) 1415 { 1416 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */ 1417 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 }; 1418 1419 if (with_variant && ar->id.bdf_ext[0] != '\0') 1420 scnprintf(variant, sizeof(variant), ",variant=%s", 1421 ar->id.bdf_ext); 1422 1423 if (ar->id.bmi_ids_valid) { 1424 scnprintf(name, name_len, 1425 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s", 1426 ath10k_bus_str(ar->hif.bus), 1427 ar->id.bmi_chip_id, 1428 ar->id.bmi_board_id, variant); 1429 goto out; 1430 } 1431 1432 scnprintf(name, name_len, 1433 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s", 1434 ath10k_bus_str(ar->hif.bus), 1435 ar->id.vendor, ar->id.device, 1436 ar->id.subsystem_vendor, ar->id.subsystem_device, variant); 1437 out: 1438 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name); 1439 1440 return 0; 1441 } 1442 1443 static int ath10k_core_fetch_board_file(struct ath10k *ar) 1444 { 1445 char boardname[100], fallback_boardname[100]; 1446 int ret; 1447 1448 ret = ath10k_core_create_board_name(ar, boardname, 1449 sizeof(boardname), true); 1450 if (ret) { 1451 ath10k_err(ar, "failed to create board name: %d", ret); 1452 return ret; 1453 } 1454 1455 ret = ath10k_core_create_board_name(ar, fallback_boardname, 1456 sizeof(boardname), false); 1457 if (ret) { 1458 ath10k_err(ar, "failed to create fallback board name: %d", ret); 1459 return ret; 1460 } 1461 1462 ar->bd_api = 2; 1463 ret = ath10k_core_fetch_board_data_api_n(ar, boardname, 1464 fallback_boardname, 1465 ATH10K_BOARD_API2_FILE); 1466 if (!ret) 1467 goto success; 1468 1469 ar->bd_api = 1; 1470 ret = ath10k_core_fetch_board_data_api_1(ar); 1471 if (ret) { 1472 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n", 1473 ar->hw_params.fw.dir); 1474 return ret; 1475 } 1476 1477 success: 1478 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api); 1479 return 0; 1480 } 1481 1482 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, 1483 struct ath10k_fw_file *fw_file) 1484 { 1485 size_t magic_len, len, ie_len; 1486 int ie_id, i, index, bit, ret; 1487 struct ath10k_fw_ie *hdr; 1488 const u8 *data; 1489 __le32 *timestamp, *version; 1490 1491 /* first fetch the firmware file (firmware-*.bin) */ 1492 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1493 name); 1494 if (IS_ERR(fw_file->firmware)) 1495 return PTR_ERR(fw_file->firmware); 1496 1497 data = fw_file->firmware->data; 1498 len = fw_file->firmware->size; 1499 1500 /* magic also includes the null byte, check that as well */ 1501 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; 1502 1503 if (len < magic_len) { 1504 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", 1505 ar->hw_params.fw.dir, name, len); 1506 ret = -EINVAL; 1507 goto err; 1508 } 1509 1510 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { 1511 ath10k_err(ar, "invalid firmware magic\n"); 1512 ret = -EINVAL; 1513 goto err; 1514 } 1515 1516 /* jump over the padding */ 1517 magic_len = ALIGN(magic_len, 4); 1518 1519 len -= magic_len; 1520 data += magic_len; 1521 1522 /* loop elements */ 1523 while (len > sizeof(struct ath10k_fw_ie)) { 1524 hdr = (struct ath10k_fw_ie *)data; 1525 1526 ie_id = le32_to_cpu(hdr->id); 1527 ie_len = le32_to_cpu(hdr->len); 1528 1529 len -= sizeof(*hdr); 1530 data += sizeof(*hdr); 1531 1532 if (len < ie_len) { 1533 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", 1534 ie_id, len, ie_len); 1535 ret = -EINVAL; 1536 goto err; 1537 } 1538 1539 switch (ie_id) { 1540 case ATH10K_FW_IE_FW_VERSION: 1541 if (ie_len > sizeof(fw_file->fw_version) - 1) 1542 break; 1543 1544 memcpy(fw_file->fw_version, data, ie_len); 1545 fw_file->fw_version[ie_len] = '\0'; 1546 1547 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1548 "found fw version %s\n", 1549 fw_file->fw_version); 1550 break; 1551 case ATH10K_FW_IE_TIMESTAMP: 1552 if (ie_len != sizeof(u32)) 1553 break; 1554 1555 timestamp = (__le32 *)data; 1556 1557 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", 1558 le32_to_cpup(timestamp)); 1559 break; 1560 case ATH10K_FW_IE_FEATURES: 1561 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1562 "found firmware features ie (%zd B)\n", 1563 ie_len); 1564 1565 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 1566 index = i / 8; 1567 bit = i % 8; 1568 1569 if (index == ie_len) 1570 break; 1571 1572 if (data[index] & (1 << bit)) { 1573 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1574 "Enabling feature bit: %i\n", 1575 i); 1576 __set_bit(i, fw_file->fw_features); 1577 } 1578 } 1579 1580 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", 1581 fw_file->fw_features, 1582 sizeof(fw_file->fw_features)); 1583 break; 1584 case ATH10K_FW_IE_FW_IMAGE: 1585 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1586 "found fw image ie (%zd B)\n", 1587 ie_len); 1588 1589 fw_file->firmware_data = data; 1590 fw_file->firmware_len = ie_len; 1591 1592 break; 1593 case ATH10K_FW_IE_OTP_IMAGE: 1594 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1595 "found otp image ie (%zd B)\n", 1596 ie_len); 1597 1598 fw_file->otp_data = data; 1599 fw_file->otp_len = ie_len; 1600 1601 break; 1602 case ATH10K_FW_IE_WMI_OP_VERSION: 1603 if (ie_len != sizeof(u32)) 1604 break; 1605 1606 version = (__le32 *)data; 1607 1608 fw_file->wmi_op_version = le32_to_cpup(version); 1609 1610 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", 1611 fw_file->wmi_op_version); 1612 break; 1613 case ATH10K_FW_IE_HTT_OP_VERSION: 1614 if (ie_len != sizeof(u32)) 1615 break; 1616 1617 version = (__le32 *)data; 1618 1619 fw_file->htt_op_version = le32_to_cpup(version); 1620 1621 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", 1622 fw_file->htt_op_version); 1623 break; 1624 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: 1625 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1626 "found fw code swap image ie (%zd B)\n", 1627 ie_len); 1628 fw_file->codeswap_data = data; 1629 fw_file->codeswap_len = ie_len; 1630 break; 1631 default: 1632 ath10k_warn(ar, "Unknown FW IE: %u\n", 1633 le32_to_cpu(hdr->id)); 1634 break; 1635 } 1636 1637 /* jump over the padding */ 1638 ie_len = ALIGN(ie_len, 4); 1639 1640 len -= ie_len; 1641 data += ie_len; 1642 } 1643 1644 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) && 1645 (!fw_file->firmware_data || !fw_file->firmware_len)) { 1646 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", 1647 ar->hw_params.fw.dir, name); 1648 ret = -ENOMEDIUM; 1649 goto err; 1650 } 1651 1652 return 0; 1653 1654 err: 1655 ath10k_core_free_firmware_files(ar); 1656 return ret; 1657 } 1658 1659 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name, 1660 size_t fw_name_len, int fw_api) 1661 { 1662 switch (ar->hif.bus) { 1663 case ATH10K_BUS_SDIO: 1664 case ATH10K_BUS_USB: 1665 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin", 1666 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus), 1667 fw_api); 1668 break; 1669 case ATH10K_BUS_PCI: 1670 case ATH10K_BUS_AHB: 1671 case ATH10K_BUS_SNOC: 1672 scnprintf(fw_name, fw_name_len, "%s-%d.bin", 1673 ATH10K_FW_FILE_BASE, fw_api); 1674 break; 1675 } 1676 } 1677 1678 static int ath10k_core_fetch_firmware_files(struct ath10k *ar) 1679 { 1680 int ret, i; 1681 char fw_name[100]; 1682 1683 /* calibration file is optional, don't check for any errors */ 1684 ath10k_fetch_cal_file(ar); 1685 1686 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) { 1687 ar->fw_api = i; 1688 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", 1689 ar->fw_api); 1690 1691 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api); 1692 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name, 1693 &ar->normal_mode_fw.fw_file); 1694 if (!ret) 1695 goto success; 1696 } 1697 1698 /* we end up here if we couldn't fetch any firmware */ 1699 1700 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d", 1701 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir, 1702 ret); 1703 1704 return ret; 1705 1706 success: 1707 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); 1708 1709 return 0; 1710 } 1711 1712 static int ath10k_core_pre_cal_download(struct ath10k *ar) 1713 { 1714 int ret; 1715 1716 ret = ath10k_download_cal_file(ar, ar->pre_cal_file); 1717 if (ret == 0) { 1718 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE; 1719 goto success; 1720 } 1721 1722 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1723 "boot did not find a pre calibration file, try DT next: %d\n", 1724 ret); 1725 1726 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data"); 1727 if (ret) { 1728 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1729 "unable to load pre cal data from DT: %d\n", ret); 1730 return ret; 1731 } 1732 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT; 1733 1734 success: 1735 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 1736 ath10k_cal_mode_str(ar->cal_mode)); 1737 1738 return 0; 1739 } 1740 1741 static int ath10k_core_pre_cal_config(struct ath10k *ar) 1742 { 1743 int ret; 1744 1745 ret = ath10k_core_pre_cal_download(ar); 1746 if (ret) { 1747 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1748 "failed to load pre cal data: %d\n", ret); 1749 return ret; 1750 } 1751 1752 ret = ath10k_core_get_board_id_from_otp(ar); 1753 if (ret) { 1754 ath10k_err(ar, "failed to get board id: %d\n", ret); 1755 return ret; 1756 } 1757 1758 ret = ath10k_download_and_run_otp(ar); 1759 if (ret) { 1760 ath10k_err(ar, "failed to run otp: %d\n", ret); 1761 return ret; 1762 } 1763 1764 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1765 "pre cal configuration done successfully\n"); 1766 1767 return 0; 1768 } 1769 1770 static int ath10k_download_cal_data(struct ath10k *ar) 1771 { 1772 int ret; 1773 1774 ret = ath10k_core_pre_cal_config(ar); 1775 if (ret == 0) 1776 return 0; 1777 1778 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1779 "pre cal download procedure failed, try cal file: %d\n", 1780 ret); 1781 1782 ret = ath10k_download_cal_file(ar, ar->cal_file); 1783 if (ret == 0) { 1784 ar->cal_mode = ATH10K_CAL_MODE_FILE; 1785 goto done; 1786 } 1787 1788 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1789 "boot did not find a calibration file, try DT next: %d\n", 1790 ret); 1791 1792 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data"); 1793 if (ret == 0) { 1794 ar->cal_mode = ATH10K_CAL_MODE_DT; 1795 goto done; 1796 } 1797 1798 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1799 "boot did not find DT entry, try target EEPROM next: %d\n", 1800 ret); 1801 1802 ret = ath10k_download_cal_eeprom(ar); 1803 if (ret == 0) { 1804 ar->cal_mode = ATH10K_CAL_MODE_EEPROM; 1805 goto done; 1806 } 1807 1808 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1809 "boot did not find target EEPROM entry, try OTP next: %d\n", 1810 ret); 1811 1812 ret = ath10k_download_and_run_otp(ar); 1813 if (ret) { 1814 ath10k_err(ar, "failed to run otp: %d\n", ret); 1815 return ret; 1816 } 1817 1818 ar->cal_mode = ATH10K_CAL_MODE_OTP; 1819 1820 done: 1821 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 1822 ath10k_cal_mode_str(ar->cal_mode)); 1823 return 0; 1824 } 1825 1826 static int ath10k_init_uart(struct ath10k *ar) 1827 { 1828 int ret; 1829 1830 /* 1831 * Explicitly setting UART prints to zero as target turns it on 1832 * based on scratch registers. 1833 */ 1834 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); 1835 if (ret) { 1836 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); 1837 return ret; 1838 } 1839 1840 if (!uart_print) 1841 return 0; 1842 1843 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); 1844 if (ret) { 1845 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 1846 return ret; 1847 } 1848 1849 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); 1850 if (ret) { 1851 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 1852 return ret; 1853 } 1854 1855 /* Set the UART baud rate to 19200. */ 1856 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); 1857 if (ret) { 1858 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); 1859 return ret; 1860 } 1861 1862 ath10k_info(ar, "UART prints enabled\n"); 1863 return 0; 1864 } 1865 1866 static int ath10k_init_hw_params(struct ath10k *ar) 1867 { 1868 const struct ath10k_hw_params *uninitialized_var(hw_params); 1869 int i; 1870 1871 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { 1872 hw_params = &ath10k_hw_params_list[i]; 1873 1874 if (hw_params->id == ar->target_version && 1875 hw_params->dev_id == ar->dev_id) 1876 break; 1877 } 1878 1879 if (i == ARRAY_SIZE(ath10k_hw_params_list)) { 1880 ath10k_err(ar, "Unsupported hardware version: 0x%x\n", 1881 ar->target_version); 1882 return -EINVAL; 1883 } 1884 1885 ar->hw_params = *hw_params; 1886 1887 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", 1888 ar->hw_params.name, ar->target_version); 1889 1890 return 0; 1891 } 1892 1893 static void ath10k_core_restart(struct work_struct *work) 1894 { 1895 struct ath10k *ar = container_of(work, struct ath10k, restart_work); 1896 int ret; 1897 1898 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 1899 1900 /* Place a barrier to make sure the compiler doesn't reorder 1901 * CRASH_FLUSH and calling other functions. 1902 */ 1903 barrier(); 1904 1905 ieee80211_stop_queues(ar->hw); 1906 ath10k_drain_tx(ar); 1907 complete(&ar->scan.started); 1908 complete(&ar->scan.completed); 1909 complete(&ar->scan.on_channel); 1910 complete(&ar->offchan_tx_completed); 1911 complete(&ar->install_key_done); 1912 complete(&ar->vdev_setup_done); 1913 complete(&ar->thermal.wmi_sync); 1914 complete(&ar->bss_survey_done); 1915 wake_up(&ar->htt.empty_tx_wq); 1916 wake_up(&ar->wmi.tx_credits_wq); 1917 wake_up(&ar->peer_mapping_wq); 1918 1919 /* TODO: We can have one instance of cancelling coverage_class_work by 1920 * moving it to ath10k_halt(), so that both stop() and restart() would 1921 * call that but it takes conf_mutex() and if we call cancel_work_sync() 1922 * with conf_mutex it will deadlock. 1923 */ 1924 cancel_work_sync(&ar->set_coverage_class_work); 1925 1926 mutex_lock(&ar->conf_mutex); 1927 1928 switch (ar->state) { 1929 case ATH10K_STATE_ON: 1930 ar->state = ATH10K_STATE_RESTARTING; 1931 ath10k_halt(ar); 1932 ath10k_scan_finish(ar); 1933 ieee80211_restart_hw(ar->hw); 1934 break; 1935 case ATH10K_STATE_OFF: 1936 /* this can happen if driver is being unloaded 1937 * or if the crash happens during FW probing 1938 */ 1939 ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); 1940 break; 1941 case ATH10K_STATE_RESTARTING: 1942 /* hw restart might be requested from multiple places */ 1943 break; 1944 case ATH10K_STATE_RESTARTED: 1945 ar->state = ATH10K_STATE_WEDGED; 1946 /* fall through */ 1947 case ATH10K_STATE_WEDGED: 1948 ath10k_warn(ar, "device is wedged, will not restart\n"); 1949 break; 1950 case ATH10K_STATE_UTF: 1951 ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); 1952 break; 1953 } 1954 1955 mutex_unlock(&ar->conf_mutex); 1956 1957 ret = ath10k_coredump_submit(ar); 1958 if (ret) 1959 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d", 1960 ret); 1961 } 1962 1963 static void ath10k_core_set_coverage_class_work(struct work_struct *work) 1964 { 1965 struct ath10k *ar = container_of(work, struct ath10k, 1966 set_coverage_class_work); 1967 1968 if (ar->hw_params.hw_ops->set_coverage_class) 1969 ar->hw_params.hw_ops->set_coverage_class(ar, -1); 1970 } 1971 1972 static int ath10k_core_init_firmware_features(struct ath10k *ar) 1973 { 1974 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 1975 1976 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) && 1977 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 1978 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); 1979 return -EINVAL; 1980 } 1981 1982 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { 1983 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", 1984 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version); 1985 return -EINVAL; 1986 } 1987 1988 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 1989 switch (ath10k_cryptmode_param) { 1990 case ATH10K_CRYPT_MODE_HW: 1991 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 1992 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 1993 break; 1994 case ATH10K_CRYPT_MODE_SW: 1995 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 1996 fw_file->fw_features)) { 1997 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); 1998 return -EINVAL; 1999 } 2000 2001 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2002 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2003 break; 2004 default: 2005 ath10k_info(ar, "invalid cryptmode: %d\n", 2006 ath10k_cryptmode_param); 2007 return -EINVAL; 2008 } 2009 2010 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT; 2011 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT; 2012 2013 if (rawmode) { 2014 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2015 fw_file->fw_features)) { 2016 ath10k_err(ar, "rawmode = 1 requires support from firmware"); 2017 return -EINVAL; 2018 } 2019 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2020 } 2021 2022 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 2023 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW; 2024 2025 /* Workaround: 2026 * 2027 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode 2028 * and causes enormous performance issues (malformed frames, 2029 * etc). 2030 * 2031 * Disabling A-MSDU makes RAW mode stable with heavy traffic 2032 * albeit a bit slower compared to regular operation. 2033 */ 2034 ar->htt.max_num_amsdu = 1; 2035 } 2036 2037 /* Backwards compatibility for firmwares without 2038 * ATH10K_FW_IE_WMI_OP_VERSION. 2039 */ 2040 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { 2041 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2042 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, 2043 fw_file->fw_features)) 2044 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2; 2045 else 2046 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; 2047 } else { 2048 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; 2049 } 2050 } 2051 2052 switch (fw_file->wmi_op_version) { 2053 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2054 ar->max_num_peers = TARGET_NUM_PEERS; 2055 ar->max_num_stations = TARGET_NUM_STATIONS; 2056 ar->max_num_vdevs = TARGET_NUM_VDEVS; 2057 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; 2058 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | 2059 WMI_STAT_PEER; 2060 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2061 break; 2062 case ATH10K_FW_WMI_OP_VERSION_10_1: 2063 case ATH10K_FW_WMI_OP_VERSION_10_2: 2064 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2065 if (ath10k_peer_stats_enabled(ar)) { 2066 ar->max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS; 2067 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS; 2068 } else { 2069 ar->max_num_peers = TARGET_10X_NUM_PEERS; 2070 ar->max_num_stations = TARGET_10X_NUM_STATIONS; 2071 } 2072 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; 2073 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; 2074 ar->fw_stats_req_mask = WMI_STAT_PEER; 2075 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2076 break; 2077 case ATH10K_FW_WMI_OP_VERSION_TLV: 2078 ar->max_num_peers = TARGET_TLV_NUM_PEERS; 2079 ar->max_num_stations = TARGET_TLV_NUM_STATIONS; 2080 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; 2081 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; 2082 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; 2083 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; 2084 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | 2085 WMI_STAT_PEER; 2086 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2087 break; 2088 case ATH10K_FW_WMI_OP_VERSION_10_4: 2089 ar->max_num_peers = TARGET_10_4_NUM_PEERS; 2090 ar->max_num_stations = TARGET_10_4_NUM_STATIONS; 2091 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; 2092 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; 2093 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; 2094 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER | 2095 WMI_10_4_STAT_PEER_EXTD | 2096 WMI_10_4_STAT_VDEV_EXTD; 2097 ar->max_spatial_stream = ar->hw_params.max_spatial_stream; 2098 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS; 2099 2100 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 2101 fw_file->fw_features)) 2102 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC; 2103 else 2104 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; 2105 break; 2106 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2107 case ATH10K_FW_WMI_OP_VERSION_MAX: 2108 WARN_ON(1); 2109 return -EINVAL; 2110 } 2111 2112 /* Backwards compatibility for firmwares without 2113 * ATH10K_FW_IE_HTT_OP_VERSION. 2114 */ 2115 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { 2116 switch (fw_file->wmi_op_version) { 2117 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2118 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; 2119 break; 2120 case ATH10K_FW_WMI_OP_VERSION_10_1: 2121 case ATH10K_FW_WMI_OP_VERSION_10_2: 2122 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2123 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; 2124 break; 2125 case ATH10K_FW_WMI_OP_VERSION_TLV: 2126 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; 2127 break; 2128 case ATH10K_FW_WMI_OP_VERSION_10_4: 2129 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2130 case ATH10K_FW_WMI_OP_VERSION_MAX: 2131 ath10k_err(ar, "htt op version not found from fw meta data"); 2132 return -EINVAL; 2133 } 2134 } 2135 2136 return 0; 2137 } 2138 2139 static int ath10k_core_reset_rx_filter(struct ath10k *ar) 2140 { 2141 int ret; 2142 int vdev_id; 2143 int vdev_type; 2144 int vdev_subtype; 2145 const u8 *vdev_addr; 2146 2147 vdev_id = 0; 2148 vdev_type = WMI_VDEV_TYPE_STA; 2149 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); 2150 vdev_addr = ar->mac_addr; 2151 2152 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype, 2153 vdev_addr); 2154 if (ret) { 2155 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret); 2156 return ret; 2157 } 2158 2159 ret = ath10k_wmi_vdev_delete(ar, vdev_id); 2160 if (ret) { 2161 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret); 2162 return ret; 2163 } 2164 2165 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be 2166 * serialized properly implicitly. 2167 * 2168 * Moreover (most) WMI commands have no explicit acknowledges. It is 2169 * possible to infer it implicitly by poking firmware with echo 2170 * command - getting a reply means all preceding comments have been 2171 * (mostly) processed. 2172 * 2173 * In case of vdev create/delete this is sufficient. 2174 * 2175 * Without this it's possible to end up with a race when HTT Rx ring is 2176 * started before vdev create/delete hack is complete allowing a short 2177 * window of opportunity to receive (and Tx ACK) a bunch of frames. 2178 */ 2179 ret = ath10k_wmi_barrier(ar); 2180 if (ret) { 2181 ath10k_err(ar, "failed to ping firmware: %d\n", ret); 2182 return ret; 2183 } 2184 2185 return 0; 2186 } 2187 2188 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, 2189 const struct ath10k_fw_components *fw) 2190 { 2191 int status; 2192 u32 val; 2193 2194 lockdep_assert_held(&ar->conf_mutex); 2195 2196 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2197 2198 ar->running_fw = fw; 2199 2200 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2201 ar->running_fw->fw_file.fw_features)) { 2202 ath10k_bmi_start(ar); 2203 2204 if (ath10k_init_configure_target(ar)) { 2205 status = -EINVAL; 2206 goto err; 2207 } 2208 2209 status = ath10k_download_cal_data(ar); 2210 if (status) 2211 goto err; 2212 2213 /* Some of of qca988x solutions are having global reset issue 2214 * during target initialization. Bypassing PLL setting before 2215 * downloading firmware and letting the SoC run on REF_CLK is 2216 * fixing the problem. Corresponding firmware change is also 2217 * needed to set the clock source once the target is 2218 * initialized. 2219 */ 2220 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, 2221 ar->running_fw->fw_file.fw_features)) { 2222 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); 2223 if (status) { 2224 ath10k_err(ar, "could not write to skip_clock_init: %d\n", 2225 status); 2226 goto err; 2227 } 2228 } 2229 2230 status = ath10k_download_fw(ar); 2231 if (status) 2232 goto err; 2233 2234 status = ath10k_init_uart(ar); 2235 if (status) 2236 goto err; 2237 2238 if (ar->hif.bus == ATH10K_BUS_SDIO) 2239 ath10k_init_sdio(ar); 2240 } 2241 2242 ar->htc.htc_ops.target_send_suspend_complete = 2243 ath10k_send_suspend_complete; 2244 2245 status = ath10k_htc_init(ar); 2246 if (status) { 2247 ath10k_err(ar, "could not init HTC (%d)\n", status); 2248 goto err; 2249 } 2250 2251 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2252 ar->running_fw->fw_file.fw_features)) { 2253 status = ath10k_bmi_done(ar); 2254 if (status) 2255 goto err; 2256 } 2257 2258 status = ath10k_wmi_attach(ar); 2259 if (status) { 2260 ath10k_err(ar, "WMI attach failed: %d\n", status); 2261 goto err; 2262 } 2263 2264 status = ath10k_htt_init(ar); 2265 if (status) { 2266 ath10k_err(ar, "failed to init htt: %d\n", status); 2267 goto err_wmi_detach; 2268 } 2269 2270 status = ath10k_htt_tx_start(&ar->htt); 2271 if (status) { 2272 ath10k_err(ar, "failed to alloc htt tx: %d\n", status); 2273 goto err_wmi_detach; 2274 } 2275 2276 /* If firmware indicates Full Rx Reorder support it must be used in a 2277 * slightly different manner. Let HTT code know. 2278 */ 2279 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, 2280 ar->wmi.svc_map)); 2281 2282 status = ath10k_htt_rx_alloc(&ar->htt); 2283 if (status) { 2284 ath10k_err(ar, "failed to alloc htt rx: %d\n", status); 2285 goto err_htt_tx_detach; 2286 } 2287 2288 status = ath10k_hif_start(ar); 2289 if (status) { 2290 ath10k_err(ar, "could not start HIF: %d\n", status); 2291 goto err_htt_rx_detach; 2292 } 2293 2294 status = ath10k_htc_wait_target(&ar->htc); 2295 if (status) { 2296 ath10k_err(ar, "failed to connect to HTC: %d\n", status); 2297 goto err_hif_stop; 2298 } 2299 2300 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 2301 status = ath10k_htt_connect(&ar->htt); 2302 if (status) { 2303 ath10k_err(ar, "failed to connect htt (%d)\n", status); 2304 goto err_hif_stop; 2305 } 2306 } 2307 2308 status = ath10k_wmi_connect(ar); 2309 if (status) { 2310 ath10k_err(ar, "could not connect wmi: %d\n", status); 2311 goto err_hif_stop; 2312 } 2313 2314 status = ath10k_htc_start(&ar->htc); 2315 if (status) { 2316 ath10k_err(ar, "failed to start htc: %d\n", status); 2317 goto err_hif_stop; 2318 } 2319 2320 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 2321 status = ath10k_wmi_wait_for_service_ready(ar); 2322 if (status) { 2323 ath10k_warn(ar, "wmi service ready event not received"); 2324 goto err_hif_stop; 2325 } 2326 } 2327 2328 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", 2329 ar->hw->wiphy->fw_version); 2330 2331 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) && 2332 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 2333 val = 0; 2334 if (ath10k_peer_stats_enabled(ar)) 2335 val = WMI_10_4_PEER_STATS; 2336 2337 /* Enable vdev stats by default */ 2338 val |= WMI_10_4_VDEV_STATS; 2339 2340 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) 2341 val |= WMI_10_4_BSS_CHANNEL_INFO_64; 2342 2343 /* 10.4 firmware supports BT-Coex without reloading firmware 2344 * via pdev param. To support Bluetooth coexistence pdev param, 2345 * WMI_COEX_GPIO_SUPPORT of extended resource config should be 2346 * enabled always. 2347 */ 2348 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && 2349 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, 2350 ar->running_fw->fw_file.fw_features)) 2351 val |= WMI_10_4_COEX_GPIO_SUPPORT; 2352 2353 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY, 2354 ar->wmi.svc_map)) 2355 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY; 2356 2357 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA, 2358 ar->wmi.svc_map)) 2359 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA; 2360 2361 status = ath10k_mac_ext_resource_config(ar, val); 2362 if (status) { 2363 ath10k_err(ar, 2364 "failed to send ext resource cfg command : %d\n", 2365 status); 2366 goto err_hif_stop; 2367 } 2368 } 2369 2370 status = ath10k_wmi_cmd_init(ar); 2371 if (status) { 2372 ath10k_err(ar, "could not send WMI init command (%d)\n", 2373 status); 2374 goto err_hif_stop; 2375 } 2376 2377 status = ath10k_wmi_wait_for_unified_ready(ar); 2378 if (status) { 2379 ath10k_err(ar, "wmi unified ready event not received\n"); 2380 goto err_hif_stop; 2381 } 2382 2383 /* Some firmware revisions do not properly set up hardware rx filter 2384 * registers. 2385 * 2386 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK 2387 * is filled with 0s instead of 1s allowing HW to respond with ACKs to 2388 * any frames that matches MAC_PCU_RX_FILTER which is also 2389 * misconfigured to accept anything. 2390 * 2391 * The ADDR1 is programmed using internal firmware structure field and 2392 * can't be (easily/sanely) reached from the driver explicitly. It is 2393 * possible to implicitly make it correct by creating a dummy vdev and 2394 * then deleting it. 2395 */ 2396 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 2397 status = ath10k_core_reset_rx_filter(ar); 2398 if (status) { 2399 ath10k_err(ar, 2400 "failed to reset rx filter: %d\n", status); 2401 goto err_hif_stop; 2402 } 2403 } 2404 2405 status = ath10k_htt_rx_ring_refill(ar); 2406 if (status) { 2407 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); 2408 goto err_hif_stop; 2409 } 2410 2411 if (ar->max_num_vdevs >= 64) 2412 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL; 2413 else 2414 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; 2415 2416 INIT_LIST_HEAD(&ar->arvifs); 2417 2418 /* we don't care about HTT in UTF mode */ 2419 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 2420 status = ath10k_htt_setup(&ar->htt); 2421 if (status) { 2422 ath10k_err(ar, "failed to setup htt: %d\n", status); 2423 goto err_hif_stop; 2424 } 2425 } 2426 2427 status = ath10k_debug_start(ar); 2428 if (status) 2429 goto err_hif_stop; 2430 2431 return 0; 2432 2433 err_hif_stop: 2434 ath10k_hif_stop(ar); 2435 err_htt_rx_detach: 2436 ath10k_htt_rx_free(&ar->htt); 2437 err_htt_tx_detach: 2438 ath10k_htt_tx_free(&ar->htt); 2439 err_wmi_detach: 2440 ath10k_wmi_detach(ar); 2441 err: 2442 return status; 2443 } 2444 EXPORT_SYMBOL(ath10k_core_start); 2445 2446 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) 2447 { 2448 int ret; 2449 unsigned long time_left; 2450 2451 reinit_completion(&ar->target_suspend); 2452 2453 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); 2454 if (ret) { 2455 ath10k_warn(ar, "could not suspend target (%d)\n", ret); 2456 return ret; 2457 } 2458 2459 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); 2460 2461 if (!time_left) { 2462 ath10k_warn(ar, "suspend timed out - target pause event never came\n"); 2463 return -ETIMEDOUT; 2464 } 2465 2466 return 0; 2467 } 2468 2469 void ath10k_core_stop(struct ath10k *ar) 2470 { 2471 lockdep_assert_held(&ar->conf_mutex); 2472 ath10k_debug_stop(ar); 2473 2474 /* try to suspend target */ 2475 if (ar->state != ATH10K_STATE_RESTARTING && 2476 ar->state != ATH10K_STATE_UTF) 2477 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); 2478 2479 ath10k_hif_stop(ar); 2480 ath10k_htt_tx_stop(&ar->htt); 2481 ath10k_htt_rx_free(&ar->htt); 2482 ath10k_wmi_detach(ar); 2483 } 2484 EXPORT_SYMBOL(ath10k_core_stop); 2485 2486 /* mac80211 manages fw/hw initialization through start/stop hooks. However in 2487 * order to know what hw capabilities should be advertised to mac80211 it is 2488 * necessary to load the firmware (and tear it down immediately since start 2489 * hook will try to init it again) before registering 2490 */ 2491 static int ath10k_core_probe_fw(struct ath10k *ar) 2492 { 2493 struct bmi_target_info target_info; 2494 int ret = 0; 2495 2496 ret = ath10k_hif_power_up(ar); 2497 if (ret) { 2498 ath10k_err(ar, "could not power on hif bus (%d)\n", ret); 2499 return ret; 2500 } 2501 2502 switch (ar->hif.bus) { 2503 case ATH10K_BUS_SDIO: 2504 memset(&target_info, 0, sizeof(target_info)); 2505 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info); 2506 if (ret) { 2507 ath10k_err(ar, "could not get target info (%d)\n", ret); 2508 goto err_power_down; 2509 } 2510 ar->target_version = target_info.version; 2511 ar->hw->wiphy->hw_version = target_info.version; 2512 break; 2513 case ATH10K_BUS_PCI: 2514 case ATH10K_BUS_AHB: 2515 case ATH10K_BUS_USB: 2516 memset(&target_info, 0, sizeof(target_info)); 2517 ret = ath10k_bmi_get_target_info(ar, &target_info); 2518 if (ret) { 2519 ath10k_err(ar, "could not get target info (%d)\n", ret); 2520 goto err_power_down; 2521 } 2522 ar->target_version = target_info.version; 2523 ar->hw->wiphy->hw_version = target_info.version; 2524 break; 2525 case ATH10K_BUS_SNOC: 2526 memset(&target_info, 0, sizeof(target_info)); 2527 ret = ath10k_hif_get_target_info(ar, &target_info); 2528 if (ret) { 2529 ath10k_err(ar, "could not get target info (%d)\n", ret); 2530 goto err_power_down; 2531 } 2532 ar->target_version = target_info.version; 2533 ar->hw->wiphy->hw_version = target_info.version; 2534 break; 2535 default: 2536 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus); 2537 } 2538 2539 ret = ath10k_init_hw_params(ar); 2540 if (ret) { 2541 ath10k_err(ar, "could not get hw params (%d)\n", ret); 2542 goto err_power_down; 2543 } 2544 2545 ret = ath10k_core_fetch_firmware_files(ar); 2546 if (ret) { 2547 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); 2548 goto err_power_down; 2549 } 2550 2551 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) != 2552 sizeof(ar->normal_mode_fw.fw_file.fw_version)); 2553 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version, 2554 sizeof(ar->hw->wiphy->fw_version)); 2555 2556 ath10k_debug_print_hwfw_info(ar); 2557 2558 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2559 ar->normal_mode_fw.fw_file.fw_features)) { 2560 ret = ath10k_core_pre_cal_download(ar); 2561 if (ret) { 2562 /* pre calibration data download is not necessary 2563 * for all the chipsets. Ignore failures and continue. 2564 */ 2565 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2566 "could not load pre cal data: %d\n", ret); 2567 } 2568 2569 ret = ath10k_core_get_board_id_from_otp(ar); 2570 if (ret && ret != -EOPNOTSUPP) { 2571 ath10k_err(ar, "failed to get board id from otp: %d\n", 2572 ret); 2573 goto err_free_firmware_files; 2574 } 2575 2576 ret = ath10k_core_check_smbios(ar); 2577 if (ret) 2578 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n"); 2579 2580 ret = ath10k_core_check_dt(ar); 2581 if (ret) 2582 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n"); 2583 2584 ret = ath10k_core_fetch_board_file(ar); 2585 if (ret) { 2586 ath10k_err(ar, "failed to fetch board file: %d\n", ret); 2587 goto err_free_firmware_files; 2588 } 2589 2590 ath10k_debug_print_board_info(ar); 2591 } 2592 2593 ret = ath10k_core_init_firmware_features(ar); 2594 if (ret) { 2595 ath10k_err(ar, "fatal problem with firmware features: %d\n", 2596 ret); 2597 goto err_free_firmware_files; 2598 } 2599 2600 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2601 ar->normal_mode_fw.fw_file.fw_features)) { 2602 ret = ath10k_swap_code_seg_init(ar, 2603 &ar->normal_mode_fw.fw_file); 2604 if (ret) { 2605 ath10k_err(ar, "failed to initialize code swap segment: %d\n", 2606 ret); 2607 goto err_free_firmware_files; 2608 } 2609 } 2610 2611 mutex_lock(&ar->conf_mutex); 2612 2613 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, 2614 &ar->normal_mode_fw); 2615 if (ret) { 2616 ath10k_err(ar, "could not init core (%d)\n", ret); 2617 goto err_unlock; 2618 } 2619 2620 ath10k_debug_print_boot_info(ar); 2621 ath10k_core_stop(ar); 2622 2623 mutex_unlock(&ar->conf_mutex); 2624 2625 ath10k_hif_power_down(ar); 2626 return 0; 2627 2628 err_unlock: 2629 mutex_unlock(&ar->conf_mutex); 2630 2631 err_free_firmware_files: 2632 ath10k_core_free_firmware_files(ar); 2633 2634 err_power_down: 2635 ath10k_hif_power_down(ar); 2636 2637 return ret; 2638 } 2639 2640 static void ath10k_core_register_work(struct work_struct *work) 2641 { 2642 struct ath10k *ar = container_of(work, struct ath10k, register_work); 2643 int status; 2644 2645 /* peer stats are enabled by default */ 2646 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); 2647 2648 status = ath10k_core_probe_fw(ar); 2649 if (status) { 2650 ath10k_err(ar, "could not probe fw (%d)\n", status); 2651 goto err; 2652 } 2653 2654 status = ath10k_mac_register(ar); 2655 if (status) { 2656 ath10k_err(ar, "could not register to mac80211 (%d)\n", status); 2657 goto err_release_fw; 2658 } 2659 2660 status = ath10k_coredump_register(ar); 2661 if (status) { 2662 ath10k_err(ar, "unable to register coredump\n"); 2663 goto err_unregister_mac; 2664 } 2665 2666 status = ath10k_debug_register(ar); 2667 if (status) { 2668 ath10k_err(ar, "unable to initialize debugfs\n"); 2669 goto err_unregister_coredump; 2670 } 2671 2672 status = ath10k_spectral_create(ar); 2673 if (status) { 2674 ath10k_err(ar, "failed to initialize spectral\n"); 2675 goto err_debug_destroy; 2676 } 2677 2678 status = ath10k_thermal_register(ar); 2679 if (status) { 2680 ath10k_err(ar, "could not register thermal device: %d\n", 2681 status); 2682 goto err_spectral_destroy; 2683 } 2684 2685 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); 2686 return; 2687 2688 err_spectral_destroy: 2689 ath10k_spectral_destroy(ar); 2690 err_debug_destroy: 2691 ath10k_debug_destroy(ar); 2692 err_unregister_coredump: 2693 ath10k_coredump_unregister(ar); 2694 err_unregister_mac: 2695 ath10k_mac_unregister(ar); 2696 err_release_fw: 2697 ath10k_core_free_firmware_files(ar); 2698 err: 2699 /* TODO: It's probably a good idea to release device from the driver 2700 * but calling device_release_driver() here will cause a deadlock. 2701 */ 2702 return; 2703 } 2704 2705 int ath10k_core_register(struct ath10k *ar, u32 chip_id) 2706 { 2707 ar->chip_id = chip_id; 2708 queue_work(ar->workqueue, &ar->register_work); 2709 2710 return 0; 2711 } 2712 EXPORT_SYMBOL(ath10k_core_register); 2713 2714 void ath10k_core_unregister(struct ath10k *ar) 2715 { 2716 cancel_work_sync(&ar->register_work); 2717 2718 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) 2719 return; 2720 2721 ath10k_thermal_unregister(ar); 2722 /* Stop spectral before unregistering from mac80211 to remove the 2723 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree 2724 * would be already be free'd recursively, leading to a double free. 2725 */ 2726 ath10k_spectral_destroy(ar); 2727 2728 /* We must unregister from mac80211 before we stop HTC and HIF. 2729 * Otherwise we will fail to submit commands to FW and mac80211 will be 2730 * unhappy about callback failures. 2731 */ 2732 ath10k_mac_unregister(ar); 2733 2734 ath10k_testmode_destroy(ar); 2735 2736 ath10k_core_free_firmware_files(ar); 2737 ath10k_core_free_board_files(ar); 2738 2739 ath10k_debug_unregister(ar); 2740 } 2741 EXPORT_SYMBOL(ath10k_core_unregister); 2742 2743 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, 2744 enum ath10k_bus bus, 2745 enum ath10k_hw_rev hw_rev, 2746 const struct ath10k_hif_ops *hif_ops) 2747 { 2748 struct ath10k *ar; 2749 int ret; 2750 2751 ar = ath10k_mac_create(priv_size); 2752 if (!ar) 2753 return NULL; 2754 2755 ar->ath_common.priv = ar; 2756 ar->ath_common.hw = ar->hw; 2757 ar->dev = dev; 2758 ar->hw_rev = hw_rev; 2759 ar->hif.ops = hif_ops; 2760 ar->hif.bus = bus; 2761 2762 switch (hw_rev) { 2763 case ATH10K_HW_QCA988X: 2764 case ATH10K_HW_QCA9887: 2765 ar->regs = &qca988x_regs; 2766 ar->hw_ce_regs = &qcax_ce_regs; 2767 ar->hw_values = &qca988x_values; 2768 break; 2769 case ATH10K_HW_QCA6174: 2770 case ATH10K_HW_QCA9377: 2771 ar->regs = &qca6174_regs; 2772 ar->hw_ce_regs = &qcax_ce_regs; 2773 ar->hw_values = &qca6174_values; 2774 break; 2775 case ATH10K_HW_QCA99X0: 2776 case ATH10K_HW_QCA9984: 2777 ar->regs = &qca99x0_regs; 2778 ar->hw_ce_regs = &qcax_ce_regs; 2779 ar->hw_values = &qca99x0_values; 2780 break; 2781 case ATH10K_HW_QCA9888: 2782 ar->regs = &qca99x0_regs; 2783 ar->hw_ce_regs = &qcax_ce_regs; 2784 ar->hw_values = &qca9888_values; 2785 break; 2786 case ATH10K_HW_QCA4019: 2787 ar->regs = &qca4019_regs; 2788 ar->hw_ce_regs = &qcax_ce_regs; 2789 ar->hw_values = &qca4019_values; 2790 break; 2791 case ATH10K_HW_WCN3990: 2792 ar->regs = &wcn3990_regs; 2793 ar->hw_ce_regs = &wcn3990_ce_regs; 2794 ar->hw_values = &wcn3990_values; 2795 break; 2796 default: 2797 ath10k_err(ar, "unsupported core hardware revision %d\n", 2798 hw_rev); 2799 ret = -ENOTSUPP; 2800 goto err_free_mac; 2801 } 2802 2803 init_completion(&ar->scan.started); 2804 init_completion(&ar->scan.completed); 2805 init_completion(&ar->scan.on_channel); 2806 init_completion(&ar->target_suspend); 2807 init_completion(&ar->wow.wakeup_completed); 2808 2809 init_completion(&ar->install_key_done); 2810 init_completion(&ar->vdev_setup_done); 2811 init_completion(&ar->thermal.wmi_sync); 2812 init_completion(&ar->bss_survey_done); 2813 2814 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); 2815 2816 ar->workqueue = create_singlethread_workqueue("ath10k_wq"); 2817 if (!ar->workqueue) 2818 goto err_free_mac; 2819 2820 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq"); 2821 if (!ar->workqueue_aux) 2822 goto err_free_wq; 2823 2824 mutex_init(&ar->conf_mutex); 2825 spin_lock_init(&ar->data_lock); 2826 spin_lock_init(&ar->txqs_lock); 2827 2828 INIT_LIST_HEAD(&ar->txqs); 2829 INIT_LIST_HEAD(&ar->peers); 2830 init_waitqueue_head(&ar->peer_mapping_wq); 2831 init_waitqueue_head(&ar->htt.empty_tx_wq); 2832 init_waitqueue_head(&ar->wmi.tx_credits_wq); 2833 2834 init_completion(&ar->offchan_tx_completed); 2835 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); 2836 skb_queue_head_init(&ar->offchan_tx_queue); 2837 2838 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); 2839 skb_queue_head_init(&ar->wmi_mgmt_tx_queue); 2840 2841 INIT_WORK(&ar->register_work, ath10k_core_register_work); 2842 INIT_WORK(&ar->restart_work, ath10k_core_restart); 2843 INIT_WORK(&ar->set_coverage_class_work, 2844 ath10k_core_set_coverage_class_work); 2845 2846 init_dummy_netdev(&ar->napi_dev); 2847 2848 ret = ath10k_coredump_create(ar); 2849 if (ret) 2850 goto err_free_aux_wq; 2851 2852 ret = ath10k_debug_create(ar); 2853 if (ret) 2854 goto err_free_coredump; 2855 2856 return ar; 2857 2858 err_free_coredump: 2859 ath10k_coredump_destroy(ar); 2860 2861 err_free_aux_wq: 2862 destroy_workqueue(ar->workqueue_aux); 2863 err_free_wq: 2864 destroy_workqueue(ar->workqueue); 2865 2866 err_free_mac: 2867 ath10k_mac_destroy(ar); 2868 2869 return NULL; 2870 } 2871 EXPORT_SYMBOL(ath10k_core_create); 2872 2873 void ath10k_core_destroy(struct ath10k *ar) 2874 { 2875 flush_workqueue(ar->workqueue); 2876 destroy_workqueue(ar->workqueue); 2877 2878 flush_workqueue(ar->workqueue_aux); 2879 destroy_workqueue(ar->workqueue_aux); 2880 2881 ath10k_debug_destroy(ar); 2882 ath10k_coredump_destroy(ar); 2883 ath10k_htt_tx_destroy(&ar->htt); 2884 ath10k_wmi_free_host_mem(ar); 2885 ath10k_mac_destroy(ar); 2886 } 2887 EXPORT_SYMBOL(ath10k_core_destroy); 2888 2889 MODULE_AUTHOR("Qualcomm Atheros"); 2890 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards."); 2891 MODULE_LICENSE("Dual BSD/GPL"); 2892