1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/firmware.h> 10 #include <linux/of.h> 11 #include <linux/property.h> 12 #include <linux/dmi.h> 13 #include <linux/ctype.h> 14 #include <linux/pm_qos.h> 15 #include <linux/nvmem-consumer.h> 16 #include <asm/byteorder.h> 17 18 #include "core.h" 19 #include "mac.h" 20 #include "htc.h" 21 #include "hif.h" 22 #include "wmi.h" 23 #include "bmi.h" 24 #include "debug.h" 25 #include "htt.h" 26 #include "testmode.h" 27 #include "wmi-ops.h" 28 #include "coredump.h" 29 30 unsigned int ath10k_debug_mask; 31 EXPORT_SYMBOL(ath10k_debug_mask); 32 33 static unsigned int ath10k_cryptmode_param; 34 static bool uart_print; 35 static bool skip_otp; 36 static bool fw_diag_log; 37 38 /* frame mode values are mapped as per enum ath10k_hw_txrx_mode */ 39 unsigned int ath10k_frame_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 40 41 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) | 42 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA); 43 44 /* FIXME: most of these should be readonly */ 45 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); 46 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644); 47 module_param(uart_print, bool, 0644); 48 module_param(skip_otp, bool, 0644); 49 module_param(fw_diag_log, bool, 0644); 50 module_param_named(frame_mode, ath10k_frame_mode, uint, 0644); 51 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444); 52 53 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 54 MODULE_PARM_DESC(uart_print, "Uart target debugging"); 55 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); 56 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software"); 57 MODULE_PARM_DESC(frame_mode, 58 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 59 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file"); 60 MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging"); 61 62 static const struct ath10k_hw_params ath10k_hw_params_list[] = { 63 { 64 .id = QCA988X_HW_2_0_VERSION, 65 .dev_id = QCA988X_2_0_DEVICE_ID, 66 .bus = ATH10K_BUS_PCI, 67 .name = "qca988x hw2.0", 68 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 69 .uart_pin = 7, 70 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 71 .otp_exe_param = 0, 72 .channel_counters_freq_hz = 88000, 73 .max_probe_resp_desc_thres = 0, 74 .cal_data_len = 2116, 75 .fw = { 76 .dir = QCA988X_HW_2_0_FW_DIR, 77 .board = QCA988X_HW_2_0_BOARD_DATA_FILE, 78 .board_size = QCA988X_BOARD_DATA_SZ, 79 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 80 }, 81 .rx_desc_ops = &qca988x_rx_desc_ops, 82 .hw_ops = &qca988x_ops, 83 .decap_align_bytes = 4, 84 .spectral_bin_discard = 0, 85 .spectral_bin_offset = 0, 86 .vht160_mcs_rx_highest = 0, 87 .vht160_mcs_tx_highest = 0, 88 .n_cipher_suites = 8, 89 .ast_skid_limit = 0x10, 90 .num_wds_entries = 0x20, 91 .target_64bit = false, 92 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 93 .shadow_reg_support = false, 94 .rri_on_ddr = false, 95 .hw_filter_reset_required = true, 96 .fw_diag_ce_download = false, 97 .credit_size_workaround = false, 98 .tx_stats_over_pktlog = true, 99 .dynamic_sar_support = false, 100 .hw_restart_disconnect = false, 101 .use_fw_tx_credits = true, 102 }, 103 { 104 .id = QCA988X_HW_2_0_VERSION, 105 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT, 106 .name = "qca988x hw2.0 ubiquiti", 107 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 108 .uart_pin = 7, 109 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 110 .otp_exe_param = 0, 111 .channel_counters_freq_hz = 88000, 112 .max_probe_resp_desc_thres = 0, 113 .cal_data_len = 2116, 114 .fw = { 115 .dir = QCA988X_HW_2_0_FW_DIR, 116 .board = QCA988X_HW_2_0_BOARD_DATA_FILE, 117 .board_size = QCA988X_BOARD_DATA_SZ, 118 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 119 }, 120 .rx_desc_ops = &qca988x_rx_desc_ops, 121 .hw_ops = &qca988x_ops, 122 .decap_align_bytes = 4, 123 .spectral_bin_discard = 0, 124 .spectral_bin_offset = 0, 125 .vht160_mcs_rx_highest = 0, 126 .vht160_mcs_tx_highest = 0, 127 .n_cipher_suites = 8, 128 .ast_skid_limit = 0x10, 129 .num_wds_entries = 0x20, 130 .target_64bit = false, 131 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 132 .shadow_reg_support = false, 133 .rri_on_ddr = false, 134 .hw_filter_reset_required = true, 135 .fw_diag_ce_download = false, 136 .credit_size_workaround = false, 137 .tx_stats_over_pktlog = true, 138 .dynamic_sar_support = false, 139 .hw_restart_disconnect = false, 140 .use_fw_tx_credits = true, 141 }, 142 { 143 .id = QCA9887_HW_1_0_VERSION, 144 .dev_id = QCA9887_1_0_DEVICE_ID, 145 .bus = ATH10K_BUS_PCI, 146 .name = "qca9887 hw1.0", 147 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, 148 .uart_pin = 7, 149 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 150 .otp_exe_param = 0, 151 .channel_counters_freq_hz = 88000, 152 .max_probe_resp_desc_thres = 0, 153 .cal_data_len = 2116, 154 .fw = { 155 .dir = QCA9887_HW_1_0_FW_DIR, 156 .board = QCA9887_HW_1_0_BOARD_DATA_FILE, 157 .board_size = QCA9887_BOARD_DATA_SZ, 158 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, 159 }, 160 .rx_desc_ops = &qca988x_rx_desc_ops, 161 .hw_ops = &qca988x_ops, 162 .decap_align_bytes = 4, 163 .spectral_bin_discard = 0, 164 .spectral_bin_offset = 0, 165 .vht160_mcs_rx_highest = 0, 166 .vht160_mcs_tx_highest = 0, 167 .n_cipher_suites = 8, 168 .ast_skid_limit = 0x10, 169 .num_wds_entries = 0x20, 170 .target_64bit = false, 171 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 172 .shadow_reg_support = false, 173 .rri_on_ddr = false, 174 .hw_filter_reset_required = true, 175 .fw_diag_ce_download = false, 176 .credit_size_workaround = false, 177 .tx_stats_over_pktlog = false, 178 .dynamic_sar_support = false, 179 .hw_restart_disconnect = false, 180 .use_fw_tx_credits = true, 181 }, 182 { 183 .id = QCA6174_HW_3_2_VERSION, 184 .dev_id = QCA6174_3_2_DEVICE_ID, 185 .bus = ATH10K_BUS_SDIO, 186 .name = "qca6174 hw3.2 sdio", 187 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 188 .uart_pin = 19, 189 .otp_exe_param = 0, 190 .channel_counters_freq_hz = 88000, 191 .max_probe_resp_desc_thres = 0, 192 .cal_data_len = 0, 193 .fw = { 194 .dir = QCA6174_HW_3_0_FW_DIR, 195 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 196 .board_size = QCA6174_BOARD_DATA_SZ, 197 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 198 }, 199 .rx_desc_ops = &qca988x_rx_desc_ops, 200 .hw_ops = &qca6174_sdio_ops, 201 .hw_clk = qca6174_clk, 202 .target_cpu_freq = 176000000, 203 .decap_align_bytes = 4, 204 .n_cipher_suites = 8, 205 .num_peers = 10, 206 .ast_skid_limit = 0x10, 207 .num_wds_entries = 0x20, 208 .uart_pin_workaround = true, 209 .tx_stats_over_pktlog = false, 210 .credit_size_workaround = false, 211 .bmi_large_size_download = true, 212 .supports_peer_stats_info = true, 213 .dynamic_sar_support = true, 214 .hw_restart_disconnect = false, 215 .use_fw_tx_credits = true, 216 }, 217 { 218 .id = QCA6174_HW_2_1_VERSION, 219 .dev_id = QCA6164_2_1_DEVICE_ID, 220 .bus = ATH10K_BUS_PCI, 221 .name = "qca6164 hw2.1", 222 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 223 .uart_pin = 6, 224 .otp_exe_param = 0, 225 .channel_counters_freq_hz = 88000, 226 .max_probe_resp_desc_thres = 0, 227 .cal_data_len = 8124, 228 .fw = { 229 .dir = QCA6174_HW_2_1_FW_DIR, 230 .board = QCA6174_HW_2_1_BOARD_DATA_FILE, 231 .board_size = QCA6174_BOARD_DATA_SZ, 232 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 233 }, 234 .rx_desc_ops = &qca988x_rx_desc_ops, 235 .hw_ops = &qca988x_ops, 236 .decap_align_bytes = 4, 237 .spectral_bin_discard = 0, 238 .spectral_bin_offset = 0, 239 .vht160_mcs_rx_highest = 0, 240 .vht160_mcs_tx_highest = 0, 241 .n_cipher_suites = 8, 242 .ast_skid_limit = 0x10, 243 .num_wds_entries = 0x20, 244 .target_64bit = false, 245 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 246 .shadow_reg_support = false, 247 .rri_on_ddr = false, 248 .hw_filter_reset_required = true, 249 .fw_diag_ce_download = false, 250 .credit_size_workaround = false, 251 .tx_stats_over_pktlog = false, 252 .dynamic_sar_support = false, 253 .hw_restart_disconnect = false, 254 .use_fw_tx_credits = true, 255 }, 256 { 257 .id = QCA6174_HW_2_1_VERSION, 258 .dev_id = QCA6174_2_1_DEVICE_ID, 259 .bus = ATH10K_BUS_PCI, 260 .name = "qca6174 hw2.1", 261 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 262 .uart_pin = 6, 263 .otp_exe_param = 0, 264 .channel_counters_freq_hz = 88000, 265 .max_probe_resp_desc_thres = 0, 266 .cal_data_len = 8124, 267 .fw = { 268 .dir = QCA6174_HW_2_1_FW_DIR, 269 .board = QCA6174_HW_2_1_BOARD_DATA_FILE, 270 .board_size = QCA6174_BOARD_DATA_SZ, 271 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 272 }, 273 .rx_desc_ops = &qca988x_rx_desc_ops, 274 .hw_ops = &qca988x_ops, 275 .decap_align_bytes = 4, 276 .spectral_bin_discard = 0, 277 .spectral_bin_offset = 0, 278 .vht160_mcs_rx_highest = 0, 279 .vht160_mcs_tx_highest = 0, 280 .n_cipher_suites = 8, 281 .ast_skid_limit = 0x10, 282 .num_wds_entries = 0x20, 283 .target_64bit = false, 284 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 285 .shadow_reg_support = false, 286 .rri_on_ddr = false, 287 .hw_filter_reset_required = true, 288 .fw_diag_ce_download = false, 289 .credit_size_workaround = false, 290 .tx_stats_over_pktlog = false, 291 .dynamic_sar_support = false, 292 .hw_restart_disconnect = false, 293 .use_fw_tx_credits = true, 294 }, 295 { 296 .id = QCA6174_HW_3_0_VERSION, 297 .dev_id = QCA6174_2_1_DEVICE_ID, 298 .bus = ATH10K_BUS_PCI, 299 .name = "qca6174 hw3.0", 300 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 301 .uart_pin = 6, 302 .otp_exe_param = 0, 303 .channel_counters_freq_hz = 88000, 304 .max_probe_resp_desc_thres = 0, 305 .cal_data_len = 8124, 306 .fw = { 307 .dir = QCA6174_HW_3_0_FW_DIR, 308 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 309 .board_size = QCA6174_BOARD_DATA_SZ, 310 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 311 }, 312 .rx_desc_ops = &qca988x_rx_desc_ops, 313 .hw_ops = &qca988x_ops, 314 .decap_align_bytes = 4, 315 .spectral_bin_discard = 0, 316 .spectral_bin_offset = 0, 317 .vht160_mcs_rx_highest = 0, 318 .vht160_mcs_tx_highest = 0, 319 .n_cipher_suites = 8, 320 .ast_skid_limit = 0x10, 321 .num_wds_entries = 0x20, 322 .target_64bit = false, 323 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 324 .shadow_reg_support = false, 325 .rri_on_ddr = false, 326 .hw_filter_reset_required = true, 327 .fw_diag_ce_download = false, 328 .credit_size_workaround = false, 329 .tx_stats_over_pktlog = false, 330 .dynamic_sar_support = false, 331 .hw_restart_disconnect = false, 332 .use_fw_tx_credits = true, 333 }, 334 { 335 .id = QCA6174_HW_3_2_VERSION, 336 .dev_id = QCA6174_2_1_DEVICE_ID, 337 .bus = ATH10K_BUS_PCI, 338 .name = "qca6174 hw3.2", 339 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 340 .uart_pin = 6, 341 .otp_exe_param = 0, 342 .channel_counters_freq_hz = 88000, 343 .max_probe_resp_desc_thres = 0, 344 .cal_data_len = 8124, 345 .fw = { 346 /* uses same binaries as hw3.0 */ 347 .dir = QCA6174_HW_3_0_FW_DIR, 348 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 349 .board_size = QCA6174_BOARD_DATA_SZ, 350 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 351 }, 352 .rx_desc_ops = &qca988x_rx_desc_ops, 353 .hw_ops = &qca6174_ops, 354 .hw_clk = qca6174_clk, 355 .target_cpu_freq = 176000000, 356 .decap_align_bytes = 4, 357 .spectral_bin_discard = 0, 358 .spectral_bin_offset = 0, 359 .vht160_mcs_rx_highest = 0, 360 .vht160_mcs_tx_highest = 0, 361 .n_cipher_suites = 8, 362 .ast_skid_limit = 0x10, 363 .num_wds_entries = 0x20, 364 .target_64bit = false, 365 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 366 .shadow_reg_support = false, 367 .rri_on_ddr = false, 368 .hw_filter_reset_required = true, 369 .fw_diag_ce_download = true, 370 .credit_size_workaround = false, 371 .tx_stats_over_pktlog = false, 372 .supports_peer_stats_info = true, 373 .dynamic_sar_support = true, 374 .hw_restart_disconnect = false, 375 .use_fw_tx_credits = true, 376 }, 377 { 378 .id = QCA99X0_HW_2_0_DEV_VERSION, 379 .dev_id = QCA99X0_2_0_DEVICE_ID, 380 .bus = ATH10K_BUS_PCI, 381 .name = "qca99x0 hw2.0", 382 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, 383 .uart_pin = 7, 384 .otp_exe_param = 0x00000700, 385 .continuous_frag_desc = true, 386 .cck_rate_map_rev2 = true, 387 .channel_counters_freq_hz = 150000, 388 .max_probe_resp_desc_thres = 24, 389 .tx_chain_mask = 0xf, 390 .rx_chain_mask = 0xf, 391 .max_spatial_stream = 4, 392 .cal_data_len = 12064, 393 .fw = { 394 .dir = QCA99X0_HW_2_0_FW_DIR, 395 .board = QCA99X0_HW_2_0_BOARD_DATA_FILE, 396 .board_size = QCA99X0_BOARD_DATA_SZ, 397 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 398 }, 399 .sw_decrypt_mcast_mgmt = true, 400 .rx_desc_ops = &qca99x0_rx_desc_ops, 401 .hw_ops = &qca99x0_ops, 402 .decap_align_bytes = 1, 403 .spectral_bin_discard = 4, 404 .spectral_bin_offset = 0, 405 .vht160_mcs_rx_highest = 0, 406 .vht160_mcs_tx_highest = 0, 407 .n_cipher_suites = 11, 408 .ast_skid_limit = 0x10, 409 .num_wds_entries = 0x20, 410 .target_64bit = false, 411 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 412 .shadow_reg_support = false, 413 .rri_on_ddr = false, 414 .hw_filter_reset_required = true, 415 .fw_diag_ce_download = false, 416 .credit_size_workaround = false, 417 .tx_stats_over_pktlog = false, 418 .dynamic_sar_support = false, 419 .hw_restart_disconnect = false, 420 .use_fw_tx_credits = true, 421 }, 422 { 423 .id = QCA9984_HW_1_0_DEV_VERSION, 424 .dev_id = QCA9984_1_0_DEVICE_ID, 425 .bus = ATH10K_BUS_PCI, 426 .name = "qca9984/qca9994 hw1.0", 427 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, 428 .uart_pin = 7, 429 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 430 .otp_exe_param = 0x00000700, 431 .continuous_frag_desc = true, 432 .cck_rate_map_rev2 = true, 433 .channel_counters_freq_hz = 150000, 434 .max_probe_resp_desc_thres = 24, 435 .tx_chain_mask = 0xf, 436 .rx_chain_mask = 0xf, 437 .max_spatial_stream = 4, 438 .cal_data_len = 12064, 439 .fw = { 440 .dir = QCA9984_HW_1_0_FW_DIR, 441 .board = QCA9984_HW_1_0_BOARD_DATA_FILE, 442 .eboard = QCA9984_HW_1_0_EBOARD_DATA_FILE, 443 .board_size = QCA99X0_BOARD_DATA_SZ, 444 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 445 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ, 446 }, 447 .sw_decrypt_mcast_mgmt = true, 448 .rx_desc_ops = &qca99x0_rx_desc_ops, 449 .hw_ops = &qca99x0_ops, 450 .decap_align_bytes = 1, 451 .spectral_bin_discard = 12, 452 .spectral_bin_offset = 8, 453 454 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz 455 * or 2x2 160Mhz, long-guard-interval. 456 */ 457 .vht160_mcs_rx_highest = 1560, 458 .vht160_mcs_tx_highest = 1560, 459 .n_cipher_suites = 11, 460 .ast_skid_limit = 0x10, 461 .num_wds_entries = 0x20, 462 .target_64bit = false, 463 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 464 .shadow_reg_support = false, 465 .rri_on_ddr = false, 466 .hw_filter_reset_required = true, 467 .fw_diag_ce_download = false, 468 .credit_size_workaround = false, 469 .tx_stats_over_pktlog = false, 470 .dynamic_sar_support = false, 471 .hw_restart_disconnect = false, 472 .use_fw_tx_credits = true, 473 }, 474 { 475 .id = QCA9888_HW_2_0_DEV_VERSION, 476 .dev_id = QCA9888_2_0_DEVICE_ID, 477 .bus = ATH10K_BUS_PCI, 478 .name = "qca9888 hw2.0", 479 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, 480 .uart_pin = 7, 481 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 482 .otp_exe_param = 0x00000700, 483 .continuous_frag_desc = true, 484 .channel_counters_freq_hz = 150000, 485 .max_probe_resp_desc_thres = 24, 486 .tx_chain_mask = 3, 487 .rx_chain_mask = 3, 488 .max_spatial_stream = 2, 489 .cal_data_len = 12064, 490 .fw = { 491 .dir = QCA9888_HW_2_0_FW_DIR, 492 .board = QCA9888_HW_2_0_BOARD_DATA_FILE, 493 .board_size = QCA99X0_BOARD_DATA_SZ, 494 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 495 }, 496 .sw_decrypt_mcast_mgmt = true, 497 .rx_desc_ops = &qca99x0_rx_desc_ops, 498 .hw_ops = &qca99x0_ops, 499 .decap_align_bytes = 1, 500 .spectral_bin_discard = 12, 501 .spectral_bin_offset = 8, 502 503 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or 504 * 1x1 160Mhz, long-guard-interval. 505 */ 506 .vht160_mcs_rx_highest = 780, 507 .vht160_mcs_tx_highest = 780, 508 .n_cipher_suites = 11, 509 .ast_skid_limit = 0x10, 510 .num_wds_entries = 0x20, 511 .target_64bit = false, 512 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 513 .shadow_reg_support = false, 514 .rri_on_ddr = false, 515 .hw_filter_reset_required = true, 516 .fw_diag_ce_download = false, 517 .credit_size_workaround = false, 518 .tx_stats_over_pktlog = false, 519 .dynamic_sar_support = false, 520 .hw_restart_disconnect = false, 521 .use_fw_tx_credits = true, 522 }, 523 { 524 .id = QCA9377_HW_1_0_DEV_VERSION, 525 .dev_id = QCA9377_1_0_DEVICE_ID, 526 .bus = ATH10K_BUS_PCI, 527 .name = "qca9377 hw1.0", 528 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 529 .uart_pin = 6, 530 .otp_exe_param = 0, 531 .channel_counters_freq_hz = 88000, 532 .max_probe_resp_desc_thres = 0, 533 .cal_data_len = 8124, 534 .fw = { 535 .dir = QCA9377_HW_1_0_FW_DIR, 536 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 537 .board_size = QCA9377_BOARD_DATA_SZ, 538 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 539 }, 540 .rx_desc_ops = &qca988x_rx_desc_ops, 541 .hw_ops = &qca988x_ops, 542 .decap_align_bytes = 4, 543 .spectral_bin_discard = 0, 544 .spectral_bin_offset = 0, 545 .vht160_mcs_rx_highest = 0, 546 .vht160_mcs_tx_highest = 0, 547 .n_cipher_suites = 8, 548 .ast_skid_limit = 0x10, 549 .num_wds_entries = 0x20, 550 .target_64bit = false, 551 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 552 .shadow_reg_support = false, 553 .rri_on_ddr = false, 554 .hw_filter_reset_required = true, 555 .fw_diag_ce_download = false, 556 .credit_size_workaround = false, 557 .tx_stats_over_pktlog = false, 558 .dynamic_sar_support = false, 559 .hw_restart_disconnect = false, 560 .use_fw_tx_credits = true, 561 }, 562 { 563 .id = QCA9377_HW_1_1_DEV_VERSION, 564 .dev_id = QCA9377_1_0_DEVICE_ID, 565 .bus = ATH10K_BUS_PCI, 566 .name = "qca9377 hw1.1", 567 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 568 .uart_pin = 6, 569 .otp_exe_param = 0, 570 .channel_counters_freq_hz = 88000, 571 .max_probe_resp_desc_thres = 0, 572 .cal_data_len = 8124, 573 .fw = { 574 .dir = QCA9377_HW_1_0_FW_DIR, 575 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 576 .board_size = QCA9377_BOARD_DATA_SZ, 577 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 578 }, 579 .rx_desc_ops = &qca988x_rx_desc_ops, 580 .hw_ops = &qca6174_ops, 581 .hw_clk = qca6174_clk, 582 .target_cpu_freq = 176000000, 583 .decap_align_bytes = 4, 584 .spectral_bin_discard = 0, 585 .spectral_bin_offset = 0, 586 .vht160_mcs_rx_highest = 0, 587 .vht160_mcs_tx_highest = 0, 588 .n_cipher_suites = 8, 589 .ast_skid_limit = 0x10, 590 .num_wds_entries = 0x20, 591 .target_64bit = false, 592 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 593 .shadow_reg_support = false, 594 .rri_on_ddr = false, 595 .hw_filter_reset_required = true, 596 .fw_diag_ce_download = true, 597 .credit_size_workaround = false, 598 .tx_stats_over_pktlog = false, 599 .dynamic_sar_support = false, 600 .hw_restart_disconnect = false, 601 .use_fw_tx_credits = true, 602 }, 603 { 604 .id = QCA9377_HW_1_1_DEV_VERSION, 605 .dev_id = QCA9377_1_0_DEVICE_ID, 606 .bus = ATH10K_BUS_SDIO, 607 .name = "qca9377 hw1.1 sdio", 608 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 609 .uart_pin = 19, 610 .otp_exe_param = 0, 611 .channel_counters_freq_hz = 88000, 612 .max_probe_resp_desc_thres = 0, 613 .cal_data_len = 8124, 614 .fw = { 615 .dir = QCA9377_HW_1_0_FW_DIR, 616 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 617 .board_size = QCA9377_BOARD_DATA_SZ, 618 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 619 }, 620 .rx_desc_ops = &qca988x_rx_desc_ops, 621 .hw_ops = &qca6174_ops, 622 .hw_clk = qca6174_clk, 623 .target_cpu_freq = 176000000, 624 .decap_align_bytes = 4, 625 .n_cipher_suites = 8, 626 .num_peers = TARGET_QCA9377_HL_NUM_PEERS, 627 .ast_skid_limit = 0x10, 628 .num_wds_entries = 0x20, 629 .uart_pin_workaround = true, 630 .credit_size_workaround = true, 631 .dynamic_sar_support = false, 632 .hw_restart_disconnect = false, 633 .use_fw_tx_credits = true, 634 }, 635 { 636 .id = QCA4019_HW_1_0_DEV_VERSION, 637 .dev_id = 0, 638 .bus = ATH10K_BUS_AHB, 639 .name = "qca4019 hw1.0", 640 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, 641 .uart_pin = 7, 642 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 643 .otp_exe_param = 0x0010000, 644 .continuous_frag_desc = true, 645 .cck_rate_map_rev2 = true, 646 .channel_counters_freq_hz = 125000, 647 .max_probe_resp_desc_thres = 24, 648 .tx_chain_mask = 0x3, 649 .rx_chain_mask = 0x3, 650 .max_spatial_stream = 2, 651 .cal_data_len = 12064, 652 .fw = { 653 .dir = QCA4019_HW_1_0_FW_DIR, 654 .board = QCA4019_HW_1_0_BOARD_DATA_FILE, 655 .board_size = QCA4019_BOARD_DATA_SZ, 656 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, 657 }, 658 .sw_decrypt_mcast_mgmt = true, 659 .rx_desc_ops = &qca99x0_rx_desc_ops, 660 .hw_ops = &qca99x0_ops, 661 .decap_align_bytes = 1, 662 .spectral_bin_discard = 4, 663 .spectral_bin_offset = 0, 664 .vht160_mcs_rx_highest = 0, 665 .vht160_mcs_tx_highest = 0, 666 .n_cipher_suites = 11, 667 .ast_skid_limit = 0x10, 668 .num_wds_entries = 0x20, 669 .target_64bit = false, 670 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 671 .shadow_reg_support = false, 672 .rri_on_ddr = false, 673 .hw_filter_reset_required = true, 674 .fw_diag_ce_download = false, 675 .credit_size_workaround = false, 676 .tx_stats_over_pktlog = false, 677 .dynamic_sar_support = false, 678 .hw_restart_disconnect = false, 679 .use_fw_tx_credits = true, 680 }, 681 { 682 .id = WCN3990_HW_1_0_DEV_VERSION, 683 .dev_id = 0, 684 .bus = ATH10K_BUS_SNOC, 685 .name = "wcn3990 hw1.0", 686 .continuous_frag_desc = true, 687 .tx_chain_mask = 0x7, 688 .rx_chain_mask = 0x7, 689 .max_spatial_stream = 4, 690 .fw = { 691 .dir = WCN3990_HW_1_0_FW_DIR, 692 }, 693 .sw_decrypt_mcast_mgmt = true, 694 .rx_desc_ops = &wcn3990_rx_desc_ops, 695 .hw_ops = &wcn3990_ops, 696 .decap_align_bytes = 1, 697 .num_peers = TARGET_HL_TLV_NUM_PEERS, 698 .n_cipher_suites = 11, 699 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT, 700 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES, 701 .target_64bit = true, 702 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, 703 .shadow_reg_support = true, 704 .rri_on_ddr = true, 705 .hw_filter_reset_required = false, 706 .fw_diag_ce_download = false, 707 .credit_size_workaround = false, 708 .tx_stats_over_pktlog = false, 709 .dynamic_sar_support = true, 710 .hw_restart_disconnect = true, 711 .use_fw_tx_credits = false, 712 }, 713 }; 714 715 static const char *const ath10k_core_fw_feature_str[] = { 716 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", 717 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", 718 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", 719 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", 720 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", 721 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", 722 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", 723 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", 724 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", 725 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", 726 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode", 727 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca", 728 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp", 729 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl", 730 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param", 731 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war", 732 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast", 733 [ATH10K_FW_FEATURE_NO_PS] = "no-ps", 734 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference", 735 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi", 736 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel", 737 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate", 738 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery", 739 }; 740 741 static unsigned int ath10k_core_get_fw_feature_str(char *buf, 742 size_t buf_len, 743 enum ath10k_fw_features feat) 744 { 745 /* make sure that ath10k_core_fw_feature_str[] gets updated */ 746 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) != 747 ATH10K_FW_FEATURE_COUNT); 748 749 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || 750 WARN_ON(!ath10k_core_fw_feature_str[feat])) { 751 return scnprintf(buf, buf_len, "bit%d", feat); 752 } 753 754 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); 755 } 756 757 void ath10k_core_get_fw_features_str(struct ath10k *ar, 758 char *buf, 759 size_t buf_len) 760 { 761 size_t len = 0; 762 int i; 763 764 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 765 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) { 766 if (len > 0) 767 len += scnprintf(buf + len, buf_len - len, ","); 768 769 len += ath10k_core_get_fw_feature_str(buf + len, 770 buf_len - len, 771 i); 772 } 773 } 774 } 775 776 static void ath10k_send_suspend_complete(struct ath10k *ar) 777 { 778 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); 779 780 complete(&ar->target_suspend); 781 } 782 783 static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode) 784 { 785 bool mtu_workaround = ar->hw_params.credit_size_workaround; 786 int ret; 787 u32 param = 0; 788 789 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256); 790 if (ret) 791 return ret; 792 793 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99); 794 if (ret) 795 return ret; 796 797 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m); 798 if (ret) 799 return ret; 800 801 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET; 802 803 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround) 804 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 805 else 806 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 807 808 if (mode == ATH10K_FIRMWARE_MODE_UTF) 809 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 810 else 811 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 812 813 ret = ath10k_bmi_write32(ar, hi_acs_flags, param); 814 if (ret) 815 return ret; 816 817 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m); 818 if (ret) 819 return ret; 820 821 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST; 822 823 ret = ath10k_bmi_write32(ar, hi_option_flag2, param); 824 if (ret) 825 return ret; 826 827 return 0; 828 } 829 830 static int ath10k_init_configure_target(struct ath10k *ar) 831 { 832 u32 param_host; 833 int ret; 834 835 /* tell target which HTC version it is used*/ 836 ret = ath10k_bmi_write32(ar, hi_app_host_interest, 837 HTC_PROTOCOL_VERSION); 838 if (ret) { 839 ath10k_err(ar, "settings HTC version failed\n"); 840 return ret; 841 } 842 843 /* set the firmware mode to STA/IBSS/AP */ 844 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); 845 if (ret) { 846 ath10k_err(ar, "setting firmware mode (1/2) failed\n"); 847 return ret; 848 } 849 850 /* TODO following parameters need to be re-visited. */ 851 /* num_device */ 852 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); 853 /* Firmware mode */ 854 /* FIXME: Why FW_MODE_AP ??.*/ 855 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); 856 /* mac_addr_method */ 857 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 858 /* firmware_bridge */ 859 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 860 /* fwsubmode */ 861 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); 862 863 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); 864 if (ret) { 865 ath10k_err(ar, "setting firmware mode (2/2) failed\n"); 866 return ret; 867 } 868 869 /* We do all byte-swapping on the host */ 870 ret = ath10k_bmi_write32(ar, hi_be, 0); 871 if (ret) { 872 ath10k_err(ar, "setting host CPU BE mode failed\n"); 873 return ret; 874 } 875 876 /* FW descriptor/Data swap flags */ 877 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); 878 879 if (ret) { 880 ath10k_err(ar, "setting FW data/desc swap flags failed\n"); 881 return ret; 882 } 883 884 /* Some devices have a special sanity check that verifies the PCI 885 * Device ID is written to this host interest var. It is known to be 886 * required to boot QCA6164. 887 */ 888 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext, 889 ar->dev_id); 890 if (ret) { 891 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret); 892 return ret; 893 } 894 895 return 0; 896 } 897 898 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, 899 const char *dir, 900 const char *file) 901 { 902 char filename[100]; 903 const struct firmware *fw; 904 int ret; 905 906 if (file == NULL) 907 return ERR_PTR(-ENOENT); 908 909 if (dir == NULL) 910 dir = "."; 911 912 snprintf(filename, sizeof(filename), "%s/%s", dir, file); 913 ret = firmware_request_nowarn(&fw, filename, ar->dev); 914 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 915 filename, ret); 916 917 if (ret) 918 return ERR_PTR(ret); 919 920 return fw; 921 } 922 923 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, 924 size_t data_len) 925 { 926 u32 board_data_size = ar->hw_params.fw.board_size; 927 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; 928 u32 board_ext_data_addr; 929 int ret; 930 931 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); 932 if (ret) { 933 ath10k_err(ar, "could not read board ext data addr (%d)\n", 934 ret); 935 return ret; 936 } 937 938 ath10k_dbg(ar, ATH10K_DBG_BOOT, 939 "boot push board extended data addr 0x%x\n", 940 board_ext_data_addr); 941 942 if (board_ext_data_addr == 0) 943 return 0; 944 945 if (data_len != (board_data_size + board_ext_data_size)) { 946 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", 947 data_len, board_data_size, board_ext_data_size); 948 return -EINVAL; 949 } 950 951 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, 952 data + board_data_size, 953 board_ext_data_size); 954 if (ret) { 955 ath10k_err(ar, "could not write board ext data (%d)\n", ret); 956 return ret; 957 } 958 959 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, 960 (board_ext_data_size << 16) | 1); 961 if (ret) { 962 ath10k_err(ar, "could not write board ext data bit (%d)\n", 963 ret); 964 return ret; 965 } 966 967 return 0; 968 } 969 970 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) 971 { 972 u32 result, address; 973 u8 board_id, chip_id; 974 bool ext_bid_support; 975 int ret, bmi_board_id_param; 976 977 address = ar->hw_params.patch_load_addr; 978 979 if (!ar->normal_mode_fw.fw_file.otp_data || 980 !ar->normal_mode_fw.fw_file.otp_len) { 981 ath10k_warn(ar, 982 "failed to retrieve board id because of invalid otp\n"); 983 return -ENODATA; 984 } 985 986 if (ar->id.bmi_ids_valid) { 987 ath10k_dbg(ar, ATH10K_DBG_BOOT, 988 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n", 989 ar->id.bmi_board_id, ar->id.bmi_chip_id); 990 goto skip_otp_download; 991 } 992 993 ath10k_dbg(ar, ATH10K_DBG_BOOT, 994 "boot upload otp to 0x%x len %zd for board id\n", 995 address, ar->normal_mode_fw.fw_file.otp_len); 996 997 ret = ath10k_bmi_fast_download(ar, address, 998 ar->normal_mode_fw.fw_file.otp_data, 999 ar->normal_mode_fw.fw_file.otp_len); 1000 if (ret) { 1001 ath10k_err(ar, "could not write otp for board id check: %d\n", 1002 ret); 1003 return ret; 1004 } 1005 1006 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1007 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1008 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1009 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID; 1010 else 1011 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID; 1012 1013 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result); 1014 if (ret) { 1015 ath10k_err(ar, "could not execute otp for board id check: %d\n", 1016 ret); 1017 return ret; 1018 } 1019 1020 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP); 1021 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP); 1022 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT); 1023 1024 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1025 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n", 1026 result, board_id, chip_id, ext_bid_support); 1027 1028 ar->id.ext_bid_supported = ext_bid_support; 1029 1030 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 || 1031 (board_id == 0)) { 1032 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1033 "board id does not exist in otp, ignore it\n"); 1034 return -EOPNOTSUPP; 1035 } 1036 1037 ar->id.bmi_ids_valid = true; 1038 ar->id.bmi_board_id = board_id; 1039 ar->id.bmi_chip_id = chip_id; 1040 1041 skip_otp_download: 1042 1043 return 0; 1044 } 1045 1046 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data) 1047 { 1048 struct ath10k *ar = data; 1049 const char *bdf_ext; 1050 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC; 1051 u8 bdf_enabled; 1052 int i; 1053 1054 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE) 1055 return; 1056 1057 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) { 1058 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1059 "wrong smbios bdf ext type length (%d).\n", 1060 hdr->length); 1061 return; 1062 } 1063 1064 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET); 1065 if (!bdf_enabled) { 1066 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n"); 1067 return; 1068 } 1069 1070 /* Only one string exists (per spec) */ 1071 bdf_ext = (char *)hdr + hdr->length; 1072 1073 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) { 1074 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1075 "bdf variant magic does not match.\n"); 1076 return; 1077 } 1078 1079 for (i = 0; i < strlen(bdf_ext); i++) { 1080 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) { 1081 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1082 "bdf variant name contains non ascii chars.\n"); 1083 return; 1084 } 1085 } 1086 1087 /* Copy extension name without magic suffix */ 1088 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic), 1089 sizeof(ar->id.bdf_ext)) < 0) { 1090 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1091 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1092 bdf_ext); 1093 return; 1094 } 1095 1096 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1097 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1098 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext); 1099 } 1100 1101 static int ath10k_core_check_smbios(struct ath10k *ar) 1102 { 1103 ar->id.bdf_ext[0] = '\0'; 1104 dmi_walk(ath10k_core_check_bdfext, ar); 1105 1106 if (ar->id.bdf_ext[0] == '\0') 1107 return -ENODATA; 1108 1109 return 0; 1110 } 1111 1112 int ath10k_core_check_dt(struct ath10k *ar) 1113 { 1114 struct device_node *node; 1115 const char *variant = NULL; 1116 1117 node = ar->dev->of_node; 1118 if (!node) 1119 return -ENOENT; 1120 1121 of_property_read_string(node, "qcom,ath10k-calibration-variant", 1122 &variant); 1123 if (!variant) 1124 return -ENODATA; 1125 1126 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0) 1127 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1128 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1129 variant); 1130 1131 return 0; 1132 } 1133 EXPORT_SYMBOL(ath10k_core_check_dt); 1134 1135 static int ath10k_download_fw(struct ath10k *ar) 1136 { 1137 u32 address, data_len; 1138 const void *data; 1139 int ret; 1140 struct pm_qos_request latency_qos; 1141 1142 address = ar->hw_params.patch_load_addr; 1143 1144 data = ar->running_fw->fw_file.firmware_data; 1145 data_len = ar->running_fw->fw_file.firmware_len; 1146 1147 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file); 1148 if (ret) { 1149 ath10k_err(ar, "failed to configure fw code swap: %d\n", 1150 ret); 1151 return ret; 1152 } 1153 1154 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1155 "boot uploading firmware image %pK len %d\n", 1156 data, data_len); 1157 1158 /* Check if device supports to download firmware via 1159 * diag copy engine. Downloading firmware via diag CE 1160 * greatly reduces the time to download firmware. 1161 */ 1162 if (ar->hw_params.fw_diag_ce_download) { 1163 ret = ath10k_hw_diag_fast_download(ar, address, 1164 data, data_len); 1165 if (ret == 0) 1166 /* firmware upload via diag ce was successful */ 1167 return 0; 1168 1169 ath10k_warn(ar, 1170 "failed to upload firmware via diag ce, trying BMI: %d", 1171 ret); 1172 } 1173 1174 memset(&latency_qos, 0, sizeof(latency_qos)); 1175 cpu_latency_qos_add_request(&latency_qos, 0); 1176 1177 ret = ath10k_bmi_fast_download(ar, address, data, data_len); 1178 1179 cpu_latency_qos_remove_request(&latency_qos); 1180 1181 return ret; 1182 } 1183 1184 void ath10k_core_free_board_files(struct ath10k *ar) 1185 { 1186 if (!IS_ERR(ar->normal_mode_fw.board)) 1187 release_firmware(ar->normal_mode_fw.board); 1188 1189 if (!IS_ERR(ar->normal_mode_fw.ext_board)) 1190 release_firmware(ar->normal_mode_fw.ext_board); 1191 1192 ar->normal_mode_fw.board = NULL; 1193 ar->normal_mode_fw.board_data = NULL; 1194 ar->normal_mode_fw.board_len = 0; 1195 ar->normal_mode_fw.ext_board = NULL; 1196 ar->normal_mode_fw.ext_board_data = NULL; 1197 ar->normal_mode_fw.ext_board_len = 0; 1198 } 1199 EXPORT_SYMBOL(ath10k_core_free_board_files); 1200 1201 static void ath10k_core_free_firmware_files(struct ath10k *ar) 1202 { 1203 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware)) 1204 release_firmware(ar->normal_mode_fw.fw_file.firmware); 1205 1206 if (!IS_ERR(ar->cal_file)) 1207 release_firmware(ar->cal_file); 1208 1209 if (!IS_ERR(ar->pre_cal_file)) 1210 release_firmware(ar->pre_cal_file); 1211 1212 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file); 1213 1214 ar->normal_mode_fw.fw_file.otp_data = NULL; 1215 ar->normal_mode_fw.fw_file.otp_len = 0; 1216 1217 ar->normal_mode_fw.fw_file.firmware = NULL; 1218 ar->normal_mode_fw.fw_file.firmware_data = NULL; 1219 ar->normal_mode_fw.fw_file.firmware_len = 0; 1220 1221 ar->cal_file = NULL; 1222 ar->pre_cal_file = NULL; 1223 } 1224 1225 static int ath10k_fetch_cal_file(struct ath10k *ar) 1226 { 1227 char filename[100]; 1228 1229 /* pre-cal-<bus>-<id>.bin */ 1230 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", 1231 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1232 1233 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1234 if (!IS_ERR(ar->pre_cal_file)) 1235 goto success; 1236 1237 /* cal-<bus>-<id>.bin */ 1238 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", 1239 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1240 1241 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1242 if (IS_ERR(ar->cal_file)) 1243 /* calibration file is optional, don't print any warnings */ 1244 return PTR_ERR(ar->cal_file); 1245 success: 1246 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", 1247 ATH10K_FW_DIR, filename); 1248 1249 return 0; 1250 } 1251 1252 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type) 1253 { 1254 const struct firmware *fw; 1255 char boardname[100]; 1256 1257 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1258 if (!ar->hw_params.fw.board) { 1259 ath10k_err(ar, "failed to find board file fw entry\n"); 1260 return -EINVAL; 1261 } 1262 1263 scnprintf(boardname, sizeof(boardname), "board-%s-%s.bin", 1264 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1265 1266 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1267 ar->hw_params.fw.dir, 1268 boardname); 1269 if (IS_ERR(ar->normal_mode_fw.board)) { 1270 fw = ath10k_fetch_fw_file(ar, 1271 ar->hw_params.fw.dir, 1272 ar->hw_params.fw.board); 1273 ar->normal_mode_fw.board = fw; 1274 } 1275 1276 if (IS_ERR(ar->normal_mode_fw.board)) 1277 return PTR_ERR(ar->normal_mode_fw.board); 1278 1279 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data; 1280 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size; 1281 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1282 if (!ar->hw_params.fw.eboard) { 1283 ath10k_err(ar, "failed to find eboard file fw entry\n"); 1284 return -EINVAL; 1285 } 1286 1287 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1288 ar->hw_params.fw.eboard); 1289 ar->normal_mode_fw.ext_board = fw; 1290 if (IS_ERR(ar->normal_mode_fw.ext_board)) 1291 return PTR_ERR(ar->normal_mode_fw.ext_board); 1292 1293 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data; 1294 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size; 1295 } 1296 1297 return 0; 1298 } 1299 1300 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar, 1301 const void *buf, size_t buf_len, 1302 const char *boardname, 1303 int bd_ie_type) 1304 { 1305 const struct ath10k_fw_ie *hdr; 1306 bool name_match_found; 1307 int ret, board_ie_id; 1308 size_t board_ie_len; 1309 const void *board_ie_data; 1310 1311 name_match_found = false; 1312 1313 /* go through ATH10K_BD_IE_BOARD_ elements */ 1314 while (buf_len > sizeof(struct ath10k_fw_ie)) { 1315 hdr = buf; 1316 board_ie_id = le32_to_cpu(hdr->id); 1317 board_ie_len = le32_to_cpu(hdr->len); 1318 board_ie_data = hdr->data; 1319 1320 buf_len -= sizeof(*hdr); 1321 buf += sizeof(*hdr); 1322 1323 if (buf_len < ALIGN(board_ie_len, 4)) { 1324 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n", 1325 buf_len, ALIGN(board_ie_len, 4)); 1326 ret = -EINVAL; 1327 goto out; 1328 } 1329 1330 switch (board_ie_id) { 1331 case ATH10K_BD_IE_BOARD_NAME: 1332 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "", 1333 board_ie_data, board_ie_len); 1334 1335 if (board_ie_len != strlen(boardname)) 1336 break; 1337 1338 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1339 if (ret) 1340 break; 1341 1342 name_match_found = true; 1343 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1344 "boot found match for name '%s'", 1345 boardname); 1346 break; 1347 case ATH10K_BD_IE_BOARD_DATA: 1348 if (!name_match_found) 1349 /* no match found */ 1350 break; 1351 1352 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1353 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1354 "boot found board data for '%s'", 1355 boardname); 1356 1357 ar->normal_mode_fw.board_data = board_ie_data; 1358 ar->normal_mode_fw.board_len = board_ie_len; 1359 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1360 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1361 "boot found eboard data for '%s'", 1362 boardname); 1363 1364 ar->normal_mode_fw.ext_board_data = board_ie_data; 1365 ar->normal_mode_fw.ext_board_len = board_ie_len; 1366 } 1367 1368 ret = 0; 1369 goto out; 1370 default: 1371 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n", 1372 board_ie_id); 1373 break; 1374 } 1375 1376 /* jump over the padding */ 1377 board_ie_len = ALIGN(board_ie_len, 4); 1378 1379 buf_len -= board_ie_len; 1380 buf += board_ie_len; 1381 } 1382 1383 /* no match found */ 1384 ret = -ENOENT; 1385 1386 out: 1387 return ret; 1388 } 1389 1390 static int ath10k_core_search_bd(struct ath10k *ar, 1391 const char *boardname, 1392 const u8 *data, 1393 size_t len) 1394 { 1395 size_t ie_len; 1396 struct ath10k_fw_ie *hdr; 1397 int ret = -ENOENT, ie_id; 1398 1399 while (len > sizeof(struct ath10k_fw_ie)) { 1400 hdr = (struct ath10k_fw_ie *)data; 1401 ie_id = le32_to_cpu(hdr->id); 1402 ie_len = le32_to_cpu(hdr->len); 1403 1404 len -= sizeof(*hdr); 1405 data = hdr->data; 1406 1407 if (len < ALIGN(ie_len, 4)) { 1408 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1409 ie_id, ie_len, len); 1410 return -EINVAL; 1411 } 1412 1413 switch (ie_id) { 1414 case ATH10K_BD_IE_BOARD: 1415 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1416 boardname, 1417 ATH10K_BD_IE_BOARD); 1418 if (ret == -ENOENT) 1419 /* no match found, continue */ 1420 break; 1421 1422 /* either found or error, so stop searching */ 1423 goto out; 1424 case ATH10K_BD_IE_BOARD_EXT: 1425 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1426 boardname, 1427 ATH10K_BD_IE_BOARD_EXT); 1428 if (ret == -ENOENT) 1429 /* no match found, continue */ 1430 break; 1431 1432 /* either found or error, so stop searching */ 1433 goto out; 1434 } 1435 1436 /* jump over the padding */ 1437 ie_len = ALIGN(ie_len, 4); 1438 1439 len -= ie_len; 1440 data += ie_len; 1441 } 1442 1443 out: 1444 /* return result of parse_bd_ie_board() or -ENOENT */ 1445 return ret; 1446 } 1447 1448 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar, 1449 const char *boardname, 1450 const char *fallback_boardname1, 1451 const char *fallback_boardname2, 1452 const char *filename) 1453 { 1454 size_t len, magic_len; 1455 const u8 *data; 1456 int ret; 1457 1458 /* Skip if already fetched during board data download */ 1459 if (!ar->normal_mode_fw.board) 1460 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1461 ar->hw_params.fw.dir, 1462 filename); 1463 if (IS_ERR(ar->normal_mode_fw.board)) 1464 return PTR_ERR(ar->normal_mode_fw.board); 1465 1466 data = ar->normal_mode_fw.board->data; 1467 len = ar->normal_mode_fw.board->size; 1468 1469 /* magic has extra null byte padded */ 1470 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1; 1471 if (len < magic_len) { 1472 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n", 1473 ar->hw_params.fw.dir, filename, len); 1474 ret = -EINVAL; 1475 goto err; 1476 } 1477 1478 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) { 1479 ath10k_err(ar, "found invalid board magic\n"); 1480 ret = -EINVAL; 1481 goto err; 1482 } 1483 1484 /* magic is padded to 4 bytes */ 1485 magic_len = ALIGN(magic_len, 4); 1486 if (len < magic_len) { 1487 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n", 1488 ar->hw_params.fw.dir, filename, len); 1489 ret = -EINVAL; 1490 goto err; 1491 } 1492 1493 data += magic_len; 1494 len -= magic_len; 1495 1496 /* attempt to find boardname in the IE list */ 1497 ret = ath10k_core_search_bd(ar, boardname, data, len); 1498 1499 /* if we didn't find it and have a fallback name, try that */ 1500 if (ret == -ENOENT && fallback_boardname1) 1501 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len); 1502 1503 if (ret == -ENOENT && fallback_boardname2) 1504 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len); 1505 1506 if (ret == -ENOENT) { 1507 ath10k_err(ar, 1508 "failed to fetch board data for %s from %s/%s\n", 1509 boardname, ar->hw_params.fw.dir, filename); 1510 ret = -ENODATA; 1511 } 1512 1513 if (ret) 1514 goto err; 1515 1516 return 0; 1517 1518 err: 1519 ath10k_core_free_board_files(ar); 1520 return ret; 1521 } 1522 1523 static int ath10k_core_create_board_name(struct ath10k *ar, char *name, 1524 size_t name_len, bool with_variant, 1525 bool with_chip_id) 1526 { 1527 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */ 1528 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 }; 1529 1530 if (with_variant && ar->id.bdf_ext[0] != '\0') 1531 scnprintf(variant, sizeof(variant), ",variant=%s", 1532 ar->id.bdf_ext); 1533 1534 if (ar->id.bmi_ids_valid) { 1535 scnprintf(name, name_len, 1536 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s", 1537 ath10k_bus_str(ar->hif.bus), 1538 ar->id.bmi_chip_id, 1539 ar->id.bmi_board_id, variant); 1540 goto out; 1541 } 1542 1543 if (ar->id.qmi_ids_valid) { 1544 if (with_chip_id) 1545 scnprintf(name, name_len, 1546 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s", 1547 ath10k_bus_str(ar->hif.bus), 1548 ar->id.qmi_board_id, ar->id.qmi_chip_id, 1549 variant); 1550 else 1551 scnprintf(name, name_len, 1552 "bus=%s,qmi-board-id=%x", 1553 ath10k_bus_str(ar->hif.bus), 1554 ar->id.qmi_board_id); 1555 goto out; 1556 } 1557 1558 scnprintf(name, name_len, 1559 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s", 1560 ath10k_bus_str(ar->hif.bus), 1561 ar->id.vendor, ar->id.device, 1562 ar->id.subsystem_vendor, ar->id.subsystem_device, variant); 1563 out: 1564 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name); 1565 1566 return 0; 1567 } 1568 1569 static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name, 1570 size_t name_len) 1571 { 1572 if (ar->id.bmi_ids_valid) { 1573 scnprintf(name, name_len, 1574 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d", 1575 ath10k_bus_str(ar->hif.bus), 1576 ar->id.bmi_chip_id, 1577 ar->id.bmi_eboard_id); 1578 1579 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name); 1580 return 0; 1581 } 1582 /* Fallback if returned board id is zero */ 1583 return -1; 1584 } 1585 1586 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type) 1587 { 1588 char boardname[100], fallback_boardname1[100], fallback_boardname2[100]; 1589 int ret; 1590 1591 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1592 /* With variant and chip id */ 1593 ret = ath10k_core_create_board_name(ar, boardname, 1594 sizeof(boardname), true, 1595 true); 1596 if (ret) { 1597 ath10k_err(ar, "failed to create board name: %d", ret); 1598 return ret; 1599 } 1600 1601 /* Without variant and only chip-id */ 1602 ret = ath10k_core_create_board_name(ar, fallback_boardname1, 1603 sizeof(boardname), false, 1604 true); 1605 if (ret) { 1606 ath10k_err(ar, "failed to create 1st fallback board name: %d", 1607 ret); 1608 return ret; 1609 } 1610 1611 /* Without variant and without chip-id */ 1612 ret = ath10k_core_create_board_name(ar, fallback_boardname2, 1613 sizeof(boardname), false, 1614 false); 1615 if (ret) { 1616 ath10k_err(ar, "failed to create 2nd fallback board name: %d", 1617 ret); 1618 return ret; 1619 } 1620 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1621 ret = ath10k_core_create_eboard_name(ar, boardname, 1622 sizeof(boardname)); 1623 if (ret) { 1624 ath10k_err(ar, "fallback to eboard.bin since board id 0"); 1625 goto fallback; 1626 } 1627 } 1628 1629 ar->bd_api = 2; 1630 ret = ath10k_core_fetch_board_data_api_n(ar, boardname, 1631 fallback_boardname1, 1632 fallback_boardname2, 1633 ATH10K_BOARD_API2_FILE); 1634 if (!ret) 1635 goto success; 1636 1637 fallback: 1638 ar->bd_api = 1; 1639 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type); 1640 if (ret) { 1641 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n", 1642 ar->hw_params.fw.dir); 1643 return ret; 1644 } 1645 1646 success: 1647 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api); 1648 return 0; 1649 } 1650 EXPORT_SYMBOL(ath10k_core_fetch_board_file); 1651 1652 static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar) 1653 { 1654 u32 result, address; 1655 u8 ext_board_id; 1656 int ret; 1657 1658 address = ar->hw_params.patch_load_addr; 1659 1660 if (!ar->normal_mode_fw.fw_file.otp_data || 1661 !ar->normal_mode_fw.fw_file.otp_len) { 1662 ath10k_warn(ar, 1663 "failed to retrieve extended board id due to otp binary missing\n"); 1664 return -ENODATA; 1665 } 1666 1667 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1668 "boot upload otp to 0x%x len %zd for ext board id\n", 1669 address, ar->normal_mode_fw.fw_file.otp_len); 1670 1671 ret = ath10k_bmi_fast_download(ar, address, 1672 ar->normal_mode_fw.fw_file.otp_data, 1673 ar->normal_mode_fw.fw_file.otp_len); 1674 if (ret) { 1675 ath10k_err(ar, "could not write otp for ext board id check: %d\n", 1676 ret); 1677 return ret; 1678 } 1679 1680 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result); 1681 if (ret) { 1682 ath10k_err(ar, "could not execute otp for ext board id check: %d\n", 1683 ret); 1684 return ret; 1685 } 1686 1687 if (!result) { 1688 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1689 "ext board id does not exist in otp, ignore it\n"); 1690 return -EOPNOTSUPP; 1691 } 1692 1693 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK; 1694 1695 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1696 "boot get otp ext board id result 0x%08x ext_board_id %d\n", 1697 result, ext_board_id); 1698 1699 ar->id.bmi_eboard_id = ext_board_id; 1700 1701 return 0; 1702 } 1703 1704 static int ath10k_download_board_data(struct ath10k *ar, const void *data, 1705 size_t data_len) 1706 { 1707 u32 board_data_size = ar->hw_params.fw.board_size; 1708 u32 eboard_data_size = ar->hw_params.fw.ext_board_size; 1709 u32 board_address; 1710 u32 ext_board_address; 1711 int ret; 1712 1713 ret = ath10k_push_board_ext_data(ar, data, data_len); 1714 if (ret) { 1715 ath10k_err(ar, "could not push board ext data (%d)\n", ret); 1716 goto exit; 1717 } 1718 1719 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address); 1720 if (ret) { 1721 ath10k_err(ar, "could not read board data addr (%d)\n", ret); 1722 goto exit; 1723 } 1724 1725 ret = ath10k_bmi_write_memory(ar, board_address, data, 1726 min_t(u32, board_data_size, 1727 data_len)); 1728 if (ret) { 1729 ath10k_err(ar, "could not write board data (%d)\n", ret); 1730 goto exit; 1731 } 1732 1733 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); 1734 if (ret) { 1735 ath10k_err(ar, "could not write board data bit (%d)\n", ret); 1736 goto exit; 1737 } 1738 1739 if (!ar->id.ext_bid_supported) 1740 goto exit; 1741 1742 /* Extended board data download */ 1743 ret = ath10k_core_get_ext_board_id_from_otp(ar); 1744 if (ret == -EOPNOTSUPP) { 1745 /* Not fetching ext_board_data if ext board id is 0 */ 1746 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n"); 1747 return 0; 1748 } else if (ret) { 1749 ath10k_err(ar, "failed to get extended board id: %d\n", ret); 1750 goto exit; 1751 } 1752 1753 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT); 1754 if (ret) 1755 goto exit; 1756 1757 if (ar->normal_mode_fw.ext_board_data) { 1758 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET; 1759 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1760 "boot writing ext board data to addr 0x%x", 1761 ext_board_address); 1762 ret = ath10k_bmi_write_memory(ar, ext_board_address, 1763 ar->normal_mode_fw.ext_board_data, 1764 min_t(u32, eboard_data_size, data_len)); 1765 if (ret) 1766 ath10k_err(ar, "failed to write ext board data: %d\n", ret); 1767 } 1768 1769 exit: 1770 return ret; 1771 } 1772 1773 static int ath10k_download_and_run_otp(struct ath10k *ar) 1774 { 1775 u32 result, address = ar->hw_params.patch_load_addr; 1776 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; 1777 int ret; 1778 1779 ret = ath10k_download_board_data(ar, 1780 ar->running_fw->board_data, 1781 ar->running_fw->board_len); 1782 if (ret) { 1783 ath10k_err(ar, "failed to download board data: %d\n", ret); 1784 return ret; 1785 } 1786 1787 /* OTP is optional */ 1788 1789 if (!ar->running_fw->fw_file.otp_data || 1790 !ar->running_fw->fw_file.otp_len) { 1791 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n", 1792 ar->running_fw->fw_file.otp_data, 1793 ar->running_fw->fw_file.otp_len); 1794 return 0; 1795 } 1796 1797 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", 1798 address, ar->running_fw->fw_file.otp_len); 1799 1800 ret = ath10k_bmi_fast_download(ar, address, 1801 ar->running_fw->fw_file.otp_data, 1802 ar->running_fw->fw_file.otp_len); 1803 if (ret) { 1804 ath10k_err(ar, "could not write otp (%d)\n", ret); 1805 return ret; 1806 } 1807 1808 /* As of now pre-cal is valid for 10_4 variants */ 1809 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1810 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1811 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1812 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL; 1813 1814 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); 1815 if (ret) { 1816 ath10k_err(ar, "could not execute otp (%d)\n", ret); 1817 return ret; 1818 } 1819 1820 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); 1821 1822 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, 1823 ar->running_fw->fw_file.fw_features)) && 1824 result != 0) { 1825 ath10k_err(ar, "otp calibration failed: %d", result); 1826 return -EINVAL; 1827 } 1828 1829 return 0; 1830 } 1831 1832 static int ath10k_download_cal_file(struct ath10k *ar, 1833 const struct firmware *file) 1834 { 1835 int ret; 1836 1837 if (!file) 1838 return -ENOENT; 1839 1840 if (IS_ERR(file)) 1841 return PTR_ERR(file); 1842 1843 ret = ath10k_download_board_data(ar, file->data, file->size); 1844 if (ret) { 1845 ath10k_err(ar, "failed to download cal_file data: %d\n", ret); 1846 return ret; 1847 } 1848 1849 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); 1850 1851 return 0; 1852 } 1853 1854 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name) 1855 { 1856 struct device_node *node; 1857 int data_len; 1858 void *data; 1859 int ret; 1860 1861 node = ar->dev->of_node; 1862 if (!node) 1863 /* Device Tree is optional, don't print any warnings if 1864 * there's no node for ath10k. 1865 */ 1866 return -ENOENT; 1867 1868 if (!of_get_property(node, dt_name, &data_len)) { 1869 /* The calibration data node is optional */ 1870 return -ENOENT; 1871 } 1872 1873 if (data_len != ar->hw_params.cal_data_len) { 1874 ath10k_warn(ar, "invalid calibration data length in DT: %d\n", 1875 data_len); 1876 ret = -EMSGSIZE; 1877 goto out; 1878 } 1879 1880 data = kmalloc(data_len, GFP_KERNEL); 1881 if (!data) { 1882 ret = -ENOMEM; 1883 goto out; 1884 } 1885 1886 ret = of_property_read_u8_array(node, dt_name, data, data_len); 1887 if (ret) { 1888 ath10k_warn(ar, "failed to read calibration data from DT: %d\n", 1889 ret); 1890 goto out_free; 1891 } 1892 1893 ret = ath10k_download_board_data(ar, data, data_len); 1894 if (ret) { 1895 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", 1896 ret); 1897 goto out_free; 1898 } 1899 1900 ret = 0; 1901 1902 out_free: 1903 kfree(data); 1904 1905 out: 1906 return ret; 1907 } 1908 1909 static int ath10k_download_cal_eeprom(struct ath10k *ar) 1910 { 1911 size_t data_len; 1912 void *data = NULL; 1913 int ret; 1914 1915 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len); 1916 if (ret) { 1917 if (ret != -EOPNOTSUPP) 1918 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n", 1919 ret); 1920 goto out_free; 1921 } 1922 1923 ret = ath10k_download_board_data(ar, data, data_len); 1924 if (ret) { 1925 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n", 1926 ret); 1927 goto out_free; 1928 } 1929 1930 ret = 0; 1931 1932 out_free: 1933 kfree(data); 1934 1935 return ret; 1936 } 1937 1938 static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name) 1939 { 1940 struct nvmem_cell *cell; 1941 void *buf; 1942 size_t len; 1943 int ret; 1944 1945 cell = devm_nvmem_cell_get(ar->dev, cell_name); 1946 if (IS_ERR(cell)) { 1947 ret = PTR_ERR(cell); 1948 return ret; 1949 } 1950 1951 buf = nvmem_cell_read(cell, &len); 1952 if (IS_ERR(buf)) 1953 return PTR_ERR(buf); 1954 1955 if (ar->hw_params.cal_data_len != len) { 1956 kfree(buf); 1957 ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n", 1958 cell_name, len, ar->hw_params.cal_data_len); 1959 return -EMSGSIZE; 1960 } 1961 1962 ret = ath10k_download_board_data(ar, buf, len); 1963 kfree(buf); 1964 if (ret) 1965 ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n", 1966 cell_name, ret); 1967 1968 return ret; 1969 } 1970 1971 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, 1972 struct ath10k_fw_file *fw_file) 1973 { 1974 size_t magic_len, len, ie_len; 1975 int ie_id, i, index, bit, ret; 1976 struct ath10k_fw_ie *hdr; 1977 const u8 *data; 1978 __le32 *timestamp, *version; 1979 1980 /* first fetch the firmware file (firmware-*.bin) */ 1981 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1982 name); 1983 if (IS_ERR(fw_file->firmware)) 1984 return PTR_ERR(fw_file->firmware); 1985 1986 data = fw_file->firmware->data; 1987 len = fw_file->firmware->size; 1988 1989 /* magic also includes the null byte, check that as well */ 1990 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; 1991 1992 if (len < magic_len) { 1993 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", 1994 ar->hw_params.fw.dir, name, len); 1995 ret = -EINVAL; 1996 goto err; 1997 } 1998 1999 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { 2000 ath10k_err(ar, "invalid firmware magic\n"); 2001 ret = -EINVAL; 2002 goto err; 2003 } 2004 2005 /* jump over the padding */ 2006 magic_len = ALIGN(magic_len, 4); 2007 2008 len -= magic_len; 2009 data += magic_len; 2010 2011 /* loop elements */ 2012 while (len > sizeof(struct ath10k_fw_ie)) { 2013 hdr = (struct ath10k_fw_ie *)data; 2014 2015 ie_id = le32_to_cpu(hdr->id); 2016 ie_len = le32_to_cpu(hdr->len); 2017 2018 len -= sizeof(*hdr); 2019 data += sizeof(*hdr); 2020 2021 if (len < ie_len) { 2022 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", 2023 ie_id, len, ie_len); 2024 ret = -EINVAL; 2025 goto err; 2026 } 2027 2028 switch (ie_id) { 2029 case ATH10K_FW_IE_FW_VERSION: 2030 if (ie_len > sizeof(fw_file->fw_version) - 1) 2031 break; 2032 2033 memcpy(fw_file->fw_version, data, ie_len); 2034 fw_file->fw_version[ie_len] = '\0'; 2035 2036 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2037 "found fw version %s\n", 2038 fw_file->fw_version); 2039 break; 2040 case ATH10K_FW_IE_TIMESTAMP: 2041 if (ie_len != sizeof(u32)) 2042 break; 2043 2044 timestamp = (__le32 *)data; 2045 2046 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", 2047 le32_to_cpup(timestamp)); 2048 break; 2049 case ATH10K_FW_IE_FEATURES: 2050 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2051 "found firmware features ie (%zd B)\n", 2052 ie_len); 2053 2054 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 2055 index = i / 8; 2056 bit = i % 8; 2057 2058 if (index == ie_len) 2059 break; 2060 2061 if (data[index] & (1 << bit)) { 2062 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2063 "Enabling feature bit: %i\n", 2064 i); 2065 __set_bit(i, fw_file->fw_features); 2066 } 2067 } 2068 2069 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", 2070 fw_file->fw_features, 2071 sizeof(fw_file->fw_features)); 2072 break; 2073 case ATH10K_FW_IE_FW_IMAGE: 2074 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2075 "found fw image ie (%zd B)\n", 2076 ie_len); 2077 2078 fw_file->firmware_data = data; 2079 fw_file->firmware_len = ie_len; 2080 2081 break; 2082 case ATH10K_FW_IE_OTP_IMAGE: 2083 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2084 "found otp image ie (%zd B)\n", 2085 ie_len); 2086 2087 fw_file->otp_data = data; 2088 fw_file->otp_len = ie_len; 2089 2090 break; 2091 case ATH10K_FW_IE_WMI_OP_VERSION: 2092 if (ie_len != sizeof(u32)) 2093 break; 2094 2095 version = (__le32 *)data; 2096 2097 fw_file->wmi_op_version = le32_to_cpup(version); 2098 2099 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", 2100 fw_file->wmi_op_version); 2101 break; 2102 case ATH10K_FW_IE_HTT_OP_VERSION: 2103 if (ie_len != sizeof(u32)) 2104 break; 2105 2106 version = (__le32 *)data; 2107 2108 fw_file->htt_op_version = le32_to_cpup(version); 2109 2110 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", 2111 fw_file->htt_op_version); 2112 break; 2113 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: 2114 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2115 "found fw code swap image ie (%zd B)\n", 2116 ie_len); 2117 fw_file->codeswap_data = data; 2118 fw_file->codeswap_len = ie_len; 2119 break; 2120 default: 2121 ath10k_warn(ar, "Unknown FW IE: %u\n", 2122 le32_to_cpu(hdr->id)); 2123 break; 2124 } 2125 2126 /* jump over the padding */ 2127 ie_len = ALIGN(ie_len, 4); 2128 2129 len -= ie_len; 2130 data += ie_len; 2131 } 2132 2133 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) && 2134 (!fw_file->firmware_data || !fw_file->firmware_len)) { 2135 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", 2136 ar->hw_params.fw.dir, name); 2137 ret = -ENOMEDIUM; 2138 goto err; 2139 } 2140 2141 return 0; 2142 2143 err: 2144 ath10k_core_free_firmware_files(ar); 2145 return ret; 2146 } 2147 2148 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name, 2149 size_t fw_name_len, int fw_api) 2150 { 2151 switch (ar->hif.bus) { 2152 case ATH10K_BUS_SDIO: 2153 case ATH10K_BUS_USB: 2154 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin", 2155 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus), 2156 fw_api); 2157 break; 2158 case ATH10K_BUS_PCI: 2159 case ATH10K_BUS_AHB: 2160 case ATH10K_BUS_SNOC: 2161 scnprintf(fw_name, fw_name_len, "%s-%d.bin", 2162 ATH10K_FW_FILE_BASE, fw_api); 2163 break; 2164 } 2165 } 2166 2167 static int ath10k_core_fetch_firmware_files(struct ath10k *ar) 2168 { 2169 int ret, i; 2170 char fw_name[100]; 2171 2172 /* calibration file is optional, don't check for any errors */ 2173 ath10k_fetch_cal_file(ar); 2174 2175 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) { 2176 ar->fw_api = i; 2177 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", 2178 ar->fw_api); 2179 2180 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api); 2181 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name, 2182 &ar->normal_mode_fw.fw_file); 2183 if (!ret) 2184 goto success; 2185 } 2186 2187 /* we end up here if we couldn't fetch any firmware */ 2188 2189 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d", 2190 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir, 2191 ret); 2192 2193 return ret; 2194 2195 success: 2196 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); 2197 2198 return 0; 2199 } 2200 2201 static int ath10k_core_pre_cal_download(struct ath10k *ar) 2202 { 2203 int ret; 2204 2205 ret = ath10k_download_cal_nvmem(ar, "pre-calibration"); 2206 if (ret == 0) { 2207 ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM; 2208 goto success; 2209 } else if (ret == -EPROBE_DEFER) { 2210 return ret; 2211 } 2212 2213 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2214 "boot did not find a pre-calibration nvmem-cell, try file next: %d\n", 2215 ret); 2216 2217 ret = ath10k_download_cal_file(ar, ar->pre_cal_file); 2218 if (ret == 0) { 2219 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE; 2220 goto success; 2221 } 2222 2223 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2224 "boot did not find a pre calibration file, try DT next: %d\n", 2225 ret); 2226 2227 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data"); 2228 if (ret) { 2229 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2230 "unable to load pre cal data from DT: %d\n", ret); 2231 return ret; 2232 } 2233 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT; 2234 2235 success: 2236 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2237 ath10k_cal_mode_str(ar->cal_mode)); 2238 2239 return 0; 2240 } 2241 2242 static int ath10k_core_pre_cal_config(struct ath10k *ar) 2243 { 2244 int ret; 2245 2246 ret = ath10k_core_pre_cal_download(ar); 2247 if (ret) { 2248 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2249 "failed to load pre cal data: %d\n", ret); 2250 return ret; 2251 } 2252 2253 ret = ath10k_core_get_board_id_from_otp(ar); 2254 if (ret) { 2255 ath10k_err(ar, "failed to get board id: %d\n", ret); 2256 return ret; 2257 } 2258 2259 ret = ath10k_download_and_run_otp(ar); 2260 if (ret) { 2261 ath10k_err(ar, "failed to run otp: %d\n", ret); 2262 return ret; 2263 } 2264 2265 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2266 "pre cal configuration done successfully\n"); 2267 2268 return 0; 2269 } 2270 2271 static int ath10k_download_cal_data(struct ath10k *ar) 2272 { 2273 int ret; 2274 2275 ret = ath10k_core_pre_cal_config(ar); 2276 if (ret == 0) 2277 return 0; 2278 2279 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2280 "pre cal download procedure failed, try cal file: %d\n", 2281 ret); 2282 2283 ret = ath10k_download_cal_nvmem(ar, "calibration"); 2284 if (ret == 0) { 2285 ar->cal_mode = ATH10K_CAL_MODE_NVMEM; 2286 goto done; 2287 } else if (ret == -EPROBE_DEFER) { 2288 return ret; 2289 } 2290 2291 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2292 "boot did not find a calibration nvmem-cell, try file next: %d\n", 2293 ret); 2294 2295 ret = ath10k_download_cal_file(ar, ar->cal_file); 2296 if (ret == 0) { 2297 ar->cal_mode = ATH10K_CAL_MODE_FILE; 2298 goto done; 2299 } 2300 2301 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2302 "boot did not find a calibration file, try DT next: %d\n", 2303 ret); 2304 2305 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data"); 2306 if (ret == 0) { 2307 ar->cal_mode = ATH10K_CAL_MODE_DT; 2308 goto done; 2309 } 2310 2311 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2312 "boot did not find DT entry, try target EEPROM next: %d\n", 2313 ret); 2314 2315 ret = ath10k_download_cal_eeprom(ar); 2316 if (ret == 0) { 2317 ar->cal_mode = ATH10K_CAL_MODE_EEPROM; 2318 goto done; 2319 } 2320 2321 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2322 "boot did not find target EEPROM entry, try OTP next: %d\n", 2323 ret); 2324 2325 ret = ath10k_download_and_run_otp(ar); 2326 if (ret) { 2327 ath10k_err(ar, "failed to run otp: %d\n", ret); 2328 return ret; 2329 } 2330 2331 ar->cal_mode = ATH10K_CAL_MODE_OTP; 2332 2333 done: 2334 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2335 ath10k_cal_mode_str(ar->cal_mode)); 2336 return 0; 2337 } 2338 2339 static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar) 2340 { 2341 struct device_node *node; 2342 u8 coex_support = 0; 2343 int ret; 2344 2345 node = ar->dev->of_node; 2346 if (!node) 2347 goto out; 2348 2349 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support); 2350 if (ret) { 2351 ar->coex_support = true; 2352 goto out; 2353 } 2354 2355 if (coex_support) { 2356 ar->coex_support = true; 2357 } else { 2358 ar->coex_support = false; 2359 ar->coex_gpio_pin = -1; 2360 goto out; 2361 } 2362 2363 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin", 2364 &ar->coex_gpio_pin); 2365 if (ret) 2366 ar->coex_gpio_pin = -1; 2367 2368 out: 2369 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n", 2370 ar->coex_support, ar->coex_gpio_pin); 2371 } 2372 2373 static int ath10k_init_uart(struct ath10k *ar) 2374 { 2375 int ret; 2376 2377 /* 2378 * Explicitly setting UART prints to zero as target turns it on 2379 * based on scratch registers. 2380 */ 2381 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); 2382 if (ret) { 2383 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); 2384 return ret; 2385 } 2386 2387 if (!uart_print) { 2388 if (ar->hw_params.uart_pin_workaround) { 2389 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, 2390 ar->hw_params.uart_pin); 2391 if (ret) { 2392 ath10k_warn(ar, "failed to set UART TX pin: %d", 2393 ret); 2394 return ret; 2395 } 2396 } 2397 2398 return 0; 2399 } 2400 2401 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); 2402 if (ret) { 2403 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2404 return ret; 2405 } 2406 2407 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); 2408 if (ret) { 2409 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2410 return ret; 2411 } 2412 2413 /* Set the UART baud rate to 19200. */ 2414 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); 2415 if (ret) { 2416 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); 2417 return ret; 2418 } 2419 2420 ath10k_info(ar, "UART prints enabled\n"); 2421 return 0; 2422 } 2423 2424 static int ath10k_init_hw_params(struct ath10k *ar) 2425 { 2426 const struct ath10k_hw_params *hw_params; 2427 int i; 2428 2429 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { 2430 hw_params = &ath10k_hw_params_list[i]; 2431 2432 if (hw_params->bus == ar->hif.bus && 2433 hw_params->id == ar->target_version && 2434 hw_params->dev_id == ar->dev_id) 2435 break; 2436 } 2437 2438 if (i == ARRAY_SIZE(ath10k_hw_params_list)) { 2439 ath10k_err(ar, "Unsupported hardware version: 0x%x\n", 2440 ar->target_version); 2441 return -EINVAL; 2442 } 2443 2444 ar->hw_params = *hw_params; 2445 2446 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", 2447 ar->hw_params.name, ar->target_version); 2448 2449 return 0; 2450 } 2451 2452 void ath10k_core_start_recovery(struct ath10k *ar) 2453 { 2454 if (test_and_set_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags)) { 2455 ath10k_warn(ar, "already restarting\n"); 2456 return; 2457 } 2458 2459 queue_work(ar->workqueue, &ar->restart_work); 2460 } 2461 EXPORT_SYMBOL(ath10k_core_start_recovery); 2462 2463 void ath10k_core_napi_enable(struct ath10k *ar) 2464 { 2465 lockdep_assert_held(&ar->conf_mutex); 2466 2467 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2468 return; 2469 2470 napi_enable(&ar->napi); 2471 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2472 } 2473 EXPORT_SYMBOL(ath10k_core_napi_enable); 2474 2475 void ath10k_core_napi_sync_disable(struct ath10k *ar) 2476 { 2477 lockdep_assert_held(&ar->conf_mutex); 2478 2479 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2480 return; 2481 2482 napi_synchronize(&ar->napi); 2483 napi_disable(&ar->napi); 2484 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2485 } 2486 EXPORT_SYMBOL(ath10k_core_napi_sync_disable); 2487 2488 static void ath10k_core_restart(struct work_struct *work) 2489 { 2490 struct ath10k *ar = container_of(work, struct ath10k, restart_work); 2491 struct ath10k_vif *arvif; 2492 int ret; 2493 2494 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2495 2496 /* Place a barrier to make sure the compiler doesn't reorder 2497 * CRASH_FLUSH and calling other functions. 2498 */ 2499 barrier(); 2500 2501 ieee80211_stop_queues(ar->hw); 2502 ath10k_drain_tx(ar); 2503 complete(&ar->scan.started); 2504 complete(&ar->scan.completed); 2505 complete(&ar->scan.on_channel); 2506 complete(&ar->offchan_tx_completed); 2507 complete(&ar->install_key_done); 2508 complete(&ar->vdev_setup_done); 2509 complete(&ar->vdev_delete_done); 2510 complete(&ar->thermal.wmi_sync); 2511 complete(&ar->bss_survey_done); 2512 wake_up(&ar->htt.empty_tx_wq); 2513 wake_up(&ar->wmi.tx_credits_wq); 2514 wake_up(&ar->peer_mapping_wq); 2515 2516 /* TODO: We can have one instance of cancelling coverage_class_work by 2517 * moving it to ath10k_halt(), so that both stop() and restart() would 2518 * call that but it takes conf_mutex() and if we call cancel_work_sync() 2519 * with conf_mutex it will deadlock. 2520 */ 2521 cancel_work_sync(&ar->set_coverage_class_work); 2522 2523 mutex_lock(&ar->conf_mutex); 2524 2525 switch (ar->state) { 2526 case ATH10K_STATE_ON: 2527 ar->state = ATH10K_STATE_RESTARTING; 2528 ath10k_halt(ar); 2529 ath10k_scan_finish(ar); 2530 if (ar->hw_params.hw_restart_disconnect) { 2531 list_for_each_entry(arvif, &ar->arvifs, list) { 2532 if (arvif->is_up && 2533 arvif->vdev_type == WMI_VDEV_TYPE_STA) 2534 ieee80211_hw_restart_disconnect(arvif->vif); 2535 } 2536 } 2537 2538 ieee80211_restart_hw(ar->hw); 2539 break; 2540 case ATH10K_STATE_OFF: 2541 /* this can happen if driver is being unloaded 2542 * or if the crash happens during FW probing 2543 */ 2544 ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); 2545 break; 2546 case ATH10K_STATE_RESTARTING: 2547 /* hw restart might be requested from multiple places */ 2548 break; 2549 case ATH10K_STATE_RESTARTED: 2550 ar->state = ATH10K_STATE_WEDGED; 2551 fallthrough; 2552 case ATH10K_STATE_WEDGED: 2553 ath10k_warn(ar, "device is wedged, will not restart\n"); 2554 break; 2555 case ATH10K_STATE_UTF: 2556 ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); 2557 break; 2558 } 2559 2560 mutex_unlock(&ar->conf_mutex); 2561 2562 ret = ath10k_coredump_submit(ar); 2563 if (ret) 2564 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d", 2565 ret); 2566 2567 complete(&ar->driver_recovery); 2568 } 2569 2570 static void ath10k_core_set_coverage_class_work(struct work_struct *work) 2571 { 2572 struct ath10k *ar = container_of(work, struct ath10k, 2573 set_coverage_class_work); 2574 2575 if (ar->hw_params.hw_ops->set_coverage_class) 2576 ar->hw_params.hw_ops->set_coverage_class(ar, -1); 2577 } 2578 2579 static int ath10k_core_init_firmware_features(struct ath10k *ar) 2580 { 2581 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2582 int max_num_peers; 2583 2584 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) && 2585 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2586 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); 2587 return -EINVAL; 2588 } 2589 2590 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { 2591 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", 2592 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version); 2593 return -EINVAL; 2594 } 2595 2596 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 2597 switch (ath10k_cryptmode_param) { 2598 case ATH10K_CRYPT_MODE_HW: 2599 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2600 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2601 break; 2602 case ATH10K_CRYPT_MODE_SW: 2603 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2604 fw_file->fw_features)) { 2605 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); 2606 return -EINVAL; 2607 } 2608 2609 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2610 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2611 break; 2612 default: 2613 ath10k_info(ar, "invalid cryptmode: %d\n", 2614 ath10k_cryptmode_param); 2615 return -EINVAL; 2616 } 2617 2618 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT; 2619 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT; 2620 2621 if (ath10k_frame_mode == ATH10K_HW_TXRX_RAW) { 2622 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2623 fw_file->fw_features)) { 2624 ath10k_err(ar, "rawmode = 1 requires support from firmware"); 2625 return -EINVAL; 2626 } 2627 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2628 } 2629 2630 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 2631 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW; 2632 2633 /* Workaround: 2634 * 2635 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode 2636 * and causes enormous performance issues (malformed frames, 2637 * etc). 2638 * 2639 * Disabling A-MSDU makes RAW mode stable with heavy traffic 2640 * albeit a bit slower compared to regular operation. 2641 */ 2642 ar->htt.max_num_amsdu = 1; 2643 } 2644 2645 /* Backwards compatibility for firmwares without 2646 * ATH10K_FW_IE_WMI_OP_VERSION. 2647 */ 2648 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { 2649 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2650 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, 2651 fw_file->fw_features)) 2652 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2; 2653 else 2654 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; 2655 } else { 2656 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; 2657 } 2658 } 2659 2660 switch (fw_file->wmi_op_version) { 2661 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2662 max_num_peers = TARGET_NUM_PEERS; 2663 ar->max_num_stations = TARGET_NUM_STATIONS; 2664 ar->max_num_vdevs = TARGET_NUM_VDEVS; 2665 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; 2666 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | 2667 WMI_STAT_PEER; 2668 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2669 break; 2670 case ATH10K_FW_WMI_OP_VERSION_10_1: 2671 case ATH10K_FW_WMI_OP_VERSION_10_2: 2672 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2673 if (ath10k_peer_stats_enabled(ar)) { 2674 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS; 2675 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS; 2676 } else { 2677 max_num_peers = TARGET_10X_NUM_PEERS; 2678 ar->max_num_stations = TARGET_10X_NUM_STATIONS; 2679 } 2680 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; 2681 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; 2682 ar->fw_stats_req_mask = WMI_STAT_PEER; 2683 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2684 break; 2685 case ATH10K_FW_WMI_OP_VERSION_TLV: 2686 max_num_peers = TARGET_TLV_NUM_PEERS; 2687 ar->max_num_stations = TARGET_TLV_NUM_STATIONS; 2688 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; 2689 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; 2690 if (ar->hif.bus == ATH10K_BUS_SDIO) 2691 ar->htt.max_num_pending_tx = 2692 TARGET_TLV_NUM_MSDU_DESC_HL; 2693 else 2694 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; 2695 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; 2696 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV | 2697 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD; 2698 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2699 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC; 2700 break; 2701 case ATH10K_FW_WMI_OP_VERSION_10_4: 2702 max_num_peers = TARGET_10_4_NUM_PEERS; 2703 ar->max_num_stations = TARGET_10_4_NUM_STATIONS; 2704 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; 2705 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; 2706 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; 2707 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER | 2708 WMI_10_4_STAT_PEER_EXTD | 2709 WMI_10_4_STAT_VDEV_EXTD; 2710 ar->max_spatial_stream = ar->hw_params.max_spatial_stream; 2711 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS; 2712 2713 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 2714 fw_file->fw_features)) 2715 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC; 2716 else 2717 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; 2718 break; 2719 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2720 case ATH10K_FW_WMI_OP_VERSION_MAX: 2721 default: 2722 WARN_ON(1); 2723 return -EINVAL; 2724 } 2725 2726 if (ar->hw_params.num_peers) 2727 ar->max_num_peers = ar->hw_params.num_peers; 2728 else 2729 ar->max_num_peers = max_num_peers; 2730 2731 /* Backwards compatibility for firmwares without 2732 * ATH10K_FW_IE_HTT_OP_VERSION. 2733 */ 2734 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { 2735 switch (fw_file->wmi_op_version) { 2736 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2737 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; 2738 break; 2739 case ATH10K_FW_WMI_OP_VERSION_10_1: 2740 case ATH10K_FW_WMI_OP_VERSION_10_2: 2741 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2742 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; 2743 break; 2744 case ATH10K_FW_WMI_OP_VERSION_TLV: 2745 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; 2746 break; 2747 case ATH10K_FW_WMI_OP_VERSION_10_4: 2748 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2749 case ATH10K_FW_WMI_OP_VERSION_MAX: 2750 ath10k_err(ar, "htt op version not found from fw meta data"); 2751 return -EINVAL; 2752 } 2753 } 2754 2755 return 0; 2756 } 2757 2758 static int ath10k_core_reset_rx_filter(struct ath10k *ar) 2759 { 2760 int ret; 2761 int vdev_id; 2762 int vdev_type; 2763 int vdev_subtype; 2764 const u8 *vdev_addr; 2765 2766 vdev_id = 0; 2767 vdev_type = WMI_VDEV_TYPE_STA; 2768 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); 2769 vdev_addr = ar->mac_addr; 2770 2771 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype, 2772 vdev_addr); 2773 if (ret) { 2774 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret); 2775 return ret; 2776 } 2777 2778 ret = ath10k_wmi_vdev_delete(ar, vdev_id); 2779 if (ret) { 2780 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret); 2781 return ret; 2782 } 2783 2784 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be 2785 * serialized properly implicitly. 2786 * 2787 * Moreover (most) WMI commands have no explicit acknowledges. It is 2788 * possible to infer it implicitly by poking firmware with echo 2789 * command - getting a reply means all preceding comments have been 2790 * (mostly) processed. 2791 * 2792 * In case of vdev create/delete this is sufficient. 2793 * 2794 * Without this it's possible to end up with a race when HTT Rx ring is 2795 * started before vdev create/delete hack is complete allowing a short 2796 * window of opportunity to receive (and Tx ACK) a bunch of frames. 2797 */ 2798 ret = ath10k_wmi_barrier(ar); 2799 if (ret) { 2800 ath10k_err(ar, "failed to ping firmware: %d\n", ret); 2801 return ret; 2802 } 2803 2804 return 0; 2805 } 2806 2807 static int ath10k_core_compat_services(struct ath10k *ar) 2808 { 2809 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2810 2811 /* all 10.x firmware versions support thermal throttling but don't 2812 * advertise the support via service flags so we have to hardcode 2813 * it here 2814 */ 2815 switch (fw_file->wmi_op_version) { 2816 case ATH10K_FW_WMI_OP_VERSION_10_1: 2817 case ATH10K_FW_WMI_OP_VERSION_10_2: 2818 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2819 case ATH10K_FW_WMI_OP_VERSION_10_4: 2820 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map); 2821 break; 2822 default: 2823 break; 2824 } 2825 2826 return 0; 2827 } 2828 2829 #define TGT_IRAM_READ_PER_ITR (8 * 1024) 2830 2831 static int ath10k_core_copy_target_iram(struct ath10k *ar) 2832 { 2833 const struct ath10k_hw_mem_layout *hw_mem; 2834 const struct ath10k_mem_region *tmp, *mem_region = NULL; 2835 dma_addr_t paddr; 2836 void *vaddr = NULL; 2837 u8 num_read_itr; 2838 int i, ret; 2839 u32 len, remaining_len; 2840 2841 /* copy target iram feature must work also when 2842 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so 2843 * _ath10k_coredump_get_mem_layout() to accomplist that 2844 */ 2845 hw_mem = _ath10k_coredump_get_mem_layout(ar); 2846 if (!hw_mem) 2847 /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then 2848 * just silently disable the feature by doing nothing 2849 */ 2850 return 0; 2851 2852 for (i = 0; i < hw_mem->region_table.size; i++) { 2853 tmp = &hw_mem->region_table.regions[i]; 2854 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) { 2855 mem_region = tmp; 2856 break; 2857 } 2858 } 2859 2860 if (!mem_region) 2861 return -ENOMEM; 2862 2863 for (i = 0; i < ar->wmi.num_mem_chunks; i++) { 2864 if (ar->wmi.mem_chunks[i].req_id == 2865 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) { 2866 vaddr = ar->wmi.mem_chunks[i].vaddr; 2867 len = ar->wmi.mem_chunks[i].len; 2868 break; 2869 } 2870 } 2871 2872 if (!vaddr || !len) { 2873 ath10k_warn(ar, "No allocated memory for IRAM back up"); 2874 return -ENOMEM; 2875 } 2876 2877 len = (len < mem_region->len) ? len : mem_region->len; 2878 paddr = mem_region->start; 2879 num_read_itr = len / TGT_IRAM_READ_PER_ITR; 2880 remaining_len = len % TGT_IRAM_READ_PER_ITR; 2881 for (i = 0; i < num_read_itr; i++) { 2882 ret = ath10k_hif_diag_read(ar, paddr, vaddr, 2883 TGT_IRAM_READ_PER_ITR); 2884 if (ret) { 2885 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2886 ret); 2887 return ret; 2888 } 2889 2890 paddr += TGT_IRAM_READ_PER_ITR; 2891 vaddr += TGT_IRAM_READ_PER_ITR; 2892 } 2893 2894 if (remaining_len) { 2895 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len); 2896 if (ret) { 2897 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2898 ret); 2899 return ret; 2900 } 2901 } 2902 2903 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n"); 2904 2905 return 0; 2906 } 2907 2908 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, 2909 const struct ath10k_fw_components *fw) 2910 { 2911 int status; 2912 u32 val; 2913 2914 lockdep_assert_held(&ar->conf_mutex); 2915 2916 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2917 2918 ar->running_fw = fw; 2919 2920 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2921 ar->running_fw->fw_file.fw_features)) { 2922 ath10k_bmi_start(ar); 2923 2924 /* Enable hardware clock to speed up firmware download */ 2925 if (ar->hw_params.hw_ops->enable_pll_clk) { 2926 status = ar->hw_params.hw_ops->enable_pll_clk(ar); 2927 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n", 2928 status); 2929 } 2930 2931 if (ath10k_init_configure_target(ar)) { 2932 status = -EINVAL; 2933 goto err; 2934 } 2935 2936 status = ath10k_download_cal_data(ar); 2937 if (status) 2938 goto err; 2939 2940 /* Some of qca988x solutions are having global reset issue 2941 * during target initialization. Bypassing PLL setting before 2942 * downloading firmware and letting the SoC run on REF_CLK is 2943 * fixing the problem. Corresponding firmware change is also 2944 * needed to set the clock source once the target is 2945 * initialized. 2946 */ 2947 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, 2948 ar->running_fw->fw_file.fw_features)) { 2949 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); 2950 if (status) { 2951 ath10k_err(ar, "could not write to skip_clock_init: %d\n", 2952 status); 2953 goto err; 2954 } 2955 } 2956 2957 status = ath10k_download_fw(ar); 2958 if (status) 2959 goto err; 2960 2961 status = ath10k_init_uart(ar); 2962 if (status) 2963 goto err; 2964 2965 if (ar->hif.bus == ATH10K_BUS_SDIO) { 2966 status = ath10k_init_sdio(ar, mode); 2967 if (status) { 2968 ath10k_err(ar, "failed to init SDIO: %d\n", status); 2969 goto err; 2970 } 2971 } 2972 } 2973 2974 ar->htc.htc_ops.target_send_suspend_complete = 2975 ath10k_send_suspend_complete; 2976 2977 status = ath10k_htc_init(ar); 2978 if (status) { 2979 ath10k_err(ar, "could not init HTC (%d)\n", status); 2980 goto err; 2981 } 2982 2983 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2984 ar->running_fw->fw_file.fw_features)) { 2985 status = ath10k_bmi_done(ar); 2986 if (status) 2987 goto err; 2988 } 2989 2990 status = ath10k_wmi_attach(ar); 2991 if (status) { 2992 ath10k_err(ar, "WMI attach failed: %d\n", status); 2993 goto err; 2994 } 2995 2996 status = ath10k_htt_init(ar); 2997 if (status) { 2998 ath10k_err(ar, "failed to init htt: %d\n", status); 2999 goto err_wmi_detach; 3000 } 3001 3002 status = ath10k_htt_tx_start(&ar->htt); 3003 if (status) { 3004 ath10k_err(ar, "failed to alloc htt tx: %d\n", status); 3005 goto err_wmi_detach; 3006 } 3007 3008 /* If firmware indicates Full Rx Reorder support it must be used in a 3009 * slightly different manner. Let HTT code know. 3010 */ 3011 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, 3012 ar->wmi.svc_map)); 3013 3014 status = ath10k_htt_rx_alloc(&ar->htt); 3015 if (status) { 3016 ath10k_err(ar, "failed to alloc htt rx: %d\n", status); 3017 goto err_htt_tx_detach; 3018 } 3019 3020 status = ath10k_hif_start(ar); 3021 if (status) { 3022 ath10k_err(ar, "could not start HIF: %d\n", status); 3023 goto err_htt_rx_detach; 3024 } 3025 3026 status = ath10k_htc_wait_target(&ar->htc); 3027 if (status) { 3028 ath10k_err(ar, "failed to connect to HTC: %d\n", status); 3029 goto err_hif_stop; 3030 } 3031 3032 status = ath10k_hif_start_post(ar); 3033 if (status) { 3034 ath10k_err(ar, "failed to swap mailbox: %d\n", status); 3035 goto err_hif_stop; 3036 } 3037 3038 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3039 status = ath10k_htt_connect(&ar->htt); 3040 if (status) { 3041 ath10k_err(ar, "failed to connect htt (%d)\n", status); 3042 goto err_hif_stop; 3043 } 3044 } 3045 3046 status = ath10k_wmi_connect(ar); 3047 if (status) { 3048 ath10k_err(ar, "could not connect wmi: %d\n", status); 3049 goto err_hif_stop; 3050 } 3051 3052 status = ath10k_htc_start(&ar->htc); 3053 if (status) { 3054 ath10k_err(ar, "failed to start htc: %d\n", status); 3055 goto err_hif_stop; 3056 } 3057 3058 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3059 status = ath10k_wmi_wait_for_service_ready(ar); 3060 if (status) { 3061 ath10k_warn(ar, "wmi service ready event not received"); 3062 goto err_hif_stop; 3063 } 3064 } 3065 3066 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", 3067 ar->hw->wiphy->fw_version); 3068 3069 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY, 3070 ar->running_fw->fw_file.fw_features)) { 3071 status = ath10k_core_copy_target_iram(ar); 3072 if (status) { 3073 ath10k_warn(ar, "failed to copy target iram contents: %d", 3074 status); 3075 goto err_hif_stop; 3076 } 3077 } 3078 3079 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) && 3080 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3081 val = 0; 3082 if (ath10k_peer_stats_enabled(ar)) 3083 val = WMI_10_4_PEER_STATS; 3084 3085 /* Enable vdev stats by default */ 3086 val |= WMI_10_4_VDEV_STATS; 3087 3088 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) 3089 val |= WMI_10_4_BSS_CHANNEL_INFO_64; 3090 3091 ath10k_core_fetch_btcoex_dt(ar); 3092 3093 /* 10.4 firmware supports BT-Coex without reloading firmware 3094 * via pdev param. To support Bluetooth coexistence pdev param, 3095 * WMI_COEX_GPIO_SUPPORT of extended resource config should be 3096 * enabled always. 3097 * 3098 * We can still enable BTCOEX if firmware has the support 3099 * even though btceox_support value is 3100 * ATH10K_DT_BTCOEX_NOT_FOUND 3101 */ 3102 3103 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && 3104 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, 3105 ar->running_fw->fw_file.fw_features) && 3106 ar->coex_support) 3107 val |= WMI_10_4_COEX_GPIO_SUPPORT; 3108 3109 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY, 3110 ar->wmi.svc_map)) 3111 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY; 3112 3113 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA, 3114 ar->wmi.svc_map)) 3115 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA; 3116 3117 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI, 3118 ar->wmi.svc_map)) 3119 val |= WMI_10_4_TX_DATA_ACK_RSSI; 3120 3121 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map)) 3122 val |= WMI_10_4_REPORT_AIRTIME; 3123 3124 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT, 3125 ar->wmi.svc_map)) 3126 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT; 3127 3128 status = ath10k_mac_ext_resource_config(ar, val); 3129 if (status) { 3130 ath10k_err(ar, 3131 "failed to send ext resource cfg command : %d\n", 3132 status); 3133 goto err_hif_stop; 3134 } 3135 } 3136 3137 status = ath10k_wmi_cmd_init(ar); 3138 if (status) { 3139 ath10k_err(ar, "could not send WMI init command (%d)\n", 3140 status); 3141 goto err_hif_stop; 3142 } 3143 3144 status = ath10k_wmi_wait_for_unified_ready(ar); 3145 if (status) { 3146 ath10k_err(ar, "wmi unified ready event not received\n"); 3147 goto err_hif_stop; 3148 } 3149 3150 status = ath10k_core_compat_services(ar); 3151 if (status) { 3152 ath10k_err(ar, "compat services failed: %d\n", status); 3153 goto err_hif_stop; 3154 } 3155 3156 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr); 3157 if (status && status != -EOPNOTSUPP) { 3158 ath10k_err(ar, 3159 "failed to set base mac address: %d\n", status); 3160 goto err_hif_stop; 3161 } 3162 3163 /* Some firmware revisions do not properly set up hardware rx filter 3164 * registers. 3165 * 3166 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK 3167 * is filled with 0s instead of 1s allowing HW to respond with ACKs to 3168 * any frames that matches MAC_PCU_RX_FILTER which is also 3169 * misconfigured to accept anything. 3170 * 3171 * The ADDR1 is programmed using internal firmware structure field and 3172 * can't be (easily/sanely) reached from the driver explicitly. It is 3173 * possible to implicitly make it correct by creating a dummy vdev and 3174 * then deleting it. 3175 */ 3176 if (ar->hw_params.hw_filter_reset_required && 3177 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3178 status = ath10k_core_reset_rx_filter(ar); 3179 if (status) { 3180 ath10k_err(ar, 3181 "failed to reset rx filter: %d\n", status); 3182 goto err_hif_stop; 3183 } 3184 } 3185 3186 status = ath10k_htt_rx_ring_refill(ar); 3187 if (status) { 3188 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); 3189 goto err_hif_stop; 3190 } 3191 3192 if (ar->max_num_vdevs >= 64) 3193 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL; 3194 else 3195 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; 3196 3197 INIT_LIST_HEAD(&ar->arvifs); 3198 3199 /* we don't care about HTT in UTF mode */ 3200 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3201 status = ath10k_htt_setup(&ar->htt); 3202 if (status) { 3203 ath10k_err(ar, "failed to setup htt: %d\n", status); 3204 goto err_hif_stop; 3205 } 3206 } 3207 3208 status = ath10k_debug_start(ar); 3209 if (status) 3210 goto err_hif_stop; 3211 3212 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log); 3213 if (status && status != -EOPNOTSUPP) { 3214 ath10k_warn(ar, "set target log mode failed: %d\n", status); 3215 goto err_hif_stop; 3216 } 3217 3218 return 0; 3219 3220 err_hif_stop: 3221 ath10k_hif_stop(ar); 3222 err_htt_rx_detach: 3223 ath10k_htt_rx_free(&ar->htt); 3224 err_htt_tx_detach: 3225 ath10k_htt_tx_free(&ar->htt); 3226 err_wmi_detach: 3227 ath10k_wmi_detach(ar); 3228 err: 3229 return status; 3230 } 3231 EXPORT_SYMBOL(ath10k_core_start); 3232 3233 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) 3234 { 3235 int ret; 3236 unsigned long time_left; 3237 3238 reinit_completion(&ar->target_suspend); 3239 3240 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); 3241 if (ret) { 3242 ath10k_warn(ar, "could not suspend target (%d)\n", ret); 3243 return ret; 3244 } 3245 3246 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); 3247 3248 if (!time_left) { 3249 ath10k_warn(ar, "suspend timed out - target pause event never came\n"); 3250 return -ETIMEDOUT; 3251 } 3252 3253 return 0; 3254 } 3255 3256 void ath10k_core_stop(struct ath10k *ar) 3257 { 3258 lockdep_assert_held(&ar->conf_mutex); 3259 ath10k_debug_stop(ar); 3260 3261 /* try to suspend target */ 3262 if (ar->state != ATH10K_STATE_RESTARTING && 3263 ar->state != ATH10K_STATE_UTF) 3264 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); 3265 3266 ath10k_hif_stop(ar); 3267 ath10k_htt_tx_stop(&ar->htt); 3268 ath10k_htt_rx_free(&ar->htt); 3269 ath10k_wmi_detach(ar); 3270 3271 ar->id.bmi_ids_valid = false; 3272 } 3273 EXPORT_SYMBOL(ath10k_core_stop); 3274 3275 /* mac80211 manages fw/hw initialization through start/stop hooks. However in 3276 * order to know what hw capabilities should be advertised to mac80211 it is 3277 * necessary to load the firmware (and tear it down immediately since start 3278 * hook will try to init it again) before registering 3279 */ 3280 static int ath10k_core_probe_fw(struct ath10k *ar) 3281 { 3282 struct bmi_target_info target_info; 3283 int ret = 0; 3284 3285 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); 3286 if (ret) { 3287 ath10k_err(ar, "could not power on hif bus (%d)\n", ret); 3288 return ret; 3289 } 3290 3291 switch (ar->hif.bus) { 3292 case ATH10K_BUS_SDIO: 3293 memset(&target_info, 0, sizeof(target_info)); 3294 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info); 3295 if (ret) { 3296 ath10k_err(ar, "could not get target info (%d)\n", ret); 3297 goto err_power_down; 3298 } 3299 ar->target_version = target_info.version; 3300 ar->hw->wiphy->hw_version = target_info.version; 3301 break; 3302 case ATH10K_BUS_PCI: 3303 case ATH10K_BUS_AHB: 3304 case ATH10K_BUS_USB: 3305 memset(&target_info, 0, sizeof(target_info)); 3306 ret = ath10k_bmi_get_target_info(ar, &target_info); 3307 if (ret) { 3308 ath10k_err(ar, "could not get target info (%d)\n", ret); 3309 goto err_power_down; 3310 } 3311 ar->target_version = target_info.version; 3312 ar->hw->wiphy->hw_version = target_info.version; 3313 break; 3314 case ATH10K_BUS_SNOC: 3315 memset(&target_info, 0, sizeof(target_info)); 3316 ret = ath10k_hif_get_target_info(ar, &target_info); 3317 if (ret) { 3318 ath10k_err(ar, "could not get target info (%d)\n", ret); 3319 goto err_power_down; 3320 } 3321 ar->target_version = target_info.version; 3322 ar->hw->wiphy->hw_version = target_info.version; 3323 break; 3324 default: 3325 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus); 3326 } 3327 3328 ret = ath10k_init_hw_params(ar); 3329 if (ret) { 3330 ath10k_err(ar, "could not get hw params (%d)\n", ret); 3331 goto err_power_down; 3332 } 3333 3334 ret = ath10k_core_fetch_firmware_files(ar); 3335 if (ret) { 3336 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); 3337 goto err_power_down; 3338 } 3339 3340 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) != 3341 sizeof(ar->normal_mode_fw.fw_file.fw_version)); 3342 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version, 3343 sizeof(ar->hw->wiphy->fw_version)); 3344 3345 ath10k_debug_print_hwfw_info(ar); 3346 3347 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3348 ar->normal_mode_fw.fw_file.fw_features)) { 3349 ret = ath10k_core_pre_cal_download(ar); 3350 if (ret) { 3351 /* pre calibration data download is not necessary 3352 * for all the chipsets. Ignore failures and continue. 3353 */ 3354 ath10k_dbg(ar, ATH10K_DBG_BOOT, 3355 "could not load pre cal data: %d\n", ret); 3356 } 3357 3358 ret = ath10k_core_get_board_id_from_otp(ar); 3359 if (ret && ret != -EOPNOTSUPP) { 3360 ath10k_err(ar, "failed to get board id from otp: %d\n", 3361 ret); 3362 goto err_free_firmware_files; 3363 } 3364 3365 ret = ath10k_core_check_smbios(ar); 3366 if (ret) 3367 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n"); 3368 3369 ret = ath10k_core_check_dt(ar); 3370 if (ret) 3371 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n"); 3372 3373 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD); 3374 if (ret) { 3375 ath10k_err(ar, "failed to fetch board file: %d\n", ret); 3376 goto err_free_firmware_files; 3377 } 3378 3379 ath10k_debug_print_board_info(ar); 3380 } 3381 3382 device_get_mac_address(ar->dev, ar->mac_addr); 3383 3384 ret = ath10k_core_init_firmware_features(ar); 3385 if (ret) { 3386 ath10k_err(ar, "fatal problem with firmware features: %d\n", 3387 ret); 3388 goto err_free_firmware_files; 3389 } 3390 3391 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3392 ar->normal_mode_fw.fw_file.fw_features)) { 3393 ret = ath10k_swap_code_seg_init(ar, 3394 &ar->normal_mode_fw.fw_file); 3395 if (ret) { 3396 ath10k_err(ar, "failed to initialize code swap segment: %d\n", 3397 ret); 3398 goto err_free_firmware_files; 3399 } 3400 } 3401 3402 mutex_lock(&ar->conf_mutex); 3403 3404 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, 3405 &ar->normal_mode_fw); 3406 if (ret) { 3407 ath10k_err(ar, "could not init core (%d)\n", ret); 3408 goto err_unlock; 3409 } 3410 3411 ath10k_debug_print_boot_info(ar); 3412 ath10k_core_stop(ar); 3413 3414 mutex_unlock(&ar->conf_mutex); 3415 3416 ath10k_hif_power_down(ar); 3417 return 0; 3418 3419 err_unlock: 3420 mutex_unlock(&ar->conf_mutex); 3421 3422 err_free_firmware_files: 3423 ath10k_core_free_firmware_files(ar); 3424 3425 err_power_down: 3426 ath10k_hif_power_down(ar); 3427 3428 return ret; 3429 } 3430 3431 static void ath10k_core_register_work(struct work_struct *work) 3432 { 3433 struct ath10k *ar = container_of(work, struct ath10k, register_work); 3434 int status; 3435 3436 /* peer stats are enabled by default */ 3437 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); 3438 3439 status = ath10k_core_probe_fw(ar); 3440 if (status) { 3441 ath10k_err(ar, "could not probe fw (%d)\n", status); 3442 goto err; 3443 } 3444 3445 status = ath10k_mac_register(ar); 3446 if (status) { 3447 ath10k_err(ar, "could not register to mac80211 (%d)\n", status); 3448 goto err_release_fw; 3449 } 3450 3451 status = ath10k_coredump_register(ar); 3452 if (status) { 3453 ath10k_err(ar, "unable to register coredump\n"); 3454 goto err_unregister_mac; 3455 } 3456 3457 status = ath10k_debug_register(ar); 3458 if (status) { 3459 ath10k_err(ar, "unable to initialize debugfs\n"); 3460 goto err_unregister_coredump; 3461 } 3462 3463 status = ath10k_spectral_create(ar); 3464 if (status) { 3465 ath10k_err(ar, "failed to initialize spectral\n"); 3466 goto err_debug_destroy; 3467 } 3468 3469 status = ath10k_thermal_register(ar); 3470 if (status) { 3471 ath10k_err(ar, "could not register thermal device: %d\n", 3472 status); 3473 goto err_spectral_destroy; 3474 } 3475 3476 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); 3477 return; 3478 3479 err_spectral_destroy: 3480 ath10k_spectral_destroy(ar); 3481 err_debug_destroy: 3482 ath10k_debug_destroy(ar); 3483 err_unregister_coredump: 3484 ath10k_coredump_unregister(ar); 3485 err_unregister_mac: 3486 ath10k_mac_unregister(ar); 3487 err_release_fw: 3488 ath10k_core_free_firmware_files(ar); 3489 err: 3490 /* TODO: It's probably a good idea to release device from the driver 3491 * but calling device_release_driver() here will cause a deadlock. 3492 */ 3493 return; 3494 } 3495 3496 int ath10k_core_register(struct ath10k *ar, 3497 const struct ath10k_bus_params *bus_params) 3498 { 3499 ar->bus_param = *bus_params; 3500 3501 queue_work(ar->workqueue, &ar->register_work); 3502 3503 return 0; 3504 } 3505 EXPORT_SYMBOL(ath10k_core_register); 3506 3507 void ath10k_core_unregister(struct ath10k *ar) 3508 { 3509 cancel_work_sync(&ar->register_work); 3510 3511 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) 3512 return; 3513 3514 ath10k_thermal_unregister(ar); 3515 /* Stop spectral before unregistering from mac80211 to remove the 3516 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree 3517 * would be already be free'd recursively, leading to a double free. 3518 */ 3519 ath10k_spectral_destroy(ar); 3520 3521 /* We must unregister from mac80211 before we stop HTC and HIF. 3522 * Otherwise we will fail to submit commands to FW and mac80211 will be 3523 * unhappy about callback failures. 3524 */ 3525 ath10k_mac_unregister(ar); 3526 3527 ath10k_testmode_destroy(ar); 3528 3529 ath10k_core_free_firmware_files(ar); 3530 ath10k_core_free_board_files(ar); 3531 3532 ath10k_debug_unregister(ar); 3533 } 3534 EXPORT_SYMBOL(ath10k_core_unregister); 3535 3536 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, 3537 enum ath10k_bus bus, 3538 enum ath10k_hw_rev hw_rev, 3539 const struct ath10k_hif_ops *hif_ops) 3540 { 3541 struct ath10k *ar; 3542 int ret; 3543 3544 ar = ath10k_mac_create(priv_size); 3545 if (!ar) 3546 return NULL; 3547 3548 ar->ath_common.priv = ar; 3549 ar->ath_common.hw = ar->hw; 3550 ar->dev = dev; 3551 ar->hw_rev = hw_rev; 3552 ar->hif.ops = hif_ops; 3553 ar->hif.bus = bus; 3554 3555 switch (hw_rev) { 3556 case ATH10K_HW_QCA988X: 3557 case ATH10K_HW_QCA9887: 3558 ar->regs = &qca988x_regs; 3559 ar->hw_ce_regs = &qcax_ce_regs; 3560 ar->hw_values = &qca988x_values; 3561 break; 3562 case ATH10K_HW_QCA6174: 3563 case ATH10K_HW_QCA9377: 3564 ar->regs = &qca6174_regs; 3565 ar->hw_ce_regs = &qcax_ce_regs; 3566 ar->hw_values = &qca6174_values; 3567 break; 3568 case ATH10K_HW_QCA99X0: 3569 case ATH10K_HW_QCA9984: 3570 ar->regs = &qca99x0_regs; 3571 ar->hw_ce_regs = &qcax_ce_regs; 3572 ar->hw_values = &qca99x0_values; 3573 break; 3574 case ATH10K_HW_QCA9888: 3575 ar->regs = &qca99x0_regs; 3576 ar->hw_ce_regs = &qcax_ce_regs; 3577 ar->hw_values = &qca9888_values; 3578 break; 3579 case ATH10K_HW_QCA4019: 3580 ar->regs = &qca4019_regs; 3581 ar->hw_ce_regs = &qcax_ce_regs; 3582 ar->hw_values = &qca4019_values; 3583 break; 3584 case ATH10K_HW_WCN3990: 3585 ar->regs = &wcn3990_regs; 3586 ar->hw_ce_regs = &wcn3990_ce_regs; 3587 ar->hw_values = &wcn3990_values; 3588 break; 3589 default: 3590 ath10k_err(ar, "unsupported core hardware revision %d\n", 3591 hw_rev); 3592 ret = -ENOTSUPP; 3593 goto err_free_mac; 3594 } 3595 3596 init_completion(&ar->scan.started); 3597 init_completion(&ar->scan.completed); 3598 init_completion(&ar->scan.on_channel); 3599 init_completion(&ar->target_suspend); 3600 init_completion(&ar->driver_recovery); 3601 init_completion(&ar->wow.wakeup_completed); 3602 3603 init_completion(&ar->install_key_done); 3604 init_completion(&ar->vdev_setup_done); 3605 init_completion(&ar->vdev_delete_done); 3606 init_completion(&ar->thermal.wmi_sync); 3607 init_completion(&ar->bss_survey_done); 3608 init_completion(&ar->peer_delete_done); 3609 init_completion(&ar->peer_stats_info_complete); 3610 3611 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); 3612 3613 ar->workqueue = create_singlethread_workqueue("ath10k_wq"); 3614 if (!ar->workqueue) 3615 goto err_free_mac; 3616 3617 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq"); 3618 if (!ar->workqueue_aux) 3619 goto err_free_wq; 3620 3621 ar->workqueue_tx_complete = 3622 create_singlethread_workqueue("ath10k_tx_complete_wq"); 3623 if (!ar->workqueue_tx_complete) 3624 goto err_free_aux_wq; 3625 3626 mutex_init(&ar->conf_mutex); 3627 mutex_init(&ar->dump_mutex); 3628 spin_lock_init(&ar->data_lock); 3629 3630 INIT_LIST_HEAD(&ar->peers); 3631 init_waitqueue_head(&ar->peer_mapping_wq); 3632 init_waitqueue_head(&ar->htt.empty_tx_wq); 3633 init_waitqueue_head(&ar->wmi.tx_credits_wq); 3634 3635 skb_queue_head_init(&ar->htt.rx_indication_head); 3636 3637 init_completion(&ar->offchan_tx_completed); 3638 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); 3639 skb_queue_head_init(&ar->offchan_tx_queue); 3640 3641 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); 3642 skb_queue_head_init(&ar->wmi_mgmt_tx_queue); 3643 3644 INIT_WORK(&ar->register_work, ath10k_core_register_work); 3645 INIT_WORK(&ar->restart_work, ath10k_core_restart); 3646 INIT_WORK(&ar->set_coverage_class_work, 3647 ath10k_core_set_coverage_class_work); 3648 3649 init_dummy_netdev(&ar->napi_dev); 3650 3651 ret = ath10k_coredump_create(ar); 3652 if (ret) 3653 goto err_free_tx_complete; 3654 3655 ret = ath10k_debug_create(ar); 3656 if (ret) 3657 goto err_free_coredump; 3658 3659 return ar; 3660 3661 err_free_coredump: 3662 ath10k_coredump_destroy(ar); 3663 err_free_tx_complete: 3664 destroy_workqueue(ar->workqueue_tx_complete); 3665 err_free_aux_wq: 3666 destroy_workqueue(ar->workqueue_aux); 3667 err_free_wq: 3668 destroy_workqueue(ar->workqueue); 3669 err_free_mac: 3670 ath10k_mac_destroy(ar); 3671 3672 return NULL; 3673 } 3674 EXPORT_SYMBOL(ath10k_core_create); 3675 3676 void ath10k_core_destroy(struct ath10k *ar) 3677 { 3678 destroy_workqueue(ar->workqueue); 3679 3680 destroy_workqueue(ar->workqueue_aux); 3681 3682 destroy_workqueue(ar->workqueue_tx_complete); 3683 3684 ath10k_debug_destroy(ar); 3685 ath10k_coredump_destroy(ar); 3686 ath10k_htt_tx_destroy(&ar->htt); 3687 ath10k_wmi_free_host_mem(ar); 3688 ath10k_mac_destroy(ar); 3689 } 3690 EXPORT_SYMBOL(ath10k_core_destroy); 3691 3692 MODULE_AUTHOR("Qualcomm Atheros"); 3693 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards."); 3694 MODULE_LICENSE("Dual BSD/GPL"); 3695