1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _CE_H_ 20 #define _CE_H_ 21 22 #include "hif.h" 23 24 #define CE_HTT_H2T_MSG_SRC_NENTRIES 8192 25 26 /* Descriptor rings must be aligned to this boundary */ 27 #define CE_DESC_RING_ALIGN 8 28 #define CE_SEND_FLAG_GATHER 0x00010000 29 30 /* 31 * Copy Engine support: low-level Target-side Copy Engine API. 32 * This is a hardware access layer used by code that understands 33 * how to use copy engines. 34 */ 35 36 struct ath10k_ce_pipe; 37 38 #define CE_DESC_FLAGS_GATHER (1 << 0) 39 #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1) 40 #define CE_WCN3990_DESC_FLAGS_GATHER BIT(31) 41 42 #define CE_DESC_FLAGS_GET_MASK GENMASK(4, 0) 43 #define CE_DESC_37BIT_ADDR_MASK GENMASK_ULL(37, 0) 44 45 /* Following desc flags are used in QCA99X0 */ 46 #define CE_DESC_FLAGS_HOST_INT_DIS (1 << 2) 47 #define CE_DESC_FLAGS_TGT_INT_DIS (1 << 3) 48 49 #define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask 50 #define CE_DESC_FLAGS_META_DATA_LSB ar->hw_values->ce_desc_meta_data_lsb 51 52 #define CE_DDR_RRI_MASK GENMASK(15, 0) 53 #define CE_DDR_DRRI_SHIFT 16 54 55 struct ce_desc { 56 __le32 addr; 57 __le16 nbytes; 58 __le16 flags; /* %CE_DESC_FLAGS_ */ 59 }; 60 61 struct ce_desc_64 { 62 __le64 addr; 63 __le16 nbytes; /* length in register map */ 64 __le16 flags; /* fw_metadata_high */ 65 __le32 toeplitz_hash_result; 66 }; 67 68 #define CE_DESC_SIZE sizeof(struct ce_desc) 69 #define CE_DESC_SIZE_64 sizeof(struct ce_desc_64) 70 71 struct ath10k_ce_ring { 72 /* Number of entries in this ring; must be power of 2 */ 73 unsigned int nentries; 74 unsigned int nentries_mask; 75 76 /* 77 * For dest ring, this is the next index to be processed 78 * by software after it was/is received into. 79 * 80 * For src ring, this is the last descriptor that was sent 81 * and completion processed by software. 82 * 83 * Regardless of src or dest ring, this is an invariant 84 * (modulo ring size): 85 * write index >= read index >= sw_index 86 */ 87 unsigned int sw_index; 88 /* cached copy */ 89 unsigned int write_index; 90 /* 91 * For src ring, this is the next index not yet processed by HW. 92 * This is a cached copy of the real HW index (read index), used 93 * for avoiding reading the HW index register more often than 94 * necessary. 95 * This extends the invariant: 96 * write index >= read index >= hw_index >= sw_index 97 * 98 * For dest ring, this is currently unused. 99 */ 100 /* cached copy */ 101 unsigned int hw_index; 102 103 /* Start of DMA-coherent area reserved for descriptors */ 104 /* Host address space */ 105 void *base_addr_owner_space_unaligned; 106 /* CE address space */ 107 u32 base_addr_ce_space_unaligned; 108 109 /* 110 * Actual start of descriptors. 111 * Aligned to descriptor-size boundary. 112 * Points into reserved DMA-coherent area, above. 113 */ 114 /* Host address space */ 115 void *base_addr_owner_space; 116 117 /* CE address space */ 118 u32 base_addr_ce_space; 119 120 char *shadow_base_unaligned; 121 struct ce_desc *shadow_base; 122 123 /* keep last */ 124 void *per_transfer_context[0]; 125 }; 126 127 struct ath10k_ce_pipe { 128 struct ath10k *ar; 129 unsigned int id; 130 131 unsigned int attr_flags; 132 133 u32 ctrl_addr; 134 135 void (*send_cb)(struct ath10k_ce_pipe *); 136 void (*recv_cb)(struct ath10k_ce_pipe *); 137 138 unsigned int src_sz_max; 139 struct ath10k_ce_ring *src_ring; 140 struct ath10k_ce_ring *dest_ring; 141 const struct ath10k_ce_ops *ops; 142 }; 143 144 /* Copy Engine settable attributes */ 145 struct ce_attr; 146 147 struct ath10k_bus_ops { 148 u32 (*read32)(struct ath10k *ar, u32 offset); 149 void (*write32)(struct ath10k *ar, u32 offset, u32 value); 150 int (*get_num_banks)(struct ath10k *ar); 151 }; 152 153 static inline struct ath10k_ce *ath10k_ce_priv(struct ath10k *ar) 154 { 155 return (struct ath10k_ce *)ar->ce_priv; 156 } 157 158 struct ath10k_ce { 159 /* protects CE info */ 160 spinlock_t ce_lock; 161 const struct ath10k_bus_ops *bus_ops; 162 struct ath10k_ce_pipe ce_states[CE_COUNT_MAX]; 163 u32 *vaddr_rri; 164 dma_addr_t paddr_rri; 165 }; 166 167 /*==================Send====================*/ 168 169 /* ath10k_ce_send flags */ 170 #define CE_SEND_FLAG_BYTE_SWAP 1 171 172 /* 173 * Queue a source buffer to be sent to an anonymous destination buffer. 174 * ce - which copy engine to use 175 * buffer - address of buffer 176 * nbytes - number of bytes to send 177 * transfer_id - arbitrary ID; reflected to destination 178 * flags - CE_SEND_FLAG_* values 179 * Returns 0 on success; otherwise an error status. 180 * 181 * Note: If no flags are specified, use CE's default data swap mode. 182 * 183 * Implementation note: pushes 1 buffer to Source ring 184 */ 185 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, 186 void *per_transfer_send_context, 187 dma_addr_t buffer, 188 unsigned int nbytes, 189 /* 14 bits */ 190 unsigned int transfer_id, 191 unsigned int flags); 192 193 int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, 194 void *per_transfer_context, 195 dma_addr_t buffer, 196 unsigned int nbytes, 197 unsigned int transfer_id, 198 unsigned int flags); 199 200 void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe); 201 202 int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe); 203 204 /*==================Recv=======================*/ 205 206 int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe); 207 int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, 208 dma_addr_t paddr); 209 void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries); 210 211 /* recv flags */ 212 /* Data is byte-swapped */ 213 #define CE_RECV_FLAG_SWAPPED 1 214 215 /* 216 * Supply data for the next completed unprocessed receive descriptor. 217 * Pops buffer from Dest ring. 218 */ 219 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, 220 void **per_transfer_contextp, 221 unsigned int *nbytesp); 222 /* 223 * Supply data for the next completed unprocessed send descriptor. 224 * Pops 1 completed send buffer from Source ring. 225 */ 226 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, 227 void **per_transfer_contextp); 228 229 int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state, 230 void **per_transfer_contextp); 231 232 /*==================CE Engine Initialization=======================*/ 233 234 int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id, 235 const struct ce_attr *attr); 236 void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id); 237 int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, 238 const struct ce_attr *attr); 239 void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id); 240 241 /*==================CE Engine Shutdown=======================*/ 242 /* 243 * Support clean shutdown by allowing the caller to revoke 244 * receive buffers. Target DMA must be stopped before using 245 * this API. 246 */ 247 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 248 void **per_transfer_contextp, 249 dma_addr_t *bufferp); 250 251 int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state, 252 void **per_transfer_contextp, 253 unsigned int *nbytesp); 254 255 /* 256 * Support clean shutdown by allowing the caller to cancel 257 * pending sends. Target DMA must be stopped before using 258 * this API. 259 */ 260 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 261 void **per_transfer_contextp, 262 dma_addr_t *bufferp, 263 unsigned int *nbytesp, 264 unsigned int *transfer_idp); 265 266 /*==================CE Interrupt Handlers====================*/ 267 void ath10k_ce_per_engine_service_any(struct ath10k *ar); 268 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id); 269 int ath10k_ce_disable_interrupts(struct ath10k *ar); 270 void ath10k_ce_enable_interrupts(struct ath10k *ar); 271 void ath10k_ce_dump_registers(struct ath10k *ar, 272 struct ath10k_fw_crash_data *crash_data); 273 void ath10k_ce_alloc_rri(struct ath10k *ar); 274 void ath10k_ce_free_rri(struct ath10k *ar); 275 276 /* ce_attr.flags values */ 277 /* Use NonSnooping PCIe accesses? */ 278 #define CE_ATTR_NO_SNOOP 1 279 280 /* Byte swap data words */ 281 #define CE_ATTR_BYTE_SWAP_DATA 2 282 283 /* Swizzle descriptors? */ 284 #define CE_ATTR_SWIZZLE_DESCRIPTORS 4 285 286 /* no interrupt on copy completion */ 287 #define CE_ATTR_DIS_INTR 8 288 289 /* Attributes of an instance of a Copy Engine */ 290 struct ce_attr { 291 /* CE_ATTR_* values */ 292 unsigned int flags; 293 294 /* #entries in source ring - Must be a power of 2 */ 295 unsigned int src_nentries; 296 297 /* 298 * Max source send size for this CE. 299 * This is also the minimum size of a destination buffer. 300 */ 301 unsigned int src_sz_max; 302 303 /* #entries in destination ring - Must be a power of 2 */ 304 unsigned int dest_nentries; 305 306 void (*send_cb)(struct ath10k_ce_pipe *); 307 void (*recv_cb)(struct ath10k_ce_pipe *); 308 }; 309 310 struct ath10k_ce_ops { 311 struct ath10k_ce_ring *(*ce_alloc_src_ring)(struct ath10k *ar, 312 u32 ce_id, 313 const struct ce_attr *attr); 314 struct ath10k_ce_ring *(*ce_alloc_dst_ring)(struct ath10k *ar, 315 u32 ce_id, 316 const struct ce_attr *attr); 317 int (*ce_rx_post_buf)(struct ath10k_ce_pipe *pipe, void *ctx, 318 dma_addr_t paddr); 319 int (*ce_completed_recv_next_nolock)(struct ath10k_ce_pipe *ce_state, 320 void **per_transfer_contextp, 321 u32 *nbytesp); 322 int (*ce_revoke_recv_next)(struct ath10k_ce_pipe *ce_state, 323 void **per_transfer_contextp, 324 dma_addr_t *nbytesp); 325 void (*ce_extract_desc_data)(struct ath10k *ar, 326 struct ath10k_ce_ring *src_ring, 327 u32 sw_index, dma_addr_t *bufferp, 328 u32 *nbytesp, u32 *transfer_idp); 329 void (*ce_free_pipe)(struct ath10k *ar, int ce_id); 330 int (*ce_send_nolock)(struct ath10k_ce_pipe *pipe, 331 void *per_transfer_context, 332 dma_addr_t buffer, u32 nbytes, 333 u32 transfer_id, u32 flags); 334 }; 335 336 static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id) 337 { 338 return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id; 339 } 340 341 #define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) (((COPY_ENGINE_BASE_ADDRESS) \ 342 - CE0_BASE_ADDRESS) / (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS)) 343 344 #define CE_SRC_RING_TO_DESC(baddr, idx) \ 345 (&(((struct ce_desc *)baddr)[idx])) 346 347 #define CE_DEST_RING_TO_DESC(baddr, idx) \ 348 (&(((struct ce_desc *)baddr)[idx])) 349 350 #define CE_SRC_RING_TO_DESC_64(baddr, idx) \ 351 (&(((struct ce_desc_64 *)baddr)[idx])) 352 353 #define CE_DEST_RING_TO_DESC_64(baddr, idx) \ 354 (&(((struct ce_desc_64 *)baddr)[idx])) 355 356 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */ 357 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \ 358 (((int)(toidx) - (int)(fromidx)) & (nentries_mask)) 359 360 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 361 #define CE_RING_IDX_ADD(nentries_mask, idx, num) \ 362 (((idx) + (num)) & (nentries_mask)) 363 364 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ 365 ar->regs->ce_wrap_intr_sum_host_msi_lsb 366 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ 367 ar->regs->ce_wrap_intr_sum_host_msi_mask 368 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \ 369 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 370 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 371 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 372 #define CE_INTERRUPT_SUMMARY (GENMASK(CE_COUNT_MAX - 1, 0)) 373 374 static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar) 375 { 376 struct ath10k_ce *ce = ath10k_ce_priv(ar); 377 378 if (!ar->hw_params.per_ce_irq) 379 return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( 380 ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS + 381 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)); 382 else 383 return CE_INTERRUPT_SUMMARY; 384 } 385 386 #endif /* _CE_H_ */ 387