1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _CE_H_ 19 #define _CE_H_ 20 21 #include "hif.h" 22 23 #define CE_HTT_H2T_MSG_SRC_NENTRIES 8192 24 25 /* Descriptor rings must be aligned to this boundary */ 26 #define CE_DESC_RING_ALIGN 8 27 #define CE_SEND_FLAG_GATHER 0x00010000 28 29 /* 30 * Copy Engine support: low-level Target-side Copy Engine API. 31 * This is a hardware access layer used by code that understands 32 * how to use copy engines. 33 */ 34 35 struct ath10k_ce_pipe; 36 37 #define CE_DESC_FLAGS_GATHER (1 << 0) 38 #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1) 39 #define CE_WCN3990_DESC_FLAGS_GATHER BIT(31) 40 41 #define CE_DESC_FLAGS_GET_MASK GENMASK(4, 0) 42 #define CE_DESC_37BIT_ADDR_MASK GENMASK_ULL(37, 0) 43 44 /* Following desc flags are used in QCA99X0 */ 45 #define CE_DESC_FLAGS_HOST_INT_DIS (1 << 2) 46 #define CE_DESC_FLAGS_TGT_INT_DIS (1 << 3) 47 48 #define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask 49 #define CE_DESC_FLAGS_META_DATA_LSB ar->hw_values->ce_desc_meta_data_lsb 50 51 struct ce_desc { 52 __le32 addr; 53 __le16 nbytes; 54 __le16 flags; /* %CE_DESC_FLAGS_ */ 55 }; 56 57 struct ce_desc_64 { 58 __le64 addr; 59 __le16 nbytes; /* length in register map */ 60 __le16 flags; /* fw_metadata_high */ 61 __le32 toeplitz_hash_result; 62 }; 63 64 #define CE_DESC_SIZE sizeof(struct ce_desc) 65 #define CE_DESC_SIZE_64 sizeof(struct ce_desc_64) 66 67 struct ath10k_ce_ring { 68 /* Number of entries in this ring; must be power of 2 */ 69 unsigned int nentries; 70 unsigned int nentries_mask; 71 72 /* 73 * For dest ring, this is the next index to be processed 74 * by software after it was/is received into. 75 * 76 * For src ring, this is the last descriptor that was sent 77 * and completion processed by software. 78 * 79 * Regardless of src or dest ring, this is an invariant 80 * (modulo ring size): 81 * write index >= read index >= sw_index 82 */ 83 unsigned int sw_index; 84 /* cached copy */ 85 unsigned int write_index; 86 /* 87 * For src ring, this is the next index not yet processed by HW. 88 * This is a cached copy of the real HW index (read index), used 89 * for avoiding reading the HW index register more often than 90 * necessary. 91 * This extends the invariant: 92 * write index >= read index >= hw_index >= sw_index 93 * 94 * For dest ring, this is currently unused. 95 */ 96 /* cached copy */ 97 unsigned int hw_index; 98 99 /* Start of DMA-coherent area reserved for descriptors */ 100 /* Host address space */ 101 void *base_addr_owner_space_unaligned; 102 /* CE address space */ 103 u32 base_addr_ce_space_unaligned; 104 105 /* 106 * Actual start of descriptors. 107 * Aligned to descriptor-size boundary. 108 * Points into reserved DMA-coherent area, above. 109 */ 110 /* Host address space */ 111 void *base_addr_owner_space; 112 113 /* CE address space */ 114 u32 base_addr_ce_space; 115 116 /* keep last */ 117 void *per_transfer_context[0]; 118 }; 119 120 struct ath10k_ce_pipe { 121 struct ath10k *ar; 122 unsigned int id; 123 124 unsigned int attr_flags; 125 126 u32 ctrl_addr; 127 128 void (*send_cb)(struct ath10k_ce_pipe *); 129 void (*recv_cb)(struct ath10k_ce_pipe *); 130 131 unsigned int src_sz_max; 132 struct ath10k_ce_ring *src_ring; 133 struct ath10k_ce_ring *dest_ring; 134 const struct ath10k_ce_ops *ops; 135 }; 136 137 /* Copy Engine settable attributes */ 138 struct ce_attr; 139 140 struct ath10k_bus_ops { 141 u32 (*read32)(struct ath10k *ar, u32 offset); 142 void (*write32)(struct ath10k *ar, u32 offset, u32 value); 143 int (*get_num_banks)(struct ath10k *ar); 144 }; 145 146 static inline struct ath10k_ce *ath10k_ce_priv(struct ath10k *ar) 147 { 148 return (struct ath10k_ce *)ar->ce_priv; 149 } 150 151 struct ath10k_ce { 152 /* protects CE info */ 153 spinlock_t ce_lock; 154 const struct ath10k_bus_ops *bus_ops; 155 struct ath10k_ce_pipe ce_states[CE_COUNT_MAX]; 156 }; 157 158 /*==================Send====================*/ 159 160 /* ath10k_ce_send flags */ 161 #define CE_SEND_FLAG_BYTE_SWAP 1 162 163 /* 164 * Queue a source buffer to be sent to an anonymous destination buffer. 165 * ce - which copy engine to use 166 * buffer - address of buffer 167 * nbytes - number of bytes to send 168 * transfer_id - arbitrary ID; reflected to destination 169 * flags - CE_SEND_FLAG_* values 170 * Returns 0 on success; otherwise an error status. 171 * 172 * Note: If no flags are specified, use CE's default data swap mode. 173 * 174 * Implementation note: pushes 1 buffer to Source ring 175 */ 176 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, 177 void *per_transfer_send_context, 178 dma_addr_t buffer, 179 unsigned int nbytes, 180 /* 14 bits */ 181 unsigned int transfer_id, 182 unsigned int flags); 183 184 int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, 185 void *per_transfer_context, 186 dma_addr_t buffer, 187 unsigned int nbytes, 188 unsigned int transfer_id, 189 unsigned int flags); 190 191 void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe); 192 193 int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe); 194 195 /*==================Recv=======================*/ 196 197 int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe); 198 int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, 199 dma_addr_t paddr); 200 void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries); 201 202 /* recv flags */ 203 /* Data is byte-swapped */ 204 #define CE_RECV_FLAG_SWAPPED 1 205 206 /* 207 * Supply data for the next completed unprocessed receive descriptor. 208 * Pops buffer from Dest ring. 209 */ 210 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, 211 void **per_transfer_contextp, 212 unsigned int *nbytesp); 213 /* 214 * Supply data for the next completed unprocessed send descriptor. 215 * Pops 1 completed send buffer from Source ring. 216 */ 217 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, 218 void **per_transfer_contextp); 219 220 int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state, 221 void **per_transfer_contextp); 222 223 /*==================CE Engine Initialization=======================*/ 224 225 int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id, 226 const struct ce_attr *attr); 227 void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id); 228 int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, 229 const struct ce_attr *attr); 230 void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id); 231 232 /*==================CE Engine Shutdown=======================*/ 233 /* 234 * Support clean shutdown by allowing the caller to revoke 235 * receive buffers. Target DMA must be stopped before using 236 * this API. 237 */ 238 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 239 void **per_transfer_contextp, 240 dma_addr_t *bufferp); 241 242 int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state, 243 void **per_transfer_contextp, 244 unsigned int *nbytesp); 245 246 /* 247 * Support clean shutdown by allowing the caller to cancel 248 * pending sends. Target DMA must be stopped before using 249 * this API. 250 */ 251 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 252 void **per_transfer_contextp, 253 dma_addr_t *bufferp, 254 unsigned int *nbytesp, 255 unsigned int *transfer_idp); 256 257 /*==================CE Interrupt Handlers====================*/ 258 void ath10k_ce_per_engine_service_any(struct ath10k *ar); 259 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id); 260 int ath10k_ce_disable_interrupts(struct ath10k *ar); 261 void ath10k_ce_enable_interrupts(struct ath10k *ar); 262 void ath10k_ce_dump_registers(struct ath10k *ar, 263 struct ath10k_fw_crash_data *crash_data); 264 265 /* ce_attr.flags values */ 266 /* Use NonSnooping PCIe accesses? */ 267 #define CE_ATTR_NO_SNOOP 1 268 269 /* Byte swap data words */ 270 #define CE_ATTR_BYTE_SWAP_DATA 2 271 272 /* Swizzle descriptors? */ 273 #define CE_ATTR_SWIZZLE_DESCRIPTORS 4 274 275 /* no interrupt on copy completion */ 276 #define CE_ATTR_DIS_INTR 8 277 278 /* Attributes of an instance of a Copy Engine */ 279 struct ce_attr { 280 /* CE_ATTR_* values */ 281 unsigned int flags; 282 283 /* #entries in source ring - Must be a power of 2 */ 284 unsigned int src_nentries; 285 286 /* 287 * Max source send size for this CE. 288 * This is also the minimum size of a destination buffer. 289 */ 290 unsigned int src_sz_max; 291 292 /* #entries in destination ring - Must be a power of 2 */ 293 unsigned int dest_nentries; 294 295 void (*send_cb)(struct ath10k_ce_pipe *); 296 void (*recv_cb)(struct ath10k_ce_pipe *); 297 }; 298 299 struct ath10k_ce_ops { 300 struct ath10k_ce_ring *(*ce_alloc_src_ring)(struct ath10k *ar, 301 u32 ce_id, 302 const struct ce_attr *attr); 303 struct ath10k_ce_ring *(*ce_alloc_dst_ring)(struct ath10k *ar, 304 u32 ce_id, 305 const struct ce_attr *attr); 306 int (*ce_rx_post_buf)(struct ath10k_ce_pipe *pipe, void *ctx, 307 dma_addr_t paddr); 308 int (*ce_completed_recv_next_nolock)(struct ath10k_ce_pipe *ce_state, 309 void **per_transfer_contextp, 310 u32 *nbytesp); 311 int (*ce_revoke_recv_next)(struct ath10k_ce_pipe *ce_state, 312 void **per_transfer_contextp, 313 dma_addr_t *nbytesp); 314 void (*ce_extract_desc_data)(struct ath10k *ar, 315 struct ath10k_ce_ring *src_ring, 316 u32 sw_index, dma_addr_t *bufferp, 317 u32 *nbytesp, u32 *transfer_idp); 318 void (*ce_free_pipe)(struct ath10k *ar, int ce_id); 319 int (*ce_send_nolock)(struct ath10k_ce_pipe *pipe, 320 void *per_transfer_context, 321 dma_addr_t buffer, u32 nbytes, 322 u32 transfer_id, u32 flags); 323 }; 324 325 static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id) 326 { 327 return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id; 328 } 329 330 #define CE_SRC_RING_TO_DESC(baddr, idx) \ 331 (&(((struct ce_desc *)baddr)[idx])) 332 333 #define CE_DEST_RING_TO_DESC(baddr, idx) \ 334 (&(((struct ce_desc *)baddr)[idx])) 335 336 #define CE_SRC_RING_TO_DESC_64(baddr, idx) \ 337 (&(((struct ce_desc_64 *)baddr)[idx])) 338 339 #define CE_DEST_RING_TO_DESC_64(baddr, idx) \ 340 (&(((struct ce_desc_64 *)baddr)[idx])) 341 342 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */ 343 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \ 344 (((int)(toidx) - (int)(fromidx)) & (nentries_mask)) 345 346 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 347 #define CE_RING_IDX_ADD(nentries_mask, idx, num) \ 348 (((idx) + (num)) & (nentries_mask)) 349 350 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ 351 ar->regs->ce_wrap_intr_sum_host_msi_lsb 352 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ 353 ar->regs->ce_wrap_intr_sum_host_msi_mask 354 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \ 355 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 356 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 357 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 358 359 static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar) 360 { 361 struct ath10k_ce *ce = ath10k_ce_priv(ar); 362 363 return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( 364 ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS + 365 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)); 366 } 367 368 #endif /* _CE_H_ */ 369