1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _CE_H_ 19 #define _CE_H_ 20 21 #include "hif.h" 22 23 24 /* Maximum number of Copy Engine's supported */ 25 #define CE_COUNT_MAX 8 26 #define CE_HTT_H2T_MSG_SRC_NENTRIES 2048 27 28 /* Descriptor rings must be aligned to this boundary */ 29 #define CE_DESC_RING_ALIGN 8 30 #define CE_SEND_FLAG_GATHER 0x00010000 31 32 /* 33 * Copy Engine support: low-level Target-side Copy Engine API. 34 * This is a hardware access layer used by code that understands 35 * how to use copy engines. 36 */ 37 38 struct ath10k_ce_pipe; 39 40 41 #define CE_DESC_FLAGS_GATHER (1 << 0) 42 #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1) 43 #define CE_DESC_FLAGS_META_DATA_MASK 0xFFFC 44 #define CE_DESC_FLAGS_META_DATA_LSB 3 45 46 struct ce_desc { 47 __le32 addr; 48 __le16 nbytes; 49 __le16 flags; /* %CE_DESC_FLAGS_ */ 50 }; 51 52 struct ath10k_ce_ring { 53 /* Number of entries in this ring; must be power of 2 */ 54 unsigned int nentries; 55 unsigned int nentries_mask; 56 57 /* 58 * For dest ring, this is the next index to be processed 59 * by software after it was/is received into. 60 * 61 * For src ring, this is the last descriptor that was sent 62 * and completion processed by software. 63 * 64 * Regardless of src or dest ring, this is an invariant 65 * (modulo ring size): 66 * write index >= read index >= sw_index 67 */ 68 unsigned int sw_index; 69 /* cached copy */ 70 unsigned int write_index; 71 /* 72 * For src ring, this is the next index not yet processed by HW. 73 * This is a cached copy of the real HW index (read index), used 74 * for avoiding reading the HW index register more often than 75 * necessary. 76 * This extends the invariant: 77 * write index >= read index >= hw_index >= sw_index 78 * 79 * For dest ring, this is currently unused. 80 */ 81 /* cached copy */ 82 unsigned int hw_index; 83 84 /* Start of DMA-coherent area reserved for descriptors */ 85 /* Host address space */ 86 void *base_addr_owner_space_unaligned; 87 /* CE address space */ 88 u32 base_addr_ce_space_unaligned; 89 90 /* 91 * Actual start of descriptors. 92 * Aligned to descriptor-size boundary. 93 * Points into reserved DMA-coherent area, above. 94 */ 95 /* Host address space */ 96 void *base_addr_owner_space; 97 98 /* CE address space */ 99 u32 base_addr_ce_space; 100 /* 101 * Start of shadow copy of descriptors, within regular memory. 102 * Aligned to descriptor-size boundary. 103 */ 104 void *shadow_base_unaligned; 105 struct ce_desc *shadow_base; 106 107 void **per_transfer_context; 108 }; 109 110 struct ath10k_ce_pipe { 111 struct ath10k *ar; 112 unsigned int id; 113 114 unsigned int attr_flags; 115 116 u32 ctrl_addr; 117 118 void (*send_cb)(struct ath10k_ce_pipe *); 119 void (*recv_cb)(struct ath10k_ce_pipe *); 120 121 unsigned int src_sz_max; 122 struct ath10k_ce_ring *src_ring; 123 struct ath10k_ce_ring *dest_ring; 124 }; 125 126 /* Copy Engine settable attributes */ 127 struct ce_attr; 128 129 /*==================Send====================*/ 130 131 /* ath10k_ce_send flags */ 132 #define CE_SEND_FLAG_BYTE_SWAP 1 133 134 /* 135 * Queue a source buffer to be sent to an anonymous destination buffer. 136 * ce - which copy engine to use 137 * buffer - address of buffer 138 * nbytes - number of bytes to send 139 * transfer_id - arbitrary ID; reflected to destination 140 * flags - CE_SEND_FLAG_* values 141 * Returns 0 on success; otherwise an error status. 142 * 143 * Note: If no flags are specified, use CE's default data swap mode. 144 * 145 * Implementation note: pushes 1 buffer to Source ring 146 */ 147 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, 148 void *per_transfer_send_context, 149 u32 buffer, 150 unsigned int nbytes, 151 /* 14 bits */ 152 unsigned int transfer_id, 153 unsigned int flags); 154 155 void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state, 156 void (*send_cb)(struct ath10k_ce_pipe *), 157 int disable_interrupts); 158 159 int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe); 160 161 /*==================Recv=======================*/ 162 163 /* 164 * Make a buffer available to receive. The buffer must be at least of a 165 * minimal size appropriate for this copy engine (src_sz_max attribute). 166 * ce - which copy engine to use 167 * per_transfer_recv_context - context passed back to caller's recv_cb 168 * buffer - address of buffer in CE space 169 * Returns 0 on success; otherwise an error status. 170 * 171 * Implemenation note: Pushes a buffer to Dest ring. 172 */ 173 int ath10k_ce_recv_buf_enqueue(struct ath10k_ce_pipe *ce_state, 174 void *per_transfer_recv_context, 175 u32 buffer); 176 177 void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state, 178 void (*recv_cb)(struct ath10k_ce_pipe *)); 179 180 /* recv flags */ 181 /* Data is byte-swapped */ 182 #define CE_RECV_FLAG_SWAPPED 1 183 184 /* 185 * Supply data for the next completed unprocessed receive descriptor. 186 * Pops buffer from Dest ring. 187 */ 188 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, 189 void **per_transfer_contextp, 190 u32 *bufferp, 191 unsigned int *nbytesp, 192 unsigned int *transfer_idp, 193 unsigned int *flagsp); 194 /* 195 * Supply data for the next completed unprocessed send descriptor. 196 * Pops 1 completed send buffer from Source ring. 197 */ 198 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, 199 void **per_transfer_contextp, 200 u32 *bufferp, 201 unsigned int *nbytesp, 202 unsigned int *transfer_idp); 203 204 /*==================CE Engine Initialization=======================*/ 205 206 /* Initialize an instance of a CE */ 207 struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar, 208 unsigned int ce_id, 209 const struct ce_attr *attr); 210 211 /*==================CE Engine Shutdown=======================*/ 212 /* 213 * Support clean shutdown by allowing the caller to revoke 214 * receive buffers. Target DMA must be stopped before using 215 * this API. 216 */ 217 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 218 void **per_transfer_contextp, 219 u32 *bufferp); 220 221 /* 222 * Support clean shutdown by allowing the caller to cancel 223 * pending sends. Target DMA must be stopped before using 224 * this API. 225 */ 226 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 227 void **per_transfer_contextp, 228 u32 *bufferp, 229 unsigned int *nbytesp, 230 unsigned int *transfer_idp); 231 232 void ath10k_ce_deinit(struct ath10k_ce_pipe *ce_state); 233 234 /*==================CE Interrupt Handlers====================*/ 235 void ath10k_ce_per_engine_service_any(struct ath10k *ar); 236 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id); 237 void ath10k_ce_disable_interrupts(struct ath10k *ar); 238 239 /* ce_attr.flags values */ 240 /* Use NonSnooping PCIe accesses? */ 241 #define CE_ATTR_NO_SNOOP 1 242 243 /* Byte swap data words */ 244 #define CE_ATTR_BYTE_SWAP_DATA 2 245 246 /* Swizzle descriptors? */ 247 #define CE_ATTR_SWIZZLE_DESCRIPTORS 4 248 249 /* no interrupt on copy completion */ 250 #define CE_ATTR_DIS_INTR 8 251 252 /* Attributes of an instance of a Copy Engine */ 253 struct ce_attr { 254 /* CE_ATTR_* values */ 255 unsigned int flags; 256 257 /* #entries in source ring - Must be a power of 2 */ 258 unsigned int src_nentries; 259 260 /* 261 * Max source send size for this CE. 262 * This is also the minimum size of a destination buffer. 263 */ 264 unsigned int src_sz_max; 265 266 /* #entries in destination ring - Must be a power of 2 */ 267 unsigned int dest_nentries; 268 }; 269 270 #define SR_BA_ADDRESS 0x0000 271 #define SR_SIZE_ADDRESS 0x0004 272 #define DR_BA_ADDRESS 0x0008 273 #define DR_SIZE_ADDRESS 0x000c 274 #define CE_CMD_ADDRESS 0x0018 275 276 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17 277 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17 278 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000 279 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ 280 (((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ 281 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 282 283 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16 284 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16 285 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000 286 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \ 287 (((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \ 288 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) 289 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ 290 (((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ 291 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 292 293 #define CE_CTRL1_DMAX_LENGTH_MSB 15 294 #define CE_CTRL1_DMAX_LENGTH_LSB 0 295 #define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff 296 #define CE_CTRL1_DMAX_LENGTH_GET(x) \ 297 (((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB) 298 #define CE_CTRL1_DMAX_LENGTH_SET(x) \ 299 (((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) 300 301 #define CE_CTRL1_ADDRESS 0x0010 302 #define CE_CTRL1_HW_MASK 0x0007ffff 303 #define CE_CTRL1_SW_MASK 0x0007ffff 304 #define CE_CTRL1_HW_WRITE_MASK 0x00000000 305 #define CE_CTRL1_SW_WRITE_MASK 0x0007ffff 306 #define CE_CTRL1_RSTMASK 0xffffffff 307 #define CE_CTRL1_RESET 0x00000080 308 309 #define CE_CMD_HALT_STATUS_MSB 3 310 #define CE_CMD_HALT_STATUS_LSB 3 311 #define CE_CMD_HALT_STATUS_MASK 0x00000008 312 #define CE_CMD_HALT_STATUS_GET(x) \ 313 (((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB) 314 #define CE_CMD_HALT_STATUS_SET(x) \ 315 (((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK) 316 #define CE_CMD_HALT_STATUS_RESET 0 317 #define CE_CMD_HALT_MSB 0 318 #define CE_CMD_HALT_MASK 0x00000001 319 320 #define HOST_IE_COPY_COMPLETE_MSB 0 321 #define HOST_IE_COPY_COMPLETE_LSB 0 322 #define HOST_IE_COPY_COMPLETE_MASK 0x00000001 323 #define HOST_IE_COPY_COMPLETE_GET(x) \ 324 (((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB) 325 #define HOST_IE_COPY_COMPLETE_SET(x) \ 326 (((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK) 327 #define HOST_IE_COPY_COMPLETE_RESET 0 328 #define HOST_IE_ADDRESS 0x002c 329 330 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010 331 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008 332 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004 333 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002 334 #define HOST_IS_COPY_COMPLETE_MASK 0x00000001 335 #define HOST_IS_ADDRESS 0x0030 336 337 #define MISC_IE_ADDRESS 0x0034 338 339 #define MISC_IS_AXI_ERR_MASK 0x00000400 340 341 #define MISC_IS_DST_ADDR_ERR_MASK 0x00000200 342 #define MISC_IS_SRC_LEN_ERR_MASK 0x00000100 343 #define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080 344 #define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040 345 #define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020 346 347 #define MISC_IS_ADDRESS 0x0038 348 349 #define SR_WR_INDEX_ADDRESS 0x003c 350 351 #define DST_WR_INDEX_ADDRESS 0x0040 352 353 #define CURRENT_SRRI_ADDRESS 0x0044 354 355 #define CURRENT_DRRI_ADDRESS 0x0048 356 357 #define SRC_WATERMARK_LOW_MSB 31 358 #define SRC_WATERMARK_LOW_LSB 16 359 #define SRC_WATERMARK_LOW_MASK 0xffff0000 360 #define SRC_WATERMARK_LOW_GET(x) \ 361 (((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB) 362 #define SRC_WATERMARK_LOW_SET(x) \ 363 (((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) 364 #define SRC_WATERMARK_LOW_RESET 0 365 #define SRC_WATERMARK_HIGH_MSB 15 366 #define SRC_WATERMARK_HIGH_LSB 0 367 #define SRC_WATERMARK_HIGH_MASK 0x0000ffff 368 #define SRC_WATERMARK_HIGH_GET(x) \ 369 (((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB) 370 #define SRC_WATERMARK_HIGH_SET(x) \ 371 (((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) 372 #define SRC_WATERMARK_HIGH_RESET 0 373 #define SRC_WATERMARK_ADDRESS 0x004c 374 375 #define DST_WATERMARK_LOW_LSB 16 376 #define DST_WATERMARK_LOW_MASK 0xffff0000 377 #define DST_WATERMARK_LOW_SET(x) \ 378 (((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) 379 #define DST_WATERMARK_LOW_RESET 0 380 #define DST_WATERMARK_HIGH_MSB 15 381 #define DST_WATERMARK_HIGH_LSB 0 382 #define DST_WATERMARK_HIGH_MASK 0x0000ffff 383 #define DST_WATERMARK_HIGH_GET(x) \ 384 (((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB) 385 #define DST_WATERMARK_HIGH_SET(x) \ 386 (((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) 387 #define DST_WATERMARK_HIGH_RESET 0 388 #define DST_WATERMARK_ADDRESS 0x0050 389 390 391 static inline u32 ath10k_ce_base_address(unsigned int ce_id) 392 { 393 return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id; 394 } 395 396 #define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \ 397 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \ 398 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \ 399 HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 400 401 #define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \ 402 MISC_IS_DST_ADDR_ERR_MASK | \ 403 MISC_IS_SRC_LEN_ERR_MASK | \ 404 MISC_IS_DST_MAX_LEN_VIO_MASK | \ 405 MISC_IS_DST_RING_OVERFLOW_MASK | \ 406 MISC_IS_SRC_RING_OVERFLOW_MASK) 407 408 #define CE_SRC_RING_TO_DESC(baddr, idx) \ 409 (&(((struct ce_desc *)baddr)[idx])) 410 411 #define CE_DEST_RING_TO_DESC(baddr, idx) \ 412 (&(((struct ce_desc *)baddr)[idx])) 413 414 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */ 415 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \ 416 (((int)(toidx)-(int)(fromidx)) & (nentries_mask)) 417 418 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 419 420 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8 421 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00 422 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \ 423 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 424 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 425 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 426 427 #define CE_INTERRUPT_SUMMARY(ar) \ 428 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \ 429 ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \ 430 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)) 431 432 #endif /* _CE_H_ */ 433