xref: /openbmc/linux/drivers/net/wireless/ath/ath10k/bmi.h (revision 92a76f6d)
1 /*
2  * Copyright (c) 2005-2011 Atheros Communications Inc.
3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  */
17 
18 #ifndef _BMI_H_
19 #define _BMI_H_
20 
21 #include "core.h"
22 
23 /*
24  * Bootloader Messaging Interface (BMI)
25  *
26  * BMI is a very simple messaging interface used during initialization
27  * to read memory, write memory, execute code, and to define an
28  * application entry PC.
29  *
30  * It is used to download an application to QCA988x, to provide
31  * patches to code that is already resident on QCA988x, and generally
32  * to examine and modify state.  The Host has an opportunity to use
33  * BMI only once during bootup.  Once the Host issues a BMI_DONE
34  * command, this opportunity ends.
35  *
36  * The Host writes BMI requests to mailbox0, and reads BMI responses
37  * from mailbox0.   BMI requests all begin with a command
38  * (see below for specific commands), and are followed by
39  * command-specific data.
40  *
41  * Flow control:
42  * The Host can only issue a command once the Target gives it a
43  * "BMI Command Credit", using AR8K Counter #4.  As soon as the
44  * Target has completed a command, it issues another BMI Command
45  * Credit (so the Host can issue the next command).
46  *
47  * BMI handles all required Target-side cache flushing.
48  */
49 
50 /* Maximum data size used for BMI transfers */
51 #define BMI_MAX_DATA_SIZE	256
52 
53 /* len = cmd + addr + length */
54 #define BMI_MAX_CMDBUF_SIZE (BMI_MAX_DATA_SIZE + \
55 			sizeof(u32) + \
56 			sizeof(u32) + \
57 			sizeof(u32))
58 
59 /* BMI Commands */
60 
61 enum bmi_cmd_id {
62 	BMI_NO_COMMAND          = 0,
63 	BMI_DONE                = 1,
64 	BMI_READ_MEMORY         = 2,
65 	BMI_WRITE_MEMORY        = 3,
66 	BMI_EXECUTE             = 4,
67 	BMI_SET_APP_START       = 5,
68 	BMI_READ_SOC_REGISTER   = 6,
69 	BMI_READ_SOC_WORD       = 6,
70 	BMI_WRITE_SOC_REGISTER  = 7,
71 	BMI_WRITE_SOC_WORD      = 7,
72 	BMI_GET_TARGET_ID       = 8,
73 	BMI_GET_TARGET_INFO     = 8,
74 	BMI_ROMPATCH_INSTALL    = 9,
75 	BMI_ROMPATCH_UNINSTALL  = 10,
76 	BMI_ROMPATCH_ACTIVATE   = 11,
77 	BMI_ROMPATCH_DEACTIVATE = 12,
78 	BMI_LZ_STREAM_START     = 13, /* should be followed by LZ_DATA */
79 	BMI_LZ_DATA             = 14,
80 	BMI_NVRAM_PROCESS       = 15,
81 };
82 
83 #define BMI_NVRAM_SEG_NAME_SZ 16
84 
85 #define BMI_PARAM_GET_EEPROM_BOARD_ID 0x10
86 
87 #define ATH10K_BMI_BOARD_ID_FROM_OTP_MASK   0x7c00
88 #define ATH10K_BMI_BOARD_ID_FROM_OTP_LSB    10
89 
90 #define ATH10K_BMI_CHIP_ID_FROM_OTP_MASK    0x18000
91 #define ATH10K_BMI_CHIP_ID_FROM_OTP_LSB     15
92 
93 #define ATH10K_BMI_BOARD_ID_STATUS_MASK 0xff
94 
95 struct bmi_cmd {
96 	__le32 id; /* enum bmi_cmd_id */
97 	union {
98 		struct {
99 		} done;
100 		struct {
101 			__le32 addr;
102 			__le32 len;
103 		} read_mem;
104 		struct {
105 			__le32 addr;
106 			__le32 len;
107 			u8 payload[0];
108 		} write_mem;
109 		struct {
110 			__le32 addr;
111 			__le32 param;
112 		} execute;
113 		struct {
114 			__le32 addr;
115 		} set_app_start;
116 		struct {
117 			__le32 addr;
118 		} read_soc_reg;
119 		struct {
120 			__le32 addr;
121 			__le32 value;
122 		} write_soc_reg;
123 		struct {
124 		} get_target_info;
125 		struct {
126 			__le32 rom_addr;
127 			__le32 ram_addr; /* or value */
128 			__le32 size;
129 			__le32 activate; /* 0=install, but dont activate */
130 		} rompatch_install;
131 		struct {
132 			__le32 patch_id;
133 		} rompatch_uninstall;
134 		struct {
135 			__le32 count;
136 			__le32 patch_ids[0]; /* length of @count */
137 		} rompatch_activate;
138 		struct {
139 			__le32 count;
140 			__le32 patch_ids[0]; /* length of @count */
141 		} rompatch_deactivate;
142 		struct {
143 			__le32 addr;
144 		} lz_start;
145 		struct {
146 			__le32 len; /* max BMI_MAX_DATA_SIZE */
147 			u8 payload[0]; /* length of @len */
148 		} lz_data;
149 		struct {
150 			u8 name[BMI_NVRAM_SEG_NAME_SZ];
151 		} nvram_process;
152 		u8 payload[BMI_MAX_CMDBUF_SIZE];
153 	};
154 } __packed;
155 
156 union bmi_resp {
157 	struct {
158 		u8 payload[0];
159 	} read_mem;
160 	struct {
161 		__le32 result;
162 	} execute;
163 	struct {
164 		__le32 value;
165 	} read_soc_reg;
166 	struct {
167 		__le32 len;
168 		__le32 version;
169 		__le32 type;
170 	} get_target_info;
171 	struct {
172 		__le32 patch_id;
173 	} rompatch_install;
174 	struct {
175 		__le32 patch_id;
176 	} rompatch_uninstall;
177 	struct {
178 		/* 0 = nothing executed
179 		 * otherwise = NVRAM segment return value */
180 		__le32 result;
181 	} nvram_process;
182 	u8 payload[BMI_MAX_CMDBUF_SIZE];
183 } __packed;
184 
185 struct bmi_target_info {
186 	u32 version;
187 	u32 type;
188 };
189 
190 /* in msec */
191 #define BMI_COMMUNICATION_TIMEOUT_HZ (2 * HZ)
192 
193 #define BMI_CE_NUM_TO_TARG 0
194 #define BMI_CE_NUM_TO_HOST 1
195 
196 void ath10k_bmi_start(struct ath10k *ar);
197 int ath10k_bmi_done(struct ath10k *ar);
198 int ath10k_bmi_get_target_info(struct ath10k *ar,
199 			       struct bmi_target_info *target_info);
200 int ath10k_bmi_read_memory(struct ath10k *ar, u32 address,
201 			   void *buffer, u32 length);
202 int ath10k_bmi_write_memory(struct ath10k *ar, u32 address,
203 			    const void *buffer, u32 length);
204 
205 #define ath10k_bmi_read32(ar, item, val)				\
206 	({								\
207 		int ret;						\
208 		u32 addr;						\
209 		__le32 tmp;						\
210 									\
211 		addr = host_interest_item_address(HI_ITEM(item));	\
212 		ret = ath10k_bmi_read_memory(ar, addr, (u8 *)&tmp, 4); \
213 		if (!ret)						\
214 			*val = __le32_to_cpu(tmp);			\
215 		ret;							\
216 	 })
217 
218 #define ath10k_bmi_write32(ar, item, val)				\
219 	({								\
220 		int ret;						\
221 		u32 address;						\
222 		__le32 v = __cpu_to_le32(val);				\
223 									\
224 		address = host_interest_item_address(HI_ITEM(item));	\
225 		ret = ath10k_bmi_write_memory(ar, address,		\
226 					      (u8 *)&v, sizeof(v));	\
227 		ret;							\
228 	})
229 
230 int ath10k_bmi_execute(struct ath10k *ar, u32 address, u32 param, u32 *result);
231 int ath10k_bmi_lz_stream_start(struct ath10k *ar, u32 address);
232 int ath10k_bmi_lz_data(struct ath10k *ar, const void *buffer, u32 length);
233 int ath10k_bmi_fast_download(struct ath10k *ar, u32 address,
234 			     const void *buffer, u32 length);
235 #endif /* _BMI_H_ */
236