1 /* 2 * Copyright (c) 2016 Qualcomm Atheros, Inc. All rights reserved. 3 * Copyright (c) 2015 The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/clk.h> 21 #include <linux/reset.h> 22 #include "core.h" 23 #include "debug.h" 24 #include "pci.h" 25 #include "ahb.h" 26 27 static const struct of_device_id ath10k_ahb_of_match[] = { 28 { .compatible = "qcom,ipq4019-wifi", 29 .data = (void *)ATH10K_HW_QCA4019 30 }, 31 { } 32 }; 33 34 MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match); 35 36 #define QCA4019_SRAM_ADDR 0x000C0000 37 #define QCA4019_SRAM_LEN 0x00040000 /* 256 kb */ 38 39 static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar) 40 { 41 return &((struct ath10k_pci *)ar->drv_priv)->ahb[0]; 42 } 43 44 static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value) 45 { 46 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 47 48 iowrite32(value, ar_ahb->mem + offset); 49 } 50 51 static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset) 52 { 53 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 54 55 return ioread32(ar_ahb->mem + offset); 56 } 57 58 static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset) 59 { 60 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 61 62 return ioread32(ar_ahb->gcc_mem + offset); 63 } 64 65 static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value) 66 { 67 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 68 69 iowrite32(value, ar_ahb->tcsr_mem + offset); 70 } 71 72 static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset) 73 { 74 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 75 76 return ioread32(ar_ahb->tcsr_mem + offset); 77 } 78 79 static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr) 80 { 81 return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 82 } 83 84 static int ath10k_ahb_get_num_banks(struct ath10k *ar) 85 { 86 if (ar->hw_rev == ATH10K_HW_QCA4019) 87 return 1; 88 89 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 90 return 1; 91 } 92 93 static int ath10k_ahb_clock_init(struct ath10k *ar) 94 { 95 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 96 struct device *dev; 97 98 dev = &ar_ahb->pdev->dev; 99 100 ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd"); 101 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) { 102 ath10k_err(ar, "failed to get cmd clk: %ld\n", 103 PTR_ERR(ar_ahb->cmd_clk)); 104 return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV; 105 } 106 107 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref"); 108 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) { 109 ath10k_err(ar, "failed to get ref clk: %ld\n", 110 PTR_ERR(ar_ahb->ref_clk)); 111 return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV; 112 } 113 114 ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc"); 115 if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { 116 ath10k_err(ar, "failed to get rtc clk: %ld\n", 117 PTR_ERR(ar_ahb->rtc_clk)); 118 return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV; 119 } 120 121 return 0; 122 } 123 124 static void ath10k_ahb_clock_deinit(struct ath10k *ar) 125 { 126 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 127 128 ar_ahb->cmd_clk = NULL; 129 ar_ahb->ref_clk = NULL; 130 ar_ahb->rtc_clk = NULL; 131 } 132 133 static int ath10k_ahb_clock_enable(struct ath10k *ar) 134 { 135 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 136 struct device *dev; 137 int ret; 138 139 dev = &ar_ahb->pdev->dev; 140 141 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) || 142 IS_ERR_OR_NULL(ar_ahb->ref_clk) || 143 IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { 144 ath10k_err(ar, "clock(s) is/are not initialized\n"); 145 ret = -EIO; 146 goto out; 147 } 148 149 ret = clk_prepare_enable(ar_ahb->cmd_clk); 150 if (ret) { 151 ath10k_err(ar, "failed to enable cmd clk: %d\n", ret); 152 goto out; 153 } 154 155 ret = clk_prepare_enable(ar_ahb->ref_clk); 156 if (ret) { 157 ath10k_err(ar, "failed to enable ref clk: %d\n", ret); 158 goto err_cmd_clk_disable; 159 } 160 161 ret = clk_prepare_enable(ar_ahb->rtc_clk); 162 if (ret) { 163 ath10k_err(ar, "failed to enable rtc clk: %d\n", ret); 164 goto err_ref_clk_disable; 165 } 166 167 return 0; 168 169 err_ref_clk_disable: 170 clk_disable_unprepare(ar_ahb->ref_clk); 171 172 err_cmd_clk_disable: 173 clk_disable_unprepare(ar_ahb->cmd_clk); 174 175 out: 176 return ret; 177 } 178 179 static void ath10k_ahb_clock_disable(struct ath10k *ar) 180 { 181 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 182 183 if (!IS_ERR_OR_NULL(ar_ahb->cmd_clk)) 184 clk_disable_unprepare(ar_ahb->cmd_clk); 185 186 if (!IS_ERR_OR_NULL(ar_ahb->ref_clk)) 187 clk_disable_unprepare(ar_ahb->ref_clk); 188 189 if (!IS_ERR_OR_NULL(ar_ahb->rtc_clk)) 190 clk_disable_unprepare(ar_ahb->rtc_clk); 191 } 192 193 static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar) 194 { 195 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 196 struct device *dev; 197 198 dev = &ar_ahb->pdev->dev; 199 200 ar_ahb->core_cold_rst = devm_reset_control_get_exclusive(dev, 201 "wifi_core_cold"); 202 if (IS_ERR(ar_ahb->core_cold_rst)) { 203 ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n", 204 PTR_ERR(ar_ahb->core_cold_rst)); 205 return PTR_ERR(ar_ahb->core_cold_rst); 206 } 207 208 ar_ahb->radio_cold_rst = devm_reset_control_get_exclusive(dev, 209 "wifi_radio_cold"); 210 if (IS_ERR(ar_ahb->radio_cold_rst)) { 211 ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n", 212 PTR_ERR(ar_ahb->radio_cold_rst)); 213 return PTR_ERR(ar_ahb->radio_cold_rst); 214 } 215 216 ar_ahb->radio_warm_rst = devm_reset_control_get_exclusive(dev, 217 "wifi_radio_warm"); 218 if (IS_ERR(ar_ahb->radio_warm_rst)) { 219 ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n", 220 PTR_ERR(ar_ahb->radio_warm_rst)); 221 return PTR_ERR(ar_ahb->radio_warm_rst); 222 } 223 224 ar_ahb->radio_srif_rst = devm_reset_control_get_exclusive(dev, 225 "wifi_radio_srif"); 226 if (IS_ERR(ar_ahb->radio_srif_rst)) { 227 ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n", 228 PTR_ERR(ar_ahb->radio_srif_rst)); 229 return PTR_ERR(ar_ahb->radio_srif_rst); 230 } 231 232 ar_ahb->cpu_init_rst = devm_reset_control_get_exclusive(dev, 233 "wifi_cpu_init"); 234 if (IS_ERR(ar_ahb->cpu_init_rst)) { 235 ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n", 236 PTR_ERR(ar_ahb->cpu_init_rst)); 237 return PTR_ERR(ar_ahb->cpu_init_rst); 238 } 239 240 return 0; 241 } 242 243 static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar) 244 { 245 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 246 247 ar_ahb->core_cold_rst = NULL; 248 ar_ahb->radio_cold_rst = NULL; 249 ar_ahb->radio_warm_rst = NULL; 250 ar_ahb->radio_srif_rst = NULL; 251 ar_ahb->cpu_init_rst = NULL; 252 } 253 254 static int ath10k_ahb_release_reset(struct ath10k *ar) 255 { 256 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 257 int ret; 258 259 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || 260 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || 261 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || 262 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { 263 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); 264 return -EINVAL; 265 } 266 267 ret = reset_control_deassert(ar_ahb->radio_cold_rst); 268 if (ret) { 269 ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret); 270 return ret; 271 } 272 273 ret = reset_control_deassert(ar_ahb->radio_warm_rst); 274 if (ret) { 275 ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret); 276 return ret; 277 } 278 279 ret = reset_control_deassert(ar_ahb->radio_srif_rst); 280 if (ret) { 281 ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret); 282 return ret; 283 } 284 285 ret = reset_control_deassert(ar_ahb->cpu_init_rst); 286 if (ret) { 287 ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret); 288 return ret; 289 } 290 291 return 0; 292 } 293 294 static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg, 295 u32 haltack_reg) 296 { 297 unsigned long timeout; 298 u32 val; 299 300 /* Issue halt axi bus request */ 301 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); 302 val |= AHB_AXI_BUS_HALT_REQ; 303 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); 304 305 /* Wait for axi bus halted ack */ 306 timeout = jiffies + msecs_to_jiffies(ATH10K_AHB_AXI_BUS_HALT_TIMEOUT); 307 do { 308 val = ath10k_ahb_tcsr_read32(ar, haltack_reg); 309 if (val & AHB_AXI_BUS_HALT_ACK) 310 break; 311 312 mdelay(1); 313 } while (time_before(jiffies, timeout)); 314 315 if (!(val & AHB_AXI_BUS_HALT_ACK)) { 316 ath10k_err(ar, "failed to halt axi bus: %d\n", val); 317 return; 318 } 319 320 ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n"); 321 } 322 323 static void ath10k_ahb_halt_chip(struct ath10k *ar) 324 { 325 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 326 u32 core_id, glb_cfg_reg, haltreq_reg, haltack_reg; 327 u32 val; 328 int ret; 329 330 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) || 331 IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || 332 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || 333 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || 334 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { 335 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); 336 return; 337 } 338 339 core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG); 340 341 switch (core_id) { 342 case 0: 343 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI0_GLB_CFG; 344 haltreq_reg = ATH10K_AHB_TCSR_WCSS0_HALTREQ; 345 haltack_reg = ATH10K_AHB_TCSR_WCSS0_HALTACK; 346 break; 347 case 1: 348 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI1_GLB_CFG; 349 haltreq_reg = ATH10K_AHB_TCSR_WCSS1_HALTREQ; 350 haltack_reg = ATH10K_AHB_TCSR_WCSS1_HALTACK; 351 break; 352 default: 353 ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n", 354 core_id); 355 return; 356 } 357 358 ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg); 359 360 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); 361 val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; 362 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); 363 364 ret = reset_control_assert(ar_ahb->core_cold_rst); 365 if (ret) 366 ath10k_err(ar, "failed to assert core cold rst: %d\n", ret); 367 msleep(1); 368 369 ret = reset_control_assert(ar_ahb->radio_cold_rst); 370 if (ret) 371 ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret); 372 msleep(1); 373 374 ret = reset_control_assert(ar_ahb->radio_warm_rst); 375 if (ret) 376 ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret); 377 msleep(1); 378 379 ret = reset_control_assert(ar_ahb->radio_srif_rst); 380 if (ret) 381 ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret); 382 msleep(1); 383 384 ret = reset_control_assert(ar_ahb->cpu_init_rst); 385 if (ret) 386 ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret); 387 msleep(10); 388 389 /* Clear halt req and core clock disable req before 390 * deasserting wifi core reset. 391 */ 392 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); 393 val &= ~AHB_AXI_BUS_HALT_REQ; 394 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); 395 396 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); 397 val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; 398 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); 399 400 ret = reset_control_deassert(ar_ahb->core_cold_rst); 401 if (ret) 402 ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret); 403 404 ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id); 405 } 406 407 static irqreturn_t ath10k_ahb_interrupt_handler(int irq, void *arg) 408 { 409 struct ath10k *ar = arg; 410 411 if (!ath10k_pci_irq_pending(ar)) 412 return IRQ_NONE; 413 414 ath10k_pci_disable_and_clear_legacy_irq(ar); 415 ath10k_pci_irq_msi_fw_mask(ar); 416 napi_schedule(&ar->napi); 417 418 return IRQ_HANDLED; 419 } 420 421 static int ath10k_ahb_request_irq_legacy(struct ath10k *ar) 422 { 423 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 424 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 425 int ret; 426 427 ret = request_irq(ar_ahb->irq, 428 ath10k_ahb_interrupt_handler, 429 IRQF_SHARED, "ath10k_ahb", ar); 430 if (ret) { 431 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 432 ar_ahb->irq, ret); 433 return ret; 434 } 435 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; 436 437 return 0; 438 } 439 440 static void ath10k_ahb_release_irq_legacy(struct ath10k *ar) 441 { 442 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 443 444 free_irq(ar_ahb->irq, ar); 445 } 446 447 static void ath10k_ahb_irq_disable(struct ath10k *ar) 448 { 449 ath10k_ce_disable_interrupts(ar); 450 ath10k_pci_disable_and_clear_legacy_irq(ar); 451 } 452 453 static int ath10k_ahb_resource_init(struct ath10k *ar) 454 { 455 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 456 struct platform_device *pdev; 457 struct device *dev; 458 struct resource *res; 459 int ret; 460 461 pdev = ar_ahb->pdev; 462 dev = &pdev->dev; 463 464 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 465 if (!res) { 466 ath10k_err(ar, "failed to get memory resource\n"); 467 ret = -ENXIO; 468 goto out; 469 } 470 471 ar_ahb->mem = devm_ioremap_resource(&pdev->dev, res); 472 if (IS_ERR(ar_ahb->mem)) { 473 ath10k_err(ar, "mem ioremap error\n"); 474 ret = PTR_ERR(ar_ahb->mem); 475 goto out; 476 } 477 478 ar_ahb->mem_len = resource_size(res); 479 480 ar_ahb->gcc_mem = ioremap_nocache(ATH10K_GCC_REG_BASE, 481 ATH10K_GCC_REG_SIZE); 482 if (!ar_ahb->gcc_mem) { 483 ath10k_err(ar, "gcc mem ioremap error\n"); 484 ret = -ENOMEM; 485 goto err_mem_unmap; 486 } 487 488 ar_ahb->tcsr_mem = ioremap_nocache(ATH10K_TCSR_REG_BASE, 489 ATH10K_TCSR_REG_SIZE); 490 if (!ar_ahb->tcsr_mem) { 491 ath10k_err(ar, "tcsr mem ioremap error\n"); 492 ret = -ENOMEM; 493 goto err_gcc_mem_unmap; 494 } 495 496 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 497 if (ret) { 498 ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret); 499 goto err_tcsr_mem_unmap; 500 } 501 502 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 503 if (ret) { 504 ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n", 505 ret); 506 goto err_tcsr_mem_unmap; 507 } 508 509 ret = ath10k_ahb_clock_init(ar); 510 if (ret) 511 goto err_tcsr_mem_unmap; 512 513 ret = ath10k_ahb_rst_ctrl_init(ar); 514 if (ret) 515 goto err_clock_deinit; 516 517 ar_ahb->irq = platform_get_irq_byname(pdev, "legacy"); 518 if (ar_ahb->irq < 0) { 519 ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq); 520 ret = ar_ahb->irq; 521 goto err_clock_deinit; 522 } 523 524 ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq); 525 526 ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n", 527 ar_ahb->mem, ar_ahb->mem_len, 528 ar_ahb->gcc_mem, ar_ahb->tcsr_mem); 529 return 0; 530 531 err_clock_deinit: 532 ath10k_ahb_clock_deinit(ar); 533 534 err_tcsr_mem_unmap: 535 iounmap(ar_ahb->tcsr_mem); 536 537 err_gcc_mem_unmap: 538 ar_ahb->tcsr_mem = NULL; 539 iounmap(ar_ahb->gcc_mem); 540 541 err_mem_unmap: 542 ar_ahb->gcc_mem = NULL; 543 devm_iounmap(&pdev->dev, ar_ahb->mem); 544 545 out: 546 ar_ahb->mem = NULL; 547 return ret; 548 } 549 550 static void ath10k_ahb_resource_deinit(struct ath10k *ar) 551 { 552 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 553 struct device *dev; 554 555 dev = &ar_ahb->pdev->dev; 556 557 if (ar_ahb->mem) 558 devm_iounmap(dev, ar_ahb->mem); 559 560 if (ar_ahb->gcc_mem) 561 iounmap(ar_ahb->gcc_mem); 562 563 if (ar_ahb->tcsr_mem) 564 iounmap(ar_ahb->tcsr_mem); 565 566 ar_ahb->mem = NULL; 567 ar_ahb->gcc_mem = NULL; 568 ar_ahb->tcsr_mem = NULL; 569 570 ath10k_ahb_clock_deinit(ar); 571 ath10k_ahb_rst_ctrl_deinit(ar); 572 } 573 574 static int ath10k_ahb_prepare_device(struct ath10k *ar) 575 { 576 u32 val; 577 int ret; 578 579 ret = ath10k_ahb_clock_enable(ar); 580 if (ret) { 581 ath10k_err(ar, "failed to enable clocks\n"); 582 return ret; 583 } 584 585 /* Clock for the target is supplied from outside of target (ie, 586 * external clock module controlled by the host). Target needs 587 * to know what frequency target cpu is configured which is needed 588 * for target internal use. Read target cpu frequency info from 589 * gcc register and write into target's scratch register where 590 * target expects this information. 591 */ 592 val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV); 593 ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val); 594 595 ret = ath10k_ahb_release_reset(ar); 596 if (ret) 597 goto err_clk_disable; 598 599 ath10k_ahb_irq_disable(ar); 600 601 ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); 602 603 ret = ath10k_pci_wait_for_target_init(ar); 604 if (ret) 605 goto err_halt_chip; 606 607 return 0; 608 609 err_halt_chip: 610 ath10k_ahb_halt_chip(ar); 611 612 err_clk_disable: 613 ath10k_ahb_clock_disable(ar); 614 615 return ret; 616 } 617 618 static int ath10k_ahb_chip_reset(struct ath10k *ar) 619 { 620 int ret; 621 622 ath10k_ahb_halt_chip(ar); 623 ath10k_ahb_clock_disable(ar); 624 625 ret = ath10k_ahb_prepare_device(ar); 626 if (ret) 627 return ret; 628 629 return 0; 630 } 631 632 static int ath10k_ahb_wake_target_cpu(struct ath10k *ar) 633 { 634 u32 addr, val; 635 636 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS; 637 val = ath10k_ahb_read32(ar, addr); 638 val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK; 639 ath10k_ahb_write32(ar, addr, val); 640 641 return 0; 642 } 643 644 static int ath10k_ahb_hif_start(struct ath10k *ar) 645 { 646 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n"); 647 648 napi_enable(&ar->napi); 649 ath10k_ce_enable_interrupts(ar); 650 ath10k_pci_enable_legacy_irq(ar); 651 652 ath10k_pci_rx_post(ar); 653 654 return 0; 655 } 656 657 static void ath10k_ahb_hif_stop(struct ath10k *ar) 658 { 659 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 660 661 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n"); 662 663 ath10k_ahb_irq_disable(ar); 664 synchronize_irq(ar_ahb->irq); 665 666 ath10k_pci_flush(ar); 667 668 napi_synchronize(&ar->napi); 669 napi_disable(&ar->napi); 670 } 671 672 static int ath10k_ahb_hif_power_up(struct ath10k *ar) 673 { 674 int ret; 675 676 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n"); 677 678 ret = ath10k_ahb_chip_reset(ar); 679 if (ret) { 680 ath10k_err(ar, "failed to reset chip: %d\n", ret); 681 goto out; 682 } 683 684 ret = ath10k_pci_init_pipes(ar); 685 if (ret) { 686 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 687 goto out; 688 } 689 690 ret = ath10k_pci_init_config(ar); 691 if (ret) { 692 ath10k_err(ar, "failed to setup init config: %d\n", ret); 693 goto err_ce_deinit; 694 } 695 696 ret = ath10k_ahb_wake_target_cpu(ar); 697 if (ret) { 698 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 699 goto err_ce_deinit; 700 } 701 702 return 0; 703 704 err_ce_deinit: 705 ath10k_pci_ce_deinit(ar); 706 out: 707 return ret; 708 } 709 710 static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 711 { 712 u32 val = 0, region = addr & 0xfffff; 713 714 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); 715 716 if (region >= QCA4019_SRAM_ADDR && region <= 717 (QCA4019_SRAM_ADDR + QCA4019_SRAM_LEN)) { 718 /* SRAM contents for QCA4019 can be directly accessed and 719 * no conversions are required 720 */ 721 val |= region; 722 } else { 723 val |= 0x100000 | region; 724 } 725 726 return val; 727 } 728 729 static const struct ath10k_hif_ops ath10k_ahb_hif_ops = { 730 .tx_sg = ath10k_pci_hif_tx_sg, 731 .diag_read = ath10k_pci_hif_diag_read, 732 .diag_write = ath10k_pci_diag_write_mem, 733 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 734 .start = ath10k_ahb_hif_start, 735 .stop = ath10k_ahb_hif_stop, 736 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 737 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 738 .send_complete_check = ath10k_pci_hif_send_complete_check, 739 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 740 .power_up = ath10k_ahb_hif_power_up, 741 .power_down = ath10k_pci_hif_power_down, 742 .read32 = ath10k_ahb_read32, 743 .write32 = ath10k_ahb_write32, 744 }; 745 746 static const struct ath10k_bus_ops ath10k_ahb_bus_ops = { 747 .read32 = ath10k_ahb_read32, 748 .write32 = ath10k_ahb_write32, 749 .get_num_banks = ath10k_ahb_get_num_banks, 750 }; 751 752 static int ath10k_ahb_probe(struct platform_device *pdev) 753 { 754 struct ath10k *ar; 755 struct ath10k_ahb *ar_ahb; 756 struct ath10k_pci *ar_pci; 757 const struct of_device_id *of_id; 758 enum ath10k_hw_rev hw_rev; 759 size_t size; 760 int ret; 761 u32 chip_id; 762 763 of_id = of_match_device(ath10k_ahb_of_match, &pdev->dev); 764 if (!of_id) { 765 dev_err(&pdev->dev, "failed to find matching device tree id\n"); 766 return -EINVAL; 767 } 768 769 hw_rev = (enum ath10k_hw_rev)of_id->data; 770 771 size = sizeof(*ar_pci) + sizeof(*ar_ahb); 772 ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB, 773 hw_rev, &ath10k_ahb_hif_ops); 774 if (!ar) { 775 dev_err(&pdev->dev, "failed to allocate core\n"); 776 return -ENOMEM; 777 } 778 779 ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n"); 780 781 ar_pci = ath10k_pci_priv(ar); 782 ar_ahb = ath10k_ahb_priv(ar); 783 784 ar_ahb->pdev = pdev; 785 platform_set_drvdata(pdev, ar); 786 787 ret = ath10k_ahb_resource_init(ar); 788 if (ret) 789 goto err_core_destroy; 790 791 ar->dev_id = 0; 792 ar_pci->mem = ar_ahb->mem; 793 ar_pci->mem_len = ar_ahb->mem_len; 794 ar_pci->ar = ar; 795 ar_pci->ce.bus_ops = &ath10k_ahb_bus_ops; 796 ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr; 797 ar->ce_priv = &ar_pci->ce; 798 799 ret = ath10k_pci_setup_resource(ar); 800 if (ret) { 801 ath10k_err(ar, "failed to setup resource: %d\n", ret); 802 goto err_resource_deinit; 803 } 804 805 ath10k_pci_init_napi(ar); 806 807 ret = ath10k_ahb_request_irq_legacy(ar); 808 if (ret) 809 goto err_free_pipes; 810 811 ret = ath10k_ahb_prepare_device(ar); 812 if (ret) 813 goto err_free_irq; 814 815 ath10k_pci_ce_deinit(ar); 816 817 chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 818 if (chip_id == 0xffffffff) { 819 ath10k_err(ar, "failed to get chip id\n"); 820 ret = -ENODEV; 821 goto err_halt_device; 822 } 823 824 ret = ath10k_core_register(ar, chip_id); 825 if (ret) { 826 ath10k_err(ar, "failed to register driver core: %d\n", ret); 827 goto err_halt_device; 828 } 829 830 return 0; 831 832 err_halt_device: 833 ath10k_ahb_halt_chip(ar); 834 ath10k_ahb_clock_disable(ar); 835 836 err_free_irq: 837 ath10k_ahb_release_irq_legacy(ar); 838 839 err_free_pipes: 840 ath10k_pci_free_pipes(ar); 841 842 err_resource_deinit: 843 ath10k_ahb_resource_deinit(ar); 844 845 err_core_destroy: 846 ath10k_core_destroy(ar); 847 platform_set_drvdata(pdev, NULL); 848 849 return ret; 850 } 851 852 static int ath10k_ahb_remove(struct platform_device *pdev) 853 { 854 struct ath10k *ar = platform_get_drvdata(pdev); 855 struct ath10k_ahb *ar_ahb; 856 857 if (!ar) 858 return -EINVAL; 859 860 ar_ahb = ath10k_ahb_priv(ar); 861 862 if (!ar_ahb) 863 return -EINVAL; 864 865 ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n"); 866 867 ath10k_core_unregister(ar); 868 ath10k_ahb_irq_disable(ar); 869 ath10k_ahb_release_irq_legacy(ar); 870 ath10k_pci_release_resource(ar); 871 ath10k_ahb_halt_chip(ar); 872 ath10k_ahb_clock_disable(ar); 873 ath10k_ahb_resource_deinit(ar); 874 ath10k_core_destroy(ar); 875 876 platform_set_drvdata(pdev, NULL); 877 878 return 0; 879 } 880 881 static struct platform_driver ath10k_ahb_driver = { 882 .driver = { 883 .name = "ath10k_ahb", 884 .of_match_table = ath10k_ahb_of_match, 885 }, 886 .probe = ath10k_ahb_probe, 887 .remove = ath10k_ahb_remove, 888 }; 889 890 int ath10k_ahb_init(void) 891 { 892 int ret; 893 894 ret = platform_driver_register(&ath10k_ahb_driver); 895 if (ret) 896 printk(KERN_ERR "failed to register ath10k ahb driver: %d\n", 897 ret); 898 return ret; 899 } 900 901 void ath10k_ahb_exit(void) 902 { 903 platform_driver_unregister(&ath10k_ahb_driver); 904 } 905