1 /* 2 * Copyright (c) 2016 Qualcomm Atheros, Inc. All rights reserved. 3 * Copyright (c) 2015 The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/clk.h> 21 #include <linux/reset.h> 22 #include "core.h" 23 #include "debug.h" 24 #include "pci.h" 25 #include "ahb.h" 26 27 static const struct of_device_id ath10k_ahb_of_match[] = { 28 { .compatible = "qcom,ipq4019-wifi", 29 .data = (void *)ATH10K_HW_QCA4019 30 }, 31 { } 32 }; 33 34 MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match); 35 36 #define QCA4019_SRAM_ADDR 0x000C0000 37 #define QCA4019_SRAM_LEN 0x00040000 /* 256 kb */ 38 39 static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar) 40 { 41 return &((struct ath10k_pci *)ar->drv_priv)->ahb[0]; 42 } 43 44 static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value) 45 { 46 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 47 48 iowrite32(value, ar_ahb->mem + offset); 49 } 50 51 static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset) 52 { 53 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 54 55 return ioread32(ar_ahb->mem + offset); 56 } 57 58 static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset) 59 { 60 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 61 62 return ioread32(ar_ahb->gcc_mem + offset); 63 } 64 65 static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value) 66 { 67 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 68 69 iowrite32(value, ar_ahb->tcsr_mem + offset); 70 } 71 72 static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset) 73 { 74 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 75 76 return ioread32(ar_ahb->tcsr_mem + offset); 77 } 78 79 static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr) 80 { 81 return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 82 } 83 84 static int ath10k_ahb_get_num_banks(struct ath10k *ar) 85 { 86 if (ar->hw_rev == ATH10K_HW_QCA4019) 87 return 1; 88 89 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 90 return 1; 91 } 92 93 static int ath10k_ahb_clock_init(struct ath10k *ar) 94 { 95 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 96 struct device *dev; 97 98 dev = &ar_ahb->pdev->dev; 99 100 ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd"); 101 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) { 102 ath10k_err(ar, "failed to get cmd clk: %ld\n", 103 PTR_ERR(ar_ahb->cmd_clk)); 104 return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV; 105 } 106 107 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref"); 108 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) { 109 ath10k_err(ar, "failed to get ref clk: %ld\n", 110 PTR_ERR(ar_ahb->ref_clk)); 111 return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV; 112 } 113 114 ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc"); 115 if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { 116 ath10k_err(ar, "failed to get rtc clk: %ld\n", 117 PTR_ERR(ar_ahb->rtc_clk)); 118 return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV; 119 } 120 121 return 0; 122 } 123 124 static void ath10k_ahb_clock_deinit(struct ath10k *ar) 125 { 126 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 127 128 ar_ahb->cmd_clk = NULL; 129 ar_ahb->ref_clk = NULL; 130 ar_ahb->rtc_clk = NULL; 131 } 132 133 static int ath10k_ahb_clock_enable(struct ath10k *ar) 134 { 135 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 136 struct device *dev; 137 int ret; 138 139 dev = &ar_ahb->pdev->dev; 140 141 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) || 142 IS_ERR_OR_NULL(ar_ahb->ref_clk) || 143 IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { 144 ath10k_err(ar, "clock(s) is/are not initialized\n"); 145 ret = -EIO; 146 goto out; 147 } 148 149 ret = clk_prepare_enable(ar_ahb->cmd_clk); 150 if (ret) { 151 ath10k_err(ar, "failed to enable cmd clk: %d\n", ret); 152 goto out; 153 } 154 155 ret = clk_prepare_enable(ar_ahb->ref_clk); 156 if (ret) { 157 ath10k_err(ar, "failed to enable ref clk: %d\n", ret); 158 goto err_cmd_clk_disable; 159 } 160 161 ret = clk_prepare_enable(ar_ahb->rtc_clk); 162 if (ret) { 163 ath10k_err(ar, "failed to enable rtc clk: %d\n", ret); 164 goto err_ref_clk_disable; 165 } 166 167 return 0; 168 169 err_ref_clk_disable: 170 clk_disable_unprepare(ar_ahb->ref_clk); 171 172 err_cmd_clk_disable: 173 clk_disable_unprepare(ar_ahb->cmd_clk); 174 175 out: 176 return ret; 177 } 178 179 static void ath10k_ahb_clock_disable(struct ath10k *ar) 180 { 181 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 182 183 if (!IS_ERR_OR_NULL(ar_ahb->cmd_clk)) 184 clk_disable_unprepare(ar_ahb->cmd_clk); 185 186 if (!IS_ERR_OR_NULL(ar_ahb->ref_clk)) 187 clk_disable_unprepare(ar_ahb->ref_clk); 188 189 if (!IS_ERR_OR_NULL(ar_ahb->rtc_clk)) 190 clk_disable_unprepare(ar_ahb->rtc_clk); 191 } 192 193 static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar) 194 { 195 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 196 struct device *dev; 197 198 dev = &ar_ahb->pdev->dev; 199 200 ar_ahb->core_cold_rst = devm_reset_control_get(dev, "wifi_core_cold"); 201 if (IS_ERR(ar_ahb->core_cold_rst)) { 202 ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n", 203 PTR_ERR(ar_ahb->core_cold_rst)); 204 return PTR_ERR(ar_ahb->core_cold_rst); 205 } 206 207 ar_ahb->radio_cold_rst = devm_reset_control_get(dev, "wifi_radio_cold"); 208 if (IS_ERR(ar_ahb->radio_cold_rst)) { 209 ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n", 210 PTR_ERR(ar_ahb->radio_cold_rst)); 211 return PTR_ERR(ar_ahb->radio_cold_rst); 212 } 213 214 ar_ahb->radio_warm_rst = devm_reset_control_get(dev, "wifi_radio_warm"); 215 if (IS_ERR(ar_ahb->radio_warm_rst)) { 216 ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n", 217 PTR_ERR(ar_ahb->radio_warm_rst)); 218 return PTR_ERR(ar_ahb->radio_warm_rst); 219 } 220 221 ar_ahb->radio_srif_rst = devm_reset_control_get(dev, "wifi_radio_srif"); 222 if (IS_ERR(ar_ahb->radio_srif_rst)) { 223 ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n", 224 PTR_ERR(ar_ahb->radio_srif_rst)); 225 return PTR_ERR(ar_ahb->radio_srif_rst); 226 } 227 228 ar_ahb->cpu_init_rst = devm_reset_control_get(dev, "wifi_cpu_init"); 229 if (IS_ERR(ar_ahb->cpu_init_rst)) { 230 ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n", 231 PTR_ERR(ar_ahb->cpu_init_rst)); 232 return PTR_ERR(ar_ahb->cpu_init_rst); 233 } 234 235 return 0; 236 } 237 238 static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar) 239 { 240 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 241 242 ar_ahb->core_cold_rst = NULL; 243 ar_ahb->radio_cold_rst = NULL; 244 ar_ahb->radio_warm_rst = NULL; 245 ar_ahb->radio_srif_rst = NULL; 246 ar_ahb->cpu_init_rst = NULL; 247 } 248 249 static int ath10k_ahb_release_reset(struct ath10k *ar) 250 { 251 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 252 int ret; 253 254 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || 255 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || 256 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || 257 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { 258 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); 259 return -EINVAL; 260 } 261 262 ret = reset_control_deassert(ar_ahb->radio_cold_rst); 263 if (ret) { 264 ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret); 265 return ret; 266 } 267 268 ret = reset_control_deassert(ar_ahb->radio_warm_rst); 269 if (ret) { 270 ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret); 271 return ret; 272 } 273 274 ret = reset_control_deassert(ar_ahb->radio_srif_rst); 275 if (ret) { 276 ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret); 277 return ret; 278 } 279 280 ret = reset_control_deassert(ar_ahb->cpu_init_rst); 281 if (ret) { 282 ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret); 283 return ret; 284 } 285 286 return 0; 287 } 288 289 static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg, 290 u32 haltack_reg) 291 { 292 unsigned long timeout; 293 u32 val; 294 295 /* Issue halt axi bus request */ 296 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); 297 val |= AHB_AXI_BUS_HALT_REQ; 298 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); 299 300 /* Wait for axi bus halted ack */ 301 timeout = jiffies + msecs_to_jiffies(ATH10K_AHB_AXI_BUS_HALT_TIMEOUT); 302 do { 303 val = ath10k_ahb_tcsr_read32(ar, haltack_reg); 304 if (val & AHB_AXI_BUS_HALT_ACK) 305 break; 306 307 mdelay(1); 308 } while (time_before(jiffies, timeout)); 309 310 if (!(val & AHB_AXI_BUS_HALT_ACK)) { 311 ath10k_err(ar, "failed to halt axi bus: %d\n", val); 312 return; 313 } 314 315 ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n"); 316 } 317 318 static void ath10k_ahb_halt_chip(struct ath10k *ar) 319 { 320 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 321 u32 core_id, glb_cfg_reg, haltreq_reg, haltack_reg; 322 u32 val; 323 int ret; 324 325 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) || 326 IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || 327 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || 328 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || 329 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { 330 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); 331 return; 332 } 333 334 core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG); 335 336 switch (core_id) { 337 case 0: 338 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI0_GLB_CFG; 339 haltreq_reg = ATH10K_AHB_TCSR_WCSS0_HALTREQ; 340 haltack_reg = ATH10K_AHB_TCSR_WCSS0_HALTACK; 341 break; 342 case 1: 343 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI1_GLB_CFG; 344 haltreq_reg = ATH10K_AHB_TCSR_WCSS1_HALTREQ; 345 haltack_reg = ATH10K_AHB_TCSR_WCSS1_HALTACK; 346 break; 347 default: 348 ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n", 349 core_id); 350 return; 351 } 352 353 ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg); 354 355 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); 356 val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; 357 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); 358 359 ret = reset_control_assert(ar_ahb->core_cold_rst); 360 if (ret) 361 ath10k_err(ar, "failed to assert core cold rst: %d\n", ret); 362 msleep(1); 363 364 ret = reset_control_assert(ar_ahb->radio_cold_rst); 365 if (ret) 366 ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret); 367 msleep(1); 368 369 ret = reset_control_assert(ar_ahb->radio_warm_rst); 370 if (ret) 371 ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret); 372 msleep(1); 373 374 ret = reset_control_assert(ar_ahb->radio_srif_rst); 375 if (ret) 376 ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret); 377 msleep(1); 378 379 ret = reset_control_assert(ar_ahb->cpu_init_rst); 380 if (ret) 381 ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret); 382 msleep(10); 383 384 /* Clear halt req and core clock disable req before 385 * deasserting wifi core reset. 386 */ 387 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); 388 val &= ~AHB_AXI_BUS_HALT_REQ; 389 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); 390 391 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); 392 val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; 393 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); 394 395 ret = reset_control_deassert(ar_ahb->core_cold_rst); 396 if (ret) 397 ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret); 398 399 ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id); 400 } 401 402 static irqreturn_t ath10k_ahb_interrupt_handler(int irq, void *arg) 403 { 404 struct ath10k *ar = arg; 405 406 if (!ath10k_pci_irq_pending(ar)) 407 return IRQ_NONE; 408 409 ath10k_pci_disable_and_clear_legacy_irq(ar); 410 ath10k_pci_irq_msi_fw_mask(ar); 411 napi_schedule(&ar->napi); 412 413 return IRQ_HANDLED; 414 } 415 416 static int ath10k_ahb_request_irq_legacy(struct ath10k *ar) 417 { 418 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 419 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 420 int ret; 421 422 ret = request_irq(ar_ahb->irq, 423 ath10k_ahb_interrupt_handler, 424 IRQF_SHARED, "ath10k_ahb", ar); 425 if (ret) { 426 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 427 ar_ahb->irq, ret); 428 return ret; 429 } 430 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; 431 432 return 0; 433 } 434 435 static void ath10k_ahb_release_irq_legacy(struct ath10k *ar) 436 { 437 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 438 439 free_irq(ar_ahb->irq, ar); 440 } 441 442 static void ath10k_ahb_irq_disable(struct ath10k *ar) 443 { 444 ath10k_ce_disable_interrupts(ar); 445 ath10k_pci_disable_and_clear_legacy_irq(ar); 446 } 447 448 static int ath10k_ahb_resource_init(struct ath10k *ar) 449 { 450 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 451 struct platform_device *pdev; 452 struct device *dev; 453 struct resource *res; 454 int ret; 455 456 pdev = ar_ahb->pdev; 457 dev = &pdev->dev; 458 459 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 460 if (!res) { 461 ath10k_err(ar, "failed to get memory resource\n"); 462 ret = -ENXIO; 463 goto out; 464 } 465 466 ar_ahb->mem = devm_ioremap_resource(&pdev->dev, res); 467 if (IS_ERR(ar_ahb->mem)) { 468 ath10k_err(ar, "mem ioremap error\n"); 469 ret = PTR_ERR(ar_ahb->mem); 470 goto out; 471 } 472 473 ar_ahb->mem_len = resource_size(res); 474 475 ar_ahb->gcc_mem = ioremap_nocache(ATH10K_GCC_REG_BASE, 476 ATH10K_GCC_REG_SIZE); 477 if (!ar_ahb->gcc_mem) { 478 ath10k_err(ar, "gcc mem ioremap error\n"); 479 ret = -ENOMEM; 480 goto err_mem_unmap; 481 } 482 483 ar_ahb->tcsr_mem = ioremap_nocache(ATH10K_TCSR_REG_BASE, 484 ATH10K_TCSR_REG_SIZE); 485 if (!ar_ahb->tcsr_mem) { 486 ath10k_err(ar, "tcsr mem ioremap error\n"); 487 ret = -ENOMEM; 488 goto err_gcc_mem_unmap; 489 } 490 491 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 492 if (ret) { 493 ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret); 494 goto err_tcsr_mem_unmap; 495 } 496 497 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 498 if (ret) { 499 ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n", 500 ret); 501 goto err_tcsr_mem_unmap; 502 } 503 504 ret = ath10k_ahb_clock_init(ar); 505 if (ret) 506 goto err_tcsr_mem_unmap; 507 508 ret = ath10k_ahb_rst_ctrl_init(ar); 509 if (ret) 510 goto err_clock_deinit; 511 512 ar_ahb->irq = platform_get_irq_byname(pdev, "legacy"); 513 if (ar_ahb->irq < 0) { 514 ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq); 515 ret = ar_ahb->irq; 516 goto err_clock_deinit; 517 } 518 519 ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq); 520 521 ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n", 522 ar_ahb->mem, ar_ahb->mem_len, 523 ar_ahb->gcc_mem, ar_ahb->tcsr_mem); 524 return 0; 525 526 err_clock_deinit: 527 ath10k_ahb_clock_deinit(ar); 528 529 err_tcsr_mem_unmap: 530 iounmap(ar_ahb->tcsr_mem); 531 532 err_gcc_mem_unmap: 533 ar_ahb->tcsr_mem = NULL; 534 iounmap(ar_ahb->gcc_mem); 535 536 err_mem_unmap: 537 ar_ahb->gcc_mem = NULL; 538 devm_iounmap(&pdev->dev, ar_ahb->mem); 539 540 out: 541 ar_ahb->mem = NULL; 542 return ret; 543 } 544 545 static void ath10k_ahb_resource_deinit(struct ath10k *ar) 546 { 547 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 548 struct device *dev; 549 550 dev = &ar_ahb->pdev->dev; 551 552 if (ar_ahb->mem) 553 devm_iounmap(dev, ar_ahb->mem); 554 555 if (ar_ahb->gcc_mem) 556 iounmap(ar_ahb->gcc_mem); 557 558 if (ar_ahb->tcsr_mem) 559 iounmap(ar_ahb->tcsr_mem); 560 561 ar_ahb->mem = NULL; 562 ar_ahb->gcc_mem = NULL; 563 ar_ahb->tcsr_mem = NULL; 564 565 ath10k_ahb_clock_deinit(ar); 566 ath10k_ahb_rst_ctrl_deinit(ar); 567 } 568 569 static int ath10k_ahb_prepare_device(struct ath10k *ar) 570 { 571 u32 val; 572 int ret; 573 574 ret = ath10k_ahb_clock_enable(ar); 575 if (ret) { 576 ath10k_err(ar, "failed to enable clocks\n"); 577 return ret; 578 } 579 580 /* Clock for the target is supplied from outside of target (ie, 581 * external clock module controlled by the host). Target needs 582 * to know what frequency target cpu is configured which is needed 583 * for target internal use. Read target cpu frequency info from 584 * gcc register and write into target's scratch register where 585 * target expects this information. 586 */ 587 val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV); 588 ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val); 589 590 ret = ath10k_ahb_release_reset(ar); 591 if (ret) 592 goto err_clk_disable; 593 594 ath10k_ahb_irq_disable(ar); 595 596 ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); 597 598 ret = ath10k_pci_wait_for_target_init(ar); 599 if (ret) 600 goto err_halt_chip; 601 602 return 0; 603 604 err_halt_chip: 605 ath10k_ahb_halt_chip(ar); 606 607 err_clk_disable: 608 ath10k_ahb_clock_disable(ar); 609 610 return ret; 611 } 612 613 static int ath10k_ahb_chip_reset(struct ath10k *ar) 614 { 615 int ret; 616 617 ath10k_ahb_halt_chip(ar); 618 ath10k_ahb_clock_disable(ar); 619 620 ret = ath10k_ahb_prepare_device(ar); 621 if (ret) 622 return ret; 623 624 return 0; 625 } 626 627 static int ath10k_ahb_wake_target_cpu(struct ath10k *ar) 628 { 629 u32 addr, val; 630 631 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS; 632 val = ath10k_ahb_read32(ar, addr); 633 val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK; 634 ath10k_ahb_write32(ar, addr, val); 635 636 return 0; 637 } 638 639 static int ath10k_ahb_hif_start(struct ath10k *ar) 640 { 641 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n"); 642 643 napi_enable(&ar->napi); 644 ath10k_ce_enable_interrupts(ar); 645 ath10k_pci_enable_legacy_irq(ar); 646 647 ath10k_pci_rx_post(ar); 648 649 return 0; 650 } 651 652 static void ath10k_ahb_hif_stop(struct ath10k *ar) 653 { 654 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 655 656 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n"); 657 658 ath10k_ahb_irq_disable(ar); 659 synchronize_irq(ar_ahb->irq); 660 661 ath10k_pci_flush(ar); 662 663 napi_synchronize(&ar->napi); 664 napi_disable(&ar->napi); 665 } 666 667 static int ath10k_ahb_hif_power_up(struct ath10k *ar) 668 { 669 int ret; 670 671 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n"); 672 673 ret = ath10k_ahb_chip_reset(ar); 674 if (ret) { 675 ath10k_err(ar, "failed to reset chip: %d\n", ret); 676 goto out; 677 } 678 679 ret = ath10k_pci_init_pipes(ar); 680 if (ret) { 681 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 682 goto out; 683 } 684 685 ret = ath10k_pci_init_config(ar); 686 if (ret) { 687 ath10k_err(ar, "failed to setup init config: %d\n", ret); 688 goto err_ce_deinit; 689 } 690 691 ret = ath10k_ahb_wake_target_cpu(ar); 692 if (ret) { 693 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 694 goto err_ce_deinit; 695 } 696 697 return 0; 698 699 err_ce_deinit: 700 ath10k_pci_ce_deinit(ar); 701 out: 702 return ret; 703 } 704 705 static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 706 { 707 u32 val = 0, region = addr & 0xfffff; 708 709 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); 710 711 if (region >= QCA4019_SRAM_ADDR && region <= 712 (QCA4019_SRAM_ADDR + QCA4019_SRAM_LEN)) { 713 /* SRAM contents for QCA4019 can be directly accessed and 714 * no conversions are required 715 */ 716 val |= region; 717 } else { 718 val |= 0x100000 | region; 719 } 720 721 return val; 722 } 723 724 static const struct ath10k_hif_ops ath10k_ahb_hif_ops = { 725 .tx_sg = ath10k_pci_hif_tx_sg, 726 .diag_read = ath10k_pci_hif_diag_read, 727 .diag_write = ath10k_pci_diag_write_mem, 728 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 729 .start = ath10k_ahb_hif_start, 730 .stop = ath10k_ahb_hif_stop, 731 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 732 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 733 .send_complete_check = ath10k_pci_hif_send_complete_check, 734 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 735 .power_up = ath10k_ahb_hif_power_up, 736 .power_down = ath10k_pci_hif_power_down, 737 .read32 = ath10k_ahb_read32, 738 .write32 = ath10k_ahb_write32, 739 }; 740 741 static const struct ath10k_bus_ops ath10k_ahb_bus_ops = { 742 .read32 = ath10k_ahb_read32, 743 .write32 = ath10k_ahb_write32, 744 .get_num_banks = ath10k_ahb_get_num_banks, 745 }; 746 747 static int ath10k_ahb_probe(struct platform_device *pdev) 748 { 749 struct ath10k *ar; 750 struct ath10k_ahb *ar_ahb; 751 struct ath10k_pci *ar_pci; 752 const struct of_device_id *of_id; 753 enum ath10k_hw_rev hw_rev; 754 size_t size; 755 int ret; 756 u32 chip_id; 757 758 of_id = of_match_device(ath10k_ahb_of_match, &pdev->dev); 759 if (!of_id) { 760 dev_err(&pdev->dev, "failed to find matching device tree id\n"); 761 return -EINVAL; 762 } 763 764 hw_rev = (enum ath10k_hw_rev)of_id->data; 765 766 size = sizeof(*ar_pci) + sizeof(*ar_ahb); 767 ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB, 768 hw_rev, &ath10k_ahb_hif_ops); 769 if (!ar) { 770 dev_err(&pdev->dev, "failed to allocate core\n"); 771 return -ENOMEM; 772 } 773 774 ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n"); 775 776 ar_pci = ath10k_pci_priv(ar); 777 ar_ahb = ath10k_ahb_priv(ar); 778 779 ar_ahb->pdev = pdev; 780 platform_set_drvdata(pdev, ar); 781 782 ret = ath10k_ahb_resource_init(ar); 783 if (ret) 784 goto err_core_destroy; 785 786 ar->dev_id = 0; 787 ar_pci->mem = ar_ahb->mem; 788 ar_pci->mem_len = ar_ahb->mem_len; 789 ar_pci->ar = ar; 790 ar_pci->bus_ops = &ath10k_ahb_bus_ops; 791 ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr; 792 793 ret = ath10k_pci_setup_resource(ar); 794 if (ret) { 795 ath10k_err(ar, "failed to setup resource: %d\n", ret); 796 goto err_resource_deinit; 797 } 798 799 ath10k_pci_init_napi(ar); 800 801 ret = ath10k_ahb_request_irq_legacy(ar); 802 if (ret) 803 goto err_free_pipes; 804 805 ret = ath10k_ahb_prepare_device(ar); 806 if (ret) 807 goto err_free_irq; 808 809 ath10k_pci_ce_deinit(ar); 810 811 chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 812 if (chip_id == 0xffffffff) { 813 ath10k_err(ar, "failed to get chip id\n"); 814 ret = -ENODEV; 815 goto err_halt_device; 816 } 817 818 ret = ath10k_core_register(ar, chip_id); 819 if (ret) { 820 ath10k_err(ar, "failed to register driver core: %d\n", ret); 821 goto err_halt_device; 822 } 823 824 return 0; 825 826 err_halt_device: 827 ath10k_ahb_halt_chip(ar); 828 ath10k_ahb_clock_disable(ar); 829 830 err_free_irq: 831 ath10k_ahb_release_irq_legacy(ar); 832 833 err_free_pipes: 834 ath10k_pci_free_pipes(ar); 835 836 err_resource_deinit: 837 ath10k_ahb_resource_deinit(ar); 838 839 err_core_destroy: 840 ath10k_core_destroy(ar); 841 platform_set_drvdata(pdev, NULL); 842 843 return ret; 844 } 845 846 static int ath10k_ahb_remove(struct platform_device *pdev) 847 { 848 struct ath10k *ar = platform_get_drvdata(pdev); 849 struct ath10k_ahb *ar_ahb; 850 851 if (!ar) 852 return -EINVAL; 853 854 ar_ahb = ath10k_ahb_priv(ar); 855 856 if (!ar_ahb) 857 return -EINVAL; 858 859 ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n"); 860 861 ath10k_core_unregister(ar); 862 ath10k_ahb_irq_disable(ar); 863 ath10k_ahb_release_irq_legacy(ar); 864 ath10k_pci_release_resource(ar); 865 ath10k_ahb_halt_chip(ar); 866 ath10k_ahb_clock_disable(ar); 867 ath10k_ahb_resource_deinit(ar); 868 ath10k_core_destroy(ar); 869 870 platform_set_drvdata(pdev, NULL); 871 872 return 0; 873 } 874 875 static struct platform_driver ath10k_ahb_driver = { 876 .driver = { 877 .name = "ath10k_ahb", 878 .of_match_table = ath10k_ahb_of_match, 879 }, 880 .probe = ath10k_ahb_probe, 881 .remove = ath10k_ahb_remove, 882 }; 883 884 int ath10k_ahb_init(void) 885 { 886 int ret; 887 888 ret = platform_driver_register(&ath10k_ahb_driver); 889 if (ret) 890 printk(KERN_ERR "failed to register ath10k ahb driver: %d\n", 891 ret); 892 return ret; 893 } 894 895 void ath10k_ahb_exit(void) 896 { 897 platform_driver_unregister(&ath10k_ahb_driver); 898 } 899