1 /* 2 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved. 3 * Copyright (c) 2015 The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/clk.h> 21 #include <linux/reset.h> 22 #include "core.h" 23 #include "debug.h" 24 #include "pci.h" 25 #include "ahb.h" 26 27 static const struct of_device_id ath10k_ahb_of_match[] = { 28 { .compatible = "qcom,ipq4019-wifi", 29 .data = (void *)ATH10K_HW_QCA4019 30 }, 31 { } 32 }; 33 34 MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match); 35 36 #define QCA4019_SRAM_ADDR 0x000C0000 37 #define QCA4019_SRAM_LEN 0x00040000 /* 256 kb */ 38 39 static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar) 40 { 41 return &((struct ath10k_pci *)ar->drv_priv)->ahb[0]; 42 } 43 44 static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value) 45 { 46 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 47 48 iowrite32(value, ar_ahb->mem + offset); 49 } 50 51 static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset) 52 { 53 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 54 55 return ioread32(ar_ahb->mem + offset); 56 } 57 58 static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset) 59 { 60 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 61 62 return ioread32(ar_ahb->gcc_mem + offset); 63 } 64 65 static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value) 66 { 67 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 68 69 iowrite32(value, ar_ahb->tcsr_mem + offset); 70 } 71 72 static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset) 73 { 74 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 75 76 return ioread32(ar_ahb->tcsr_mem + offset); 77 } 78 79 static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr) 80 { 81 return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 82 } 83 84 static int ath10k_ahb_get_num_banks(struct ath10k *ar) 85 { 86 if (ar->hw_rev == ATH10K_HW_QCA4019) 87 return 1; 88 89 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 90 return 1; 91 } 92 93 static int ath10k_ahb_clock_init(struct ath10k *ar) 94 { 95 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 96 struct device *dev; 97 98 dev = &ar_ahb->pdev->dev; 99 100 ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd"); 101 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) { 102 ath10k_err(ar, "failed to get cmd clk: %ld\n", 103 PTR_ERR(ar_ahb->cmd_clk)); 104 return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV; 105 } 106 107 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref"); 108 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) { 109 ath10k_err(ar, "failed to get ref clk: %ld\n", 110 PTR_ERR(ar_ahb->ref_clk)); 111 return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV; 112 } 113 114 ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc"); 115 if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { 116 ath10k_err(ar, "failed to get rtc clk: %ld\n", 117 PTR_ERR(ar_ahb->rtc_clk)); 118 return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV; 119 } 120 121 return 0; 122 } 123 124 static void ath10k_ahb_clock_deinit(struct ath10k *ar) 125 { 126 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 127 128 ar_ahb->cmd_clk = NULL; 129 ar_ahb->ref_clk = NULL; 130 ar_ahb->rtc_clk = NULL; 131 } 132 133 static int ath10k_ahb_clock_enable(struct ath10k *ar) 134 { 135 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 136 struct device *dev; 137 int ret; 138 139 dev = &ar_ahb->pdev->dev; 140 141 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) || 142 IS_ERR_OR_NULL(ar_ahb->ref_clk) || 143 IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { 144 ath10k_err(ar, "clock(s) is/are not initialized\n"); 145 ret = -EIO; 146 goto out; 147 } 148 149 ret = clk_prepare_enable(ar_ahb->cmd_clk); 150 if (ret) { 151 ath10k_err(ar, "failed to enable cmd clk: %d\n", ret); 152 goto out; 153 } 154 155 ret = clk_prepare_enable(ar_ahb->ref_clk); 156 if (ret) { 157 ath10k_err(ar, "failed to enable ref clk: %d\n", ret); 158 goto err_cmd_clk_disable; 159 } 160 161 ret = clk_prepare_enable(ar_ahb->rtc_clk); 162 if (ret) { 163 ath10k_err(ar, "failed to enable rtc clk: %d\n", ret); 164 goto err_ref_clk_disable; 165 } 166 167 return 0; 168 169 err_ref_clk_disable: 170 clk_disable_unprepare(ar_ahb->ref_clk); 171 172 err_cmd_clk_disable: 173 clk_disable_unprepare(ar_ahb->cmd_clk); 174 175 out: 176 return ret; 177 } 178 179 static void ath10k_ahb_clock_disable(struct ath10k *ar) 180 { 181 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 182 183 clk_disable_unprepare(ar_ahb->cmd_clk); 184 185 clk_disable_unprepare(ar_ahb->ref_clk); 186 187 clk_disable_unprepare(ar_ahb->rtc_clk); 188 } 189 190 static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar) 191 { 192 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 193 struct device *dev; 194 195 dev = &ar_ahb->pdev->dev; 196 197 ar_ahb->core_cold_rst = devm_reset_control_get_exclusive(dev, 198 "wifi_core_cold"); 199 if (IS_ERR(ar_ahb->core_cold_rst)) { 200 ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n", 201 PTR_ERR(ar_ahb->core_cold_rst)); 202 return PTR_ERR(ar_ahb->core_cold_rst); 203 } 204 205 ar_ahb->radio_cold_rst = devm_reset_control_get_exclusive(dev, 206 "wifi_radio_cold"); 207 if (IS_ERR(ar_ahb->radio_cold_rst)) { 208 ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n", 209 PTR_ERR(ar_ahb->radio_cold_rst)); 210 return PTR_ERR(ar_ahb->radio_cold_rst); 211 } 212 213 ar_ahb->radio_warm_rst = devm_reset_control_get_exclusive(dev, 214 "wifi_radio_warm"); 215 if (IS_ERR(ar_ahb->radio_warm_rst)) { 216 ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n", 217 PTR_ERR(ar_ahb->radio_warm_rst)); 218 return PTR_ERR(ar_ahb->radio_warm_rst); 219 } 220 221 ar_ahb->radio_srif_rst = devm_reset_control_get_exclusive(dev, 222 "wifi_radio_srif"); 223 if (IS_ERR(ar_ahb->radio_srif_rst)) { 224 ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n", 225 PTR_ERR(ar_ahb->radio_srif_rst)); 226 return PTR_ERR(ar_ahb->radio_srif_rst); 227 } 228 229 ar_ahb->cpu_init_rst = devm_reset_control_get_exclusive(dev, 230 "wifi_cpu_init"); 231 if (IS_ERR(ar_ahb->cpu_init_rst)) { 232 ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n", 233 PTR_ERR(ar_ahb->cpu_init_rst)); 234 return PTR_ERR(ar_ahb->cpu_init_rst); 235 } 236 237 return 0; 238 } 239 240 static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar) 241 { 242 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 243 244 ar_ahb->core_cold_rst = NULL; 245 ar_ahb->radio_cold_rst = NULL; 246 ar_ahb->radio_warm_rst = NULL; 247 ar_ahb->radio_srif_rst = NULL; 248 ar_ahb->cpu_init_rst = NULL; 249 } 250 251 static int ath10k_ahb_release_reset(struct ath10k *ar) 252 { 253 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 254 int ret; 255 256 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || 257 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || 258 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || 259 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { 260 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); 261 return -EINVAL; 262 } 263 264 ret = reset_control_deassert(ar_ahb->radio_cold_rst); 265 if (ret) { 266 ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret); 267 return ret; 268 } 269 270 ret = reset_control_deassert(ar_ahb->radio_warm_rst); 271 if (ret) { 272 ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret); 273 return ret; 274 } 275 276 ret = reset_control_deassert(ar_ahb->radio_srif_rst); 277 if (ret) { 278 ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret); 279 return ret; 280 } 281 282 ret = reset_control_deassert(ar_ahb->cpu_init_rst); 283 if (ret) { 284 ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret); 285 return ret; 286 } 287 288 return 0; 289 } 290 291 static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg, 292 u32 haltack_reg) 293 { 294 unsigned long timeout; 295 u32 val; 296 297 /* Issue halt axi bus request */ 298 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); 299 val |= AHB_AXI_BUS_HALT_REQ; 300 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); 301 302 /* Wait for axi bus halted ack */ 303 timeout = jiffies + msecs_to_jiffies(ATH10K_AHB_AXI_BUS_HALT_TIMEOUT); 304 do { 305 val = ath10k_ahb_tcsr_read32(ar, haltack_reg); 306 if (val & AHB_AXI_BUS_HALT_ACK) 307 break; 308 309 mdelay(1); 310 } while (time_before(jiffies, timeout)); 311 312 if (!(val & AHB_AXI_BUS_HALT_ACK)) { 313 ath10k_err(ar, "failed to halt axi bus: %d\n", val); 314 return; 315 } 316 317 ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n"); 318 } 319 320 static void ath10k_ahb_halt_chip(struct ath10k *ar) 321 { 322 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 323 u32 core_id, glb_cfg_reg, haltreq_reg, haltack_reg; 324 u32 val; 325 int ret; 326 327 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) || 328 IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || 329 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || 330 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || 331 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { 332 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); 333 return; 334 } 335 336 core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG); 337 338 switch (core_id) { 339 case 0: 340 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI0_GLB_CFG; 341 haltreq_reg = ATH10K_AHB_TCSR_WCSS0_HALTREQ; 342 haltack_reg = ATH10K_AHB_TCSR_WCSS0_HALTACK; 343 break; 344 case 1: 345 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI1_GLB_CFG; 346 haltreq_reg = ATH10K_AHB_TCSR_WCSS1_HALTREQ; 347 haltack_reg = ATH10K_AHB_TCSR_WCSS1_HALTACK; 348 break; 349 default: 350 ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n", 351 core_id); 352 return; 353 } 354 355 ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg); 356 357 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); 358 val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; 359 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); 360 361 ret = reset_control_assert(ar_ahb->core_cold_rst); 362 if (ret) 363 ath10k_err(ar, "failed to assert core cold rst: %d\n", ret); 364 msleep(1); 365 366 ret = reset_control_assert(ar_ahb->radio_cold_rst); 367 if (ret) 368 ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret); 369 msleep(1); 370 371 ret = reset_control_assert(ar_ahb->radio_warm_rst); 372 if (ret) 373 ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret); 374 msleep(1); 375 376 ret = reset_control_assert(ar_ahb->radio_srif_rst); 377 if (ret) 378 ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret); 379 msleep(1); 380 381 ret = reset_control_assert(ar_ahb->cpu_init_rst); 382 if (ret) 383 ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret); 384 msleep(10); 385 386 /* Clear halt req and core clock disable req before 387 * deasserting wifi core reset. 388 */ 389 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); 390 val &= ~AHB_AXI_BUS_HALT_REQ; 391 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); 392 393 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); 394 val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; 395 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); 396 397 ret = reset_control_deassert(ar_ahb->core_cold_rst); 398 if (ret) 399 ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret); 400 401 ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id); 402 } 403 404 static irqreturn_t ath10k_ahb_interrupt_handler(int irq, void *arg) 405 { 406 struct ath10k *ar = arg; 407 408 if (!ath10k_pci_irq_pending(ar)) 409 return IRQ_NONE; 410 411 ath10k_pci_disable_and_clear_legacy_irq(ar); 412 ath10k_pci_irq_msi_fw_mask(ar); 413 napi_schedule(&ar->napi); 414 415 return IRQ_HANDLED; 416 } 417 418 static int ath10k_ahb_request_irq_legacy(struct ath10k *ar) 419 { 420 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 421 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 422 int ret; 423 424 ret = request_irq(ar_ahb->irq, 425 ath10k_ahb_interrupt_handler, 426 IRQF_SHARED, "ath10k_ahb", ar); 427 if (ret) { 428 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 429 ar_ahb->irq, ret); 430 return ret; 431 } 432 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; 433 434 return 0; 435 } 436 437 static void ath10k_ahb_release_irq_legacy(struct ath10k *ar) 438 { 439 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 440 441 free_irq(ar_ahb->irq, ar); 442 } 443 444 static void ath10k_ahb_irq_disable(struct ath10k *ar) 445 { 446 ath10k_ce_disable_interrupts(ar); 447 ath10k_pci_disable_and_clear_legacy_irq(ar); 448 } 449 450 static int ath10k_ahb_resource_init(struct ath10k *ar) 451 { 452 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 453 struct platform_device *pdev; 454 struct device *dev; 455 struct resource *res; 456 int ret; 457 458 pdev = ar_ahb->pdev; 459 dev = &pdev->dev; 460 461 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 462 if (!res) { 463 ath10k_err(ar, "failed to get memory resource\n"); 464 ret = -ENXIO; 465 goto out; 466 } 467 468 ar_ahb->mem = devm_ioremap_resource(&pdev->dev, res); 469 if (IS_ERR(ar_ahb->mem)) { 470 ath10k_err(ar, "mem ioremap error\n"); 471 ret = PTR_ERR(ar_ahb->mem); 472 goto out; 473 } 474 475 ar_ahb->mem_len = resource_size(res); 476 477 ar_ahb->gcc_mem = ioremap_nocache(ATH10K_GCC_REG_BASE, 478 ATH10K_GCC_REG_SIZE); 479 if (!ar_ahb->gcc_mem) { 480 ath10k_err(ar, "gcc mem ioremap error\n"); 481 ret = -ENOMEM; 482 goto err_mem_unmap; 483 } 484 485 ar_ahb->tcsr_mem = ioremap_nocache(ATH10K_TCSR_REG_BASE, 486 ATH10K_TCSR_REG_SIZE); 487 if (!ar_ahb->tcsr_mem) { 488 ath10k_err(ar, "tcsr mem ioremap error\n"); 489 ret = -ENOMEM; 490 goto err_gcc_mem_unmap; 491 } 492 493 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 494 if (ret) { 495 ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret); 496 goto err_tcsr_mem_unmap; 497 } 498 499 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 500 if (ret) { 501 ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n", 502 ret); 503 goto err_tcsr_mem_unmap; 504 } 505 506 ret = ath10k_ahb_clock_init(ar); 507 if (ret) 508 goto err_tcsr_mem_unmap; 509 510 ret = ath10k_ahb_rst_ctrl_init(ar); 511 if (ret) 512 goto err_clock_deinit; 513 514 ar_ahb->irq = platform_get_irq_byname(pdev, "legacy"); 515 if (ar_ahb->irq < 0) { 516 ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq); 517 ret = ar_ahb->irq; 518 goto err_clock_deinit; 519 } 520 521 ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq); 522 523 ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n", 524 ar_ahb->mem, ar_ahb->mem_len, 525 ar_ahb->gcc_mem, ar_ahb->tcsr_mem); 526 return 0; 527 528 err_clock_deinit: 529 ath10k_ahb_clock_deinit(ar); 530 531 err_tcsr_mem_unmap: 532 iounmap(ar_ahb->tcsr_mem); 533 534 err_gcc_mem_unmap: 535 ar_ahb->tcsr_mem = NULL; 536 iounmap(ar_ahb->gcc_mem); 537 538 err_mem_unmap: 539 ar_ahb->gcc_mem = NULL; 540 devm_iounmap(&pdev->dev, ar_ahb->mem); 541 542 out: 543 ar_ahb->mem = NULL; 544 return ret; 545 } 546 547 static void ath10k_ahb_resource_deinit(struct ath10k *ar) 548 { 549 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 550 struct device *dev; 551 552 dev = &ar_ahb->pdev->dev; 553 554 if (ar_ahb->mem) 555 devm_iounmap(dev, ar_ahb->mem); 556 557 if (ar_ahb->gcc_mem) 558 iounmap(ar_ahb->gcc_mem); 559 560 if (ar_ahb->tcsr_mem) 561 iounmap(ar_ahb->tcsr_mem); 562 563 ar_ahb->mem = NULL; 564 ar_ahb->gcc_mem = NULL; 565 ar_ahb->tcsr_mem = NULL; 566 567 ath10k_ahb_clock_deinit(ar); 568 ath10k_ahb_rst_ctrl_deinit(ar); 569 } 570 571 static int ath10k_ahb_prepare_device(struct ath10k *ar) 572 { 573 u32 val; 574 int ret; 575 576 ret = ath10k_ahb_clock_enable(ar); 577 if (ret) { 578 ath10k_err(ar, "failed to enable clocks\n"); 579 return ret; 580 } 581 582 /* Clock for the target is supplied from outside of target (ie, 583 * external clock module controlled by the host). Target needs 584 * to know what frequency target cpu is configured which is needed 585 * for target internal use. Read target cpu frequency info from 586 * gcc register and write into target's scratch register where 587 * target expects this information. 588 */ 589 val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV); 590 ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val); 591 592 ret = ath10k_ahb_release_reset(ar); 593 if (ret) 594 goto err_clk_disable; 595 596 ath10k_ahb_irq_disable(ar); 597 598 ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); 599 600 ret = ath10k_pci_wait_for_target_init(ar); 601 if (ret) 602 goto err_halt_chip; 603 604 return 0; 605 606 err_halt_chip: 607 ath10k_ahb_halt_chip(ar); 608 609 err_clk_disable: 610 ath10k_ahb_clock_disable(ar); 611 612 return ret; 613 } 614 615 static int ath10k_ahb_chip_reset(struct ath10k *ar) 616 { 617 int ret; 618 619 ath10k_ahb_halt_chip(ar); 620 ath10k_ahb_clock_disable(ar); 621 622 ret = ath10k_ahb_prepare_device(ar); 623 if (ret) 624 return ret; 625 626 return 0; 627 } 628 629 static int ath10k_ahb_wake_target_cpu(struct ath10k *ar) 630 { 631 u32 addr, val; 632 633 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS; 634 val = ath10k_ahb_read32(ar, addr); 635 val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK; 636 ath10k_ahb_write32(ar, addr, val); 637 638 return 0; 639 } 640 641 static int ath10k_ahb_hif_start(struct ath10k *ar) 642 { 643 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n"); 644 645 napi_enable(&ar->napi); 646 ath10k_ce_enable_interrupts(ar); 647 ath10k_pci_enable_legacy_irq(ar); 648 649 ath10k_pci_rx_post(ar); 650 651 return 0; 652 } 653 654 static void ath10k_ahb_hif_stop(struct ath10k *ar) 655 { 656 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 657 658 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n"); 659 660 ath10k_ahb_irq_disable(ar); 661 synchronize_irq(ar_ahb->irq); 662 663 ath10k_pci_flush(ar); 664 665 napi_synchronize(&ar->napi); 666 napi_disable(&ar->napi); 667 } 668 669 static int ath10k_ahb_hif_power_up(struct ath10k *ar) 670 { 671 int ret; 672 673 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n"); 674 675 ret = ath10k_ahb_chip_reset(ar); 676 if (ret) { 677 ath10k_err(ar, "failed to reset chip: %d\n", ret); 678 goto out; 679 } 680 681 ret = ath10k_pci_init_pipes(ar); 682 if (ret) { 683 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 684 goto out; 685 } 686 687 ret = ath10k_pci_init_config(ar); 688 if (ret) { 689 ath10k_err(ar, "failed to setup init config: %d\n", ret); 690 goto err_ce_deinit; 691 } 692 693 ret = ath10k_ahb_wake_target_cpu(ar); 694 if (ret) { 695 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 696 goto err_ce_deinit; 697 } 698 699 return 0; 700 701 err_ce_deinit: 702 ath10k_pci_ce_deinit(ar); 703 out: 704 return ret; 705 } 706 707 static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 708 { 709 u32 val = 0, region = addr & 0xfffff; 710 711 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); 712 713 if (region >= QCA4019_SRAM_ADDR && region <= 714 (QCA4019_SRAM_ADDR + QCA4019_SRAM_LEN)) { 715 /* SRAM contents for QCA4019 can be directly accessed and 716 * no conversions are required 717 */ 718 val |= region; 719 } else { 720 val |= 0x100000 | region; 721 } 722 723 return val; 724 } 725 726 static const struct ath10k_hif_ops ath10k_ahb_hif_ops = { 727 .tx_sg = ath10k_pci_hif_tx_sg, 728 .diag_read = ath10k_pci_hif_diag_read, 729 .diag_write = ath10k_pci_diag_write_mem, 730 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 731 .start = ath10k_ahb_hif_start, 732 .stop = ath10k_ahb_hif_stop, 733 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 734 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 735 .send_complete_check = ath10k_pci_hif_send_complete_check, 736 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 737 .power_up = ath10k_ahb_hif_power_up, 738 .power_down = ath10k_pci_hif_power_down, 739 .read32 = ath10k_ahb_read32, 740 .write32 = ath10k_ahb_write32, 741 }; 742 743 static const struct ath10k_bus_ops ath10k_ahb_bus_ops = { 744 .read32 = ath10k_ahb_read32, 745 .write32 = ath10k_ahb_write32, 746 .get_num_banks = ath10k_ahb_get_num_banks, 747 }; 748 749 static int ath10k_ahb_probe(struct platform_device *pdev) 750 { 751 struct ath10k *ar; 752 struct ath10k_ahb *ar_ahb; 753 struct ath10k_pci *ar_pci; 754 const struct of_device_id *of_id; 755 enum ath10k_hw_rev hw_rev; 756 size_t size; 757 int ret; 758 u32 chip_id; 759 760 of_id = of_match_device(ath10k_ahb_of_match, &pdev->dev); 761 if (!of_id) { 762 dev_err(&pdev->dev, "failed to find matching device tree id\n"); 763 return -EINVAL; 764 } 765 766 hw_rev = (enum ath10k_hw_rev)of_id->data; 767 768 size = sizeof(*ar_pci) + sizeof(*ar_ahb); 769 ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB, 770 hw_rev, &ath10k_ahb_hif_ops); 771 if (!ar) { 772 dev_err(&pdev->dev, "failed to allocate core\n"); 773 return -ENOMEM; 774 } 775 776 ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n"); 777 778 ar_pci = ath10k_pci_priv(ar); 779 ar_ahb = ath10k_ahb_priv(ar); 780 781 ar_ahb->pdev = pdev; 782 platform_set_drvdata(pdev, ar); 783 784 ret = ath10k_ahb_resource_init(ar); 785 if (ret) 786 goto err_core_destroy; 787 788 ar->dev_id = 0; 789 ar_pci->mem = ar_ahb->mem; 790 ar_pci->mem_len = ar_ahb->mem_len; 791 ar_pci->ar = ar; 792 ar_pci->ce.bus_ops = &ath10k_ahb_bus_ops; 793 ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr; 794 ar->ce_priv = &ar_pci->ce; 795 796 ret = ath10k_pci_setup_resource(ar); 797 if (ret) { 798 ath10k_err(ar, "failed to setup resource: %d\n", ret); 799 goto err_resource_deinit; 800 } 801 802 ath10k_pci_init_napi(ar); 803 804 ret = ath10k_ahb_request_irq_legacy(ar); 805 if (ret) 806 goto err_free_pipes; 807 808 ret = ath10k_ahb_prepare_device(ar); 809 if (ret) 810 goto err_free_irq; 811 812 ath10k_pci_ce_deinit(ar); 813 814 chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 815 if (chip_id == 0xffffffff) { 816 ath10k_err(ar, "failed to get chip id\n"); 817 ret = -ENODEV; 818 goto err_halt_device; 819 } 820 821 ret = ath10k_core_register(ar, chip_id); 822 if (ret) { 823 ath10k_err(ar, "failed to register driver core: %d\n", ret); 824 goto err_halt_device; 825 } 826 827 return 0; 828 829 err_halt_device: 830 ath10k_ahb_halt_chip(ar); 831 ath10k_ahb_clock_disable(ar); 832 833 err_free_irq: 834 ath10k_ahb_release_irq_legacy(ar); 835 836 err_free_pipes: 837 ath10k_pci_free_pipes(ar); 838 839 err_resource_deinit: 840 ath10k_ahb_resource_deinit(ar); 841 842 err_core_destroy: 843 ath10k_core_destroy(ar); 844 platform_set_drvdata(pdev, NULL); 845 846 return ret; 847 } 848 849 static int ath10k_ahb_remove(struct platform_device *pdev) 850 { 851 struct ath10k *ar = platform_get_drvdata(pdev); 852 struct ath10k_ahb *ar_ahb; 853 854 if (!ar) 855 return -EINVAL; 856 857 ar_ahb = ath10k_ahb_priv(ar); 858 859 if (!ar_ahb) 860 return -EINVAL; 861 862 ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n"); 863 864 ath10k_core_unregister(ar); 865 ath10k_ahb_irq_disable(ar); 866 ath10k_ahb_release_irq_legacy(ar); 867 ath10k_pci_release_resource(ar); 868 ath10k_ahb_halt_chip(ar); 869 ath10k_ahb_clock_disable(ar); 870 ath10k_ahb_resource_deinit(ar); 871 ath10k_core_destroy(ar); 872 873 platform_set_drvdata(pdev, NULL); 874 875 return 0; 876 } 877 878 static struct platform_driver ath10k_ahb_driver = { 879 .driver = { 880 .name = "ath10k_ahb", 881 .of_match_table = ath10k_ahb_of_match, 882 }, 883 .probe = ath10k_ahb_probe, 884 .remove = ath10k_ahb_remove, 885 }; 886 887 int ath10k_ahb_init(void) 888 { 889 int ret; 890 891 ret = platform_driver_register(&ath10k_ahb_driver); 892 if (ret) 893 printk(KERN_ERR "failed to register ath10k ahb driver: %d\n", 894 ret); 895 return ret; 896 } 897 898 void ath10k_ahb_exit(void) 899 { 900 platform_driver_unregister(&ath10k_ahb_driver); 901 } 902