1 /* 2 * Copyright (c) 2016 Qualcomm Atheros, Inc. All rights reserved. 3 * Copyright (c) 2015 The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/clk.h> 21 #include <linux/reset.h> 22 #include "core.h" 23 #include "debug.h" 24 #include "pci.h" 25 #include "ahb.h" 26 27 static const struct of_device_id ath10k_ahb_of_match[] = { 28 { .compatible = "qcom,ipq4019-wifi", 29 .data = (void *)ATH10K_HW_QCA4019 30 }, 31 { } 32 }; 33 34 MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match); 35 36 static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar) 37 { 38 return &((struct ath10k_pci *)ar->drv_priv)->ahb[0]; 39 } 40 41 static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value) 42 { 43 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 44 45 iowrite32(value, ar_ahb->mem + offset); 46 } 47 48 static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset) 49 { 50 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 51 52 return ioread32(ar_ahb->mem + offset); 53 } 54 55 static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset) 56 { 57 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 58 59 return ioread32(ar_ahb->gcc_mem + offset); 60 } 61 62 static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value) 63 { 64 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 65 66 iowrite32(value, ar_ahb->tcsr_mem + offset); 67 } 68 69 static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset) 70 { 71 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 72 73 return ioread32(ar_ahb->tcsr_mem + offset); 74 } 75 76 static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr) 77 { 78 return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 79 } 80 81 static int ath10k_ahb_get_num_banks(struct ath10k *ar) 82 { 83 if (ar->hw_rev == ATH10K_HW_QCA4019) 84 return 1; 85 86 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 87 return 1; 88 } 89 90 static int ath10k_ahb_clock_init(struct ath10k *ar) 91 { 92 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 93 struct device *dev; 94 95 dev = &ar_ahb->pdev->dev; 96 97 ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd"); 98 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) { 99 ath10k_err(ar, "failed to get cmd clk: %ld\n", 100 PTR_ERR(ar_ahb->cmd_clk)); 101 return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV; 102 } 103 104 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref"); 105 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) { 106 ath10k_err(ar, "failed to get ref clk: %ld\n", 107 PTR_ERR(ar_ahb->ref_clk)); 108 return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV; 109 } 110 111 ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc"); 112 if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { 113 ath10k_err(ar, "failed to get rtc clk: %ld\n", 114 PTR_ERR(ar_ahb->rtc_clk)); 115 return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV; 116 } 117 118 return 0; 119 } 120 121 static void ath10k_ahb_clock_deinit(struct ath10k *ar) 122 { 123 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 124 125 ar_ahb->cmd_clk = NULL; 126 ar_ahb->ref_clk = NULL; 127 ar_ahb->rtc_clk = NULL; 128 } 129 130 static int ath10k_ahb_clock_enable(struct ath10k *ar) 131 { 132 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 133 struct device *dev; 134 int ret; 135 136 dev = &ar_ahb->pdev->dev; 137 138 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) || 139 IS_ERR_OR_NULL(ar_ahb->ref_clk) || 140 IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { 141 ath10k_err(ar, "clock(s) is/are not initialized\n"); 142 ret = -EIO; 143 goto out; 144 } 145 146 ret = clk_prepare_enable(ar_ahb->cmd_clk); 147 if (ret) { 148 ath10k_err(ar, "failed to enable cmd clk: %d\n", ret); 149 goto out; 150 } 151 152 ret = clk_prepare_enable(ar_ahb->ref_clk); 153 if (ret) { 154 ath10k_err(ar, "failed to enable ref clk: %d\n", ret); 155 goto err_cmd_clk_disable; 156 } 157 158 ret = clk_prepare_enable(ar_ahb->rtc_clk); 159 if (ret) { 160 ath10k_err(ar, "failed to enable rtc clk: %d\n", ret); 161 goto err_ref_clk_disable; 162 } 163 164 return 0; 165 166 err_ref_clk_disable: 167 clk_disable_unprepare(ar_ahb->ref_clk); 168 169 err_cmd_clk_disable: 170 clk_disable_unprepare(ar_ahb->cmd_clk); 171 172 out: 173 return ret; 174 } 175 176 static void ath10k_ahb_clock_disable(struct ath10k *ar) 177 { 178 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 179 180 if (!IS_ERR_OR_NULL(ar_ahb->cmd_clk)) 181 clk_disable_unprepare(ar_ahb->cmd_clk); 182 183 if (!IS_ERR_OR_NULL(ar_ahb->ref_clk)) 184 clk_disable_unprepare(ar_ahb->ref_clk); 185 186 if (!IS_ERR_OR_NULL(ar_ahb->rtc_clk)) 187 clk_disable_unprepare(ar_ahb->rtc_clk); 188 } 189 190 static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar) 191 { 192 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 193 struct device *dev; 194 195 dev = &ar_ahb->pdev->dev; 196 197 ar_ahb->core_cold_rst = devm_reset_control_get(dev, "wifi_core_cold"); 198 if (IS_ERR(ar_ahb->core_cold_rst)) { 199 ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n", 200 PTR_ERR(ar_ahb->core_cold_rst)); 201 return PTR_ERR(ar_ahb->core_cold_rst); 202 } 203 204 ar_ahb->radio_cold_rst = devm_reset_control_get(dev, "wifi_radio_cold"); 205 if (IS_ERR(ar_ahb->radio_cold_rst)) { 206 ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n", 207 PTR_ERR(ar_ahb->radio_cold_rst)); 208 return PTR_ERR(ar_ahb->radio_cold_rst); 209 } 210 211 ar_ahb->radio_warm_rst = devm_reset_control_get(dev, "wifi_radio_warm"); 212 if (IS_ERR(ar_ahb->radio_warm_rst)) { 213 ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n", 214 PTR_ERR(ar_ahb->radio_warm_rst)); 215 return PTR_ERR(ar_ahb->radio_warm_rst); 216 } 217 218 ar_ahb->radio_srif_rst = devm_reset_control_get(dev, "wifi_radio_srif"); 219 if (IS_ERR(ar_ahb->radio_srif_rst)) { 220 ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n", 221 PTR_ERR(ar_ahb->radio_srif_rst)); 222 return PTR_ERR(ar_ahb->radio_srif_rst); 223 } 224 225 ar_ahb->cpu_init_rst = devm_reset_control_get(dev, "wifi_cpu_init"); 226 if (IS_ERR(ar_ahb->cpu_init_rst)) { 227 ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n", 228 PTR_ERR(ar_ahb->cpu_init_rst)); 229 return PTR_ERR(ar_ahb->cpu_init_rst); 230 } 231 232 return 0; 233 } 234 235 static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar) 236 { 237 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 238 239 ar_ahb->core_cold_rst = NULL; 240 ar_ahb->radio_cold_rst = NULL; 241 ar_ahb->radio_warm_rst = NULL; 242 ar_ahb->radio_srif_rst = NULL; 243 ar_ahb->cpu_init_rst = NULL; 244 } 245 246 static int ath10k_ahb_release_reset(struct ath10k *ar) 247 { 248 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 249 int ret; 250 251 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || 252 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || 253 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || 254 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { 255 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); 256 return -EINVAL; 257 } 258 259 ret = reset_control_deassert(ar_ahb->radio_cold_rst); 260 if (ret) { 261 ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret); 262 return ret; 263 } 264 265 ret = reset_control_deassert(ar_ahb->radio_warm_rst); 266 if (ret) { 267 ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret); 268 return ret; 269 } 270 271 ret = reset_control_deassert(ar_ahb->radio_srif_rst); 272 if (ret) { 273 ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret); 274 return ret; 275 } 276 277 ret = reset_control_deassert(ar_ahb->cpu_init_rst); 278 if (ret) { 279 ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret); 280 return ret; 281 } 282 283 return 0; 284 } 285 286 static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg, 287 u32 haltack_reg) 288 { 289 unsigned long timeout; 290 u32 val; 291 292 /* Issue halt axi bus request */ 293 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); 294 val |= AHB_AXI_BUS_HALT_REQ; 295 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); 296 297 /* Wait for axi bus halted ack */ 298 timeout = jiffies + msecs_to_jiffies(ATH10K_AHB_AXI_BUS_HALT_TIMEOUT); 299 do { 300 val = ath10k_ahb_tcsr_read32(ar, haltack_reg); 301 if (val & AHB_AXI_BUS_HALT_ACK) 302 break; 303 304 mdelay(1); 305 } while (time_before(jiffies, timeout)); 306 307 if (!(val & AHB_AXI_BUS_HALT_ACK)) { 308 ath10k_err(ar, "failed to halt axi bus: %d\n", val); 309 return; 310 } 311 312 ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n"); 313 } 314 315 static void ath10k_ahb_halt_chip(struct ath10k *ar) 316 { 317 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 318 u32 core_id, glb_cfg_reg, haltreq_reg, haltack_reg; 319 u32 val; 320 int ret; 321 322 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) || 323 IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || 324 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || 325 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || 326 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { 327 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); 328 return; 329 } 330 331 core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG); 332 333 switch (core_id) { 334 case 0: 335 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI0_GLB_CFG; 336 haltreq_reg = ATH10K_AHB_TCSR_WCSS0_HALTREQ; 337 haltack_reg = ATH10K_AHB_TCSR_WCSS0_HALTACK; 338 break; 339 case 1: 340 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI1_GLB_CFG; 341 haltreq_reg = ATH10K_AHB_TCSR_WCSS1_HALTREQ; 342 haltack_reg = ATH10K_AHB_TCSR_WCSS1_HALTACK; 343 break; 344 default: 345 ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n", 346 core_id); 347 return; 348 } 349 350 ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg); 351 352 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); 353 val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; 354 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); 355 356 ret = reset_control_assert(ar_ahb->core_cold_rst); 357 if (ret) 358 ath10k_err(ar, "failed to assert core cold rst: %d\n", ret); 359 msleep(1); 360 361 ret = reset_control_assert(ar_ahb->radio_cold_rst); 362 if (ret) 363 ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret); 364 msleep(1); 365 366 ret = reset_control_assert(ar_ahb->radio_warm_rst); 367 if (ret) 368 ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret); 369 msleep(1); 370 371 ret = reset_control_assert(ar_ahb->radio_srif_rst); 372 if (ret) 373 ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret); 374 msleep(1); 375 376 ret = reset_control_assert(ar_ahb->cpu_init_rst); 377 if (ret) 378 ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret); 379 msleep(10); 380 381 /* Clear halt req and core clock disable req before 382 * deasserting wifi core reset. 383 */ 384 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); 385 val &= ~AHB_AXI_BUS_HALT_REQ; 386 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); 387 388 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); 389 val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; 390 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); 391 392 ret = reset_control_deassert(ar_ahb->core_cold_rst); 393 if (ret) 394 ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret); 395 396 ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id); 397 } 398 399 static irqreturn_t ath10k_ahb_interrupt_handler(int irq, void *arg) 400 { 401 struct ath10k *ar = arg; 402 403 if (!ath10k_pci_irq_pending(ar)) 404 return IRQ_NONE; 405 406 ath10k_pci_disable_and_clear_legacy_irq(ar); 407 ath10k_pci_irq_msi_fw_mask(ar); 408 napi_schedule(&ar->napi); 409 410 return IRQ_HANDLED; 411 } 412 413 static int ath10k_ahb_request_irq_legacy(struct ath10k *ar) 414 { 415 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 416 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 417 int ret; 418 419 ret = request_irq(ar_ahb->irq, 420 ath10k_ahb_interrupt_handler, 421 IRQF_SHARED, "ath10k_ahb", ar); 422 if (ret) { 423 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 424 ar_ahb->irq, ret); 425 return ret; 426 } 427 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; 428 429 return 0; 430 } 431 432 static void ath10k_ahb_release_irq_legacy(struct ath10k *ar) 433 { 434 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 435 436 free_irq(ar_ahb->irq, ar); 437 } 438 439 static void ath10k_ahb_irq_disable(struct ath10k *ar) 440 { 441 ath10k_ce_disable_interrupts(ar); 442 ath10k_pci_disable_and_clear_legacy_irq(ar); 443 } 444 445 static int ath10k_ahb_resource_init(struct ath10k *ar) 446 { 447 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 448 struct platform_device *pdev; 449 struct device *dev; 450 struct resource *res; 451 int ret; 452 453 pdev = ar_ahb->pdev; 454 dev = &pdev->dev; 455 456 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 457 if (!res) { 458 ath10k_err(ar, "failed to get memory resource\n"); 459 ret = -ENXIO; 460 goto out; 461 } 462 463 ar_ahb->mem = devm_ioremap_resource(&pdev->dev, res); 464 if (IS_ERR(ar_ahb->mem)) { 465 ath10k_err(ar, "mem ioremap error\n"); 466 ret = PTR_ERR(ar_ahb->mem); 467 goto out; 468 } 469 470 ar_ahb->mem_len = resource_size(res); 471 472 ar_ahb->gcc_mem = ioremap_nocache(ATH10K_GCC_REG_BASE, 473 ATH10K_GCC_REG_SIZE); 474 if (!ar_ahb->gcc_mem) { 475 ath10k_err(ar, "gcc mem ioremap error\n"); 476 ret = -ENOMEM; 477 goto err_mem_unmap; 478 } 479 480 ar_ahb->tcsr_mem = ioremap_nocache(ATH10K_TCSR_REG_BASE, 481 ATH10K_TCSR_REG_SIZE); 482 if (!ar_ahb->tcsr_mem) { 483 ath10k_err(ar, "tcsr mem ioremap error\n"); 484 ret = -ENOMEM; 485 goto err_gcc_mem_unmap; 486 } 487 488 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 489 if (ret) { 490 ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret); 491 goto err_tcsr_mem_unmap; 492 } 493 494 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 495 if (ret) { 496 ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n", 497 ret); 498 goto err_tcsr_mem_unmap; 499 } 500 501 ret = ath10k_ahb_clock_init(ar); 502 if (ret) 503 goto err_tcsr_mem_unmap; 504 505 ret = ath10k_ahb_rst_ctrl_init(ar); 506 if (ret) 507 goto err_clock_deinit; 508 509 ar_ahb->irq = platform_get_irq_byname(pdev, "legacy"); 510 if (ar_ahb->irq < 0) { 511 ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq); 512 ret = ar_ahb->irq; 513 goto err_clock_deinit; 514 } 515 516 ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq); 517 518 ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n", 519 ar_ahb->mem, ar_ahb->mem_len, 520 ar_ahb->gcc_mem, ar_ahb->tcsr_mem); 521 return 0; 522 523 err_clock_deinit: 524 ath10k_ahb_clock_deinit(ar); 525 526 err_tcsr_mem_unmap: 527 iounmap(ar_ahb->tcsr_mem); 528 529 err_gcc_mem_unmap: 530 ar_ahb->tcsr_mem = NULL; 531 iounmap(ar_ahb->gcc_mem); 532 533 err_mem_unmap: 534 ar_ahb->gcc_mem = NULL; 535 devm_iounmap(&pdev->dev, ar_ahb->mem); 536 537 out: 538 ar_ahb->mem = NULL; 539 return ret; 540 } 541 542 static void ath10k_ahb_resource_deinit(struct ath10k *ar) 543 { 544 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 545 struct device *dev; 546 547 dev = &ar_ahb->pdev->dev; 548 549 if (ar_ahb->mem) 550 devm_iounmap(dev, ar_ahb->mem); 551 552 if (ar_ahb->gcc_mem) 553 iounmap(ar_ahb->gcc_mem); 554 555 if (ar_ahb->tcsr_mem) 556 iounmap(ar_ahb->tcsr_mem); 557 558 ar_ahb->mem = NULL; 559 ar_ahb->gcc_mem = NULL; 560 ar_ahb->tcsr_mem = NULL; 561 562 ath10k_ahb_clock_deinit(ar); 563 ath10k_ahb_rst_ctrl_deinit(ar); 564 } 565 566 static int ath10k_ahb_prepare_device(struct ath10k *ar) 567 { 568 u32 val; 569 int ret; 570 571 ret = ath10k_ahb_clock_enable(ar); 572 if (ret) { 573 ath10k_err(ar, "failed to enable clocks\n"); 574 return ret; 575 } 576 577 /* Clock for the target is supplied from outside of target (ie, 578 * external clock module controlled by the host). Target needs 579 * to know what frequency target cpu is configured which is needed 580 * for target internal use. Read target cpu frequency info from 581 * gcc register and write into target's scratch register where 582 * target expects this information. 583 */ 584 val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV); 585 ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val); 586 587 ret = ath10k_ahb_release_reset(ar); 588 if (ret) 589 goto err_clk_disable; 590 591 ath10k_ahb_irq_disable(ar); 592 593 ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); 594 595 ret = ath10k_pci_wait_for_target_init(ar); 596 if (ret) 597 goto err_halt_chip; 598 599 return 0; 600 601 err_halt_chip: 602 ath10k_ahb_halt_chip(ar); 603 604 err_clk_disable: 605 ath10k_ahb_clock_disable(ar); 606 607 return ret; 608 } 609 610 static int ath10k_ahb_chip_reset(struct ath10k *ar) 611 { 612 int ret; 613 614 ath10k_ahb_halt_chip(ar); 615 ath10k_ahb_clock_disable(ar); 616 617 ret = ath10k_ahb_prepare_device(ar); 618 if (ret) 619 return ret; 620 621 return 0; 622 } 623 624 static int ath10k_ahb_wake_target_cpu(struct ath10k *ar) 625 { 626 u32 addr, val; 627 628 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS; 629 val = ath10k_ahb_read32(ar, addr); 630 val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK; 631 ath10k_ahb_write32(ar, addr, val); 632 633 return 0; 634 } 635 636 static int ath10k_ahb_hif_start(struct ath10k *ar) 637 { 638 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n"); 639 640 ath10k_ce_enable_interrupts(ar); 641 ath10k_pci_enable_legacy_irq(ar); 642 643 ath10k_pci_rx_post(ar); 644 645 return 0; 646 } 647 648 static void ath10k_ahb_hif_stop(struct ath10k *ar) 649 { 650 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 651 652 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n"); 653 654 ath10k_ahb_irq_disable(ar); 655 synchronize_irq(ar_ahb->irq); 656 657 ath10k_pci_flush(ar); 658 659 napi_synchronize(&ar->napi); 660 napi_disable(&ar->napi); 661 } 662 663 static int ath10k_ahb_hif_power_up(struct ath10k *ar) 664 { 665 int ret; 666 667 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n"); 668 669 ret = ath10k_ahb_chip_reset(ar); 670 if (ret) { 671 ath10k_err(ar, "failed to reset chip: %d\n", ret); 672 goto out; 673 } 674 675 ret = ath10k_pci_init_pipes(ar); 676 if (ret) { 677 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 678 goto out; 679 } 680 681 ret = ath10k_pci_init_config(ar); 682 if (ret) { 683 ath10k_err(ar, "failed to setup init config: %d\n", ret); 684 goto err_ce_deinit; 685 } 686 687 ret = ath10k_ahb_wake_target_cpu(ar); 688 if (ret) { 689 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 690 goto err_ce_deinit; 691 } 692 napi_enable(&ar->napi); 693 694 return 0; 695 696 err_ce_deinit: 697 ath10k_pci_ce_deinit(ar); 698 out: 699 return ret; 700 } 701 702 static const struct ath10k_hif_ops ath10k_ahb_hif_ops = { 703 .tx_sg = ath10k_pci_hif_tx_sg, 704 .diag_read = ath10k_pci_hif_diag_read, 705 .diag_write = ath10k_pci_diag_write_mem, 706 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 707 .start = ath10k_ahb_hif_start, 708 .stop = ath10k_ahb_hif_stop, 709 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 710 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 711 .send_complete_check = ath10k_pci_hif_send_complete_check, 712 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 713 .power_up = ath10k_ahb_hif_power_up, 714 .power_down = ath10k_pci_hif_power_down, 715 .read32 = ath10k_ahb_read32, 716 .write32 = ath10k_ahb_write32, 717 }; 718 719 static const struct ath10k_bus_ops ath10k_ahb_bus_ops = { 720 .read32 = ath10k_ahb_read32, 721 .write32 = ath10k_ahb_write32, 722 .get_num_banks = ath10k_ahb_get_num_banks, 723 }; 724 725 static int ath10k_ahb_probe(struct platform_device *pdev) 726 { 727 struct ath10k *ar; 728 struct ath10k_ahb *ar_ahb; 729 struct ath10k_pci *ar_pci; 730 const struct of_device_id *of_id; 731 enum ath10k_hw_rev hw_rev; 732 size_t size; 733 int ret; 734 u32 chip_id; 735 736 of_id = of_match_device(ath10k_ahb_of_match, &pdev->dev); 737 if (!of_id) { 738 dev_err(&pdev->dev, "failed to find matching device tree id\n"); 739 return -EINVAL; 740 } 741 742 hw_rev = (enum ath10k_hw_rev)of_id->data; 743 744 size = sizeof(*ar_pci) + sizeof(*ar_ahb); 745 ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB, 746 hw_rev, &ath10k_ahb_hif_ops); 747 if (!ar) { 748 dev_err(&pdev->dev, "failed to allocate core\n"); 749 return -ENOMEM; 750 } 751 752 ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n"); 753 754 ar_pci = ath10k_pci_priv(ar); 755 ar_ahb = ath10k_ahb_priv(ar); 756 757 ar_ahb->pdev = pdev; 758 platform_set_drvdata(pdev, ar); 759 760 ret = ath10k_ahb_resource_init(ar); 761 if (ret) 762 goto err_core_destroy; 763 764 ar->dev_id = 0; 765 ar_pci->mem = ar_ahb->mem; 766 ar_pci->mem_len = ar_ahb->mem_len; 767 ar_pci->ar = ar; 768 ar_pci->bus_ops = &ath10k_ahb_bus_ops; 769 770 ret = ath10k_pci_setup_resource(ar); 771 if (ret) { 772 ath10k_err(ar, "failed to setup resource: %d\n", ret); 773 goto err_resource_deinit; 774 } 775 776 ath10k_pci_init_napi(ar); 777 778 ret = ath10k_ahb_request_irq_legacy(ar); 779 if (ret) 780 goto err_free_pipes; 781 782 ret = ath10k_ahb_prepare_device(ar); 783 if (ret) 784 goto err_free_irq; 785 786 ath10k_pci_ce_deinit(ar); 787 788 chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 789 if (chip_id == 0xffffffff) { 790 ath10k_err(ar, "failed to get chip id\n"); 791 ret = -ENODEV; 792 goto err_halt_device; 793 } 794 795 ret = ath10k_core_register(ar, chip_id); 796 if (ret) { 797 ath10k_err(ar, "failed to register driver core: %d\n", ret); 798 goto err_halt_device; 799 } 800 801 return 0; 802 803 err_halt_device: 804 ath10k_ahb_halt_chip(ar); 805 ath10k_ahb_clock_disable(ar); 806 807 err_free_irq: 808 ath10k_ahb_release_irq_legacy(ar); 809 810 err_free_pipes: 811 ath10k_pci_free_pipes(ar); 812 813 err_resource_deinit: 814 ath10k_ahb_resource_deinit(ar); 815 816 err_core_destroy: 817 ath10k_core_destroy(ar); 818 platform_set_drvdata(pdev, NULL); 819 820 return ret; 821 } 822 823 static int ath10k_ahb_remove(struct platform_device *pdev) 824 { 825 struct ath10k *ar = platform_get_drvdata(pdev); 826 struct ath10k_ahb *ar_ahb; 827 828 if (!ar) 829 return -EINVAL; 830 831 ar_ahb = ath10k_ahb_priv(ar); 832 833 if (!ar_ahb) 834 return -EINVAL; 835 836 ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n"); 837 838 ath10k_core_unregister(ar); 839 ath10k_ahb_irq_disable(ar); 840 ath10k_ahb_release_irq_legacy(ar); 841 ath10k_pci_release_resource(ar); 842 ath10k_ahb_halt_chip(ar); 843 ath10k_ahb_clock_disable(ar); 844 ath10k_ahb_resource_deinit(ar); 845 ath10k_core_destroy(ar); 846 847 platform_set_drvdata(pdev, NULL); 848 849 return 0; 850 } 851 852 static struct platform_driver ath10k_ahb_driver = { 853 .driver = { 854 .name = "ath10k_ahb", 855 .of_match_table = ath10k_ahb_of_match, 856 }, 857 .probe = ath10k_ahb_probe, 858 .remove = ath10k_ahb_remove, 859 }; 860 861 int ath10k_ahb_init(void) 862 { 863 int ret; 864 865 ret = platform_driver_register(&ath10k_ahb_driver); 866 if (ret) 867 printk(KERN_ERR "failed to register ath10k ahb driver: %d\n", 868 ret); 869 return ret; 870 } 871 872 void ath10k_ahb_exit(void) 873 { 874 platform_driver_unregister(&ath10k_ahb_driver); 875 } 876