1 /* 2 * Copyright (c) 2016 Qualcomm Atheros, Inc. All rights reserved. 3 * Copyright (c) 2015 The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/clk.h> 21 #include <linux/reset.h> 22 #include "core.h" 23 #include "debug.h" 24 #include "pci.h" 25 #include "ahb.h" 26 27 static const struct of_device_id ath10k_ahb_of_match[] = { 28 /* TODO: enable this entry once everything in place. 29 * { .compatible = "qcom,ipq4019-wifi", 30 * .data = (void *)ATH10K_HW_QCA4019 }, 31 */ 32 { } 33 }; 34 35 MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match); 36 37 static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar) 38 { 39 return &((struct ath10k_pci *)ar->drv_priv)->ahb[0]; 40 } 41 42 static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value) 43 { 44 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 45 46 iowrite32(value, ar_ahb->mem + offset); 47 } 48 49 static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset) 50 { 51 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 52 53 return ioread32(ar_ahb->mem + offset); 54 } 55 56 static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset) 57 { 58 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 59 60 return ioread32(ar_ahb->gcc_mem + offset); 61 } 62 63 static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value) 64 { 65 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 66 67 iowrite32(value, ar_ahb->tcsr_mem + offset); 68 } 69 70 static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset) 71 { 72 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 73 74 return ioread32(ar_ahb->tcsr_mem + offset); 75 } 76 77 static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr) 78 { 79 return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 80 } 81 82 static int ath10k_ahb_get_num_banks(struct ath10k *ar) 83 { 84 if (ar->hw_rev == ATH10K_HW_QCA4019) 85 return 1; 86 87 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 88 return 1; 89 } 90 91 static int ath10k_ahb_clock_init(struct ath10k *ar) 92 { 93 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 94 struct device *dev; 95 int ret; 96 97 dev = &ar_ahb->pdev->dev; 98 99 ar_ahb->cmd_clk = clk_get(dev, "wifi_wcss_cmd"); 100 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) { 101 ath10k_err(ar, "failed to get cmd clk: %ld\n", 102 PTR_ERR(ar_ahb->cmd_clk)); 103 ret = ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV; 104 goto out; 105 } 106 107 ar_ahb->ref_clk = clk_get(dev, "wifi_wcss_ref"); 108 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) { 109 ath10k_err(ar, "failed to get ref clk: %ld\n", 110 PTR_ERR(ar_ahb->ref_clk)); 111 ret = ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV; 112 goto err_cmd_clk_put; 113 } 114 115 ar_ahb->rtc_clk = clk_get(dev, "wifi_wcss_rtc"); 116 if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { 117 ath10k_err(ar, "failed to get rtc clk: %ld\n", 118 PTR_ERR(ar_ahb->rtc_clk)); 119 ret = ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV; 120 goto err_ref_clk_put; 121 } 122 123 return 0; 124 125 err_ref_clk_put: 126 clk_put(ar_ahb->ref_clk); 127 128 err_cmd_clk_put: 129 clk_put(ar_ahb->cmd_clk); 130 131 out: 132 return ret; 133 } 134 135 static void ath10k_ahb_clock_deinit(struct ath10k *ar) 136 { 137 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 138 139 if (!IS_ERR_OR_NULL(ar_ahb->cmd_clk)) 140 clk_put(ar_ahb->cmd_clk); 141 142 if (!IS_ERR_OR_NULL(ar_ahb->ref_clk)) 143 clk_put(ar_ahb->ref_clk); 144 145 if (!IS_ERR_OR_NULL(ar_ahb->rtc_clk)) 146 clk_put(ar_ahb->rtc_clk); 147 148 ar_ahb->cmd_clk = NULL; 149 ar_ahb->ref_clk = NULL; 150 ar_ahb->rtc_clk = NULL; 151 } 152 153 static int ath10k_ahb_clock_enable(struct ath10k *ar) 154 { 155 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 156 struct device *dev; 157 int ret; 158 159 dev = &ar_ahb->pdev->dev; 160 161 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) || 162 IS_ERR_OR_NULL(ar_ahb->ref_clk) || 163 IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { 164 ath10k_err(ar, "clock(s) is/are not initialized\n"); 165 ret = -EIO; 166 goto out; 167 } 168 169 ret = clk_prepare_enable(ar_ahb->cmd_clk); 170 if (ret) { 171 ath10k_err(ar, "failed to enable cmd clk: %d\n", ret); 172 goto out; 173 } 174 175 ret = clk_prepare_enable(ar_ahb->ref_clk); 176 if (ret) { 177 ath10k_err(ar, "failed to enable ref clk: %d\n", ret); 178 goto err_cmd_clk_disable; 179 } 180 181 ret = clk_prepare_enable(ar_ahb->rtc_clk); 182 if (ret) { 183 ath10k_err(ar, "failed to enable rtc clk: %d\n", ret); 184 goto err_ref_clk_disable; 185 } 186 187 return 0; 188 189 err_ref_clk_disable: 190 clk_disable_unprepare(ar_ahb->ref_clk); 191 192 err_cmd_clk_disable: 193 clk_disable_unprepare(ar_ahb->cmd_clk); 194 195 out: 196 return ret; 197 } 198 199 static void ath10k_ahb_clock_disable(struct ath10k *ar) 200 { 201 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 202 203 if (!IS_ERR_OR_NULL(ar_ahb->cmd_clk)) 204 clk_disable_unprepare(ar_ahb->cmd_clk); 205 206 if (!IS_ERR_OR_NULL(ar_ahb->ref_clk)) 207 clk_disable_unprepare(ar_ahb->ref_clk); 208 209 if (!IS_ERR_OR_NULL(ar_ahb->rtc_clk)) 210 clk_disable_unprepare(ar_ahb->rtc_clk); 211 } 212 213 static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar) 214 { 215 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 216 struct device *dev; 217 int ret; 218 219 dev = &ar_ahb->pdev->dev; 220 221 ar_ahb->core_cold_rst = reset_control_get(dev, "wifi_core_cold"); 222 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst)) { 223 ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n", 224 PTR_ERR(ar_ahb->core_cold_rst)); 225 ret = ar_ahb->core_cold_rst ? 226 PTR_ERR(ar_ahb->core_cold_rst) : -ENODEV; 227 goto out; 228 } 229 230 ar_ahb->radio_cold_rst = reset_control_get(dev, "wifi_radio_cold"); 231 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst)) { 232 ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n", 233 PTR_ERR(ar_ahb->radio_cold_rst)); 234 ret = ar_ahb->radio_cold_rst ? 235 PTR_ERR(ar_ahb->radio_cold_rst) : -ENODEV; 236 goto err_core_cold_rst_put; 237 } 238 239 ar_ahb->radio_warm_rst = reset_control_get(dev, "wifi_radio_warm"); 240 if (IS_ERR_OR_NULL(ar_ahb->radio_warm_rst)) { 241 ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n", 242 PTR_ERR(ar_ahb->radio_warm_rst)); 243 ret = ar_ahb->radio_warm_rst ? 244 PTR_ERR(ar_ahb->radio_warm_rst) : -ENODEV; 245 goto err_radio_cold_rst_put; 246 } 247 248 ar_ahb->radio_srif_rst = reset_control_get(dev, "wifi_radio_srif"); 249 if (IS_ERR_OR_NULL(ar_ahb->radio_srif_rst)) { 250 ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n", 251 PTR_ERR(ar_ahb->radio_srif_rst)); 252 ret = ar_ahb->radio_srif_rst ? 253 PTR_ERR(ar_ahb->radio_srif_rst) : -ENODEV; 254 goto err_radio_warm_rst_put; 255 } 256 257 ar_ahb->cpu_init_rst = reset_control_get(dev, "wifi_cpu_init"); 258 if (IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { 259 ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n", 260 PTR_ERR(ar_ahb->cpu_init_rst)); 261 ret = ar_ahb->cpu_init_rst ? 262 PTR_ERR(ar_ahb->cpu_init_rst) : -ENODEV; 263 goto err_radio_srif_rst_put; 264 } 265 266 return 0; 267 268 err_radio_srif_rst_put: 269 reset_control_put(ar_ahb->radio_srif_rst); 270 271 err_radio_warm_rst_put: 272 reset_control_put(ar_ahb->radio_warm_rst); 273 274 err_radio_cold_rst_put: 275 reset_control_put(ar_ahb->radio_cold_rst); 276 277 err_core_cold_rst_put: 278 reset_control_put(ar_ahb->core_cold_rst); 279 280 out: 281 return ret; 282 } 283 284 static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar) 285 { 286 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 287 288 if (!IS_ERR_OR_NULL(ar_ahb->core_cold_rst)) 289 reset_control_put(ar_ahb->core_cold_rst); 290 291 if (!IS_ERR_OR_NULL(ar_ahb->radio_cold_rst)) 292 reset_control_put(ar_ahb->radio_cold_rst); 293 294 if (!IS_ERR_OR_NULL(ar_ahb->radio_warm_rst)) 295 reset_control_put(ar_ahb->radio_warm_rst); 296 297 if (!IS_ERR_OR_NULL(ar_ahb->radio_srif_rst)) 298 reset_control_put(ar_ahb->radio_srif_rst); 299 300 if (!IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) 301 reset_control_put(ar_ahb->cpu_init_rst); 302 303 ar_ahb->core_cold_rst = NULL; 304 ar_ahb->radio_cold_rst = NULL; 305 ar_ahb->radio_warm_rst = NULL; 306 ar_ahb->radio_srif_rst = NULL; 307 ar_ahb->cpu_init_rst = NULL; 308 } 309 310 static int ath10k_ahb_release_reset(struct ath10k *ar) 311 { 312 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 313 int ret; 314 315 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || 316 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || 317 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || 318 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { 319 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); 320 return -EINVAL; 321 } 322 323 ret = reset_control_deassert(ar_ahb->radio_cold_rst); 324 if (ret) { 325 ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret); 326 return ret; 327 } 328 329 ret = reset_control_deassert(ar_ahb->radio_warm_rst); 330 if (ret) { 331 ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret); 332 return ret; 333 } 334 335 ret = reset_control_deassert(ar_ahb->radio_srif_rst); 336 if (ret) { 337 ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret); 338 return ret; 339 } 340 341 ret = reset_control_deassert(ar_ahb->cpu_init_rst); 342 if (ret) { 343 ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret); 344 return ret; 345 } 346 347 return 0; 348 } 349 350 static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg, 351 u32 haltack_reg) 352 { 353 unsigned long timeout; 354 u32 val; 355 356 /* Issue halt axi bus request */ 357 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); 358 val |= AHB_AXI_BUS_HALT_REQ; 359 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); 360 361 /* Wait for axi bus halted ack */ 362 timeout = jiffies + msecs_to_jiffies(ATH10K_AHB_AXI_BUS_HALT_TIMEOUT); 363 do { 364 val = ath10k_ahb_tcsr_read32(ar, haltack_reg); 365 if (val & AHB_AXI_BUS_HALT_ACK) 366 break; 367 368 mdelay(1); 369 } while (time_before(jiffies, timeout)); 370 371 if (!(val & AHB_AXI_BUS_HALT_ACK)) { 372 ath10k_err(ar, "failed to halt axi bus: %d\n", val); 373 return; 374 } 375 376 ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n"); 377 } 378 379 static void ath10k_ahb_halt_chip(struct ath10k *ar) 380 { 381 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 382 u32 core_id, glb_cfg_reg, haltreq_reg, haltack_reg; 383 u32 val; 384 int ret; 385 386 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) || 387 IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || 388 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || 389 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || 390 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { 391 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); 392 return; 393 } 394 395 core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG); 396 397 switch (core_id) { 398 case 0: 399 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI0_GLB_CFG; 400 haltreq_reg = ATH10K_AHB_TCSR_WCSS0_HALTREQ; 401 haltack_reg = ATH10K_AHB_TCSR_WCSS0_HALTACK; 402 break; 403 case 1: 404 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI1_GLB_CFG; 405 haltreq_reg = ATH10K_AHB_TCSR_WCSS1_HALTREQ; 406 haltack_reg = ATH10K_AHB_TCSR_WCSS1_HALTACK; 407 break; 408 default: 409 ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n", 410 core_id); 411 return; 412 } 413 414 ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg); 415 416 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); 417 val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; 418 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); 419 420 ret = reset_control_assert(ar_ahb->core_cold_rst); 421 if (ret) 422 ath10k_err(ar, "failed to assert core cold rst: %d\n", ret); 423 msleep(1); 424 425 ret = reset_control_assert(ar_ahb->radio_cold_rst); 426 if (ret) 427 ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret); 428 msleep(1); 429 430 ret = reset_control_assert(ar_ahb->radio_warm_rst); 431 if (ret) 432 ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret); 433 msleep(1); 434 435 ret = reset_control_assert(ar_ahb->radio_srif_rst); 436 if (ret) 437 ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret); 438 msleep(1); 439 440 ret = reset_control_assert(ar_ahb->cpu_init_rst); 441 if (ret) 442 ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret); 443 msleep(10); 444 445 /* Clear halt req and core clock disable req before 446 * deasserting wifi core reset. 447 */ 448 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); 449 val &= ~AHB_AXI_BUS_HALT_REQ; 450 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); 451 452 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); 453 val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; 454 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); 455 456 ret = reset_control_deassert(ar_ahb->core_cold_rst); 457 if (ret) 458 ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret); 459 460 ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id); 461 } 462 463 static irqreturn_t ath10k_ahb_interrupt_handler(int irq, void *arg) 464 { 465 struct ath10k *ar = arg; 466 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 467 468 if (!ath10k_pci_irq_pending(ar)) 469 return IRQ_NONE; 470 471 ath10k_pci_disable_and_clear_legacy_irq(ar); 472 tasklet_schedule(&ar_pci->intr_tq); 473 474 return IRQ_HANDLED; 475 } 476 477 static int ath10k_ahb_request_irq_legacy(struct ath10k *ar) 478 { 479 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 480 int ret; 481 482 ret = request_irq(ar_ahb->irq, 483 ath10k_ahb_interrupt_handler, 484 IRQF_SHARED, "ath10k_ahb", ar); 485 if (ret) { 486 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 487 ar_ahb->irq, ret); 488 return ret; 489 } 490 491 return 0; 492 } 493 494 static void ath10k_ahb_release_irq_legacy(struct ath10k *ar) 495 { 496 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 497 498 free_irq(ar_ahb->irq, ar); 499 } 500 501 static void ath10k_ahb_irq_disable(struct ath10k *ar) 502 { 503 ath10k_ce_disable_interrupts(ar); 504 ath10k_pci_disable_and_clear_legacy_irq(ar); 505 } 506 507 static int ath10k_ahb_resource_init(struct ath10k *ar) 508 { 509 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 510 struct platform_device *pdev; 511 struct device *dev; 512 struct resource *res; 513 int ret; 514 515 pdev = ar_ahb->pdev; 516 dev = &pdev->dev; 517 518 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 519 if (!res) { 520 ath10k_err(ar, "failed to get memory resource\n"); 521 ret = -ENXIO; 522 goto out; 523 } 524 525 ar_ahb->mem = devm_ioremap_resource(&pdev->dev, res); 526 if (IS_ERR(ar_ahb->mem)) { 527 ath10k_err(ar, "mem ioremap error\n"); 528 ret = PTR_ERR(ar_ahb->mem); 529 goto out; 530 } 531 532 ar_ahb->mem_len = resource_size(res); 533 534 ar_ahb->gcc_mem = ioremap_nocache(ATH10K_GCC_REG_BASE, 535 ATH10K_GCC_REG_SIZE); 536 if (!ar_ahb->gcc_mem) { 537 ath10k_err(ar, "gcc mem ioremap error\n"); 538 ret = -ENOMEM; 539 goto err_mem_unmap; 540 } 541 542 ar_ahb->tcsr_mem = ioremap_nocache(ATH10K_TCSR_REG_BASE, 543 ATH10K_TCSR_REG_SIZE); 544 if (!ar_ahb->tcsr_mem) { 545 ath10k_err(ar, "tcsr mem ioremap error\n"); 546 ret = -ENOMEM; 547 goto err_gcc_mem_unmap; 548 } 549 550 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 551 if (ret) { 552 ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret); 553 goto err_tcsr_mem_unmap; 554 } 555 556 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 557 if (ret) { 558 ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n", 559 ret); 560 goto err_tcsr_mem_unmap; 561 } 562 563 ret = ath10k_ahb_clock_init(ar); 564 if (ret) 565 goto err_tcsr_mem_unmap; 566 567 ret = ath10k_ahb_rst_ctrl_init(ar); 568 if (ret) 569 goto err_clock_deinit; 570 571 ar_ahb->irq = platform_get_irq_byname(pdev, "legacy"); 572 if (ar_ahb->irq < 0) { 573 ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq); 574 goto err_clock_deinit; 575 } 576 577 ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq); 578 579 ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%p mem_len: %lu gcc mem: 0x%p tcsr_mem: 0x%p\n", 580 ar_ahb->mem, ar_ahb->mem_len, 581 ar_ahb->gcc_mem, ar_ahb->tcsr_mem); 582 return 0; 583 584 err_clock_deinit: 585 ath10k_ahb_clock_deinit(ar); 586 587 err_tcsr_mem_unmap: 588 iounmap(ar_ahb->tcsr_mem); 589 590 err_gcc_mem_unmap: 591 ar_ahb->tcsr_mem = NULL; 592 iounmap(ar_ahb->gcc_mem); 593 594 err_mem_unmap: 595 ar_ahb->gcc_mem = NULL; 596 devm_iounmap(&pdev->dev, ar_ahb->mem); 597 598 out: 599 ar_ahb->mem = NULL; 600 return ret; 601 } 602 603 static void ath10k_ahb_resource_deinit(struct ath10k *ar) 604 { 605 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 606 struct device *dev; 607 608 dev = &ar_ahb->pdev->dev; 609 610 if (ar_ahb->mem) 611 devm_iounmap(dev, ar_ahb->mem); 612 613 if (ar_ahb->gcc_mem) 614 iounmap(ar_ahb->gcc_mem); 615 616 if (ar_ahb->tcsr_mem) 617 iounmap(ar_ahb->tcsr_mem); 618 619 ar_ahb->mem = NULL; 620 ar_ahb->gcc_mem = NULL; 621 ar_ahb->tcsr_mem = NULL; 622 623 ath10k_ahb_clock_deinit(ar); 624 ath10k_ahb_rst_ctrl_deinit(ar); 625 } 626 627 static int ath10k_ahb_prepare_device(struct ath10k *ar) 628 { 629 u32 val; 630 int ret; 631 632 ret = ath10k_ahb_clock_enable(ar); 633 if (ret) { 634 ath10k_err(ar, "failed to enable clocks\n"); 635 return ret; 636 } 637 638 /* Clock for the target is supplied from outside of target (ie, 639 * external clock module controlled by the host). Target needs 640 * to know what frequency target cpu is configured which is needed 641 * for target internal use. Read target cpu frequency info from 642 * gcc register and write into target's scratch register where 643 * target expects this information. 644 */ 645 val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV); 646 ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val); 647 648 ret = ath10k_ahb_release_reset(ar); 649 if (ret) 650 goto err_clk_disable; 651 652 ath10k_ahb_irq_disable(ar); 653 654 ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); 655 656 ret = ath10k_pci_wait_for_target_init(ar); 657 if (ret) 658 goto err_halt_chip; 659 660 return 0; 661 662 err_halt_chip: 663 ath10k_ahb_halt_chip(ar); 664 665 err_clk_disable: 666 ath10k_ahb_clock_disable(ar); 667 668 return ret; 669 } 670 671 static int ath10k_ahb_chip_reset(struct ath10k *ar) 672 { 673 int ret; 674 675 ath10k_ahb_halt_chip(ar); 676 ath10k_ahb_clock_disable(ar); 677 678 ret = ath10k_ahb_prepare_device(ar); 679 if (ret) 680 return ret; 681 682 return 0; 683 } 684 685 static int ath10k_ahb_wake_target_cpu(struct ath10k *ar) 686 { 687 u32 addr, val; 688 689 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS; 690 val = ath10k_ahb_read32(ar, addr); 691 val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK; 692 ath10k_ahb_write32(ar, addr, val); 693 694 return 0; 695 } 696 697 static int ath10k_ahb_hif_start(struct ath10k *ar) 698 { 699 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n"); 700 701 ath10k_ce_enable_interrupts(ar); 702 ath10k_pci_enable_legacy_irq(ar); 703 704 ath10k_pci_rx_post(ar); 705 706 return 0; 707 } 708 709 static void ath10k_ahb_hif_stop(struct ath10k *ar) 710 { 711 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); 712 713 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n"); 714 715 ath10k_ahb_irq_disable(ar); 716 synchronize_irq(ar_ahb->irq); 717 718 ath10k_pci_flush(ar); 719 } 720 721 static int ath10k_ahb_hif_power_up(struct ath10k *ar) 722 { 723 int ret; 724 725 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n"); 726 727 ret = ath10k_ahb_chip_reset(ar); 728 if (ret) { 729 ath10k_err(ar, "failed to reset chip: %d\n", ret); 730 goto out; 731 } 732 733 ret = ath10k_pci_init_pipes(ar); 734 if (ret) { 735 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 736 goto out; 737 } 738 739 ret = ath10k_pci_init_config(ar); 740 if (ret) { 741 ath10k_err(ar, "failed to setup init config: %d\n", ret); 742 goto err_ce_deinit; 743 } 744 745 ret = ath10k_ahb_wake_target_cpu(ar); 746 if (ret) { 747 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 748 goto err_ce_deinit; 749 } 750 751 return 0; 752 753 err_ce_deinit: 754 ath10k_pci_ce_deinit(ar); 755 out: 756 return ret; 757 } 758 759 static const struct ath10k_hif_ops ath10k_ahb_hif_ops = { 760 .tx_sg = ath10k_pci_hif_tx_sg, 761 .diag_read = ath10k_pci_hif_diag_read, 762 .diag_write = ath10k_pci_diag_write_mem, 763 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 764 .start = ath10k_ahb_hif_start, 765 .stop = ath10k_ahb_hif_stop, 766 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 767 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 768 .send_complete_check = ath10k_pci_hif_send_complete_check, 769 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 770 .power_up = ath10k_ahb_hif_power_up, 771 .power_down = ath10k_pci_hif_power_down, 772 .read32 = ath10k_ahb_read32, 773 .write32 = ath10k_ahb_write32, 774 }; 775 776 static const struct ath10k_bus_ops ath10k_ahb_bus_ops = { 777 .read32 = ath10k_ahb_read32, 778 .write32 = ath10k_ahb_write32, 779 .get_num_banks = ath10k_ahb_get_num_banks, 780 }; 781 782 static int ath10k_ahb_probe(struct platform_device *pdev) 783 { 784 struct ath10k *ar; 785 struct ath10k_ahb *ar_ahb; 786 struct ath10k_pci *ar_pci; 787 const struct of_device_id *of_id; 788 enum ath10k_hw_rev hw_rev; 789 size_t size; 790 int ret; 791 u32 chip_id; 792 793 of_id = of_match_device(ath10k_ahb_of_match, &pdev->dev); 794 if (!of_id) { 795 dev_err(&pdev->dev, "failed to find matching device tree id\n"); 796 return -EINVAL; 797 } 798 799 hw_rev = (enum ath10k_hw_rev)of_id->data; 800 801 size = sizeof(*ar_pci) + sizeof(*ar_ahb); 802 ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB, 803 hw_rev, &ath10k_ahb_hif_ops); 804 if (!ar) { 805 dev_err(&pdev->dev, "failed to allocate core\n"); 806 return -ENOMEM; 807 } 808 809 ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n"); 810 811 ar_pci = ath10k_pci_priv(ar); 812 ar_ahb = ath10k_ahb_priv(ar); 813 814 ar_ahb->pdev = pdev; 815 platform_set_drvdata(pdev, ar); 816 817 ret = ath10k_ahb_resource_init(ar); 818 if (ret) 819 goto err_core_destroy; 820 821 ar->dev_id = 0; 822 ar_pci->mem = ar_ahb->mem; 823 ar_pci->mem_len = ar_ahb->mem_len; 824 ar_pci->ar = ar; 825 ar_pci->bus_ops = &ath10k_ahb_bus_ops; 826 827 ret = ath10k_pci_setup_resource(ar); 828 if (ret) { 829 ath10k_err(ar, "failed to setup resource: %d\n", ret); 830 goto err_resource_deinit; 831 } 832 833 ath10k_pci_init_irq_tasklets(ar); 834 835 ret = ath10k_ahb_request_irq_legacy(ar); 836 if (ret) 837 goto err_free_pipes; 838 839 ret = ath10k_ahb_prepare_device(ar); 840 if (ret) 841 goto err_free_irq; 842 843 ath10k_pci_ce_deinit(ar); 844 845 chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 846 if (chip_id == 0xffffffff) { 847 ath10k_err(ar, "failed to get chip id\n"); 848 goto err_halt_device; 849 } 850 851 ret = ath10k_core_register(ar, chip_id); 852 if (ret) { 853 ath10k_err(ar, "failed to register driver core: %d\n", ret); 854 goto err_halt_device; 855 } 856 857 return 0; 858 859 err_halt_device: 860 ath10k_ahb_halt_chip(ar); 861 ath10k_ahb_clock_disable(ar); 862 863 err_free_irq: 864 ath10k_ahb_release_irq_legacy(ar); 865 866 err_free_pipes: 867 ath10k_pci_free_pipes(ar); 868 869 err_resource_deinit: 870 ath10k_ahb_resource_deinit(ar); 871 872 err_core_destroy: 873 ath10k_core_destroy(ar); 874 platform_set_drvdata(pdev, NULL); 875 876 return ret; 877 } 878 879 static int ath10k_ahb_remove(struct platform_device *pdev) 880 { 881 struct ath10k *ar = platform_get_drvdata(pdev); 882 struct ath10k_ahb *ar_ahb; 883 884 if (!ar) 885 return -EINVAL; 886 887 ar_ahb = ath10k_ahb_priv(ar); 888 889 if (!ar_ahb) 890 return -EINVAL; 891 892 ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n"); 893 894 ath10k_core_unregister(ar); 895 ath10k_ahb_irq_disable(ar); 896 ath10k_ahb_release_irq_legacy(ar); 897 ath10k_pci_release_resource(ar); 898 ath10k_ahb_halt_chip(ar); 899 ath10k_ahb_clock_disable(ar); 900 ath10k_ahb_resource_deinit(ar); 901 ath10k_core_destroy(ar); 902 903 platform_set_drvdata(pdev, NULL); 904 905 return 0; 906 } 907 908 static struct platform_driver ath10k_ahb_driver = { 909 .driver = { 910 .name = "ath10k_ahb", 911 .of_match_table = ath10k_ahb_of_match, 912 }, 913 .probe = ath10k_ahb_probe, 914 .remove = ath10k_ahb_remove, 915 }; 916 917 int ath10k_ahb_init(void) 918 { 919 int ret; 920 921 printk(KERN_ERR "AHB support is still work in progress\n"); 922 923 ret = platform_driver_register(&ath10k_ahb_driver); 924 if (ret) 925 printk(KERN_ERR "failed to register ath10k ahb driver: %d\n", 926 ret); 927 return ret; 928 } 929 930 void ath10k_ahb_exit(void) 931 { 932 platform_driver_unregister(&ath10k_ahb_driver); 933 } 934