1b7d572e1SPontus Fuchs /* 2b7d572e1SPontus Fuchs * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr> 3b7d572e1SPontus Fuchs * Copyright (c) 2006 Sam Leffler, Errno Consulting 4b7d572e1SPontus Fuchs * Copyright (c) 2007 Christoph Hellwig <hch@lst.de> 5b7d572e1SPontus Fuchs * Copyright (c) 2008-2009 Weongyo Jeong <weongyo@freebsd.org> 6b7d572e1SPontus Fuchs * Copyright (c) 2012 Pontus Fuchs <pontus.fuchs@gmail.com> 7b7d572e1SPontus Fuchs * 8b7d572e1SPontus Fuchs * Permission to use, copy, modify, and/or distribute this software for any 9b7d572e1SPontus Fuchs * purpose with or without fee is hereby granted, provided that the above 10b7d572e1SPontus Fuchs * copyright notice and this permission notice appear in all copies. 11b7d572e1SPontus Fuchs * 12b7d572e1SPontus Fuchs * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13b7d572e1SPontus Fuchs * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14b7d572e1SPontus Fuchs * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15b7d572e1SPontus Fuchs * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16b7d572e1SPontus Fuchs * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17b7d572e1SPontus Fuchs * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18b7d572e1SPontus Fuchs * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19b7d572e1SPontus Fuchs */ 20b7d572e1SPontus Fuchs 21b7d572e1SPontus Fuchs /* all fields are big endian */ 22b7d572e1SPontus Fuchs struct ar5523_fwblock { 23b7d572e1SPontus Fuchs __be32 flags; 24b7d572e1SPontus Fuchs #define AR5523_WRITE_BLOCK (1 << 4) 25b7d572e1SPontus Fuchs 26b7d572e1SPontus Fuchs __be32 len; 27b7d572e1SPontus Fuchs #define AR5523_MAX_FWBLOCK_SIZE 2048 28b7d572e1SPontus Fuchs 29b7d572e1SPontus Fuchs __be32 total; 30b7d572e1SPontus Fuchs __be32 remain; 31b7d572e1SPontus Fuchs __be32 rxtotal; 32b7d572e1SPontus Fuchs __be32 pad[123]; 33b7d572e1SPontus Fuchs } __packed; 34b7d572e1SPontus Fuchs 35b7d572e1SPontus Fuchs #define AR5523_MAX_RXCMDSZ 1024 36b7d572e1SPontus Fuchs #define AR5523_MAX_TXCMDSZ 1024 37b7d572e1SPontus Fuchs 38b7d572e1SPontus Fuchs struct ar5523_cmd_hdr { 39b7d572e1SPontus Fuchs __be32 len; 40b7d572e1SPontus Fuchs __be32 code; 41b7d572e1SPontus Fuchs /* NB: these are defined for rev 1.5 firmware; rev 1.6 is different */ 42b7d572e1SPontus Fuchs /* messages from Host -> Target */ 43b7d572e1SPontus Fuchs #define WDCMSG_HOST_AVAILABLE 0x01 44b7d572e1SPontus Fuchs #define WDCMSG_BIND 0x02 45b7d572e1SPontus Fuchs #define WDCMSG_TARGET_RESET 0x03 46b7d572e1SPontus Fuchs #define WDCMSG_TARGET_GET_CAPABILITY 0x04 47b7d572e1SPontus Fuchs #define WDCMSG_TARGET_SET_CONFIG 0x05 48b7d572e1SPontus Fuchs #define WDCMSG_TARGET_GET_STATUS 0x06 49b7d572e1SPontus Fuchs #define WDCMSG_TARGET_GET_STATS 0x07 50b7d572e1SPontus Fuchs #define WDCMSG_TARGET_START 0x08 51b7d572e1SPontus Fuchs #define WDCMSG_TARGET_STOP 0x09 52b7d572e1SPontus Fuchs #define WDCMSG_TARGET_ENABLE 0x0a 53b7d572e1SPontus Fuchs #define WDCMSG_TARGET_DISABLE 0x0b 54b7d572e1SPontus Fuchs #define WDCMSG_CREATE_CONNECTION 0x0c 55b7d572e1SPontus Fuchs #define WDCMSG_UPDATE_CONNECT_ATTR 0x0d 56b7d572e1SPontus Fuchs #define WDCMSG_DELETE_CONNECT 0x0e 57b7d572e1SPontus Fuchs #define WDCMSG_SEND 0x0f 58b7d572e1SPontus Fuchs #define WDCMSG_FLUSH 0x10 59b7d572e1SPontus Fuchs /* messages from Target -> Host */ 60b7d572e1SPontus Fuchs #define WDCMSG_STATS_UPDATE 0x11 61b7d572e1SPontus Fuchs #define WDCMSG_BMISS 0x12 62b7d572e1SPontus Fuchs #define WDCMSG_DEVICE_AVAIL 0x13 63b7d572e1SPontus Fuchs #define WDCMSG_SEND_COMPLETE 0x14 64b7d572e1SPontus Fuchs #define WDCMSG_DATA_AVAIL 0x15 65b7d572e1SPontus Fuchs #define WDCMSG_SET_PWR_MODE 0x16 66b7d572e1SPontus Fuchs #define WDCMSG_BMISS_ACK 0x17 67b7d572e1SPontus Fuchs #define WDCMSG_SET_LED_STEADY 0x18 68b7d572e1SPontus Fuchs #define WDCMSG_SET_LED_BLINK 0x19 69b7d572e1SPontus Fuchs /* more messages */ 70b7d572e1SPontus Fuchs #define WDCMSG_SETUP_BEACON_DESC 0x1a 71b7d572e1SPontus Fuchs #define WDCMSG_BEACON_INIT 0x1b 72b7d572e1SPontus Fuchs #define WDCMSG_RESET_KEY_CACHE 0x1c 73b7d572e1SPontus Fuchs #define WDCMSG_RESET_KEY_CACHE_ENTRY 0x1d 74b7d572e1SPontus Fuchs #define WDCMSG_SET_KEY_CACHE_ENTRY 0x1e 75b7d572e1SPontus Fuchs #define WDCMSG_SET_DECOMP_MASK 0x1f 76b7d572e1SPontus Fuchs #define WDCMSG_SET_REGULATORY_DOMAIN 0x20 77b7d572e1SPontus Fuchs #define WDCMSG_SET_LED_STATE 0x21 78b7d572e1SPontus Fuchs #define WDCMSG_WRITE_ASSOCID 0x22 79b7d572e1SPontus Fuchs #define WDCMSG_SET_STA_BEACON_TIMERS 0x23 80b7d572e1SPontus Fuchs #define WDCMSG_GET_TSF 0x24 81b7d572e1SPontus Fuchs #define WDCMSG_RESET_TSF 0x25 82b7d572e1SPontus Fuchs #define WDCMSG_SET_ADHOC_MODE 0x26 83b7d572e1SPontus Fuchs #define WDCMSG_SET_BASIC_RATE 0x27 84b7d572e1SPontus Fuchs #define WDCMSG_MIB_CONTROL 0x28 85b7d572e1SPontus Fuchs #define WDCMSG_GET_CHANNEL_DATA 0x29 86b7d572e1SPontus Fuchs #define WDCMSG_GET_CUR_RSSI 0x2a 87b7d572e1SPontus Fuchs #define WDCMSG_SET_ANTENNA_SWITCH 0x2b 88b7d572e1SPontus Fuchs #define WDCMSG_USE_SHORT_SLOT_TIME 0x2f 89b7d572e1SPontus Fuchs #define WDCMSG_SET_POWER_MODE 0x30 90b7d572e1SPontus Fuchs #define WDCMSG_SETUP_PSPOLL_DESC 0x31 91b7d572e1SPontus Fuchs #define WDCMSG_SET_RX_MULTICAST_FILTER 0x32 92b7d572e1SPontus Fuchs #define WDCMSG_RX_FILTER 0x33 93b7d572e1SPontus Fuchs #define WDCMSG_PER_CALIBRATION 0x34 94b7d572e1SPontus Fuchs #define WDCMSG_RESET 0x35 95b7d572e1SPontus Fuchs #define WDCMSG_DISABLE 0x36 96b7d572e1SPontus Fuchs #define WDCMSG_PHY_DISABLE 0x37 97b7d572e1SPontus Fuchs #define WDCMSG_SET_TX_POWER_LIMIT 0x38 98b7d572e1SPontus Fuchs #define WDCMSG_SET_TX_QUEUE_PARAMS 0x39 99b7d572e1SPontus Fuchs #define WDCMSG_SETUP_TX_QUEUE 0x3a 100b7d572e1SPontus Fuchs #define WDCMSG_RELEASE_TX_QUEUE 0x3b 101b7d572e1SPontus Fuchs #define WDCMSG_SET_DEFAULT_KEY 0x43 102b7d572e1SPontus Fuchs 103b7d572e1SPontus Fuchs __u32 priv; /* driver private data, 104b7d572e1SPontus Fuchs don't care about endianess */ 105b7d572e1SPontus Fuchs __be32 magic; 106b7d572e1SPontus Fuchs __be32 reserved2[4]; 107b7d572e1SPontus Fuchs }; 108b7d572e1SPontus Fuchs 109b7d572e1SPontus Fuchs struct ar5523_cmd_host_available { 110b7d572e1SPontus Fuchs __be32 sw_ver_major; 111b7d572e1SPontus Fuchs __be32 sw_ver_minor; 112b7d572e1SPontus Fuchs __be32 sw_ver_patch; 113b7d572e1SPontus Fuchs __be32 sw_ver_build; 114b7d572e1SPontus Fuchs } __packed; 115b7d572e1SPontus Fuchs 116b7d572e1SPontus Fuchs #define ATH_SW_VER_MAJOR 1 117b7d572e1SPontus Fuchs #define ATH_SW_VER_MINOR 5 118b7d572e1SPontus Fuchs #define ATH_SW_VER_PATCH 0 119b7d572e1SPontus Fuchs #define ATH_SW_VER_BUILD 9999 120b7d572e1SPontus Fuchs 121b7d572e1SPontus Fuchs struct ar5523_chunk { 122b7d572e1SPontus Fuchs u8 seqnum; /* sequence number for ordering */ 123b7d572e1SPontus Fuchs u8 flags; 124b7d572e1SPontus Fuchs #define UATH_CFLAGS_FINAL 0x01 /* final chunk of a msg */ 125b7d572e1SPontus Fuchs #define UATH_CFLAGS_RXMSG 0x02 /* chunk contains rx completion */ 126b7d572e1SPontus Fuchs #define UATH_CFLAGS_DEBUG 0x04 /* for debugging */ 127b7d572e1SPontus Fuchs __be16 length; /* chunk size in bytes */ 128b7d572e1SPontus Fuchs /* chunk data follows */ 129b7d572e1SPontus Fuchs } __packed; 130b7d572e1SPontus Fuchs 131b7d572e1SPontus Fuchs /* 132b7d572e1SPontus Fuchs * Message format for a WDCMSG_DATA_AVAIL message from Target to Host. 133b7d572e1SPontus Fuchs */ 134b7d572e1SPontus Fuchs struct ar5523_rx_desc { 135b7d572e1SPontus Fuchs __be32 len; /* msg length including header */ 136b7d572e1SPontus Fuchs __be32 code; /* WDCMSG_DATA_AVAIL */ 137b7d572e1SPontus Fuchs __be32 gennum; /* generation number */ 138b7d572e1SPontus Fuchs __be32 status; /* start of RECEIVE_INFO */ 139b7d572e1SPontus Fuchs #define UATH_STATUS_OK 0 140b7d572e1SPontus Fuchs #define UATH_STATUS_STOP_IN_PROGRESS 1 141b7d572e1SPontus Fuchs #define UATH_STATUS_CRC_ERR 2 142b7d572e1SPontus Fuchs #define UATH_STATUS_PHY_ERR 3 143b7d572e1SPontus Fuchs #define UATH_STATUS_DECRYPT_CRC_ERR 4 144b7d572e1SPontus Fuchs #define UATH_STATUS_DECRYPT_MIC_ERR 5 145b7d572e1SPontus Fuchs #define UATH_STATUS_DECOMP_ERR 6 146b7d572e1SPontus Fuchs #define UATH_STATUS_KEY_ERR 7 147b7d572e1SPontus Fuchs #define UATH_STATUS_ERR 8 148b7d572e1SPontus Fuchs __be32 tstamp_low; /* low-order 32-bits of rx timestamp */ 149b7d572e1SPontus Fuchs __be32 tstamp_high; /* high-order 32-bits of rx timestamp */ 150b7d572e1SPontus Fuchs __be32 framelen; /* frame length */ 151b7d572e1SPontus Fuchs __be32 rate; /* rx rate code */ 152b7d572e1SPontus Fuchs __be32 antenna; 153b7d572e1SPontus Fuchs __be32 rssi; 154b7d572e1SPontus Fuchs __be32 channel; 155b7d572e1SPontus Fuchs __be32 phyerror; 156b7d572e1SPontus Fuchs __be32 connix; /* key table ix for bss traffic */ 157b7d572e1SPontus Fuchs __be32 decrypterror; 158b7d572e1SPontus Fuchs __be32 keycachemiss; 159b7d572e1SPontus Fuchs __be32 pad; /* XXX? */ 160b7d572e1SPontus Fuchs } __packed; 161b7d572e1SPontus Fuchs 162b7d572e1SPontus Fuchs struct ar5523_tx_desc { 163b7d572e1SPontus Fuchs __be32 msglen; 164d01a303eSPontus Fuchs u32 msgid; /* msg id (supplied by host) */ 165b7d572e1SPontus Fuchs __be32 type; /* opcode: WDMSG_SEND or WDCMSG_FLUSH */ 166b7d572e1SPontus Fuchs __be32 txqid; /* tx queue id and flags */ 167b7d572e1SPontus Fuchs #define UATH_TXQID_MASK 0x0f 168b7d572e1SPontus Fuchs #define UATH_TXQID_MINRATE 0x10 /* use min tx rate */ 169b7d572e1SPontus Fuchs #define UATH_TXQID_FF 0x20 /* content is fast frame */ 170b7d572e1SPontus Fuchs __be32 connid; /* tx connection id */ 171b7d572e1SPontus Fuchs #define UATH_ID_INVALID 0xffffffff /* for sending prior to connection */ 172b7d572e1SPontus Fuchs __be32 flags; /* non-zero if response desired */ 173b7d572e1SPontus Fuchs #define UATH_TX_NOTIFY (1 << 24) /* f/w will send a UATH_NOTIF_TX */ 174b7d572e1SPontus Fuchs __be32 buflen; /* payload length */ 175b7d572e1SPontus Fuchs } __packed; 176b7d572e1SPontus Fuchs 177b7d572e1SPontus Fuchs 178b7d572e1SPontus Fuchs #define AR5523_ID_BSS 2 179b7d572e1SPontus Fuchs #define AR5523_ID_BROADCAST 0xffffffff 180b7d572e1SPontus Fuchs 181b7d572e1SPontus Fuchs /* structure for command UATH_CMD_WRITE_MAC */ 182b7d572e1SPontus Fuchs struct ar5523_write_mac { 183b7d572e1SPontus Fuchs __be32 reg; 184b7d572e1SPontus Fuchs __be32 len; 185b7d572e1SPontus Fuchs u8 data[32]; 186b7d572e1SPontus Fuchs } __packed; 187b7d572e1SPontus Fuchs 188b7d572e1SPontus Fuchs struct ar5523_cmd_rateset { 189b7d572e1SPontus Fuchs __u8 length; 190b7d572e1SPontus Fuchs #define AR5523_MAX_NRATES 32 191b7d572e1SPontus Fuchs __u8 set[AR5523_MAX_NRATES]; 192b7d572e1SPontus Fuchs }; 193b7d572e1SPontus Fuchs 194b7d572e1SPontus Fuchs struct ar5523_cmd_set_associd { /* AR5523_WRITE_ASSOCID */ 195b7d572e1SPontus Fuchs __be32 defaultrateix; 196b7d572e1SPontus Fuchs __be32 associd; 197b7d572e1SPontus Fuchs __be32 timoffset; 198b7d572e1SPontus Fuchs __be32 turboprime; 199b7d572e1SPontus Fuchs __u8 bssid[6]; 200b7d572e1SPontus Fuchs } __packed; 201b7d572e1SPontus Fuchs 202b7d572e1SPontus Fuchs /* structure for command WDCMSG_RESET */ 203b7d572e1SPontus Fuchs struct ar5523_cmd_reset { 204b7d572e1SPontus Fuchs __be32 flags; /* channel flags */ 205b7d572e1SPontus Fuchs #define UATH_CHAN_TURBO 0x0100 206b7d572e1SPontus Fuchs #define UATH_CHAN_CCK 0x0200 207b7d572e1SPontus Fuchs #define UATH_CHAN_OFDM 0x0400 208b7d572e1SPontus Fuchs #define UATH_CHAN_2GHZ 0x1000 209b7d572e1SPontus Fuchs #define UATH_CHAN_5GHZ 0x2000 210b7d572e1SPontus Fuchs __be32 freq; /* channel frequency */ 211b7d572e1SPontus Fuchs __be32 maxrdpower; 212b7d572e1SPontus Fuchs __be32 cfgctl; 213b7d572e1SPontus Fuchs __be32 twiceantennareduction; 214b7d572e1SPontus Fuchs __be32 channelchange; 215b7d572e1SPontus Fuchs __be32 keeprccontent; 216b7d572e1SPontus Fuchs } __packed; 217b7d572e1SPontus Fuchs 218b7d572e1SPontus Fuchs /* structure for command WDCMSG_SET_BASIC_RATE */ 219b7d572e1SPontus Fuchs struct ar5523_cmd_rates { 220b7d572e1SPontus Fuchs __be32 connid; 221b7d572e1SPontus Fuchs __be32 keeprccontent; 222b7d572e1SPontus Fuchs __be32 size; 223b7d572e1SPontus Fuchs struct ar5523_cmd_rateset rateset; 224b7d572e1SPontus Fuchs } __packed; 225b7d572e1SPontus Fuchs 226b7d572e1SPontus Fuchs enum { 227b7d572e1SPontus Fuchs WLAN_MODE_NONE = 0, 228b7d572e1SPontus Fuchs WLAN_MODE_11b, 229b7d572e1SPontus Fuchs WLAN_MODE_11a, 230b7d572e1SPontus Fuchs WLAN_MODE_11g, 231b7d572e1SPontus Fuchs WLAN_MODE_11a_TURBO, 232b7d572e1SPontus Fuchs WLAN_MODE_11g_TURBO, 233b7d572e1SPontus Fuchs WLAN_MODE_11a_TURBO_PRIME, 234b7d572e1SPontus Fuchs WLAN_MODE_11g_TURBO_PRIME, 235b7d572e1SPontus Fuchs WLAN_MODE_11a_XR, 236b7d572e1SPontus Fuchs WLAN_MODE_11g_XR, 237b7d572e1SPontus Fuchs }; 238b7d572e1SPontus Fuchs 239b7d572e1SPontus Fuchs struct ar5523_cmd_connection_attr { 240b7d572e1SPontus Fuchs __be32 longpreambleonly; 241b7d572e1SPontus Fuchs struct ar5523_cmd_rateset rateset; 242b7d572e1SPontus Fuchs __be32 wlanmode; 243b7d572e1SPontus Fuchs } __packed; 244b7d572e1SPontus Fuchs 245b7d572e1SPontus Fuchs /* structure for command AR5523_CREATE_CONNECTION */ 246b7d572e1SPontus Fuchs struct ar5523_cmd_create_connection { 247b7d572e1SPontus Fuchs __be32 connid; 248b7d572e1SPontus Fuchs __be32 bssid; 249b7d572e1SPontus Fuchs __be32 size; 250b7d572e1SPontus Fuchs struct ar5523_cmd_connection_attr connattr; 251b7d572e1SPontus Fuchs } __packed; 252b7d572e1SPontus Fuchs 253b7d572e1SPontus Fuchs struct ar5523_cmd_ledsteady { /* WDCMSG_SET_LED_STEADY */ 254b7d572e1SPontus Fuchs __be32 lednum; 255b7d572e1SPontus Fuchs #define UATH_LED_LINK 0 256b7d572e1SPontus Fuchs #define UATH_LED_ACTIVITY 1 257b7d572e1SPontus Fuchs __be32 ledmode; 258b7d572e1SPontus Fuchs #define UATH_LED_OFF 0 259b7d572e1SPontus Fuchs #define UATH_LED_ON 1 260b7d572e1SPontus Fuchs } __packed; 261b7d572e1SPontus Fuchs 262b7d572e1SPontus Fuchs struct ar5523_cmd_ledblink { /* WDCMSG_SET_LED_BLINK */ 263b7d572e1SPontus Fuchs __be32 lednum; 264b7d572e1SPontus Fuchs __be32 ledmode; 265b7d572e1SPontus Fuchs __be32 blinkrate; 266b7d572e1SPontus Fuchs __be32 slowmode; 267b7d572e1SPontus Fuchs } __packed; 268b7d572e1SPontus Fuchs 269b7d572e1SPontus Fuchs struct ar5523_cmd_ledstate { /* WDCMSG_SET_LED_STATE */ 270b7d572e1SPontus Fuchs __be32 connected; 271b7d572e1SPontus Fuchs } __packed; 272b7d572e1SPontus Fuchs 273b7d572e1SPontus Fuchs struct ar5523_cmd_txq_attr { 274b7d572e1SPontus Fuchs __be32 priority; 275b7d572e1SPontus Fuchs __be32 aifs; 276b7d572e1SPontus Fuchs __be32 logcwmin; 277b7d572e1SPontus Fuchs __be32 logcwmax; 278b7d572e1SPontus Fuchs __be32 bursttime; 279b7d572e1SPontus Fuchs __be32 mode; 280b7d572e1SPontus Fuchs __be32 qflags; 281b7d572e1SPontus Fuchs } __packed; 282b7d572e1SPontus Fuchs 283b7d572e1SPontus Fuchs struct ar5523_cmd_txq_setup { /* WDCMSG_SETUP_TX_QUEUE */ 284b7d572e1SPontus Fuchs __be32 qid; 285b7d572e1SPontus Fuchs __be32 len; 286b7d572e1SPontus Fuchs struct ar5523_cmd_txq_attr attr; 287b7d572e1SPontus Fuchs } __packed; 288b7d572e1SPontus Fuchs 289b7d572e1SPontus Fuchs struct ar5523_cmd_rx_filter { /* WDCMSG_RX_FILTER */ 290b7d572e1SPontus Fuchs __be32 bits; 291b7d572e1SPontus Fuchs #define UATH_FILTER_RX_UCAST 0x00000001 292b7d572e1SPontus Fuchs #define UATH_FILTER_RX_MCAST 0x00000002 293b7d572e1SPontus Fuchs #define UATH_FILTER_RX_BCAST 0x00000004 294b7d572e1SPontus Fuchs #define UATH_FILTER_RX_CONTROL 0x00000008 295b7d572e1SPontus Fuchs #define UATH_FILTER_RX_BEACON 0x00000010 /* beacon frames */ 296b7d572e1SPontus Fuchs #define UATH_FILTER_RX_PROM 0x00000020 /* promiscuous mode */ 297b7d572e1SPontus Fuchs #define UATH_FILTER_RX_PHY_ERR 0x00000040 /* phy errors */ 298b7d572e1SPontus Fuchs #define UATH_FILTER_RX_PHY_RADAR 0x00000080 /* radar phy errors */ 299b7d572e1SPontus Fuchs #define UATH_FILTER_RX_XR_POOL 0x00000400 /* XR group polls */ 300b7d572e1SPontus Fuchs #define UATH_FILTER_RX_PROBE_REQ 0x00000800 301b7d572e1SPontus Fuchs __be32 op; 302b7d572e1SPontus Fuchs #define UATH_FILTER_OP_INIT 0x0 303b7d572e1SPontus Fuchs #define UATH_FILTER_OP_SET 0x1 304b7d572e1SPontus Fuchs #define UATH_FILTER_OP_CLEAR 0x2 305b7d572e1SPontus Fuchs #define UATH_FILTER_OP_TEMP 0x3 306b7d572e1SPontus Fuchs #define UATH_FILTER_OP_RESTORE 0x4 307b7d572e1SPontus Fuchs } __packed; 308b7d572e1SPontus Fuchs 309b7d572e1SPontus Fuchs enum { 310b7d572e1SPontus Fuchs CFG_NONE, /* Sentinal to indicate "no config" */ 311b7d572e1SPontus Fuchs CFG_REG_DOMAIN, /* Regulatory Domain */ 312b7d572e1SPontus Fuchs CFG_RATE_CONTROL_ENABLE, 313b7d572e1SPontus Fuchs CFG_DEF_XMIT_DATA_RATE, /* NB: if rate control is not enabled */ 314b7d572e1SPontus Fuchs CFG_HW_TX_RETRIES, 315b7d572e1SPontus Fuchs CFG_SW_TX_RETRIES, 316b7d572e1SPontus Fuchs CFG_SLOW_CLOCK_ENABLE, 317b7d572e1SPontus Fuchs CFG_COMP_PROC, 318b7d572e1SPontus Fuchs CFG_USER_RTS_THRESHOLD, 319b7d572e1SPontus Fuchs CFG_XR2NORM_RATE_THRESHOLD, 320b7d572e1SPontus Fuchs CFG_XRMODE_SWITCH_COUNT, 321b7d572e1SPontus Fuchs CFG_PROTECTION_TYPE, 322b7d572e1SPontus Fuchs CFG_BURST_SEQ_THRESHOLD, 323b7d572e1SPontus Fuchs CFG_ABOLT, 324b7d572e1SPontus Fuchs CFG_IQ_LOG_COUNT_MAX, 325b7d572e1SPontus Fuchs CFG_MODE_CTS, 326b7d572e1SPontus Fuchs CFG_WME_ENABLED, 327b7d572e1SPontus Fuchs CFG_GPRS_CBR_PERIOD, 328b7d572e1SPontus Fuchs CFG_SERVICE_TYPE, 329b7d572e1SPontus Fuchs /* MAC Address to use. Overrides EEPROM */ 330b7d572e1SPontus Fuchs CFG_MAC_ADDR, 331b7d572e1SPontus Fuchs CFG_DEBUG_EAR, 332b7d572e1SPontus Fuchs CFG_INIT_REGS, 333b7d572e1SPontus Fuchs /* An ID for use in error & debug messages */ 334b7d572e1SPontus Fuchs CFG_DEBUG_ID, 335b7d572e1SPontus Fuchs CFG_COMP_WIN_SZ, 336b7d572e1SPontus Fuchs CFG_DIVERSITY_CTL, 337b7d572e1SPontus Fuchs CFG_TP_SCALE, 338b7d572e1SPontus Fuchs CFG_TPC_HALF_DBM5, 339b7d572e1SPontus Fuchs CFG_TPC_HALF_DBM2, 340b7d572e1SPontus Fuchs CFG_OVERRD_TX_POWER, 341b7d572e1SPontus Fuchs CFG_USE_32KHZ_CLOCK, 342b7d572e1SPontus Fuchs CFG_GMODE_PROTECTION, 343b7d572e1SPontus Fuchs CFG_GMODE_PROTECT_RATE_INDEX, 344b7d572e1SPontus Fuchs CFG_GMODE_NON_ERP_PREAMBLE, 345b7d572e1SPontus Fuchs CFG_WDC_TRANSPORT_CHUNK_SIZE, 346b7d572e1SPontus Fuchs }; 347b7d572e1SPontus Fuchs 348b7d572e1SPontus Fuchs enum { 349b7d572e1SPontus Fuchs /* Sentinal to indicate "no capability" */ 350b7d572e1SPontus Fuchs CAP_NONE, 351b7d572e1SPontus Fuchs CAP_ALL, /* ALL capabilities */ 352b7d572e1SPontus Fuchs CAP_TARGET_VERSION, 353b7d572e1SPontus Fuchs CAP_TARGET_REVISION, 354b7d572e1SPontus Fuchs CAP_MAC_VERSION, 355b7d572e1SPontus Fuchs CAP_MAC_REVISION, 356b7d572e1SPontus Fuchs CAP_PHY_REVISION, 357b7d572e1SPontus Fuchs CAP_ANALOG_5GHz_REVISION, 358b7d572e1SPontus Fuchs CAP_ANALOG_2GHz_REVISION, 359b7d572e1SPontus Fuchs /* Target supports WDC message debug features */ 360b7d572e1SPontus Fuchs CAP_DEBUG_WDCMSG_SUPPORT, 361b7d572e1SPontus Fuchs 362b7d572e1SPontus Fuchs CAP_REG_DOMAIN, 363b7d572e1SPontus Fuchs CAP_COUNTRY_CODE, 364b7d572e1SPontus Fuchs CAP_REG_CAP_BITS, 365b7d572e1SPontus Fuchs 366b7d572e1SPontus Fuchs CAP_WIRELESS_MODES, 367b7d572e1SPontus Fuchs CAP_CHAN_SPREAD_SUPPORT, 368b7d572e1SPontus Fuchs CAP_SLEEP_AFTER_BEACON_BROKEN, 369b7d572e1SPontus Fuchs CAP_COMPRESS_SUPPORT, 370b7d572e1SPontus Fuchs CAP_BURST_SUPPORT, 371b7d572e1SPontus Fuchs CAP_FAST_FRAMES_SUPPORT, 372b7d572e1SPontus Fuchs CAP_CHAP_TUNING_SUPPORT, 373b7d572e1SPontus Fuchs CAP_TURBOG_SUPPORT, 374b7d572e1SPontus Fuchs CAP_TURBO_PRIME_SUPPORT, 375b7d572e1SPontus Fuchs CAP_DEVICE_TYPE, 376b7d572e1SPontus Fuchs CAP_XR_SUPPORT, 377b7d572e1SPontus Fuchs CAP_WME_SUPPORT, 378b7d572e1SPontus Fuchs CAP_TOTAL_QUEUES, 379b7d572e1SPontus Fuchs CAP_CONNECTION_ID_MAX, /* Should absorb CAP_KEY_CACHE_SIZE */ 380b7d572e1SPontus Fuchs 381b7d572e1SPontus Fuchs CAP_LOW_5GHZ_CHAN, 382b7d572e1SPontus Fuchs CAP_HIGH_5GHZ_CHAN, 383b7d572e1SPontus Fuchs CAP_LOW_2GHZ_CHAN, 384b7d572e1SPontus Fuchs CAP_HIGH_2GHZ_CHAN, 385b7d572e1SPontus Fuchs 386b7d572e1SPontus Fuchs CAP_MIC_AES_CCM, 387b7d572e1SPontus Fuchs CAP_MIC_CKIP, 388b7d572e1SPontus Fuchs CAP_MIC_TKIP, 389b7d572e1SPontus Fuchs CAP_MIC_TKIP_WME, 390b7d572e1SPontus Fuchs CAP_CIPHER_AES_CCM, 391b7d572e1SPontus Fuchs CAP_CIPHER_CKIP, 392b7d572e1SPontus Fuchs CAP_CIPHER_TKIP, 393b7d572e1SPontus Fuchs 394b7d572e1SPontus Fuchs CAP_TWICE_ANTENNAGAIN_5G, 395b7d572e1SPontus Fuchs CAP_TWICE_ANTENNAGAIN_2G, 396b7d572e1SPontus Fuchs }; 397b7d572e1SPontus Fuchs 398b7d572e1SPontus Fuchs enum { 399b7d572e1SPontus Fuchs ST_NONE, /* Sentinal to indicate "no status" */ 400b7d572e1SPontus Fuchs ST_ALL, 401b7d572e1SPontus Fuchs ST_SERVICE_TYPE, 402b7d572e1SPontus Fuchs ST_WLAN_MODE, 403b7d572e1SPontus Fuchs ST_FREQ, 404b7d572e1SPontus Fuchs ST_BAND, 405b7d572e1SPontus Fuchs ST_LAST_RSSI, 406b7d572e1SPontus Fuchs ST_PS_FRAMES_DROPPED, 407b7d572e1SPontus Fuchs ST_CACHED_DEF_ANT, 408b7d572e1SPontus Fuchs ST_COUNT_OTHER_RX_ANT, 409b7d572e1SPontus Fuchs ST_USE_FAST_DIVERSITY, 410b7d572e1SPontus Fuchs ST_MAC_ADDR, 411b7d572e1SPontus Fuchs ST_RX_GENERATION_NUM, 412b7d572e1SPontus Fuchs ST_TX_QUEUE_DEPTH, 413b7d572e1SPontus Fuchs ST_SERIAL_NUMBER, 414b7d572e1SPontus Fuchs ST_WDC_TRANSPORT_CHUNK_SIZE, 415b7d572e1SPontus Fuchs }; 416b7d572e1SPontus Fuchs 417b7d572e1SPontus Fuchs enum { 418b7d572e1SPontus Fuchs TARGET_DEVICE_AWAKE, 419b7d572e1SPontus Fuchs TARGET_DEVICE_SLEEP, 420b7d572e1SPontus Fuchs TARGET_DEVICE_PWRDN, 421b7d572e1SPontus Fuchs TARGET_DEVICE_PWRSAVE, 422b7d572e1SPontus Fuchs TARGET_DEVICE_SUSPEND, 423b7d572e1SPontus Fuchs TARGET_DEVICE_RESUME, 424b7d572e1SPontus Fuchs }; 425b7d572e1SPontus Fuchs 426b7d572e1SPontus Fuchs /* this is in net/ieee80211.h, but that conflicts with the mac80211 headers */ 427b7d572e1SPontus Fuchs #define IEEE80211_2ADDR_LEN 16 428b7d572e1SPontus Fuchs 429b7d572e1SPontus Fuchs #define AR5523_MIN_RXBUFSZ \ 430b7d572e1SPontus Fuchs (((sizeof(__be32) + IEEE80211_2ADDR_LEN + \ 431b7d572e1SPontus Fuchs sizeof(struct ar5523_rx_desc)) + 3) & ~3) 432