1 // SPDX-License-Identifier: GPL-2.0-only 2 3 /* 4 * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP) 5 * 6 * Copyright (c) 2003, Jouni Malinen <j@w1.fi> 7 * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net> 8 * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com> 9 * and used with permission. 10 * 11 * Much thanks to Infineon-ADMtek for their support of this driver. 12 */ 13 14 #include <linux/interrupt.h> 15 #include <linux/if.h> 16 #include <linux/skbuff.h> 17 #include <linux/slab.h> 18 #include <linux/etherdevice.h> 19 #include <linux/pci.h> 20 #include <linux/delay.h> 21 #include <linux/crc32.h> 22 #include <linux/eeprom_93cx6.h> 23 #include <linux/module.h> 24 #include <net/mac80211.h> 25 26 #include "adm8211.h" 27 28 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); 29 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>"); 30 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211"); 31 MODULE_SUPPORTED_DEVICE("ADM8211"); 32 MODULE_LICENSE("GPL"); 33 34 static unsigned int tx_ring_size __read_mostly = 16; 35 static unsigned int rx_ring_size __read_mostly = 16; 36 37 module_param(tx_ring_size, uint, 0); 38 module_param(rx_ring_size, uint, 0); 39 40 static const struct pci_device_id adm8211_pci_id_table[] = { 41 /* ADMtek ADM8211 */ 42 { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */ 43 { PCI_DEVICE(0x1200, 0x8201) }, /* ? */ 44 { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */ 45 { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */ 46 { 0 } 47 }; 48 49 static struct ieee80211_rate adm8211_rates[] = { 50 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 51 { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 52 { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 53 { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 54 { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */ 55 }; 56 57 static const struct ieee80211_channel adm8211_channels[] = { 58 { .center_freq = 2412}, 59 { .center_freq = 2417}, 60 { .center_freq = 2422}, 61 { .center_freq = 2427}, 62 { .center_freq = 2432}, 63 { .center_freq = 2437}, 64 { .center_freq = 2442}, 65 { .center_freq = 2447}, 66 { .center_freq = 2452}, 67 { .center_freq = 2457}, 68 { .center_freq = 2462}, 69 { .center_freq = 2467}, 70 { .center_freq = 2472}, 71 { .center_freq = 2484}, 72 }; 73 74 75 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom) 76 { 77 struct adm8211_priv *priv = eeprom->data; 78 u32 reg = ADM8211_CSR_READ(SPR); 79 80 eeprom->reg_data_in = reg & ADM8211_SPR_SDI; 81 eeprom->reg_data_out = reg & ADM8211_SPR_SDO; 82 eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK; 83 eeprom->reg_chip_select = reg & ADM8211_SPR_SCS; 84 } 85 86 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom) 87 { 88 struct adm8211_priv *priv = eeprom->data; 89 u32 reg = 0x4000 | ADM8211_SPR_SRS; 90 91 if (eeprom->reg_data_in) 92 reg |= ADM8211_SPR_SDI; 93 if (eeprom->reg_data_out) 94 reg |= ADM8211_SPR_SDO; 95 if (eeprom->reg_data_clock) 96 reg |= ADM8211_SPR_SCLK; 97 if (eeprom->reg_chip_select) 98 reg |= ADM8211_SPR_SCS; 99 100 ADM8211_CSR_WRITE(SPR, reg); 101 ADM8211_CSR_READ(SPR); /* eeprom_delay */ 102 } 103 104 static int adm8211_read_eeprom(struct ieee80211_hw *dev) 105 { 106 struct adm8211_priv *priv = dev->priv; 107 unsigned int words, i; 108 struct ieee80211_chan_range chan_range; 109 u16 cr49; 110 struct eeprom_93cx6 eeprom = { 111 .data = priv, 112 .register_read = adm8211_eeprom_register_read, 113 .register_write = adm8211_eeprom_register_write 114 }; 115 116 if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) { 117 /* 256 * 16-bit = 512 bytes */ 118 eeprom.width = PCI_EEPROM_WIDTH_93C66; 119 words = 256; 120 } else { 121 /* 64 * 16-bit = 128 bytes */ 122 eeprom.width = PCI_EEPROM_WIDTH_93C46; 123 words = 64; 124 } 125 126 priv->eeprom_len = words * 2; 127 priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL); 128 if (!priv->eeprom) 129 return -ENOMEM; 130 131 eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words); 132 133 cr49 = le16_to_cpu(priv->eeprom->cr49); 134 priv->rf_type = (cr49 >> 3) & 0x7; 135 switch (priv->rf_type) { 136 case ADM8211_TYPE_INTERSIL: 137 case ADM8211_TYPE_RFMD: 138 case ADM8211_TYPE_MARVEL: 139 case ADM8211_TYPE_AIROHA: 140 case ADM8211_TYPE_ADMTEK: 141 break; 142 143 default: 144 if (priv->pdev->revision < ADM8211_REV_CA) 145 priv->rf_type = ADM8211_TYPE_RFMD; 146 else 147 priv->rf_type = ADM8211_TYPE_AIROHA; 148 149 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n", 150 pci_name(priv->pdev), (cr49 >> 3) & 0x7); 151 } 152 153 priv->bbp_type = cr49 & 0x7; 154 switch (priv->bbp_type) { 155 case ADM8211_TYPE_INTERSIL: 156 case ADM8211_TYPE_RFMD: 157 case ADM8211_TYPE_MARVEL: 158 case ADM8211_TYPE_AIROHA: 159 case ADM8211_TYPE_ADMTEK: 160 break; 161 default: 162 if (priv->pdev->revision < ADM8211_REV_CA) 163 priv->bbp_type = ADM8211_TYPE_RFMD; 164 else 165 priv->bbp_type = ADM8211_TYPE_ADMTEK; 166 167 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n", 168 pci_name(priv->pdev), cr49 >> 3); 169 } 170 171 if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) { 172 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n", 173 pci_name(priv->pdev), priv->eeprom->country_code); 174 175 chan_range = cranges[2]; 176 } else 177 chan_range = cranges[priv->eeprom->country_code]; 178 179 printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n", 180 pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max); 181 182 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels)); 183 184 memcpy(priv->channels, adm8211_channels, sizeof(priv->channels)); 185 priv->band.channels = priv->channels; 186 priv->band.n_channels = ARRAY_SIZE(adm8211_channels); 187 priv->band.bitrates = adm8211_rates; 188 priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates); 189 190 for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++) 191 if (i < chan_range.min || i > chan_range.max) 192 priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED; 193 194 switch (priv->eeprom->specific_bbptype) { 195 case ADM8211_BBP_RFMD3000: 196 case ADM8211_BBP_RFMD3002: 197 case ADM8211_BBP_ADM8011: 198 priv->specific_bbptype = priv->eeprom->specific_bbptype; 199 break; 200 201 default: 202 if (priv->pdev->revision < ADM8211_REV_CA) 203 priv->specific_bbptype = ADM8211_BBP_RFMD3000; 204 else 205 priv->specific_bbptype = ADM8211_BBP_ADM8011; 206 207 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n", 208 pci_name(priv->pdev), priv->eeprom->specific_bbptype); 209 } 210 211 switch (priv->eeprom->specific_rftype) { 212 case ADM8211_RFMD2948: 213 case ADM8211_RFMD2958: 214 case ADM8211_RFMD2958_RF3000_CONTROL_POWER: 215 case ADM8211_MAX2820: 216 case ADM8211_AL2210L: 217 priv->transceiver_type = priv->eeprom->specific_rftype; 218 break; 219 220 default: 221 if (priv->pdev->revision == ADM8211_REV_BA) 222 priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER; 223 else if (priv->pdev->revision == ADM8211_REV_CA) 224 priv->transceiver_type = ADM8211_AL2210L; 225 else if (priv->pdev->revision == ADM8211_REV_AB) 226 priv->transceiver_type = ADM8211_RFMD2948; 227 228 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n", 229 pci_name(priv->pdev), priv->eeprom->specific_rftype); 230 231 break; 232 } 233 234 printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d " 235 "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type, 236 priv->bbp_type, priv->specific_bbptype, priv->transceiver_type); 237 238 return 0; 239 } 240 241 static inline void adm8211_write_sram(struct ieee80211_hw *dev, 242 u32 addr, u32 data) 243 { 244 struct adm8211_priv *priv = dev->priv; 245 246 ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR | 247 (priv->pdev->revision < ADM8211_REV_BA ? 248 0 : ADM8211_WEPCTL_SEL_WEPTABLE )); 249 ADM8211_CSR_READ(WEPCTL); 250 msleep(1); 251 252 ADM8211_CSR_WRITE(WESK, data); 253 ADM8211_CSR_READ(WESK); 254 msleep(1); 255 } 256 257 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev, 258 unsigned int addr, u8 *buf, 259 unsigned int len) 260 { 261 struct adm8211_priv *priv = dev->priv; 262 u32 reg = ADM8211_CSR_READ(WEPCTL); 263 unsigned int i; 264 265 if (priv->pdev->revision < ADM8211_REV_BA) { 266 for (i = 0; i < len; i += 2) { 267 u16 val = buf[i] | (buf[i + 1] << 8); 268 adm8211_write_sram(dev, addr + i / 2, val); 269 } 270 } else { 271 for (i = 0; i < len; i += 4) { 272 u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) | 273 (buf[i + 2] << 16) | (buf[i + 3] << 24); 274 adm8211_write_sram(dev, addr + i / 4, val); 275 } 276 } 277 278 ADM8211_CSR_WRITE(WEPCTL, reg); 279 } 280 281 static void adm8211_clear_sram(struct ieee80211_hw *dev) 282 { 283 struct adm8211_priv *priv = dev->priv; 284 u32 reg = ADM8211_CSR_READ(WEPCTL); 285 unsigned int addr; 286 287 for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++) 288 adm8211_write_sram(dev, addr, 0); 289 290 ADM8211_CSR_WRITE(WEPCTL, reg); 291 } 292 293 static int adm8211_get_stats(struct ieee80211_hw *dev, 294 struct ieee80211_low_level_stats *stats) 295 { 296 struct adm8211_priv *priv = dev->priv; 297 298 memcpy(stats, &priv->stats, sizeof(*stats)); 299 300 return 0; 301 } 302 303 static void adm8211_interrupt_tci(struct ieee80211_hw *dev) 304 { 305 struct adm8211_priv *priv = dev->priv; 306 unsigned int dirty_tx; 307 308 spin_lock(&priv->lock); 309 310 for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) { 311 unsigned int entry = dirty_tx % priv->tx_ring_size; 312 u32 status = le32_to_cpu(priv->tx_ring[entry].status); 313 struct ieee80211_tx_info *txi; 314 struct adm8211_tx_ring_info *info; 315 struct sk_buff *skb; 316 317 if (status & TDES0_CONTROL_OWN || 318 !(status & TDES0_CONTROL_DONE)) 319 break; 320 321 info = &priv->tx_buffers[entry]; 322 skb = info->skb; 323 txi = IEEE80211_SKB_CB(skb); 324 325 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */ 326 327 pci_unmap_single(priv->pdev, info->mapping, 328 info->skb->len, PCI_DMA_TODEVICE); 329 330 ieee80211_tx_info_clear_status(txi); 331 332 skb_pull(skb, sizeof(struct adm8211_tx_hdr)); 333 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen); 334 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) && 335 !(status & TDES0_STATUS_ES)) 336 txi->flags |= IEEE80211_TX_STAT_ACK; 337 338 ieee80211_tx_status_irqsafe(dev, skb); 339 340 info->skb = NULL; 341 } 342 343 if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2) 344 ieee80211_wake_queue(dev, 0); 345 346 priv->dirty_tx = dirty_tx; 347 spin_unlock(&priv->lock); 348 } 349 350 351 static void adm8211_interrupt_rci(struct ieee80211_hw *dev) 352 { 353 struct adm8211_priv *priv = dev->priv; 354 unsigned int entry = priv->cur_rx % priv->rx_ring_size; 355 u32 status; 356 unsigned int pktlen; 357 struct sk_buff *skb, *newskb; 358 unsigned int limit = priv->rx_ring_size; 359 u8 rssi, rate; 360 361 while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) { 362 if (!limit--) 363 break; 364 365 status = le32_to_cpu(priv->rx_ring[entry].status); 366 rate = (status & RDES0_STATUS_RXDR) >> 12; 367 rssi = le32_to_cpu(priv->rx_ring[entry].length) & 368 RDES1_STATUS_RSSI; 369 370 pktlen = status & RDES0_STATUS_FL; 371 if (pktlen > RX_PKT_SIZE) { 372 if (net_ratelimit()) 373 wiphy_debug(dev->wiphy, "frame too long (%d)\n", 374 pktlen); 375 pktlen = RX_PKT_SIZE; 376 } 377 378 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) { 379 skb = NULL; /* old buffer will be reused */ 380 /* TODO: update RX error stats */ 381 /* TODO: check RDES0_STATUS_CRC*E */ 382 } else if (pktlen < RX_COPY_BREAK) { 383 skb = dev_alloc_skb(pktlen); 384 if (skb) { 385 pci_dma_sync_single_for_cpu( 386 priv->pdev, 387 priv->rx_buffers[entry].mapping, 388 pktlen, PCI_DMA_FROMDEVICE); 389 skb_put_data(skb, 390 skb_tail_pointer(priv->rx_buffers[entry].skb), 391 pktlen); 392 pci_dma_sync_single_for_device( 393 priv->pdev, 394 priv->rx_buffers[entry].mapping, 395 RX_PKT_SIZE, PCI_DMA_FROMDEVICE); 396 } 397 } else { 398 newskb = dev_alloc_skb(RX_PKT_SIZE); 399 if (newskb) { 400 skb = priv->rx_buffers[entry].skb; 401 skb_put(skb, pktlen); 402 pci_unmap_single( 403 priv->pdev, 404 priv->rx_buffers[entry].mapping, 405 RX_PKT_SIZE, PCI_DMA_FROMDEVICE); 406 priv->rx_buffers[entry].skb = newskb; 407 priv->rx_buffers[entry].mapping = 408 pci_map_single(priv->pdev, 409 skb_tail_pointer(newskb), 410 RX_PKT_SIZE, 411 PCI_DMA_FROMDEVICE); 412 if (pci_dma_mapping_error(priv->pdev, 413 priv->rx_buffers[entry].mapping)) { 414 priv->rx_buffers[entry].skb = NULL; 415 dev_kfree_skb(newskb); 416 skb = NULL; 417 /* TODO: update rx dropped stats */ 418 } 419 } else { 420 skb = NULL; 421 /* TODO: update rx dropped stats */ 422 } 423 424 priv->rx_ring[entry].buffer1 = 425 cpu_to_le32(priv->rx_buffers[entry].mapping); 426 } 427 428 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN | 429 RDES0_STATUS_SQL); 430 priv->rx_ring[entry].length = 431 cpu_to_le32(RX_PKT_SIZE | 432 (entry == priv->rx_ring_size - 1 ? 433 RDES1_CONTROL_RER : 0)); 434 435 if (skb) { 436 struct ieee80211_rx_status rx_status = {0}; 437 438 if (priv->pdev->revision < ADM8211_REV_CA) 439 rx_status.signal = rssi; 440 else 441 rx_status.signal = 100 - rssi; 442 443 rx_status.rate_idx = rate; 444 445 rx_status.freq = adm8211_channels[priv->channel - 1].center_freq; 446 rx_status.band = NL80211_BAND_2GHZ; 447 448 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); 449 ieee80211_rx_irqsafe(dev, skb); 450 } 451 452 entry = (++priv->cur_rx) % priv->rx_ring_size; 453 } 454 455 /* TODO: check LPC and update stats? */ 456 } 457 458 459 static irqreturn_t adm8211_interrupt(int irq, void *dev_id) 460 { 461 #define ADM8211_INT(x) \ 462 do { \ 463 if (unlikely(stsr & ADM8211_STSR_ ## x)) \ 464 wiphy_debug(dev->wiphy, "%s\n", #x); \ 465 } while (0) 466 467 struct ieee80211_hw *dev = dev_id; 468 struct adm8211_priv *priv = dev->priv; 469 u32 stsr = ADM8211_CSR_READ(STSR); 470 ADM8211_CSR_WRITE(STSR, stsr); 471 if (stsr == 0xffffffff) 472 return IRQ_HANDLED; 473 474 if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS))) 475 return IRQ_HANDLED; 476 477 if (stsr & ADM8211_STSR_RCI) 478 adm8211_interrupt_rci(dev); 479 if (stsr & ADM8211_STSR_TCI) 480 adm8211_interrupt_tci(dev); 481 482 ADM8211_INT(PCF); 483 ADM8211_INT(BCNTC); 484 ADM8211_INT(GPINT); 485 ADM8211_INT(ATIMTC); 486 ADM8211_INT(TSFTF); 487 ADM8211_INT(TSCZ); 488 ADM8211_INT(SQL); 489 ADM8211_INT(WEPTD); 490 ADM8211_INT(ATIME); 491 ADM8211_INT(TEIS); 492 ADM8211_INT(FBE); 493 ADM8211_INT(REIS); 494 ADM8211_INT(GPTT); 495 ADM8211_INT(RPS); 496 ADM8211_INT(RDU); 497 ADM8211_INT(TUF); 498 ADM8211_INT(TPS); 499 500 return IRQ_HANDLED; 501 502 #undef ADM8211_INT 503 } 504 505 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\ 506 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev, \ 507 u16 addr, u32 value) { \ 508 struct adm8211_priv *priv = dev->priv; \ 509 unsigned int i; \ 510 u32 reg, bitbuf; \ 511 \ 512 value &= v_mask; \ 513 addr &= a_mask; \ 514 bitbuf = (value << v_shift) | (addr << a_shift); \ 515 \ 516 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1); \ 517 ADM8211_CSR_READ(SYNRF); \ 518 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0); \ 519 ADM8211_CSR_READ(SYNRF); \ 520 \ 521 if (prewrite) { \ 522 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0); \ 523 ADM8211_CSR_READ(SYNRF); \ 524 } \ 525 \ 526 for (i = 0; i <= bits; i++) { \ 527 if (bitbuf & (1 << (bits - i))) \ 528 reg = ADM8211_SYNRF_WRITE_SYNDATA_1; \ 529 else \ 530 reg = ADM8211_SYNRF_WRITE_SYNDATA_0; \ 531 \ 532 ADM8211_CSR_WRITE(SYNRF, reg); \ 533 ADM8211_CSR_READ(SYNRF); \ 534 \ 535 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \ 536 ADM8211_CSR_READ(SYNRF); \ 537 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \ 538 ADM8211_CSR_READ(SYNRF); \ 539 } \ 540 \ 541 if (postwrite == 1) { \ 542 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0); \ 543 ADM8211_CSR_READ(SYNRF); \ 544 } \ 545 if (postwrite == 2) { \ 546 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1); \ 547 ADM8211_CSR_READ(SYNRF); \ 548 } \ 549 \ 550 ADM8211_CSR_WRITE(SYNRF, 0); \ 551 ADM8211_CSR_READ(SYNRF); \ 552 } 553 554 WRITE_SYN(max2820, 0x00FFF, 0, 0x0F, 12, 15, 1, 1) 555 WRITE_SYN(al2210l, 0xFFFFF, 4, 0x0F, 0, 23, 1, 1) 556 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1) 557 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F, 0, 21, 0, 2) 558 559 #undef WRITE_SYN 560 561 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data) 562 { 563 struct adm8211_priv *priv = dev->priv; 564 unsigned int timeout; 565 u32 reg; 566 567 timeout = 10; 568 while (timeout > 0) { 569 reg = ADM8211_CSR_READ(BBPCTL); 570 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD))) 571 break; 572 timeout--; 573 msleep(2); 574 } 575 576 if (timeout == 0) { 577 wiphy_debug(dev->wiphy, 578 "adm8211_write_bbp(%d,%d) failed prewrite (reg=0x%08x)\n", 579 addr, data, reg); 580 return -ETIMEDOUT; 581 } 582 583 switch (priv->bbp_type) { 584 case ADM8211_TYPE_INTERSIL: 585 reg = ADM8211_BBPCTL_MMISEL; /* three wire interface */ 586 break; 587 case ADM8211_TYPE_RFMD: 588 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP | 589 (0x01 << 18); 590 break; 591 case ADM8211_TYPE_ADMTEK: 592 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP | 593 (0x05 << 18); 594 break; 595 } 596 reg |= ADM8211_BBPCTL_WR | (addr << 8) | data; 597 598 ADM8211_CSR_WRITE(BBPCTL, reg); 599 600 timeout = 10; 601 while (timeout > 0) { 602 reg = ADM8211_CSR_READ(BBPCTL); 603 if (!(reg & ADM8211_BBPCTL_WR)) 604 break; 605 timeout--; 606 msleep(2); 607 } 608 609 if (timeout == 0) { 610 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) & 611 ~ADM8211_BBPCTL_WR); 612 wiphy_debug(dev->wiphy, 613 "adm8211_write_bbp(%d,%d) failed postwrite (reg=0x%08x)\n", 614 addr, data, reg); 615 return -ETIMEDOUT; 616 } 617 618 return 0; 619 } 620 621 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan) 622 { 623 static const u32 adm8211_rfmd2958_reg5[] = 624 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340, 625 0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7}; 626 static const u32 adm8211_rfmd2958_reg6[] = 627 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000, 628 0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745}; 629 630 struct adm8211_priv *priv = dev->priv; 631 u8 ant_power = priv->ant_power > 0x3F ? 632 priv->eeprom->antenna_power[chan - 1] : priv->ant_power; 633 u8 tx_power = priv->tx_power > 0x3F ? 634 priv->eeprom->tx_power[chan - 1] : priv->tx_power; 635 u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ? 636 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff; 637 u8 lnags_thresh = priv->lnags_threshold == 0xFF ? 638 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold; 639 u32 reg; 640 641 ADM8211_IDLE(); 642 643 /* Program synthesizer to new channel */ 644 switch (priv->transceiver_type) { 645 case ADM8211_RFMD2958: 646 case ADM8211_RFMD2958_RF3000_CONTROL_POWER: 647 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007); 648 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033); 649 650 adm8211_rf_write_syn_rfmd2958(dev, 0x05, 651 adm8211_rfmd2958_reg5[chan - 1]); 652 adm8211_rf_write_syn_rfmd2958(dev, 0x06, 653 adm8211_rfmd2958_reg6[chan - 1]); 654 break; 655 656 case ADM8211_RFMD2948: 657 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF, 658 SI4126_MAIN_XINDIV2); 659 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN, 660 SI4126_POWERDOWN_PDIB | 661 SI4126_POWERDOWN_PDRB); 662 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0); 663 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV, 664 (chan == 14 ? 665 2110 : (2033 + (chan * 5)))); 666 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496); 667 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44); 668 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44); 669 break; 670 671 case ADM8211_MAX2820: 672 adm8211_rf_write_syn_max2820(dev, 0x3, 673 (chan == 14 ? 0x054 : (0x7 + (chan * 5)))); 674 break; 675 676 case ADM8211_AL2210L: 677 adm8211_rf_write_syn_al2210l(dev, 0x0, 678 (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5)))); 679 break; 680 681 default: 682 wiphy_debug(dev->wiphy, "unsupported transceiver type %d\n", 683 priv->transceiver_type); 684 break; 685 } 686 687 /* write BBP regs */ 688 if (priv->bbp_type == ADM8211_TYPE_RFMD) { 689 690 /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */ 691 /* TODO: remove if SMC 2635W doesn't need this */ 692 if (priv->transceiver_type == ADM8211_RFMD2948) { 693 reg = ADM8211_CSR_READ(GPIO); 694 reg &= 0xfffc0000; 695 reg |= ADM8211_CSR_GPIO_EN0; 696 if (chan != 14) 697 reg |= ADM8211_CSR_GPIO_O0; 698 ADM8211_CSR_WRITE(GPIO, reg); 699 } 700 701 if (priv->transceiver_type == ADM8211_RFMD2958) { 702 /* set PCNT2 */ 703 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100); 704 /* set PCNT1 P_DESIRED/MID_BIAS */ 705 reg = le16_to_cpu(priv->eeprom->cr49); 706 reg >>= 13; 707 reg <<= 15; 708 reg |= ant_power << 9; 709 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg); 710 /* set TXRX TX_GAIN */ 711 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 | 712 (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0)); 713 } else { 714 reg = ADM8211_CSR_READ(PLCPHD); 715 reg &= 0xff00ffff; 716 reg |= tx_power << 18; 717 ADM8211_CSR_WRITE(PLCPHD, reg); 718 } 719 720 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF | 721 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST); 722 ADM8211_CSR_READ(SYNRF); 723 msleep(30); 724 725 /* RF3000 BBP */ 726 if (priv->transceiver_type != ADM8211_RFMD2958) 727 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 728 tx_power<<2); 729 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff); 730 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh); 731 adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ? 732 priv->eeprom->cr28 : 0); 733 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29); 734 735 ADM8211_CSR_WRITE(SYNRF, 0); 736 737 /* Nothing to do for ADMtek BBP */ 738 } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK) 739 wiphy_debug(dev->wiphy, "unsupported BBP type %d\n", 740 priv->bbp_type); 741 742 ADM8211_RESTORE(); 743 744 /* update current channel for adhoc (and maybe AP mode) */ 745 reg = ADM8211_CSR_READ(CAP0); 746 reg &= ~0xF; 747 reg |= chan; 748 ADM8211_CSR_WRITE(CAP0, reg); 749 750 return 0; 751 } 752 753 static void adm8211_update_mode(struct ieee80211_hw *dev) 754 { 755 struct adm8211_priv *priv = dev->priv; 756 757 ADM8211_IDLE(); 758 759 priv->soft_rx_crc = 0; 760 switch (priv->mode) { 761 case NL80211_IFTYPE_STATION: 762 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA); 763 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR; 764 break; 765 case NL80211_IFTYPE_ADHOC: 766 priv->nar &= ~ADM8211_NAR_PR; 767 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR; 768 769 /* don't trust the error bits on rev 0x20 and up in adhoc */ 770 if (priv->pdev->revision >= ADM8211_REV_BA) 771 priv->soft_rx_crc = 1; 772 break; 773 case NL80211_IFTYPE_MONITOR: 774 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST); 775 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR; 776 break; 777 } 778 779 ADM8211_RESTORE(); 780 } 781 782 static void adm8211_hw_init_syn(struct ieee80211_hw *dev) 783 { 784 struct adm8211_priv *priv = dev->priv; 785 786 switch (priv->transceiver_type) { 787 case ADM8211_RFMD2958: 788 case ADM8211_RFMD2958_RF3000_CONTROL_POWER: 789 /* comments taken from ADMtek vendor driver */ 790 791 /* Reset RF2958 after power on */ 792 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000); 793 /* Initialize RF VCO Core Bias to maximum */ 794 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F); 795 /* Initialize IF PLL */ 796 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03); 797 /* Initialize IF PLL Coarse Tuning */ 798 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F); 799 /* Initialize RF PLL */ 800 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403); 801 /* Initialize RF PLL Coarse Tuning */ 802 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F); 803 /* Initialize TX gain and filter BW (R9) */ 804 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 805 (priv->transceiver_type == ADM8211_RFMD2958 ? 806 0x10050 : 0x00050)); 807 /* Initialize CAL register */ 808 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8); 809 break; 810 811 case ADM8211_MAX2820: 812 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E); 813 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001); 814 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054); 815 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310); 816 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000); 817 break; 818 819 case ADM8211_AL2210L: 820 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C); 821 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB); 822 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F); 823 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9); 824 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280); 825 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641); 826 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130); 827 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000); 828 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F); 829 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C); 830 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000); 831 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000); 832 break; 833 834 case ADM8211_RFMD2948: 835 default: 836 break; 837 } 838 } 839 840 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev) 841 { 842 struct adm8211_priv *priv = dev->priv; 843 u32 reg; 844 845 /* write addresses */ 846 if (priv->bbp_type == ADM8211_TYPE_INTERSIL) { 847 ADM8211_CSR_WRITE(MMIWA, 0x100E0C0A); 848 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E); 849 ADM8211_CSR_WRITE(MMIRD1, 0x00100000); 850 } else if (priv->bbp_type == ADM8211_TYPE_RFMD || 851 priv->bbp_type == ADM8211_TYPE_ADMTEK) { 852 /* check specific BBP type */ 853 switch (priv->specific_bbptype) { 854 case ADM8211_BBP_RFMD3000: 855 case ADM8211_BBP_RFMD3002: 856 ADM8211_CSR_WRITE(MMIWA, 0x00009101); 857 ADM8211_CSR_WRITE(MMIRD0, 0x00000301); 858 break; 859 860 case ADM8211_BBP_ADM8011: 861 ADM8211_CSR_WRITE(MMIWA, 0x00008903); 862 ADM8211_CSR_WRITE(MMIRD0, 0x00001716); 863 864 reg = ADM8211_CSR_READ(BBPCTL); 865 reg &= ~ADM8211_BBPCTL_TYPE; 866 reg |= 0x5 << 18; 867 ADM8211_CSR_WRITE(BBPCTL, reg); 868 break; 869 } 870 871 switch (priv->pdev->revision) { 872 case ADM8211_REV_CA: 873 if (priv->transceiver_type == ADM8211_RFMD2958 || 874 priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER || 875 priv->transceiver_type == ADM8211_RFMD2948) 876 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22); 877 else if (priv->transceiver_type == ADM8211_MAX2820 || 878 priv->transceiver_type == ADM8211_AL2210L) 879 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22); 880 break; 881 882 case ADM8211_REV_BA: 883 reg = ADM8211_CSR_READ(MMIRD1); 884 reg &= 0x0000FFFF; 885 reg |= 0x7e100000; 886 ADM8211_CSR_WRITE(MMIRD1, reg); 887 break; 888 889 case ADM8211_REV_AB: 890 case ADM8211_REV_AF: 891 default: 892 ADM8211_CSR_WRITE(MMIRD1, 0x7e100000); 893 break; 894 } 895 896 /* For RFMD */ 897 ADM8211_CSR_WRITE(MACTEST, 0x800); 898 } 899 900 adm8211_hw_init_syn(dev); 901 902 /* Set RF Power control IF pin to PE1+PHYRST# */ 903 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF | 904 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST); 905 ADM8211_CSR_READ(SYNRF); 906 msleep(20); 907 908 /* write BBP regs */ 909 if (priv->bbp_type == ADM8211_TYPE_RFMD) { 910 /* RF3000 BBP */ 911 /* another set: 912 * 11: c8 913 * 14: 14 914 * 15: 50 (chan 1..13; chan 14: d0) 915 * 1c: 00 916 * 1d: 84 917 */ 918 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80); 919 /* antenna selection: diversity */ 920 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80); 921 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74); 922 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38); 923 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40); 924 925 if (priv->eeprom->major_version < 2) { 926 adm8211_write_bbp(dev, 0x1c, 0x00); 927 adm8211_write_bbp(dev, 0x1d, 0x80); 928 } else { 929 if (priv->pdev->revision == ADM8211_REV_BA) 930 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28); 931 else 932 adm8211_write_bbp(dev, 0x1c, 0x00); 933 934 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29); 935 } 936 } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) { 937 /* reset baseband */ 938 adm8211_write_bbp(dev, 0x00, 0xFF); 939 /* antenna selection: diversity */ 940 adm8211_write_bbp(dev, 0x07, 0x0A); 941 942 /* TODO: find documentation for this */ 943 switch (priv->transceiver_type) { 944 case ADM8211_RFMD2958: 945 case ADM8211_RFMD2958_RF3000_CONTROL_POWER: 946 adm8211_write_bbp(dev, 0x00, 0x00); 947 adm8211_write_bbp(dev, 0x01, 0x00); 948 adm8211_write_bbp(dev, 0x02, 0x00); 949 adm8211_write_bbp(dev, 0x03, 0x00); 950 adm8211_write_bbp(dev, 0x06, 0x0f); 951 adm8211_write_bbp(dev, 0x09, 0x00); 952 adm8211_write_bbp(dev, 0x0a, 0x00); 953 adm8211_write_bbp(dev, 0x0b, 0x00); 954 adm8211_write_bbp(dev, 0x0c, 0x00); 955 adm8211_write_bbp(dev, 0x0f, 0xAA); 956 adm8211_write_bbp(dev, 0x10, 0x8c); 957 adm8211_write_bbp(dev, 0x11, 0x43); 958 adm8211_write_bbp(dev, 0x18, 0x40); 959 adm8211_write_bbp(dev, 0x20, 0x23); 960 adm8211_write_bbp(dev, 0x21, 0x02); 961 adm8211_write_bbp(dev, 0x22, 0x28); 962 adm8211_write_bbp(dev, 0x23, 0x30); 963 adm8211_write_bbp(dev, 0x24, 0x2d); 964 adm8211_write_bbp(dev, 0x28, 0x35); 965 adm8211_write_bbp(dev, 0x2a, 0x8c); 966 adm8211_write_bbp(dev, 0x2b, 0x81); 967 adm8211_write_bbp(dev, 0x2c, 0x44); 968 adm8211_write_bbp(dev, 0x2d, 0x0A); 969 adm8211_write_bbp(dev, 0x29, 0x40); 970 adm8211_write_bbp(dev, 0x60, 0x08); 971 adm8211_write_bbp(dev, 0x64, 0x01); 972 break; 973 974 case ADM8211_MAX2820: 975 adm8211_write_bbp(dev, 0x00, 0x00); 976 adm8211_write_bbp(dev, 0x01, 0x00); 977 adm8211_write_bbp(dev, 0x02, 0x00); 978 adm8211_write_bbp(dev, 0x03, 0x00); 979 adm8211_write_bbp(dev, 0x06, 0x0f); 980 adm8211_write_bbp(dev, 0x09, 0x05); 981 adm8211_write_bbp(dev, 0x0a, 0x02); 982 adm8211_write_bbp(dev, 0x0b, 0x00); 983 adm8211_write_bbp(dev, 0x0c, 0x0f); 984 adm8211_write_bbp(dev, 0x0f, 0x55); 985 adm8211_write_bbp(dev, 0x10, 0x8d); 986 adm8211_write_bbp(dev, 0x11, 0x43); 987 adm8211_write_bbp(dev, 0x18, 0x4a); 988 adm8211_write_bbp(dev, 0x20, 0x20); 989 adm8211_write_bbp(dev, 0x21, 0x02); 990 adm8211_write_bbp(dev, 0x22, 0x23); 991 adm8211_write_bbp(dev, 0x23, 0x30); 992 adm8211_write_bbp(dev, 0x24, 0x2d); 993 adm8211_write_bbp(dev, 0x2a, 0x8c); 994 adm8211_write_bbp(dev, 0x2b, 0x81); 995 adm8211_write_bbp(dev, 0x2c, 0x44); 996 adm8211_write_bbp(dev, 0x29, 0x4a); 997 adm8211_write_bbp(dev, 0x60, 0x2b); 998 adm8211_write_bbp(dev, 0x64, 0x01); 999 break; 1000 1001 case ADM8211_AL2210L: 1002 adm8211_write_bbp(dev, 0x00, 0x00); 1003 adm8211_write_bbp(dev, 0x01, 0x00); 1004 adm8211_write_bbp(dev, 0x02, 0x00); 1005 adm8211_write_bbp(dev, 0x03, 0x00); 1006 adm8211_write_bbp(dev, 0x06, 0x0f); 1007 adm8211_write_bbp(dev, 0x07, 0x05); 1008 adm8211_write_bbp(dev, 0x08, 0x03); 1009 adm8211_write_bbp(dev, 0x09, 0x00); 1010 adm8211_write_bbp(dev, 0x0a, 0x00); 1011 adm8211_write_bbp(dev, 0x0b, 0x00); 1012 adm8211_write_bbp(dev, 0x0c, 0x10); 1013 adm8211_write_bbp(dev, 0x0f, 0x55); 1014 adm8211_write_bbp(dev, 0x10, 0x8d); 1015 adm8211_write_bbp(dev, 0x11, 0x43); 1016 adm8211_write_bbp(dev, 0x18, 0x4a); 1017 adm8211_write_bbp(dev, 0x20, 0x20); 1018 adm8211_write_bbp(dev, 0x21, 0x02); 1019 adm8211_write_bbp(dev, 0x22, 0x23); 1020 adm8211_write_bbp(dev, 0x23, 0x30); 1021 adm8211_write_bbp(dev, 0x24, 0x2d); 1022 adm8211_write_bbp(dev, 0x2a, 0xaa); 1023 adm8211_write_bbp(dev, 0x2b, 0x81); 1024 adm8211_write_bbp(dev, 0x2c, 0x44); 1025 adm8211_write_bbp(dev, 0x29, 0xfa); 1026 adm8211_write_bbp(dev, 0x60, 0x2d); 1027 adm8211_write_bbp(dev, 0x64, 0x01); 1028 break; 1029 1030 case ADM8211_RFMD2948: 1031 break; 1032 1033 default: 1034 wiphy_debug(dev->wiphy, "unsupported transceiver %d\n", 1035 priv->transceiver_type); 1036 break; 1037 } 1038 } else 1039 wiphy_debug(dev->wiphy, "unsupported BBP %d\n", priv->bbp_type); 1040 1041 ADM8211_CSR_WRITE(SYNRF, 0); 1042 1043 /* Set RF CAL control source to MAC control */ 1044 reg = ADM8211_CSR_READ(SYNCTL); 1045 reg |= ADM8211_SYNCTL_SELCAL; 1046 ADM8211_CSR_WRITE(SYNCTL, reg); 1047 1048 return 0; 1049 } 1050 1051 /* configures hw beacons/probe responses */ 1052 static int adm8211_set_rate(struct ieee80211_hw *dev) 1053 { 1054 struct adm8211_priv *priv = dev->priv; 1055 u32 reg; 1056 int i = 0; 1057 u8 rate_buf[12] = {0}; 1058 1059 /* write supported rates */ 1060 if (priv->pdev->revision != ADM8211_REV_BA) { 1061 rate_buf[0] = ARRAY_SIZE(adm8211_rates); 1062 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++) 1063 rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80; 1064 } else { 1065 /* workaround for rev BA specific bug */ 1066 rate_buf[0] = 0x04; 1067 rate_buf[1] = 0x82; 1068 rate_buf[2] = 0x04; 1069 rate_buf[3] = 0x0b; 1070 rate_buf[4] = 0x16; 1071 } 1072 1073 adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf, 1074 ARRAY_SIZE(adm8211_rates) + 1); 1075 1076 reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */ 1077 reg |= 1 << 15; /* short preamble */ 1078 reg |= 110 << 24; 1079 ADM8211_CSR_WRITE(PLCPHD, reg); 1080 1081 /* MTMLT = 512 TU (max TX MSDU lifetime) 1082 * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate) 1083 * SRTYLIM = 224 (short retry limit, TX header value is default) */ 1084 ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0)); 1085 1086 return 0; 1087 } 1088 1089 static void adm8211_hw_init(struct ieee80211_hw *dev) 1090 { 1091 struct adm8211_priv *priv = dev->priv; 1092 u32 reg; 1093 u8 cline; 1094 1095 reg = ADM8211_CSR_READ(PAR); 1096 reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME; 1097 reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL); 1098 1099 if (!pci_set_mwi(priv->pdev)) { 1100 reg |= 0x1 << 24; 1101 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline); 1102 1103 switch (cline) { 1104 case 0x8: 1105 reg |= (0x1 << 14); 1106 break; 1107 case 0x10: 1108 reg |= (0x2 << 14); 1109 break; 1110 case 0x20: 1111 reg |= (0x3 << 14); 1112 break; 1113 default: 1114 reg |= (0x0 << 14); 1115 break; 1116 } 1117 } 1118 1119 ADM8211_CSR_WRITE(PAR, reg); 1120 1121 reg = ADM8211_CSR_READ(CSR_TEST1); 1122 reg &= ~(0xF << 28); 1123 reg |= (1 << 28) | (1 << 31); 1124 ADM8211_CSR_WRITE(CSR_TEST1, reg); 1125 1126 /* lose link after 4 lost beacons */ 1127 reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE; 1128 ADM8211_CSR_WRITE(WCSR, reg); 1129 1130 /* Disable APM, enable receive FIFO threshold, and set drain receive 1131 * threshold to store-and-forward */ 1132 reg = ADM8211_CSR_READ(CMDR); 1133 reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT); 1134 reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF; 1135 ADM8211_CSR_WRITE(CMDR, reg); 1136 1137 adm8211_set_rate(dev); 1138 1139 /* 4-bit values: 1140 * PWR1UP = 8 * 2 ms 1141 * PWR0PAPE = 8 us or 5 us 1142 * PWR1PAPE = 1 us or 3 us 1143 * PWR0TRSW = 5 us 1144 * PWR1TRSW = 12 us 1145 * PWR0PE2 = 13 us 1146 * PWR1PE2 = 1 us 1147 * PWR0TXPE = 8 or 6 */ 1148 if (priv->pdev->revision < ADM8211_REV_CA) 1149 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18); 1150 else 1151 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16); 1152 1153 /* Enable store and forward for transmit */ 1154 priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB; 1155 ADM8211_CSR_WRITE(NAR, priv->nar); 1156 1157 /* Reset RF */ 1158 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO); 1159 ADM8211_CSR_READ(SYNRF); 1160 msleep(10); 1161 ADM8211_CSR_WRITE(SYNRF, 0); 1162 ADM8211_CSR_READ(SYNRF); 1163 msleep(5); 1164 1165 /* Set CFP Max Duration to 0x10 TU */ 1166 reg = ADM8211_CSR_READ(CFPP); 1167 reg &= ~(0xffff << 8); 1168 reg |= 0x0010 << 8; 1169 ADM8211_CSR_WRITE(CFPP, reg); 1170 1171 /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us 1172 * TUCNT = 0x3ff - Tu counter 1024 us */ 1173 ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff); 1174 1175 /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us), 1176 * DIFS=50 us, EIFS=100 us */ 1177 if (priv->pdev->revision < ADM8211_REV_CA) 1178 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) | 1179 (50 << 9) | 100); 1180 else 1181 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) | 1182 (50 << 9) | 100); 1183 1184 /* PCNT = 1 (MAC idle time awake/sleep, unit S) 1185 * RMRD = 2346 * 8 + 1 us (max RX duration) */ 1186 ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769); 1187 1188 /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */ 1189 ADM8211_CSR_WRITE(RSPT, 0xffffff00); 1190 1191 /* Initialize BBP (and SYN) */ 1192 adm8211_hw_init_bbp(dev); 1193 1194 /* make sure interrupts are off */ 1195 ADM8211_CSR_WRITE(IER, 0); 1196 1197 /* ACK interrupts */ 1198 ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR)); 1199 1200 /* Setup WEP (turns it off for now) */ 1201 reg = ADM8211_CSR_READ(MACTEST); 1202 reg &= ~(7 << 20); 1203 ADM8211_CSR_WRITE(MACTEST, reg); 1204 1205 reg = ADM8211_CSR_READ(WEPCTL); 1206 reg &= ~ADM8211_WEPCTL_WEPENABLE; 1207 reg |= ADM8211_WEPCTL_WEPRXBYP; 1208 ADM8211_CSR_WRITE(WEPCTL, reg); 1209 1210 /* Clear the missed-packet counter. */ 1211 ADM8211_CSR_READ(LPC); 1212 } 1213 1214 static int adm8211_hw_reset(struct ieee80211_hw *dev) 1215 { 1216 struct adm8211_priv *priv = dev->priv; 1217 u32 reg, tmp; 1218 int timeout = 100; 1219 1220 /* Power-on issue */ 1221 /* TODO: check if this is necessary */ 1222 ADM8211_CSR_WRITE(FRCTL, 0); 1223 1224 /* Reset the chip */ 1225 tmp = ADM8211_CSR_READ(PAR); 1226 ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR); 1227 1228 while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--) 1229 msleep(50); 1230 1231 if (timeout <= 0) 1232 return -ETIMEDOUT; 1233 1234 ADM8211_CSR_WRITE(PAR, tmp); 1235 1236 if (priv->pdev->revision == ADM8211_REV_BA && 1237 (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER || 1238 priv->transceiver_type == ADM8211_RFMD2958)) { 1239 reg = ADM8211_CSR_READ(CSR_TEST1); 1240 reg |= (1 << 4) | (1 << 5); 1241 ADM8211_CSR_WRITE(CSR_TEST1, reg); 1242 } else if (priv->pdev->revision == ADM8211_REV_CA) { 1243 reg = ADM8211_CSR_READ(CSR_TEST1); 1244 reg &= ~((1 << 4) | (1 << 5)); 1245 ADM8211_CSR_WRITE(CSR_TEST1, reg); 1246 } 1247 1248 ADM8211_CSR_WRITE(FRCTL, 0); 1249 1250 reg = ADM8211_CSR_READ(CSR_TEST0); 1251 reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */ 1252 ADM8211_CSR_WRITE(CSR_TEST0, reg); 1253 1254 adm8211_clear_sram(dev); 1255 1256 return 0; 1257 } 1258 1259 static u64 adm8211_get_tsft(struct ieee80211_hw *dev, 1260 struct ieee80211_vif *vif) 1261 { 1262 struct adm8211_priv *priv = dev->priv; 1263 u32 tsftl; 1264 u64 tsft; 1265 1266 tsftl = ADM8211_CSR_READ(TSFTL); 1267 tsft = ADM8211_CSR_READ(TSFTH); 1268 tsft <<= 32; 1269 tsft |= tsftl; 1270 1271 return tsft; 1272 } 1273 1274 static void adm8211_set_interval(struct ieee80211_hw *dev, 1275 unsigned short bi, unsigned short li) 1276 { 1277 struct adm8211_priv *priv = dev->priv; 1278 u32 reg; 1279 1280 /* BP (beacon interval) = data->beacon_interval 1281 * LI (listen interval) = data->listen_interval (in beacon intervals) */ 1282 reg = (bi << 16) | li; 1283 ADM8211_CSR_WRITE(BPLI, reg); 1284 } 1285 1286 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid) 1287 { 1288 struct adm8211_priv *priv = dev->priv; 1289 u32 reg; 1290 1291 ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid)); 1292 reg = ADM8211_CSR_READ(ABDA1); 1293 reg &= 0x0000ffff; 1294 reg |= (bssid[4] << 16) | (bssid[5] << 24); 1295 ADM8211_CSR_WRITE(ABDA1, reg); 1296 } 1297 1298 static int adm8211_config(struct ieee80211_hw *dev, u32 changed) 1299 { 1300 struct adm8211_priv *priv = dev->priv; 1301 struct ieee80211_conf *conf = &dev->conf; 1302 int channel = 1303 ieee80211_frequency_to_channel(conf->chandef.chan->center_freq); 1304 1305 if (channel != priv->channel) { 1306 priv->channel = channel; 1307 adm8211_rf_set_channel(dev, priv->channel); 1308 } 1309 1310 return 0; 1311 } 1312 1313 static void adm8211_bss_info_changed(struct ieee80211_hw *dev, 1314 struct ieee80211_vif *vif, 1315 struct ieee80211_bss_conf *conf, 1316 u32 changes) 1317 { 1318 struct adm8211_priv *priv = dev->priv; 1319 1320 if (!(changes & BSS_CHANGED_BSSID)) 1321 return; 1322 1323 if (!ether_addr_equal(conf->bssid, priv->bssid)) { 1324 adm8211_set_bssid(dev, conf->bssid); 1325 memcpy(priv->bssid, conf->bssid, ETH_ALEN); 1326 } 1327 } 1328 1329 static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw, 1330 struct netdev_hw_addr_list *mc_list) 1331 { 1332 unsigned int bit_nr; 1333 u32 mc_filter[2]; 1334 struct netdev_hw_addr *ha; 1335 1336 mc_filter[1] = mc_filter[0] = 0; 1337 1338 netdev_hw_addr_list_for_each(ha, mc_list) { 1339 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1340 1341 bit_nr &= 0x3F; 1342 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1343 } 1344 1345 return mc_filter[0] | ((u64)(mc_filter[1]) << 32); 1346 } 1347 1348 static void adm8211_configure_filter(struct ieee80211_hw *dev, 1349 unsigned int changed_flags, 1350 unsigned int *total_flags, 1351 u64 multicast) 1352 { 1353 static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 1354 struct adm8211_priv *priv = dev->priv; 1355 unsigned int new_flags; 1356 u32 mc_filter[2]; 1357 1358 mc_filter[0] = multicast; 1359 mc_filter[1] = multicast >> 32; 1360 1361 new_flags = 0; 1362 1363 if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) { 1364 new_flags |= FIF_ALLMULTI; 1365 priv->nar &= ~ADM8211_NAR_PR; 1366 priv->nar |= ADM8211_NAR_MM; 1367 mc_filter[1] = mc_filter[0] = ~0; 1368 } else { 1369 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR); 1370 } 1371 1372 ADM8211_IDLE_RX(); 1373 1374 ADM8211_CSR_WRITE(MAR0, mc_filter[0]); 1375 ADM8211_CSR_WRITE(MAR1, mc_filter[1]); 1376 ADM8211_CSR_READ(NAR); 1377 1378 if (priv->nar & ADM8211_NAR_PR) 1379 ieee80211_hw_set(dev, RX_INCLUDES_FCS); 1380 else 1381 __clear_bit(IEEE80211_HW_RX_INCLUDES_FCS, dev->flags); 1382 1383 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) 1384 adm8211_set_bssid(dev, bcast); 1385 else 1386 adm8211_set_bssid(dev, priv->bssid); 1387 1388 ADM8211_RESTORE(); 1389 1390 *total_flags = new_flags; 1391 } 1392 1393 static int adm8211_add_interface(struct ieee80211_hw *dev, 1394 struct ieee80211_vif *vif) 1395 { 1396 struct adm8211_priv *priv = dev->priv; 1397 if (priv->mode != NL80211_IFTYPE_MONITOR) 1398 return -EOPNOTSUPP; 1399 1400 switch (vif->type) { 1401 case NL80211_IFTYPE_STATION: 1402 priv->mode = vif->type; 1403 break; 1404 default: 1405 return -EOPNOTSUPP; 1406 } 1407 1408 ADM8211_IDLE(); 1409 1410 ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)vif->addr)); 1411 ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(vif->addr + 4))); 1412 1413 adm8211_update_mode(dev); 1414 1415 ADM8211_RESTORE(); 1416 1417 return 0; 1418 } 1419 1420 static void adm8211_remove_interface(struct ieee80211_hw *dev, 1421 struct ieee80211_vif *vif) 1422 { 1423 struct adm8211_priv *priv = dev->priv; 1424 priv->mode = NL80211_IFTYPE_MONITOR; 1425 } 1426 1427 static int adm8211_init_rings(struct ieee80211_hw *dev) 1428 { 1429 struct adm8211_priv *priv = dev->priv; 1430 struct adm8211_desc *desc = NULL; 1431 struct adm8211_rx_ring_info *rx_info; 1432 struct adm8211_tx_ring_info *tx_info; 1433 unsigned int i; 1434 1435 for (i = 0; i < priv->rx_ring_size; i++) { 1436 desc = &priv->rx_ring[i]; 1437 desc->status = 0; 1438 desc->length = cpu_to_le32(RX_PKT_SIZE); 1439 priv->rx_buffers[i].skb = NULL; 1440 } 1441 /* Mark the end of RX ring; hw returns to base address after this 1442 * descriptor */ 1443 desc->length |= cpu_to_le32(RDES1_CONTROL_RER); 1444 1445 for (i = 0; i < priv->rx_ring_size; i++) { 1446 desc = &priv->rx_ring[i]; 1447 rx_info = &priv->rx_buffers[i]; 1448 1449 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE); 1450 if (rx_info->skb == NULL) 1451 break; 1452 rx_info->mapping = pci_map_single(priv->pdev, 1453 skb_tail_pointer(rx_info->skb), 1454 RX_PKT_SIZE, 1455 PCI_DMA_FROMDEVICE); 1456 if (pci_dma_mapping_error(priv->pdev, rx_info->mapping)) { 1457 dev_kfree_skb(rx_info->skb); 1458 rx_info->skb = NULL; 1459 break; 1460 } 1461 1462 desc->buffer1 = cpu_to_le32(rx_info->mapping); 1463 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL); 1464 } 1465 1466 /* Setup TX ring. TX buffers descriptors will be filled in as needed */ 1467 for (i = 0; i < priv->tx_ring_size; i++) { 1468 desc = &priv->tx_ring[i]; 1469 tx_info = &priv->tx_buffers[i]; 1470 1471 tx_info->skb = NULL; 1472 tx_info->mapping = 0; 1473 desc->status = 0; 1474 } 1475 desc->length = cpu_to_le32(TDES1_CONTROL_TER); 1476 1477 priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0; 1478 ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma); 1479 ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma); 1480 1481 return 0; 1482 } 1483 1484 static void adm8211_free_rings(struct ieee80211_hw *dev) 1485 { 1486 struct adm8211_priv *priv = dev->priv; 1487 unsigned int i; 1488 1489 for (i = 0; i < priv->rx_ring_size; i++) { 1490 if (!priv->rx_buffers[i].skb) 1491 continue; 1492 1493 pci_unmap_single( 1494 priv->pdev, 1495 priv->rx_buffers[i].mapping, 1496 RX_PKT_SIZE, PCI_DMA_FROMDEVICE); 1497 1498 dev_kfree_skb(priv->rx_buffers[i].skb); 1499 } 1500 1501 for (i = 0; i < priv->tx_ring_size; i++) { 1502 if (!priv->tx_buffers[i].skb) 1503 continue; 1504 1505 pci_unmap_single(priv->pdev, 1506 priv->tx_buffers[i].mapping, 1507 priv->tx_buffers[i].skb->len, 1508 PCI_DMA_TODEVICE); 1509 1510 dev_kfree_skb(priv->tx_buffers[i].skb); 1511 } 1512 } 1513 1514 static int adm8211_start(struct ieee80211_hw *dev) 1515 { 1516 struct adm8211_priv *priv = dev->priv; 1517 int retval; 1518 1519 /* Power up MAC and RF chips */ 1520 retval = adm8211_hw_reset(dev); 1521 if (retval) { 1522 wiphy_err(dev->wiphy, "hardware reset failed\n"); 1523 goto fail; 1524 } 1525 1526 retval = adm8211_init_rings(dev); 1527 if (retval) { 1528 wiphy_err(dev->wiphy, "failed to initialize rings\n"); 1529 goto fail; 1530 } 1531 1532 /* Init hardware */ 1533 adm8211_hw_init(dev); 1534 adm8211_rf_set_channel(dev, priv->channel); 1535 1536 retval = request_irq(priv->pdev->irq, adm8211_interrupt, 1537 IRQF_SHARED, "adm8211", dev); 1538 if (retval) { 1539 wiphy_err(dev->wiphy, "failed to register IRQ handler\n"); 1540 goto fail; 1541 } 1542 1543 ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE | 1544 ADM8211_IER_RCIE | ADM8211_IER_TCIE | 1545 ADM8211_IER_TDUIE | ADM8211_IER_GPTIE); 1546 priv->mode = NL80211_IFTYPE_MONITOR; 1547 adm8211_update_mode(dev); 1548 ADM8211_CSR_WRITE(RDR, 0); 1549 1550 adm8211_set_interval(dev, 100, 10); 1551 return 0; 1552 1553 fail: 1554 return retval; 1555 } 1556 1557 static void adm8211_stop(struct ieee80211_hw *dev) 1558 { 1559 struct adm8211_priv *priv = dev->priv; 1560 1561 priv->mode = NL80211_IFTYPE_UNSPECIFIED; 1562 priv->nar = 0; 1563 ADM8211_CSR_WRITE(NAR, 0); 1564 ADM8211_CSR_WRITE(IER, 0); 1565 ADM8211_CSR_READ(NAR); 1566 1567 free_irq(priv->pdev->irq, dev); 1568 1569 adm8211_free_rings(dev); 1570 } 1571 1572 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len, 1573 int plcp_signal, int short_preamble) 1574 { 1575 /* Alternative calculation from NetBSD: */ 1576 1577 /* IEEE 802.11b durations for DSSS PHY in microseconds */ 1578 #define IEEE80211_DUR_DS_LONG_PREAMBLE 144 1579 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72 1580 #define IEEE80211_DUR_DS_FAST_PLCPHDR 24 1581 #define IEEE80211_DUR_DS_SLOW_PLCPHDR 48 1582 #define IEEE80211_DUR_DS_SLOW_ACK 112 1583 #define IEEE80211_DUR_DS_FAST_ACK 56 1584 #define IEEE80211_DUR_DS_SLOW_CTS 112 1585 #define IEEE80211_DUR_DS_FAST_CTS 56 1586 #define IEEE80211_DUR_DS_SLOT 20 1587 #define IEEE80211_DUR_DS_SIFS 10 1588 1589 int remainder; 1590 1591 *dur = (80 * (24 + payload_len) + plcp_signal - 1) 1592 / plcp_signal; 1593 1594 if (plcp_signal <= PLCP_SIGNAL_2M) 1595 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 1596 *dur += 3 * (IEEE80211_DUR_DS_SIFS + 1597 IEEE80211_DUR_DS_SHORT_PREAMBLE + 1598 IEEE80211_DUR_DS_FAST_PLCPHDR) + 1599 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 1600 else 1601 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 1602 *dur += 3 * (IEEE80211_DUR_DS_SIFS + 1603 IEEE80211_DUR_DS_SHORT_PREAMBLE + 1604 IEEE80211_DUR_DS_FAST_PLCPHDR) + 1605 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 1606 1607 /* lengthen duration if long preamble */ 1608 if (!short_preamble) 1609 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 1610 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 1611 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 1612 IEEE80211_DUR_DS_FAST_PLCPHDR); 1613 1614 1615 *plcp = (80 * len) / plcp_signal; 1616 remainder = (80 * len) % plcp_signal; 1617 if (plcp_signal == PLCP_SIGNAL_11M && 1618 remainder <= 30 && remainder > 0) 1619 *plcp = (*plcp | 0x8000) + 1; 1620 else if (remainder) 1621 (*plcp)++; 1622 } 1623 1624 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */ 1625 static int adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb, 1626 u16 plcp_signal, 1627 size_t hdrlen) 1628 { 1629 struct adm8211_priv *priv = dev->priv; 1630 unsigned long flags; 1631 dma_addr_t mapping; 1632 unsigned int entry; 1633 u32 flag; 1634 1635 mapping = pci_map_single(priv->pdev, skb->data, skb->len, 1636 PCI_DMA_TODEVICE); 1637 if (pci_dma_mapping_error(priv->pdev, mapping)) 1638 return -ENOMEM; 1639 1640 spin_lock_irqsave(&priv->lock, flags); 1641 1642 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2) 1643 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS; 1644 else 1645 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS; 1646 1647 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2) 1648 ieee80211_stop_queue(dev, 0); 1649 1650 entry = priv->cur_tx % priv->tx_ring_size; 1651 1652 priv->tx_buffers[entry].skb = skb; 1653 priv->tx_buffers[entry].mapping = mapping; 1654 priv->tx_buffers[entry].hdrlen = hdrlen; 1655 priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping); 1656 1657 if (entry == priv->tx_ring_size - 1) 1658 flag |= TDES1_CONTROL_TER; 1659 priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len); 1660 1661 /* Set TX rate (SIGNAL field in PLCP PPDU format) */ 1662 flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */; 1663 priv->tx_ring[entry].status = cpu_to_le32(flag); 1664 1665 priv->cur_tx++; 1666 1667 spin_unlock_irqrestore(&priv->lock, flags); 1668 1669 /* Trigger transmit poll */ 1670 ADM8211_CSR_WRITE(TDR, 0); 1671 1672 return 0; 1673 } 1674 1675 /* Put adm8211_tx_hdr on skb and transmit */ 1676 static void adm8211_tx(struct ieee80211_hw *dev, 1677 struct ieee80211_tx_control *control, 1678 struct sk_buff *skb) 1679 { 1680 struct adm8211_tx_hdr *txhdr; 1681 size_t payload_len, hdrlen; 1682 int plcp, dur, len, plcp_signal, short_preamble; 1683 struct ieee80211_hdr *hdr; 1684 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1685 struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info); 1686 u8 rc_flags; 1687 1688 rc_flags = info->control.rates[0].flags; 1689 short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 1690 plcp_signal = txrate->bitrate; 1691 1692 hdr = (struct ieee80211_hdr *)skb->data; 1693 hdrlen = ieee80211_hdrlen(hdr->frame_control); 1694 memcpy(skb->cb, skb->data, hdrlen); 1695 hdr = (struct ieee80211_hdr *)skb->cb; 1696 skb_pull(skb, hdrlen); 1697 payload_len = skb->len; 1698 1699 txhdr = skb_push(skb, sizeof(*txhdr)); 1700 memset(txhdr, 0, sizeof(*txhdr)); 1701 memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN); 1702 txhdr->signal = plcp_signal; 1703 txhdr->frame_body_size = cpu_to_le16(payload_len); 1704 txhdr->frame_control = hdr->frame_control; 1705 1706 len = hdrlen + payload_len + FCS_LEN; 1707 1708 txhdr->frag = cpu_to_le16(0x0FFF); 1709 adm8211_calc_durations(&dur, &plcp, payload_len, 1710 len, plcp_signal, short_preamble); 1711 txhdr->plcp_frag_head_len = cpu_to_le16(plcp); 1712 txhdr->plcp_frag_tail_len = cpu_to_le16(plcp); 1713 txhdr->dur_frag_head = cpu_to_le16(dur); 1714 txhdr->dur_frag_tail = cpu_to_le16(dur); 1715 1716 txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER); 1717 1718 if (short_preamble) 1719 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE); 1720 1721 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) 1722 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS); 1723 1724 txhdr->retry_limit = info->control.rates[0].count; 1725 1726 if (adm8211_tx_raw(dev, skb, plcp_signal, hdrlen)) { 1727 /* Drop packet */ 1728 ieee80211_free_txskb(dev, skb); 1729 } 1730 } 1731 1732 static int adm8211_alloc_rings(struct ieee80211_hw *dev) 1733 { 1734 struct adm8211_priv *priv = dev->priv; 1735 unsigned int ring_size; 1736 1737 priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size + 1738 sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL); 1739 if (!priv->rx_buffers) 1740 return -ENOMEM; 1741 1742 priv->tx_buffers = (void *)priv->rx_buffers + 1743 sizeof(*priv->rx_buffers) * priv->rx_ring_size; 1744 1745 /* Allocate TX/RX descriptors */ 1746 ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size + 1747 sizeof(struct adm8211_desc) * priv->tx_ring_size; 1748 priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size, 1749 &priv->rx_ring_dma); 1750 1751 if (!priv->rx_ring) { 1752 kfree(priv->rx_buffers); 1753 priv->rx_buffers = NULL; 1754 priv->tx_buffers = NULL; 1755 return -ENOMEM; 1756 } 1757 1758 priv->tx_ring = priv->rx_ring + priv->rx_ring_size; 1759 priv->tx_ring_dma = priv->rx_ring_dma + 1760 sizeof(struct adm8211_desc) * priv->rx_ring_size; 1761 1762 return 0; 1763 } 1764 1765 static const struct ieee80211_ops adm8211_ops = { 1766 .tx = adm8211_tx, 1767 .start = adm8211_start, 1768 .stop = adm8211_stop, 1769 .add_interface = adm8211_add_interface, 1770 .remove_interface = adm8211_remove_interface, 1771 .config = adm8211_config, 1772 .bss_info_changed = adm8211_bss_info_changed, 1773 .prepare_multicast = adm8211_prepare_multicast, 1774 .configure_filter = adm8211_configure_filter, 1775 .get_stats = adm8211_get_stats, 1776 .get_tsf = adm8211_get_tsft 1777 }; 1778 1779 static int adm8211_probe(struct pci_dev *pdev, 1780 const struct pci_device_id *id) 1781 { 1782 struct ieee80211_hw *dev; 1783 struct adm8211_priv *priv; 1784 unsigned long mem_len; 1785 unsigned int io_len; 1786 int err; 1787 u32 reg; 1788 u8 perm_addr[ETH_ALEN]; 1789 1790 err = pci_enable_device(pdev); 1791 if (err) { 1792 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n", 1793 pci_name(pdev)); 1794 return err; 1795 } 1796 1797 io_len = pci_resource_len(pdev, 0); 1798 mem_len = pci_resource_len(pdev, 1); 1799 if (io_len < 256 || mem_len < 1024) { 1800 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n", 1801 pci_name(pdev)); 1802 goto err_disable_pdev; 1803 } 1804 1805 1806 /* check signature */ 1807 pci_read_config_dword(pdev, 0x80 /* CR32 */, ®); 1808 if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) { 1809 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n", 1810 pci_name(pdev), reg); 1811 goto err_disable_pdev; 1812 } 1813 1814 err = pci_request_regions(pdev, "adm8211"); 1815 if (err) { 1816 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n", 1817 pci_name(pdev)); 1818 return err; /* someone else grabbed it? don't disable it */ 1819 } 1820 1821 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) || 1822 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 1823 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n", 1824 pci_name(pdev)); 1825 goto err_free_reg; 1826 } 1827 1828 pci_set_master(pdev); 1829 1830 dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops); 1831 if (!dev) { 1832 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n", 1833 pci_name(pdev)); 1834 err = -ENOMEM; 1835 goto err_free_reg; 1836 } 1837 priv = dev->priv; 1838 priv->pdev = pdev; 1839 1840 spin_lock_init(&priv->lock); 1841 1842 SET_IEEE80211_DEV(dev, &pdev->dev); 1843 1844 pci_set_drvdata(pdev, dev); 1845 1846 priv->map = pci_iomap(pdev, 1, mem_len); 1847 if (!priv->map) 1848 priv->map = pci_iomap(pdev, 0, io_len); 1849 1850 if (!priv->map) { 1851 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n", 1852 pci_name(pdev)); 1853 err = -ENOMEM; 1854 goto err_free_dev; 1855 } 1856 1857 priv->rx_ring_size = rx_ring_size; 1858 priv->tx_ring_size = tx_ring_size; 1859 1860 err = adm8211_alloc_rings(dev); 1861 if (err) { 1862 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n", 1863 pci_name(pdev)); 1864 goto err_iounmap; 1865 } 1866 1867 *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0)); 1868 *(__le16 *)&perm_addr[4] = 1869 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF); 1870 1871 if (!is_valid_ether_addr(perm_addr)) { 1872 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n", 1873 pci_name(pdev)); 1874 eth_random_addr(perm_addr); 1875 } 1876 SET_IEEE80211_PERM_ADDR(dev, perm_addr); 1877 1878 dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr); 1879 /* dev->flags = RX_INCLUDES_FCS in promisc mode */ 1880 ieee80211_hw_set(dev, SIGNAL_UNSPEC); 1881 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 1882 1883 dev->max_signal = 100; /* FIXME: find better value */ 1884 1885 dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */ 1886 1887 priv->retry_limit = 3; 1888 priv->ant_power = 0x40; 1889 priv->tx_power = 0x40; 1890 priv->lpf_cutoff = 0xFF; 1891 priv->lnags_threshold = 0xFF; 1892 priv->mode = NL80211_IFTYPE_UNSPECIFIED; 1893 1894 /* Power-on issue. EEPROM won't read correctly without */ 1895 if (pdev->revision >= ADM8211_REV_BA) { 1896 ADM8211_CSR_WRITE(FRCTL, 0); 1897 ADM8211_CSR_READ(FRCTL); 1898 ADM8211_CSR_WRITE(FRCTL, 1); 1899 ADM8211_CSR_READ(FRCTL); 1900 msleep(100); 1901 } 1902 1903 err = adm8211_read_eeprom(dev); 1904 if (err) { 1905 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n", 1906 pci_name(pdev)); 1907 goto err_free_desc; 1908 } 1909 1910 priv->channel = 1; 1911 1912 dev->wiphy->bands[NL80211_BAND_2GHZ] = &priv->band; 1913 1914 wiphy_ext_feature_set(dev->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 1915 1916 err = ieee80211_register_hw(dev); 1917 if (err) { 1918 printk(KERN_ERR "%s (adm8211): Cannot register device\n", 1919 pci_name(pdev)); 1920 goto err_free_eeprom; 1921 } 1922 1923 wiphy_info(dev->wiphy, "hwaddr %pM, Rev 0x%02x\n", 1924 dev->wiphy->perm_addr, pdev->revision); 1925 1926 return 0; 1927 1928 err_free_eeprom: 1929 kfree(priv->eeprom); 1930 1931 err_free_desc: 1932 pci_free_consistent(pdev, 1933 sizeof(struct adm8211_desc) * priv->rx_ring_size + 1934 sizeof(struct adm8211_desc) * priv->tx_ring_size, 1935 priv->rx_ring, priv->rx_ring_dma); 1936 kfree(priv->rx_buffers); 1937 1938 err_iounmap: 1939 pci_iounmap(pdev, priv->map); 1940 1941 err_free_dev: 1942 ieee80211_free_hw(dev); 1943 1944 err_free_reg: 1945 pci_release_regions(pdev); 1946 1947 err_disable_pdev: 1948 pci_disable_device(pdev); 1949 return err; 1950 } 1951 1952 1953 static void adm8211_remove(struct pci_dev *pdev) 1954 { 1955 struct ieee80211_hw *dev = pci_get_drvdata(pdev); 1956 struct adm8211_priv *priv; 1957 1958 if (!dev) 1959 return; 1960 1961 ieee80211_unregister_hw(dev); 1962 1963 priv = dev->priv; 1964 1965 pci_free_consistent(pdev, 1966 sizeof(struct adm8211_desc) * priv->rx_ring_size + 1967 sizeof(struct adm8211_desc) * priv->tx_ring_size, 1968 priv->rx_ring, priv->rx_ring_dma); 1969 1970 kfree(priv->rx_buffers); 1971 kfree(priv->eeprom); 1972 pci_iounmap(pdev, priv->map); 1973 pci_release_regions(pdev); 1974 pci_disable_device(pdev); 1975 ieee80211_free_hw(dev); 1976 } 1977 1978 1979 #ifdef CONFIG_PM 1980 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state) 1981 { 1982 pci_save_state(pdev); 1983 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1984 return 0; 1985 } 1986 1987 static int adm8211_resume(struct pci_dev *pdev) 1988 { 1989 pci_set_power_state(pdev, PCI_D0); 1990 pci_restore_state(pdev); 1991 return 0; 1992 } 1993 #endif /* CONFIG_PM */ 1994 1995 1996 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table); 1997 1998 /* TODO: implement enable_wake */ 1999 static struct pci_driver adm8211_driver = { 2000 .name = "adm8211", 2001 .id_table = adm8211_pci_id_table, 2002 .probe = adm8211_probe, 2003 .remove = adm8211_remove, 2004 #ifdef CONFIG_PM 2005 .suspend = adm8211_suspend, 2006 .resume = adm8211_resume, 2007 #endif /* CONFIG_PM */ 2008 }; 2009 2010 module_pci_driver(adm8211_driver); 2011